| “Bounded Proof” sign-off with formal coverage | Abhishek Anand, Chinyu Chen, Bathri Narayanan Subramanian, Joe Hupcey | | | | | | | |
| “C” you on the faster side: Accelerating SV DPI based co-simulation | Parag Goel, Amit Sharma, and Hari Vinodh Balisetty | | | | | | | |
| “C” you on the faster side: Accelerating SV DPI based co-simulation | Hari Vinod Balisetty, Parag Goel, and Amit Sharma | | | | | | | |
| “In-Emulator” UVM++ Randomized Testbenches for High Performance Functional Verification | Adnan Hamid and David Kelf | | | | | | | |
| “Shift left” Hierarchical Low-Power Static Verification Using SAM | Bharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal | | | | | | | |
| “Shift left” Hierarchical Low-Power Static Verification Using SAM | Bharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal | | | | | | | |
| “What-If” analysis of Safety Mechanism’s impacts on ETHMAC design under Functional Safety flow | Udaykrishna J, Sujatha Hiremath, Kapil Kumar, Sachin Pathak, Gaurav Goel | | | | | | | |
| 1,2,3,…8 simple steps towards a single digital signal processing testbench supporting heterogeneous interfaces and datatypes | Nico Lugil | | | | | | | |
| 1,2,3,…8 simple steps towards a single digital signal processing testbench supporting heterogeneous interfaces and datatypes | Nico Lugil | | | | | | | |
| 400G IPU Case Study: Demonstrating Shift-left of Soft Logic RTL Development on Real World Design using Intel Agilex FPGA SystemC Model | Pravat K Nayak, Vikrant Kapila, Pushpa Naik & Niketkumar Sharma | | | | | | | |
| 5.1 Smart Verification leveraging PSS; 5.2 When Automotive FuSa Met IC | David Hwang and Sera Gao | | | | | | | |
| 5G – Chances and Challenges from Test & Measurement Perspective | Meik Kottkamp | | | | | | | |
| 5G / NR Explained From 3GPP 5G Standard Fundamentals To 5G Enabled Verticals | Michael Faerber and Kilian Roth | | | | | | | |
| 5G for people and things Spectrum Opportunities and Challenges of 5G | | | | | | | | |
| A 30 Minute Project Makeover Using Continuous Integration | JL Gray and Gordon McGregor | | | | | | | |
| A 30 Minute Project Makeover Using Continuous Integration | JL Gray | | | | | | | |
| A 360 Degree View of UVM Events | Vikas Billa, Nagesh Kokonda | | | | | | | |
| A 360 Degree View of UVM Events – A Case Study | Deepak Kumar E V, Sathish Dadi, and Vikas Billa | | | | | | | |
| A 360 Degree View of UVM Events (A Case Study) | Deepak Kumar E V, Sathish Dadi, and Vikas Billa | | | | | | | |
| A Client-Server Method for Register Design and Documentation | Scott D Orangio and Julien Gagnon | | | | | | | |
| A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISC V Core | Junaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, Aashir Ahsan | | | | | | | |
| A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISCV Core | Junaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, and Aashir Ahsan | | | | | | | |
| A comparison of methodologies to simulate mixed-signal IC | Simone Fontanesi, Karsten Einwich, Paul Ehrlich, Gaetano Formato, Andrea Possemato | | | | | | | |
| A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance Analysis | Bishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel | | | | | | | |
| A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance Analysis. | Bishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel | | | | | | | |
| A Compositional Simulation Framework for Testing Adversarial Robustness of Deep Neural Networks | Youssef Maher Nader, Mostafa Lotfy Hatab, Mazen Mostafa Ghaleb, Safia Medhat Bakr, Tasneem A. Awaad, Ahmed AlGanzouri, Mohamed Abdelsalam, and M. Watheq El-Kharashi | | | | | | | |
| A Compositional Simulation Framework for Testing Adversarial Robustness of Deep Neural Networks | Youssef Maher Nader; Mostafa Lotfy Hatab; Mazen Mostafa Ghaleb; Safia Medhat Bakr; Tasneem A. Awaad; Ahmed AlGanzouri; Mohamed Abdelsalam; M. Watheq El-Kharashi | | | | | | | |
| A Comprehensive High Speed Link Verification Test Bench Harnessing Scripting to Achieve Faster Functional Coverage Closure. | Piyush Tankwal, Arnab Ghosh, Piyush Agnihotri, Mukesh Gandhi, Parag S Lonkar | | | | | | | |
| A Comprehensive Verification Platform for RISC-V based Processors | Emre Karabulut, Berk Kisinbay, Abdullah Yildiz and Rifat Demircioglu | | | | | | | |
| A Comprehensive Verification Platform for RISC-V based Processors | Emre Karabulut, Berk Kisinbay, Abdullah Yildiz, and Rifat Demircioglu | | | | | | | |
| A concept for expanding a UVM testbench to the analog-centric toplevel | Felix Assmann, Axel Strobel and Hans Zander | | | | | | | |
| A concept for expanding a UVM testbenchto the analog-centric toplevel | Felix Assmann, Axel Strobel and Hans Zander | | | | | | | |
| A Configurable, Re-usable UVM Environment Coupled with Advanced Spice Simulator for Analog and Mixed-Signal Verification of a Display PMIC | | | | | | | | |
| A Coverage-Driven Formal Methodology for Verification Sign-off | Ang Li, Hao Chen, Jason K Yu, Ee Loon Teoh, and Iswerya Prem Anand | | | | | | | |
| A Coverage-Driven Formal Methodology for Verification Sign-off | Ang Li, Hao Chen, Jason K Yu, Ee Loon Teoh and, Iswerya Prem Anand | | | | | | | |
| A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMS | Muhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, Daniel Große | | | | | | | |
| A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMS | Muhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, Daniel Große | | | | | | | |
| A Dyadic Transformation Based Methodology To Achieve Coverage Driven Verification Goal | Swapnajit Mitra | | | | | | | |
| A Dyadic Transformation Based Methodology to Achieve Coverage Driven Verification Goal | Swapnajit Mitra | | | | | | | |
| A Dynamic Approach Towards Register Coverage Generation and Collection to Reduce Compilation Overhead of Traditional UVM Register Layers | Subham Banerjee | | | | | | | |
| A Faster and Efficient Timing Constraint Verification Methodology for GFX SOCs | Vineeth B, Deepmala Sachan | | | | | | | |
| A Faster and Efficient Timing Constraint Verification Methodology for GFX SOCs | Vineeth B, Deepmala Sachan | | | | | | | |
| A Formal Verification App Towards Efficient Chip-Wide Clock Gating Verification | Prosenjit Chatterjee, Scott Fields, and Syed Suhaib | | | | | | | |
| A Formal Verification App Towards Efficient, Chip-Wide Clock Gating Verification | Prosenjit Chatterjee, Scott Fields, and Syed Suhaib | | | | | | | |
| A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog-AMS | Mike Bartley and Jeganath Gandhi R | | | | | | | |
| A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog-AMS | Mike Bartley, Jeganath Gandhi R | | | | | | | |
| A Framework for the Execution of Python Tests in SystemC and Specman Testbenches | Christoph Tietz, Sebastian Stieber , Najdet Charaf, Diana Göhringer | | | | | | | |
| A Framework for the Execution of Python Tests in SystemC and Specman Testbenches | Christoph Tietz, Sebastian Stieber, Najdet Charaf, Diana Göhringer | | | | | | | |
| A Framework for Verification of Program Control Unit of VLIW processors | Santhosh Billava, Sharangdhar M Honwadkar | | | | | | | |
| A Framework for Verification of Program Control Unit of VLIW Processors | Santhosh Billava, Sharangdhar M Honwadkar | | | | | | | |
| A Generic Approach to Handling Sideband Signals | Markus Brosch and Salman Tanvir | | | | | | | |
| A Generic Configurable Error Injection Agent for On-Chip Memories | Niharika Sachdeva, Arjun Suresh Kumar, Damandeep Saini, Anil Deshpande, Ravi Teja Gopagiri, Somasunder KS, Jaechul Park | | | | | | | |
| A Generic Configurable Error Injection Agent for All On-Chip Memories | Niharika Sachdeva, Arjun Suresh Kumar, Raviteja Gopagiri, Anil Deshpande, Somasunder Kattepura Sreenath, Damandeep Saini | | | | | | | |
| A Generic Configurable Error Injection Agent for All On-Chip Memories | Anil Deshpande, Jaechul Park, Niharika Sachdeva, Arjun Suresh Kumar, Raviteja Gopagiri, Somasund Kattepura Sreenath, Damandeep Saini | | | | | | | |
| A Generic Configurable Error Injection Agent for On-Chip Memories | Niharika Sachdeva, Arjun Suresh Kumar, Raviteja Gopagiri, Anil Deshpande, Somasunder Kattepura Sreenath | | | | | | | |
| A Generic Verification Methodology for Chip to Chip Interrupt Handling in a Multi-Chip SoC (3DIC) | Vignesh Adiththan, Padma Vutukuru, Lalithraj Mailappa, Sekhar Dangudubiyyam | | | | | | | |
| A Generic Verification Methodology for Chip to Chip Interrupt Handling in a Multi-Chip SoC (3DIC) | Vignesh Adiththan, Padma Vutukuru, Lalithraj Mailappa, Sekhar Dangudubiyyam | | | | | | | |
| A Guide To Using Continuous Integration Within The Verification Environment | Jason Sprott | | | | | | | |
| A Guide To Using Continuous Integration Within The Verification Environment | Jason Sprott, André Winkelmann, and Gordon McGregor | | | | | | | |
| A Guide To Using Continuous Integration Within The Verification Environment | André Winkelmann, Jason Sprott, and Gordon McGregor | | | | | | | |
| A Hardware and Software integrated power optimization approach with power aware simulations at SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | | | |
| A Hardware and Software Integrated Power Optimization Approach with Power Aware Simulations at SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | | | |
| A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power Intent | Vijay Kumar Sankaran, Lakshmanan Balasubramanian, Bharath Kumar Poluri, Venkatraman Ramakrishnan, Badrinarayan Zanwar, and Qingyu Lin | | | | | | | |
| A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power Intent | Qingyu Lin | | | | | | | |
| A Holistic Overview on Preventive & Corrective Action To Handle Glitches | Rohit Kumar Sinha, Parimal Das | 2022 | India | Poster | | y2022 | india | poster |
| A Holistic View of Mixed-Language IP Integration | Pankaj Singh and Gaurav Kumar Verma | | | | | | | |
| A Hybrid Approach For Interrupts Verification | Giovanni Auditore, Francesco Rua’, Qibo Peng | | | | | | | |
| A Hybrid Approach To Interrupt Verification | Giovanni Auditore, Francesco Rua’, Qibo Peng | | | | | | | |
| A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGA | Antonis Papagrigoriou, Miltos D. Grammatikakis and Voula Piperaki | | | | | | | |
| A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGA* | Antonis Papagrigoriou, Antonis Papagrigoriou and Voula Piperaki | | | | | | | |
| A Hybrid Verification Solution to RISC V Vector Extension | Chenghuan Li, Yanhua Feng, Liam Li | | | | | | | |
| A Hybrid Verification Solution to RISC-V Vector Extension | Chenghuan Li, Yanhua Feng, and Liam Li | | | | | | | |
| A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation | Thomas Soong, Christopher Browne, and Chenhui Huang | | | | | | | |
| A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation | Thomas Soong, Chenhui Huang, and Christopher Browne | | | | | | | |
| A Meta-Model-Based Approach for Semantic Fault Modeling on Multiple Abstraction Levels | Michael Schwarz and Moomen Chaari, Bogdan-Andrei Tabacaru | | | | | | | |
| A Meta-Model-Based Approach for Semantic Fault Modeling on Multiple Abstraction Levels | M. Schwarz M. Chaari, B.-A. Tabacaru, and W. Ecker | | | | | | | |
| A Meta-Modeling-Based Approach for Automatic Generation of Fault-Injection Processes | Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, and Thomas Kruse | | | | | | | |
| A Meta-Modeling-Based Approach for Automatic Generation of Fault-Injection Processes | B.-A. Tabacaru, M. Chaari, W. Ecker, and T. Kruse | | | | | | | |
| A Method to Accelerate SoC Implementation Cycle by Automatically Generating CDC Constraints | Ashish Hari, Sulabh Kumar Khare | 2015 | India | Presentation | | y2015 | india | presentation |
| A Methodology for Evaluating SI Artefacts in DDR4-3DS PHY using Channel Modelling | Aditya S Kumar, Gowdra Bomanna Chethan, Shivani Maurya, Anil Deshpande, Somasunder Kattepura Sreenath | | | | | | | |
| A Methodology for Interrupt Analysis in Virtual Platforms | Puneet Dhar | | | | | | | |
| A Methodology for Power and Energy Efficient Systems Design | Mohammed Fahad | | | | | | | |
| A Methodology for Using Traffic Generators with Real-Time Constraints | Avinash Mehta | | | | | | | |
| A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation Acceleration | Horace Chan, Brian Vandegriend, and Efrat Shneydor | | | | | | | |
| A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation Acceleration | Horace Chan, Brian Vandegriend, and Efrat Shneydor | | | | | | | |
| A Methodology to Reuse Unit Level Validation Infrastructure | Ashutosh Parkhi | | | | | | | |
| A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores | W. W. Chen, N. Tusinschi and T. L. Anderson | | | | | | | |
| A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores | W. W. Chen, N. Tusinschi, and T. L. Anderson | | | | | | | |
| A Metric-driven Methodology For Firmware Verification In Simulation/Emulation Environments | Goran Savić | | | | | | | |
| A Mixed Signal System Design Methodology in SystemC AMS for Automotive Audio Power Amplifiers | Skule Pramm, Joen Westendorp, and Quino Sandifort | | | | | | | |
| A Model-Based Reusable Framework to Parallelize Hardware and Software Development | Jouni Sillanpää, Håkan Pettersson & Tom Richter | | | | | | | |
| A Mutually-Exclusive Deployment of Formal and Simulation Techniques Using Proof-Core Analysis | Keerthikumara Devarajegowda, Jeroen Vliegen, Goran Petrovity, and Kawe Fotouhi | | | | | | | |
| A Mutually-Exclusive Deployment of Formal and Simulation Techniques Using Proof-Core Analysis | Keerthikumara Devarajegowda, Jeroen Vliegen, Goran Petrovity, and Kawe Fotouhi | | | | | | | |
| A New Approach for Generating View Generators | Johannes Schreiner, Felix Willgerodt, and Wolfgang Ecker | | | | | | | |
| A New Approach for Generating View Generators | Johannes Schreiner, Felix Willgerodt, and Wolfgang Ecker | | | | | | | |
| A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain Crossings | Omri Dassa and Yossi (Joseph) Mirsky | | | | | | | |
| A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain Crossings | Omri Dassa, Yossi Mirsky | | | | | | | |
| A New Approach to Low-Power Verification: Low Power Apps | Madhur Bhargava and Awashesh Kumar | | | | | | | |
| A New Class Of Registers | M. Peryer and D. Aerne | 2016 | United States | Paper | | y2016 | united-states | paper |
| A New Class Of Registers | Mark Peryer and David Aerne | | | | | | | |
| A New Epoch is Beginning: Are You Getting Ready for Stepping Into UVM-1.2? | Roman Wang,Uwe Simm | | | | | | | |
| A New Epoch is Beginning: Are You Getting Ready for Stepping Into UVM-1.2? | Roman Wang, Uwe Simm | | | | | | | |
| A NOVEL AND EFFICIENT METHODOLOGY TO EXPEDITE COMPLEX SOC DV CLOSURE BY LEVERAGING MODULARLY ARCHITECTURED SCALABLE ENVIRONMENT | Vinay Swargam, Guttapalem Yatisha, Ayush Agrawal, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | | | |
| A Novel Approach to Accelerate Latency of Assertion Simulation | Jack Yen, Felix Tung | | | | | | | |
| A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM Domains | Subham Banerjee and Keshava Krishna Raja | | | | | | | |
| A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM Domains | | | | | | | | |
| A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoC | Harshal Kothari, Manishadevi Satyanarayana Cheernam, Vignesh Adiththan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | | | |
| A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoC | Harshal Kothari, Manishadevi Satyanarayana Cheernam, Vignesh Adiththan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | | | |
| A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoC | Harshal Kothari, Manishadevi Satyanarayana Cheernam, Vignesh Adiththan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | | | |
| A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development | Harshal Kothari, Vinay Swargam, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | | | |
| A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development | Harshal Kothari, Vinay Swargam, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | | | |
| A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development | Harshal Kothari, Vinay Swargam, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | | | |
| A Novel Approach to Functional Test Development and Execution using High-Speed IO | Marcus Schulze Westenhorst, Jörg Simon, Markus Bücker, Klaus Dieter Hilliges, Michael Braun | | | | | | | |
| A NOVEL APPROACH TO HARDWARE CONTROLLED POWER AWARE VERIFICATION WITH OPTIMISED POWER CONSUMPTION TECHNIQUES AT SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | | | |
| A NOVEL APPROACH TO HARDWARE CONTROLLED POWER AWARE VERIFICATION WITH OPTIMISED POWER CONSUMPTION TECHNIQUES AT SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | | | |
| A Novel Approach to Hardware Controlled Power Aware Verification with Optimized Power Consumption Techniques at SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | | | |
| A Novel Approach To In-System SRAM Repair Verification in Embedded SoC to Bridge Gap between Test and Functional Mode | Harshal Kothari, Eldin Ben Jacob, Ajay Vamshi Krishna, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | | | |
| A Novel Approach to Reduce Power Consumption By Bridging The Gap between Standalone Functional Scenario and Real Time Scenario at SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | | | |
| A Novel Approach to Reuse Firmware for Verification of Controller based Sub-Systems using PSS | Vishnu Ramadas, Simranjit Singh, Ashwani Aggarwal, Woojoo Space Kim , Seonil Brian Choi | | | | | | | |
| A novel approach to standardize reusable Modular Plug and Play Skeleton Structure (MPPSS) to expedite verification closure | Himanshu Dixit, Chandrachud Murali, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | | | |
| A novel approach to standardize reusable Modular Plug and Play Skeleton Structure (MPPSS) to expedite verification closure | Chandrachud Murali, Himanshu Dixit, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | | | |
| A Novel Approach to Standardize Verification Configurations using YAML | Nikhil Tambekar | | | | | | | |
| A Novel Approach to Standardize Verification Configurations using YAML | Nikhil Tambekar | | | | | | | |
| A Novel Approach to Verify CNN Based Image Processing Unit | Sumit K. Kulshreshtha, Raghavendra J N | | | | | | | |
| A Novel Framework to Accelerate System Validation on Emulation | Manoj Sharma Khandelwal, Rinkesh Yadav, Sarang Kalbande & Garima Srivastav | | | | | | | |
| A Novel Performance Evaluation Methodology using Virtual Prototyping and Emulation | WoojooSpace Kim | | | | | | | |
| A Novel Performance Evaluation Methodology using Virtual Prototyping and Emulation | Woojoo Space Kim | | | | | | | |
| A Novel Processor Verification Methodology based on UVM | Abhineet Bhojak, Tejbal Prasad, and Stephan Herrmann | | | | | | | |
| A Novel Variation-Aware Mixed-Signal Verification Methodology to achieve High-Sigma Variation coverage at nanometer designs | Tibi Galambos, Sumit Vishwakarma | | | | | | | |
| A perfect blend of verification techniques, platforms, and AI-empowered debugging in Ethernet Subsystem Verification | Olivera Stojanovic & Tijana Misic | | | | | | | |
| A Practical Approach to Measuring and Improving the Functional Verification of Embedded Software | Stéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès | | | | | | | |
| A Practical Approach to Measuring and Improving the Functional Verification of Embedded Software | Stéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès | | | | | | | |
| A Practical Look @ SystemVerilog Coverage – Tips, Tricks, and Gotchas | Doug Smith and John Aynsley | | | | | | | |
| A Pragmatic Approach Leveraging Portable Stimulus from Subsystem to SoC level and SoC Emulation | Karandeep Singh, Aditya Chopra, Joachim Geishauser, Nitin Verma | | | | | | | |
| A Pragmatic Approach Leveraging Portable Stimulus from Subsystem to SoC level and SoC Emulation | Karandeep Singh, Aditya Chopra, Joachim Geishauser, Nitin Verma | | | | | | | |
| A Pragmatic Approach to Metastability-Aware Simulation | Joseph Bulone, Roger Sabbagh | | | | | | | |
| A Pragmatic Approach to Metastability-Aware Simulation | Joseph Bulone, Roger Sabbagh | | | | | | | |
| A real world application of IP-XACT for IP packaging Bridging the usability gap | Philip Todd | | | | | | | |
| A real world application of IP-XACT for IP packaging Bridging the usability gap | Philip Todd | | | | | | | |
| A Real-World Clock Generator Class for UVM | Rhitam Datta, Ankit Somani | | | | | | | |
| A Recipe for swift Tape-out of Derivative SoCs: A Comprehensive Validation Approach using Formal-based Sequential Equivalence and Connectivity Checking | Priyanshu Jain, Saket Gaddagi, Sandeep Kumar and Ipshita Tripathi | | | | | | | |
| A Reconfigurable And Fully Automated SRAM Environment Generation Flow for Robust Verification And To Accelerate DV Closure | Vinay Swargam, Lakshmana Kumar Arumugasamy, Sriram Kazhiyur Sounderrajan | | | | | | | |
| A Reconfigurable Interface Architecture to Protect System IP | Arshad Riazuddin, Shoab A. Khan | | | | | | | |
| A Reconfigurable Interface Architecture to Protect System IP | Arshad Riazuddin, Shoab A. Khan | | | | | | | |
| A Reusability Combat in UVM Callbacks vs Factory | Deepak Kumar EV, Vikas Billa, Satish Dadi, Ranganath Kempanahally | | | | | | | |
| A Reusable, Scalable Formal App for Verifying Any Configuration of 3D IC Connectivity | Daniel Han, Walter Sze, Benjamin Ting, and Darrow Chu | | | | | | | |
| A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage | Ashutosh Mishra, Suresh Vasu | | | | | | | |
| A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage | Ashutosh Mishra, Suresh Vasu | | | | | | | |
| A scalable VIP component to increase robustness of co-verification within an ASIC | Mario de Matteis, Matteo Barbati | | | | | | | |
| A scalableVIP component to increase robustness of co-verification within an ASIC | Mario de Matteis & Matteo Barbati | | | | | | | |
| A Semi-Formal Verification Methodology for Efficient Configuration Coverage of Highly Configurable Digital Designs | Aman Kumar, Sebastian Simon | | | | | | | |
| A Shift-left Methodology for an Early Power Closure Using EDCs and Power Analysis | Mohammed Fahad | | | | | | | |
| A shift-left Methodology for an early power closure using PowerPro | Mohammed Fahad | | | | | | | |
| A Simplified Approach Using UVM Sequence Items for Layering Protocol Verification | Christine Thomson and Haiqian Yu | | | | | | | |
| A Simplified Approach Using UVM Sequence Items for Layering Protocol Verification | Haiqian Yu and Christine Thomson | | | | | | | |
| A Simulation Expert’s Guide to Formally Proving SW Status and Interrupts | Neil Johnson | | | | | | | |
| A Simulation Expert’s Guide to Formally Verifying Software Status and Interrupts | Neil Johnson | | | | | | | |
| A single generated UVM Register Model to handle multiple DUT configurations | Salvatore Marco Rosselli and Giuseppe Falconeri | | | | | | | |
| A SMART GENERATION OF DESIGN ATTRIBUTES FOR VERIFICATION CLOSURE USING SPECMAN | Meirav Nitzan, Yael Kinderman, and Efrat Gavish | | | | | | | |
| A Smart Synchronizer – Pragmatic way to cross asynchronous clock domains | Priyank Parakh and Steven J Kommrusch | | | | | | | |
| A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic | Priya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed | | | | | | | |
| A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic | Priya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed | | | | | | | |
| A Statistical and Model-Driven Approach for Comprehensive Fault Propagation Analysis of RISC-V Variants | Endri Kaja, Nicolas Gerlin, Ungsang Yun, Jad Al Halabi, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker | | | | | | | |
| A Statistical and Model-Driven Approach for Comprehensive Fault Propagation Analysis of RISC-V Variants | Endri Kaja, Nicolas Gerlin, Ungsang Yun, Jad Al Halabi, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker | | | | | | | |
| A Step Towards Zero Silicon Bugs Using Assertion Based Assumption Validation | Rohit Kumar Sinha and Babu Christie | | | | | | | |
| A Step towards Zero Silicon Bugs: SVA Protocol Based Assumption Validation | Rohit Kumar Sinha and Babu Christie | | | | | | | |
| A streamlined approach to validate FP matrix multiplication with formal | Gerardo Nahum, Nicolae Tusinschi, Seiya Nakagawa | | | | | | | |
| A Structured Approach to verify Ties, Unconnected Signals and Parameters | Saurabh Singh, Peter Limmer, and Thomas Luedeke | | | | | | | |
| A Structured Approach to verify Ties, Unconnected Signals and Parameters | Saurabh Singh, Peter Limmer, and Thomas Luedeke | | | | | | | |
| A Study on Virtual Prototyping based Design Verification Methodology | Woojoo Kim, Kunhyuk Kang, Seonil Brian Choi | | | | | | | |
| A Study on Virtual Prototyping based Design Verification Methodology | Woojoo Kim, Kunhyuk Kang, and Seonil Brian Choi. | | | | | | | |
| A Survey of Machine Learning Applications in Functional Verification | Dan Yu, Harry Foster, Tom Fitzpatrick | | | | | | | |
| A Systematic Approach to Power State Table (PST) Debugging | Bhaskar Pal | | | | | | | |
| A Systematic Approach to Power State Table (PST) Debugging | Bhaskar Pal, Suman Nandan, Kaushik De, and Rajarshi Mukherjee | | | | | | | |
| A Systematic Formal Reuse Methodology: From Blocks to SoC Systems | Hao Chen, Yi Sun, Ang Li, and Dorry Cao | | | | | | | |
| A Systematic Methodology for Verifying Clock Domain Crossing Reconvergence | Priya Viswanathan | | | | | | | |
| A Systematic Take on Addressing Dynamic CDC Verification Challenges | Sukriti Bisht, Sulabh Kumar Khare, and Ashish Hari | | | | | | | |
| A Systematic Take on Addressing Dynamic CDC Verification Challenges | Sukriti Bisht, Sulabh Kumar Khare, and Ashish Hari | | | | | | | |
| A SystemC Library for Advanced TLM Verification | Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen | | | | | | | |
| A SystemC Library for Advanced Verification – Towards an Enhanced OVM/UVM for SystemC | Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen | | | | | | | |
| A SystemC-based UVM verification infrastructure | Mike Bartley and Harshavardhan Narla | | | | | | | |
| A SystemC-based UVM verification infrastructure | Mike Bartley and Harshavardhan Narla | | | | | | | |
| A SystemVerilog Framework for Easy Method Advice in Object-oriented Test Benches | Eric Ohana | | | | | | | |
| A SystemVerilog Framework for Easy Method Advice in Object-oriented Test Benches | Eric Ohana | | | | | | | |
| A SystemVerilog Framework for Efficient Randomization of Images with Complex Inter-Pixel Dependencies | Axel Voss, Gabriel Jönsson, and Lars Viklund | | | | | | | |
| A Tale of Two Languages – SystemVerilog and SystemC | David C Black | | | | | | | |
| A Tale of Two Languages: SystemVerilog & SystemC | David C Black | | | | | | | |
| A Tool for Investigating Cyber-Physical Systems via SystemC AMS Virtual Prototypes Derived from SysML Models | Daniela Genius; Ludovic Apvrille | | | | | | | |
| A Unified Framework for Multilanguage Verification IPs Integration | Surinder Sood, Selvakumar Krishnamoorthy, Guarav Jalan | | | | | | | |
| A Unified Testbench Architecture Solution for Verifying Variants of A PLL IP | Deepa Ananthanarayanan and Malathi Chikkanna | | | | | | | |
| A Unified Testbench Architecture Solution for Verifying Variants of the PLL IP | Deepa Ananthanarayanan and Malathi Chikkanna | | | | | | | |
| A Universal DFT Verification Environment: Filling the Gap between Function Simulation and ATE Test | Rui Huang | | | | | | | |
| A Universal DFT Verification Environment: Filling the Gap between Function Simulation and ATE Test | Rui Huang | | | | | | | |
| A UVM Based Methodology for Processor Verification | Abhineet Bhojak, Stephan Herrmann, and TejbalPrasad | | | | | | | |
| A UVM Based Methodology for Processor Verification | Abhineet Bhojak, Tejbal Prasad | | | | | | | |
| A UVM Multi-Agent Verification IP architecture to enable Next-Gen protocols with enhanced reusability, controllability and observability | Prathik R, Ramesh Madatha, Girish Gupta, Tony George | | | | | | | |
| A UVM Multi-Agent Verification IP architecture to enable Next-Gen protocols with enhanced reusability, controllability and observability | Prathik R, Ramesh Madatha, Girish Kumar Gupta, Tony Gladvin George | | | | | | | |
| A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers | Jaeha Kim | | | | | | | |
| A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers | Jaeha Kim | | | | | | | |
| A UVM SystemVerilog Testbench for 5G/LTE Multi-Standard RF Transceiver | Byeong Kyu Kim, Jaeha Kim | | | | | | | |
| A UVM SystemVerilog Testbench for 5G/LTE Multi-Standard RF Transceiver | ByeongKyu Kim, Jaeha Kim | | | | | | | |
| A UVM SystemVerilog Testbench for Analog/Mixed-Signal Verification: A Digitally-Programmable Analog Filter Example | Charles Dančak | | | | | | | |
| A UVM SystemVerilog Testbench for Directed & Random Testing of an AMS LDO Voltage Regulator | Charles Dančak | | | | | | | |
| A UVM SystemVerilog Testbench for Directed & Random Testing of an AMS LDO Voltage Regulator | Charles Dančak | | | | | | | |
| A UVM SystemVerilog Testbench for Directed and Random Testing of an AMS Low-Dropout Voltage Regulator | Charles Dančak | | | | | | | |
| A UVM Test-bench Skeleton Leveraging the Event Pool and Sequence Layering | Marcela Zachariasova, Jiri Bartak, Tomas Pehnelt & Jan Riha | | | | | | | |
| A UVM Testbench for Analog Verification: A Programmable Filter Example | Charles Dančak | | | | | | | |
| A UVM-based Approach for Rapidly Verifying Digital Interrupt Structures | Christoph Rumpler, Alexander W. Rath, Sebastian Simon, and Heinz Endres | | | | | | | |
| A UVM-based Approach for Rapidly Verifying Digital Interrupt Structures | Christoph Rumpler, Alexander W. Rath, and Sebastian Simon | | | | | | | |
| A Volterra-Series Model in SystemVerilog/XMODEL for Nonlinear RF Low-Noise Amplifiers | Chan Young Park, Jaeha Kim | | | | | | | |
| A Wholistic Approach to Optimizing Your System Verification Flow | Ross Dickson, Lance Tamura, Michael Young | | | | | | | |
| Absolute GLS Verification An Early Simulation of Design Timing Constraints | Ateet Mishra, Deepak Mahajan, Shiva Belwal | | | | | | | |
| Abstract Layer for Firmware Access: A Unique Approach for SOC Functional Verification | Gupta Girish Kumar, Rugmini Navia Vishnu, Choudhary Praval, Syed Mobeenuddin | | | | | | | |
| Accelerate Coverage Closure from Day-1 with AI-driven Verification | Malay Ganai, Will Chen, Srikanth Vadanaparthi | | | | | | | |
| Accelerate Functional Coverage Closure Using Machine-Learning-Based Test Selection | Jakub Pluciński, Łukasz Bielecki, Robert Synoczek, Emelie Andersson, Antii Löytynoja, Cristian Macario | | | | | | | |
| Accelerate Functional Coverage Closure Using Machine-Learning-Based Test Selection | Jakub Pluciński, Łukasz Bielecki, Robert Synoczek, Emelie Andersson, Antii Löytynoja & Cristian Macario | | | | | | | |
| Accelerated Coverage Closure by Utilizing Local Structure in the RTL Code | Rhys Buggy, Gokce Sarar, Guillaume Shippee, Han Nuou, Vishal Karna, Tushit Jain | | | | | | | |
| Accelerated simulation through design partition and HDL to C++ compilation | Theta Yang | | | | | | | |
| Accelerated simulation through design partition and HDL to C++ compilation | Theta Yang and Sga Sun | | | | | | | |
| Accelerated SOC verification Using UVM Methodology for a Mix-signal Low Power Design | Giuseppe Scata, Ashwini Padoor, Vladimir Milosevic | | | | | | | |
| Accelerated SOC Verification Using UVM Methodology for a Mixed-Signal Low Power Design | Giuseppe Scata, Ashwini Padoor, Vladimir Milosevic | | | | | | | |
| Accelerated Verification of NAND Flash Memory using HW Emulator | Seyeol Yang, Byungwoo Kang, Seoyeon Bae, Choi Jaehyeon, Jintae Kim, Dongeun Lee, Junho Ahn | | | | | | | |
| Accelerated Verification of NAND Flash Memory using HW Emulator | Seyeol Yang, Byungwoo Kang, Seoyeon Bae, Choi Jaehyeon, Jintae Kim, Dongeun Lee, Junho Ahn | | | | | | | |
| Accelerated, High Quality SoC Memory Map Verification using Formal Techniques | Cletan Sequeira, Rajesh Kedia, Lokesh Babu Pundreeka, and Bijitendra Mittra | | | | | | | |
| Accelerated, High Quality SoC Memory Map Verification using Formal Techniques | Cletan Sequeira, Rajesh Kedia, Lokesh Babu Pundreeka, and Bijitendra Mittra | | | | | | | |
| Accelerating and Improving FPGA Design Reviews Using Analysis Tools | Anna Tseng, Kurt Takara and Abdelouahab Ayari | | | | | | | |
| Accelerating and Improving FPGA Design Reviews Using Analysis Tools | Abdelouahab Ayari, Anna Tseng, and Kurt Takara | | | | | | | |
| Accelerating Automotive Ethernet validation by leveraging Synopsys Virtualizer with TraceCompass | Ashish Gandhi, Praveen Kumar Kondugari, and Sam Tennent | | | | | | | |
| Accelerating Automotive Ethernet validation by leveraging Synopsys Virtualizer with TraceCompass | Ashish Gandhi, Praveen Kumar Kondugari and Sam Tennent | | | | | | | |
| Accelerating CDC Verification Closure on Gate-Level Designs | Anwesha Choudhury and Ashish Hari | | | | | | | |
| Accelerating CDC Verification Closure on Gate-Level Designs | Anwesha Choudhury and Ashish Hari | | | | | | | |
| Accelerating Complex System Simulation using Parallel SystemC and FPGAs | Stanislaw Kaushanski, Johannes Wirth, Eyck Jentzsch, Andreas Koch | | | | | | | |
| Accelerating Complex System Simulation using Parallel SystemC and FPGAs | Stanislaw Kaushanski, Johannes Wirth, Eyck Jentzsch & Andreas Koch | | | | | | | |
| Accelerating Error Handling Verification of Complex Systems: A Formal Approach | Bhushan Parikh, Peter Graniello, and Neha Rajendra | | | | | | | |
| Accelerating Error Handling Verification Of Complex Systems: A Formal Approach | Bhushan Parikh, Peter Graniello, Neha Rajendra | | | | | | | |
| Accelerating Functional Verification Through Stabilization of Testbench Using AI/ML | Srikanth Vadanaparthi, Pooja Ganesh, Dharmesh Mahay, Malay Ganai | | | | | | | |
| Accelerating Functional Verification Coverage Data Manipulation Using Map Reduce | Eman El Mandouh, A. Gamal, A. Khaled, B. Amr G. Wassal, and Elsayed Hemayed | | | | | | | |
| Accelerating Functional Verification Coverage Data Manipulation Using Map Reduce | Eman El Mandouh, A. Gamal, A. Khaled, T. Ibrahim, Amr G. Wassal, Elsayed Hemayed | | | | | | | |
| Accelerating Functional Verification Through Stabilization of Testbench Using AI/ML | Srikanth Vadanaparthi, Pooja Ganesh, Dharmesh Mahay, Malay Ganai | | | | | | | |
| Accelerating ML TB Integration for Reusability Using UVM ML OA | Saleem Khan, Prasanna Kumar | 2017 | India | Presentation | | y2017 | india | presentation |
| Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing Products | Yoga Priya Vadivelu, Arpan Shah, Deepinder Singh Mohoora, Ullas, and Praveen Buddireddy | | | | | | | |
| Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing Products | Yoga Priya Vadivelu, Arpan Shah, Deepinder Singh Mohoora, Ullas, and Praveen Buddireddy | | | | | | | |
| Accelerating RTL Simulation Techniques | Lior Grinzaig | | | | | | | |
| Accelerating RTL Simulation Techniques | Lior Grinzaig | | | | | | | |
| Accelerating Semiconductor Time to ISO 26262 Compliance | Kirankumar Karanam | | | | | | | |
| Accelerating SoC Sensor Network Verification Sign-off through Dynamic and Formal Synergy | Vinod Usha, Shreeram Hegde, Prasad Reddy | | | | | | | |
| Accelerating SoC Sensor Network Verification Sign-off through Dynamic and Formal Synergy | Vinod Usha, Shreeram Hegde, Prasad Reddy | | | | | | | |
| Accelerating SoC Verification Signoff using Save & Restart/Dynamic Test Reload Enhanced Regression flow | Vanshlata B, Divya M, Garima S, Seonil Brian Choi | | | | | | | |
| Accelerating SOC Verification Using Process Automation and Integration | Seonghee Yim, Hanna Jang, Sunchang Choi, and Seonil Brian Choi | | | | | | | |
| Accelerating SOC Verification, Reducing Simulation Turnaround Time & Diskspace Optimization using Dynamic Test Reload (DTR) | Prashant Hota & Shekhar Jha | | | | | | | |
| Accelerating the IP Design Cycle with Formal Techniques Beyond Everyday FPV | Bhushan Parikh, Shaman Narayana, Buck Lem, David Cassetti | | | | | | | |
| Accelerating the SoC Integration Verification Cycle Time Leveraging the Legacy Design Confidence | Abhinav Parashar, Prasanth Kumar Narava | | | | | | | |
| Accelerating the SoC Integration Verification Cycle Time Leveraging the Legacy Design Confidence | Abhinav Parashar, Prasanth Kumar Narava | | | | | | | |
| Acceleration of Coreless SoC Design-Verification using PSS on Configurable Testbench in Multi-Link PCIe Subsystems | Thanu Ganapathy, Pravin Kumar, Garima Srivastava, Seonil Brian Choi, Harish Peta | | | | | | | |
| Acceleration of product and test environment development using SystemC-TLM | Florian Barrau, Alexandre Piccini, Alexandre Nabais Moreno, Mark Burton, Luc Michel, Clement Descha | | | | | | | |
| Acceleration of product and test environment using SystemC TLM | Florian Barrau, Alexandre Piccini, Alexandre Nabais Mark Burton, Luc Michel, and Clement Deschamps | | | | | | | |
| Acceleration Startup Design & Verification | Tim Sun, Barry Yin, and Haifeng Jiang | | | | | | | |
| Accellera FS WG Update | Alessandra Nardi, Ghani Kanawati | | | | | | | |
| Accellera Functional Safety Working Group Update and Next Steps | Alessandra Nardi | | | | | | | |
| Accellera Functional Safety Working Group Update and Next Steps | Alessandra Nardi, Ghani Kanawati | | | | | | | |
| Accellera PSS being adopted in real projects Tutorial | Accellera Systems Initiative | | | | | | | |
| Accellera Systems Initiative SystemC Standards Update | Bishnupriya Bhattacharya | | | | | | | |
| Accellera Systems InitiativeSystemC Standards Update | Martin Barnasconi, Philipp A. Hartmann, Trevor Wieman | | | | | | | |
| Accellera Systems InitiativeSystemC Standards Update | Martin Barnasconi, Philipp A. Hartmann, and Stephan Schulz | | | | | | | |
| Accellera Update | Lu Dai | | | | | | | |
| Accellera UVM-AMS Standard Update | Tom Fitzpatrick and Tim Pylant | | | | | | | |
| Accellera, Standards, and Semiconductor Supply Chain | Lu Dai | | | | | | | |
| Ace’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power Consumption | Mehul Kumar, Tushar Mattu, and Amir Nilipour | 2016 | United States | Paper | | y2016 | united-states | paper |
| ACE’ing the Verification of a Coherent System Using UVM | Romondy Luo, Ray Varghese, Parag Goel, Amit Sharma, Satyapriya Acharya, and Peer Mohammed | | | | | | | |
| ACE’ing the Verification of a Coherent System Using UVM | Parag Goel; Amit Sharma, Ray Varghese, Romondy Luo, Satyapriya Acharya, Peer Mohammed | | | | | | | |
| ACE’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power Consumption | Mehul Kumar, Shawn Honess, Amir Nilipour, and Tushar Mattu | | | | | | | |
| Achieve Complete SoC Memory Map Verification Through Efficient Combination of Formal and Simulation Techniques | Clemens Roettgermann, Peter Limmer, and Michael Rohleder | | | | | | | |
| Achieve Complete SoC Memory Map Verification through Efficient Combination of Formal and Simulation Techniques | Clemens Roettgermann, Peter Limmer, and Michael Rohleder | | | | | | | |
| Achieve Faster Debug Closure by Applying Big Data & Advanced RCA Technologies | Sundararajan Ananthakrishnan, Sundararajan PH | | | | | | | |
| Achieving End-to-End Formal Verification of Large Floating-Point Dot Product Accumulate Systolic Units | Emiliano Morini, Bill Zorn, Disha Puri, Madhurima Eranki, Shravya Jampana | | | | | | | |
| Achieving End-to-End Formal Verification of Large Floating-Point Dot Product Accumulate Systolic Designs | Emiliano Morini, Bill Zorn, Disha Puri, Madhurima Eranki, Shravya Jampana | | | | | | | |
| Achieving Faster Code Coverage Closure using High-Level Synthesis | Surendhar Thudukuchi Chandrapandiyan, Preetham Lakshmikanthan, Ashwani Aggarwal, Youngchan Lee, Youngsik Kim, Seonil Brian Choi | | | | | | | |
| Achieving Faster Reset Verification Closure with Intelligent Reset Domain Crossings Detection | Milanpreet Kaur and Sulabh Kumar Khare | | | | | | | |
| Achieving Faster Reset Verification Closure with Intelligent Reset Domain Crossings Detection | Milanpreet Kaur and Sulabh Kumar Khare | | | | | | | |
| Achieving First-Time Success with a UPF-based Low Power Verification Flow | Kjeld Svendsen, Chuck Seeley, and Erich Marschner | | | | | | | |
| Achieving Portable Stimulus with Graph-Based Verification – Tutorial | Josef Derner, Holger Horbach, Frederic Krampac, Staffan Berg | | | | | | | |
| Achieving Real Time Performance for Algorithms Using SOC TLM Model | Saurin Patel, Pushkar Sareen, Sharath Naidu, Baljinder S Sood | | | | | | | |
| Achieving system dependability: the role of automation and scalability | Alessandra Nardi | | | | | | | |
| Achieving system dependability: the role of automation and scalability | Teo Cupaiuolo, Paul Baron, Ghani Kanawati | | | | | | | |
| Activity Trend Guided Efficient Approach to Peak Power Estimation Using Emulation | Gaurav Saharawat, Saurabh Jain, and Madhur Bhatia | | | | | | | |
| Activity Trend Guided Efficient Approach to Peak Power Estimation Using Emulation | Gaurav Saharawat, Saurabh Jain, and Madhur Bhatia | | | | | | | |
| Adapting the UVM Register Abstraction Layer for Burst Access | Mark Villalpando | | | | | | | |
| Adapting the UVM Register Layer for Burst Access | M. P. Villalpando | | | | | | | |
| Adaptive Test Generation for Fast Functional Coverage Closure | Azade Nazi, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhoseini, Richard Ho | | | | | | | |
| Adaptive Test Generation for Fast Functional Coverage Closure | Azade Naziz, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhosseiniz, and Richard Ho | | | | | | | |
| Adaptive UVM AMOD Testbench for Configurable DSI IP | Krishnapal Singh, Pavan Yeluri, Ranjith Nair | | | | | | | |
| Adding Agility to Hardware Design-Verification using UVM & Assertions | Francois Cerisier, Ajeetha Kumari, Gurubasappa, Srujana Reddy | | | | | | | |
| Addressing Asynchronous FIFO Verification Challenge | Anchal Gupta, Ashish Hari, Sulabh Kumar Khare | | | | | | | |
| Addressing Asynchronous FIFO Verification Challenge | Anchal Gupta, Ashish Hari and Sulabh Kumar Khare | | | | | | | |
| Addressing Challenges in Verification of DSP based Audio IPs using a Novel Hybrid-TestBench Architecture | Suvadeep Bose, Kanak Singh Rajput, Parag S Lonkar, Somasunder K Sreenath | | | | | | | |
| Addressing HW/SW Interface Quality through Standards | David Murray and Sean Boyan | | | | | | | |
| Addressing Renewed Gate Level Simulation Needs for 10nm-28nm and Below | Gagandeep Singh | | | | | | | |
| Addressing Shared IP Instances in a Multi-CPU System Using Fabric Switch A Comprehensive Solution | Priyanka Gharat, Avnita Pal, Sastry Puranapanda | | | | | | | |
| Addressing Shared IP Instances in a MultiCPU System Using Fabric Switch | Priyanka Gharat, Avnita Pal, Sastry Puranapanda | | | | | | | |
| Addressing the Challenges of ABV in Complex SOCs | Rithin A N, Arif M, Rupinjeet Singh, Jeevan | | | | | | | |
| Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail Macros | Brandon Skaggs | | | | | | | |
| Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail Macros | Brandon S. Skaggs | | | | | | | |
| Addressing the Challenges of Reset Verification in SoC Designs | Chris Kwok, Priya Viswanathan, and Ping Yeung | | | | | | | |
| Addressing the Challenges of Reset Verification in SoC Designs | Chris Kwok, Priya Viswanathan, and Ping Yeung | | | | | | | |
| Addressing the Complex Challenges in Low-Power Design and Verification | Madhur Bhargava, Durgesh Prasad, Jitesh Bansal, and Gabriel Chidolue | | | | | | | |
| Addressing the Complex Challenges in Low-Power Design and Verification | Madhur Bhargava, Durgesh Prasad, and Jitesh Bansal | | | | | | | |
| Addressing the verification challenge of SERDES-based FPGAs: The performance/accuracy/efficiency trade-off | Chris Schalick | | | | | | | |
| Adopting Accellera’s Portable Stimulus Standard: Early Development and Validation using Virtual Prototyping | Simranjit Singh, Ashwani Aggarwal, Harshita Prabha, Vishnu Ramadas, Seonil Brian Choi, Woojoo Space Kim | | | | | | | |
| Adopting UVM for FPGA Verification | Kamalesh Vikramasimhan, Shridevi Biradar | | | | | | | |
| Adopting UVM for safety Verification requirements | Srinivasan Venkatarmanan, Hemakiran Kolli, Gurubasappa Kinagi, and Satinder Paul Singh | | | | | | | |
| Adopting UVM for safety Verification requirements | Srinivasan Venkatarmanan, Hema Kiran, and Satinder Paul Singh | | | | | | | |
| Advance Approach for Formal Verification of Configurable Pulse Width Modulation Controller | Sumit K. Kulshreshtha, Raghavendra J N | | | | | | | |
| Advance your Design and Verification Flow Using IP XACT | Edwin Dankert, Maximilian Albrecht and Vincent Thibaut | | | | | | | |
| Advanced Digital-Centric Mixed-Signal Methodology | Michael Kontz, David Lacey, and Peter Maroni | | | | | | | |
| Advanced Digital-Centric Mixed-Signal Methodology | Michael Kontz, David Lacey, and Peter Maroni | | | | | | | |
| Advanced Functional Verification for Automotive System on a Chip | Jaein Hong, Jieun Jeong , Namyoung Kim, Hongkyu Kim, Sungcheol Park, | | | | | | | |
| Advanced Functional Verification for Automotive System on a Chip | Jaein Hong, Jieun Jeong, Namyoung Kim, Hongkyu Kim, and Sungcheol Park | | | | | | | |
| Advanced Functional Verification Methodology Using UVM For Complex DSP Algorithms In Mixed Signal RF SoCs | Srinivas Aluri and Jaimin Mehta | | | | | | | |
| Advanced Functional Verification Methodology Using UVM for complex DSP Algorithms in Mixed Signal RF SoCs | Srinivas Aluri and Jaimin Mehta | | | | | | | |
| Advanced RISC-V Verification Technique Learnings for SoC Validation | David Kelf, Nambi Ju | | | | | | | |
| Advanced RISC-V Verification Technique Learnings for SoC Validation | David Kelf, Nambi Ju | | | | | | | |
| Advanced SOC Randomization Tool for Complex SOC Level Verification | Marvin Mei, Chris Weller, Michael Sedmak, and Zhiqiang Ren | | | | | | | |
| Advanced specification driven methodology for quick and accurate RDC signoff | Sai Jagadeesh Ambati, Sulabh Kumar Khare, Atul Sharma | | | | | | | |
| Advanced Techniques for ARM L2 Cache Verification in an Accelerated Hardware and Software environment | Rob Pelt and Jay O’Donnell | | | | | | | |
| Advanced Techniques for AXI Fabric Verification in a Software/Hardware OVM Environment | Galen Blake and Steve Chappell | | | | | | | |
| Advanced Techniques to Accomplish Power Aware CDC Verification | Rohit K Sinha, Ashish Hari and Sulabh Kumar Khare | | | | | | | |
| Advanced Testbench Configuration with Resources | Mark Glasser | | | | | | | |
| Advanced UCIe-based Chiplets verification from IP to SoC | Anunay Bajaj, Moshik Rubin | | | | | | | |
| Advanced Usage Models for Continuous Integration in Verification Environments | John Dickol | | | | | | | |
| Advanced Usage Models for Continuous Integration in Verification Environments | John Dickol | | | | | | | |
| Advanced UVM Based Chip Verification Methodologies with Full Analog Functionality | Simul Barua, FNU Farshad, Henry Chang | | | | | | | |
| Advanced UVM Based Chip Verification Methodologies with Full Analog Functionality | Simul Barua, FNU Farshad, Henry Chang | | | | | | | |
| Advanced UVM Coding Techniques | David Long | | | | | | | |
| Advanced UVM Command Line Processor | Siddharth Krishna Kumar | | | | | | | |
| Advanced UVM Command Line Processor for Central Maintenance and Randomization of Control Knobs | Siddharth Krishna Kumar | | | | | | | |
| Advanced UVM in the real world ‐ Tutorial | Mark Litterick, Jason Sprott, Jonathan Bromley, and Vanessa Cooper | | | | | | | |
| Advanced UVM Register Modeling | Mark Litterick and Marcus Harnisch | | | | | | | |
| Advanced UVM Register Modeling | Mark Litterick | | | | | | | |
| Advanced UVM Tutorial Taking Reuse to the Next Level | Mark Litterick, Jason Sprott, and Jonathan Bromley | | | | | | | |
| Advanced UVM, Multi-Interface, Reactive Stimulus Techniques | Clifford E. Cummings, Stephen DOnofrio, Jeff Wilcox, Heath Chambers | | | | | | | |
| Advanced, High Throughput Debug From Design to Silicon | Gordon Allan & Michael Horn | | | | | | | |
| Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IP | Eldhose P.M, Sagar Jayakrishnan, Suraj Vijay Shetty, Kuntal Pandya, Parag S. Lonkar | | | | | | | |
| Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IP | Eldhose P.M, Sagar Jayakrishnan, Suraj Vijay Shetty, Kuntal Pandya, Parag S. Lonkar | | | | | | | |
| Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification Cycle | Charul Agrawal, Ashwin Vijayan, and Jakub Dudek | | | | | | | |
| Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification Cycle | Charul Agrawal, Ashwin Vijayan, and Jakub Dudek | | | | | | | |
| Advancing system-level verification using UVM in SystemC | Martin Barnasconi, François Pêcheux, and Thilo Vörtler | | | | | | | |
| Advancing system-level verification using UVM in SystemC | Martin Barnasconi, François Pêcheux, and Thilo Vörtler | | | | | | | |
| Advancing the SystemC Ecosystem | Philipp A Hartmann, Jerome Cornet, Martin Scnierginger, and Frederic Doucet | | | | | | | |
| Advancing traceability and consistency in Verification and Validation | Walter Tibboel and Martin Barnasconi | | | | | | | |
| Advancing traceability and consistency in Verification and Validation | Walter Tibboel and Martin Barnasconi | | | | | | | |
| Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC. | Nipun Bhatt | | | | | | | |
| Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC. | Nipun Bhatt | | | | | | | |
| Agile and dynamic functional coverage using SQL on the cloud | Filip Dojcinovic and Mihailo Ivanovic | | | | | | | |
| Agile and dynamic functional coverage using SQL on the cloud | Filip Dojcinovic and Mihailo Ivanovic | 2019 | Europe | Presentation | | y2019 | europe | presentation |
| Agile Approaches to ASIC Verification (A3V) – A Novel Agile Flow in Functional Verification | Adithya Rangan, Vidyasagar Kantamneni, Vishal Dalal | | | | | | | |
| Agile Approaches to ASIC Verification (A3V) – A Novel Agile Flow in Functional Verification | Adithya Rangan CK, Vidyasagar Kantamneni, Vishal Dalal | | | | | | | |
| Agnostic UVM-XX Testbench Generation | Jacob Andersen, Stephan Gerth, and Filippo Dughetti | | | | | | | |
| Agnostic UVM-XX Testbench Generation Replace XX (almost) as you see fit! | Jacob Andersen, Stephan Gerth, and Filippo Dughetti | | | | | | | |
| AI based Media Functional Safety and Reliability verification in Safety-Critical Autonomous Systems | Suresh Vasu, Palanivel Guruvareddiar | | | | | | | |
| AI based Media Functional Safety and Reliability Verification in Safety-Critical Autonomous Systems | Suresh Vasu, Palanivel Guruvareddiar | | | | | | | |
| AI Driven Verification | Curtis Tsai | | | | | | | |
| AI-based Algorithms to Analyze and Optimize Performance Verification Efforts | Saksham Mehra, Raghu Alamuri, Sharada Vajja | | | | | | | |
| Algorithm Verification with Open Source and System Verilog | Andra Socianu and Daniel Ciupitu | | | | | | | |
| All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification | Aman Kumar, Deepak Narayan Gadde Thomas Nalapat, Evgenii Rezunov, Fabio Cappellini | | | | | | | |
| All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification | Deepak Narayan Gadde, Aman Kumar, Thomas Nalapat, Evgenii Rezunov, Fabio Cappellini | | | | | | | |
| AMS Verification at SoC Level: A Practical Approach for Using VAMS vs SPICE Views | Nitin Pant, Gautham Harinarayan, Manmohan Rana | | | | | | | |
| AMS Verification in a UVM Environment | Silvia Strähle | | | | | | | |
| AMS Verification in a UVM Environment | Silvia Strähle | | | | | | | |
| An Accelerated System Level CPU Verification through Simulation-Emulation Co-Existence | Ruchi Misra, Samridh Deva, Sai Krishna Pallekonda, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi | | | | | | | |
| An Accelerated System Level CPU Verification through Simulation-Emulation Co-Existence | Ruchi Misra, Samridh Deva, P Sai Krishna, Alok Kumar, Garima Srivastava YoungSik Kim, Seonil Brian Choi | | | | | | | |
| An Analysis of Stimulus Techniques for Efficient Functional Coverage Closure | Caglayan Yalein, Aileen McCabe | | | | | | | |
| An Analytical View of Test Results Using CityScapes | Markus Borg, Andreas Brytting, and Daniel Hansson | | | | | | | |
| An Analytical View of Test Results Using CityScapes | Markus Borg, Andreas Brytting, and Daniel Hansson | | | | | | | |
| An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 Experience | Mahesha Shankarathota, Vybhava S, and Indrajit Dutta | | | | | | | |
| An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 Experience | Mahesha Shankarathota, Vybhava S, and Indrajit Dutta | | | | | | | |
| An Assertion Based Approach to Implement VHDL Functional Coverage | Michael Wazlowski, Susan Eickhoff, Michael Debole, and Tagbo Ekwueme-Okoli | | | | | | | |
| An Assertion Based Approach to Implement VHDL Functional Coverage | Susan Eickhoff, Michael DeBole, and Tagbo Ekwueme-Okoli | | | | | | | |
| An Automated Formal Verification Flow for Safety Registers | Holger Busch | | | | | | | |
| An Automated Formal Verification Flow for Safety Registers | Holger Busch | | | | | | | |
| An Automated Pre-silicon IP Trustworthiness Assessment for Hardware Assurance | John Hallman, David Landoll, Sergio Marchese, Sven Beyer, Garrett Chan, Salam Zantout and Vikram Rao | | | | | | | |
| An Automated Pre-silicon IP Trustworthiness Assessment for Hardware Assurance | J. Hallman, D. Landoll, S. Marchese, S. Beyer, G. Chan, S. Zantout, and V. Rao | | | | | | | |
| An Automated Systematic CDC Verification Methodology based on SDC Setup | Ashish Hari, Sulabh Kumar Khare | | | | | | | |
| An Automated Validation Framework for Power Management and Data Retention Logic Kits of Standard Cell Library | Akshay Kamath, Bharath Kumar, Sunil Aggarwal, Subramanian Parameswaran, Parag Lonkar, Debi Prasanna, Somasunder Sreenath | | | | | | | |
| An Automatic Visual System Performance Stress Test for TLM Designs | George F. Frazier, Neeti Bhatnagar, and Woody Larue | | | | | | | |
| An Easy VE/DUV Integration Approach | Uwe Simm | | | | | | | |
| An Easy VE/DUV Integration Approach | Uwe Simm | | | | | | | |
| An Easy VE/DUV Integration Approach | Uwe Simm | | | | | | | |
| An Effective Design and Verification Methodology for Digital PLL | Biju Viswanathan, Rajagopal P.C, Ramya Nair S. R, Joseph J Vettickatt, and Jobin Cyriac | | | | | | | |
| An Effective Design and Verification Methodology for Digital PLL | Biju Viswanathan, Rajagopal P.C, Ramya Nair S. R, Joseph J Vettickatt, and Jobin Cyriac | | | | | | | |
| An efficient analog fault-injection flow harnessing the power of abstraction | Renaud Gillon, Enrico Fraccaroliy, and Franco Fummi | | | | | | | |
| An Efficient and Modular Approach for Formally Verifying Cache Implementations | M, Achutha KiranKumar V and Abhijith A Bharadwaj | | | | | | | |
| An Efficient and Modular Approach for Formally Verifying Cache implementations | M Achutha KiranKumar V, Abhijith A Bharadwaj, and Bindumadhava S S | | | | | | | |
| An Efficient Method to Verify Dynamic IP Clock Frequency on SOC Level by Using Auto-generated Active Clock Monitor | Jaecheon Kim, Gyuhong Lee, Yeonho Jeong, Hyunsun Ahn, Daewoo Kim, Seonil Brian Choi | | | | | | | |
| An Efficient Methodology for Mutation-Coverage-Collection of Formal-Property-Checking | Holger Busch | | | | | | | |
| An Efficient Methodology for Mutation-Coverage-Collection of Formal-Property-Checking | Holger Busch | | | | | | | |
| An efficient requirements-driven and scenario-driven verification flow | Heino van Orsouw | | | | | | | |
| An efficient requirements-driven and scenario-driven verification flow | Walter Tibboel, Heino van Orsouw, and Shuang Han | | | | | | | |
| An Efficient Verification Framework for Audio/Video Interface Protocols | Noha Shaarawy, Mustafa Khairallah, Khaled Khalifa, Hany Salah, Amr Salah and Maged Ghoneima | | | | | | | |
| An Efficient Verification Methodology to Achieve DV Sign-off with Emphasis on Quality and Quicker DV Cycle | Piyush Agnihotri, Nirmal Kumar, Arnab Ghosh, Parag S Lonkar | | | | | | | |
| An Efficient Verification Methodology to Achieve DV Sign-off with Emphasis on Quality and Quicker DV Cycle | Piyush Agnihotri, Nirmal Kumar, Arnab Ghosh, Parag S Lonkar | | | | | | | |
| An Elegant scoreboard eco-system deploying UVM Callbacks, Parameterization for Multimedia designs from Imaging perspective | Chakravarthi Devakinanda Vurukutla, Sahana Ranganathan, Devendra Satish Bilaye, Vivek Kumar & Karthik Majeti | | | | | | | |
| An Elegant scoreboard eco-system deploying UVM Callbacks, Parameterization for Multimedia designs from Imaging perspective | Chakravarthi Devakinanda, Sahana Ranganathan, Devendra Satish Bilaye, Vivek Kumar & Karthik Majeti | | | | | | | |
| An end-to-end approach to Design and Verify Battery Management Systems: from Requirements to Virtual Field Testing | Irina Costachescu, Marius-Lucian Andrei, Manuel Fedou, Conrado Ramirez Garcia, | | | | | | | |
| An end-to-end approach to Design and Verify BMS: from Requirements to Virtual Field Testing | Conrado Ramirez, Irina Costachescu, Marius Andrei, Carlos Villegas | | | | | | | |
| An Enhanced DV Approach for Effectively Verifying High Speed, Low Power MIPI-MPHY 5.0 Designs | Eldhose PM, Kuntal Pandya, Sagar Jayakrishanan, Suraj Vijay Shetty, Parag S Lonkar | | | | | | | |
| An Enhanced DV Approach for Effectively Verifying High Speed, Low Power MIPI-MPHY5.0 Designs | Eldhose P.M, Sagar Jayakrishnan, Suraj Vijay Shetty, Kuntal Pandya, Parag S. Lonkar | | | | | | | |
| An Enhanced Stimulus and Checking Mechanism on Cache Verification | Chenghuan Li, Xiaohui Zhao, and Yunyang Song | | | | | | | |
| An Equivalent Modeling Approach for High-Density DRAM Array System-Level Design-Space Exploration in SystemVerilog | Seyoung Kim, Jaeha Kim | | | | | | | |
| An Experience of Complex Design Validation: How to Make Semiformal Verification Work | Sabih Agbaria, Dan Carmi, Orly Cohen, Dmitry Korchemny, Michael Lifshits, and Alexander Nadel | | | | | | | |
| An experience to finish code refinement earlier at behavioral level | Dae-Han Youn, Sik Kim, Byeong Min, and Kyu-Myung Choi | | | | | | | |
| An Expert System Based Tool for Pre-design Chip Power Estimation | Bhanu Singh, Arunprasath Shankar, Francis Wolff, and Christos Papachristou | | | | | | | |
| An Expert System Based Tool for Pre-design Chip Power Estimation | Bhanu Singh, Arunprasath Shankar, Francis Wolff, and Christos Papachristou | | | | | | | |
| An Improved Methodology for Debugging UPF Issues at SoC level Power Aware Simulations | Ruchi Misra, S Shrinidhi Rao, Alok Kumar, Garima Srivastava & Sarang Kalbande | | | | | | | |
| An Industry Proven UVM Reuse Methodology for Coverage Driven Block Level Verification to SW Driven Chip Level Verification Across Simulation & Emulation | Pradeep Salla, Keshav Joshi | | | | | | | |
| An Innovative Methodology for RTL and Verification IP Sharing Between Two Projects | Albert Xu and Joonyoung Kim | | | | | | | |
| An Innovative Methodology for RTL and Verification IP Sharing Between Two Projects | Albert Xu and Joonyoung Kim | | | | | | | |
| An Innovative Methodology for Verifying Mixed-Signal Components | Fabian Delguste and Graeme Nunn | | | | | | | |
| An Integrated Framework for Power Aware Verification | Harsh Chilwal, Manish Jain, and Bhaskar Pal | | | | | | | |
| An Introduction to the Accellera Portable Stimulus Standard | Srivatsa Vasudevan, Pradeep Salla, Sharon Rosenberg, Adnan Hamid, Karthick Gururaj, Srivatsa Vasudevan, Bishnupriya Bhattacharya | | | | | | | |
| An Introduction to using Event-B for Cyber-Physical System Specification and Design | John Colley and Michael Butler | | | | | | | |
| An Open and Fast Virtual Platform for TriCore™-based SoCs Using QEMU | Bastian Koppelmann, Bernd Messidat, Markus Becker, and Christoph Kuznik | | | | | | | |
| An Open and Fast Virtual Platform for TriCore™-based SoCs Using QEMU | Bastian Koppelmann | | | | | | | |
| An open and flexible SystemC to VHDL workflow for rapid prototyping | Bastian Farkas, Syed Abbas Ali Shah, Jan Wagner, Rolf Meyer, Rainer Buchty, and Mladen Berekovic | | | | | | | |
| An open and flexible SystemC to VHDL workflow for rapid prototyping | Bastian Farkas | | | | | | | |
| An Overview of Ethernet 10Base-T1S in Automotive SoC and its Verification | Bipul Halder, Jagtar Singh, Sahana S, Pushpal Nautiyal, Gaurav Chugh | | | | | | | |
| An Overview of Security Annotation for Electronic Design Integration (SA-EDI) Standard | Sohrab Aftabjahani | | | | | | | |
| Analog Modelling to Suit Emulation for Hardware-Software Co-Verification | Saranya Das | | | | | | | |
| Analog Modelling to Suit Emulation for Hardware-Software Co-Verification | Saranya Das | | | | | | | |
| Analog Transaction Level Modeling for Verification of Mixed-Signal-Blocks | Alexander W. Rath, Volkan Esen, and Wolfgang Ecker | | | | | | | |
| Analog Transaction Level Modeling for Verification of Mixed-Signal-Blocks | Alexander W. Rath | | | | | | | |
| Analysis of TLM-2.0 and it’s Applicability to Non Memory Mapped Interfaces | Guillaume Delbergue, Mark Burton, and Bertrand Le Gal and Christophe Jego | | | | | | | |
| Analysis of TLM-2.0 and it’s Applicability to Non Memory Mapped Interfaces | Delbergue Guillaume | | | | | | | |
| Apples versus Apples HVL Comparison Finally Arrives Comparing OVM SystemVerilog to OVM e | Brett Lammers and Riccardo Oddone | | | | | | | |
| Application Abstraction Layer: The Carpool Lane on the SoC Verification Freeway | Abhisek Verma, Varun S, and Subramanian Kuppusamy | | | | | | | |
| Application Abstraction Layer: The Carpool Lane on the SoC Verification Freeway | Abhisek Verma, Varun S, and Subramanian Kuppusamy | | | | | | | |
| Application of SystemC/SystemC-AMS in 3G Virtual Prototyping | Tao Huang and Stefan Heinen | | | | | | | |
| Application Optimized HW/SW Design & Verification of a Machine Learning SoC | Lauro Rizzatti, Russell Klein, Stephen Bailey, and Andrew Meier | | | | | | | |
| Applying Big Data to Next-Generation Coverage Analysis and Closure | Tom Fitzpatrick, Darron May, Thom Ellis, Athira Panicker and Francisco Chen | | | | | | | |
| Applying Design Patterns to accelerate development of reusable, configurable and portable UVCs. | | | | | | | | |
| Applying Design Patterns to Maximize Verification Reuse at Block, Subsystem and System on Chip Level | Paul Kaunds, Revati Bothe and Jesvin Johnson | | | | | | | |
| Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical Properties | K. Selyunin, T. Nguyen, A.D. Basa, E. Bartocci, D. Nickovic, and R. Grosu | | | | | | | |
| Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical Properties | Konstantin Selyunin, Thang Nguyen, Andrei-Daniel Basa, Ezio Bartocci, Dejan Nickovic, and Radu Grosu | | | | | | | |
| Applying Test-Driven Development Methods to Design Verification Software | Doug Gibson and Mike Kontz | | | | | | | |
| Applying Test-Driven Development Methods to Design Verification Software in UVM-e | Doug Gibson and Mike Kontz | | | | | | | |
| Applying Transaction-level Debug and Analysis Techniques to DUT Simulated Activity Using Data- Mining Techniques | Leo Chai, Bindesh Patel, and Jun Zhao | | | | | | | |
| Applying Transaction-level Debug and Analysis Techniques to DUT Simulated Activity Using Data-Mining Techniques | Leo Chai, Jun Zhao, and Bindesh Patel | | | | | | | |
| ARC EM Core with Safety Package – ISO 26262 Certification | Vikas Bhandari | | | | | | | |
| Architecting “Checker IP” for AMBA protocols | Srinivasan Venkataramanan and Ajeetha Kumari | | | | | | | |
| Architecting “Checker IP” for AMBA protocols | Ajeetha Kumari and Srinivasan Venkataramanan | | | | | | | |
| Architectural Evaluation Of a Programmable Accelerator For Baseband, Phy and Video Applications Using High Level Synthesis | Andy Fox, Tigran Sargsyan, and Steven Anderson | | | | | | | |
| Architectural Evaluation of a Programmable Accelerator for Baseband, Phy and Video Applications using High Level Synthesis | Andy Fox, Tigran Sargsyan, and Steven Anderson | | | | | | | |
| Architectural Formal Verification of System-Level Deadlocks | Mandar Munishwar and Vigyan Singhal | | | | | | | |
| Architectural Formal Verification of System-Level Deadlocks | Mandar Munishwar1, Naveed Zaman, Anshul Jain, HarGovind Singh, and Vigyan Singhal | | | | | | | |
| Architecturally Scalable Testbench for Complex SoC | Senthilnath Subbarayan, Arulanandan Jacob, Sandeep Kumar | | | | | | | |
| Architectures to tradeoff performance vs debug for software development on emulation platforms | Loganath Ramachandran, Ragavendar Swamisai, Makato Ikeda | | | | | | | |
| Architectures to Tradeoff Performance vs. Debug for Software Development on Emulation Platform | Loganath Ramachandran, Ragavendar Swamisai, Makato Ikeda | | | | | | | |
| Are My Fault Campaigns Providing Accurate Results for ISO 26262 Certification? | Hyunsun Ahn, James Kim, Arun Gogineni, Ann Keffer, MyungKyoon Yim, Soobon Kim, Youngsik Kim, Seonil Brian Choi | | | | | | | |
| Are OVM & UVM Macros Evil? A Cost-Benefit Analysis | Adam Erickson | | | | | | | |
| Are you really confident that you are getting the very best from your verification resources? | Darron May and Fritz Ferstl | | | | | | | |
| Are you really confident that you are getting the very best from your verification resources? | Darron May and Fritz Ferstl | | | | | | | |
| Are You Safe Yet? Safety Mechanism Insertion and Validation | Ping Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen | | | | | | | |
| Are You Safe Yet? Safety Mechanism Insertion and Validation | Ping Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen | | | | | | | |
| Are You Smarter Than Your Testbench? With a little work you can be. | Rich Edelman and Raghu Ardeishar | | | | | | | |
| Are You Smarter Than Your Testbench? With a little work you could be | Rich Edelman and Raghu Ardeishar | | | | | | | |
| Arithmetic Overflow Verification using Formal LINT | Kaiwen Chin, Esra Sahin Basaran, Kranthi Pamarthi | | | | | | | |
| Arithmetic Overflow Verification using Formal LINT | Kaiwen Chin, Esra Sahin Basaran, Kranthi Pamarthi | | | | | | | |
| ASIC-Strength Verification in a Fast-Moving FPGA World | Bryan Murdock | | | | | | | |
| ASIC-Strength Verification in a Fast-Moving FPGA World | Bryan Murdock | | | | | | | |
| ASIL B/D Fault Campaign Strategy for Computer Vision core using Soft Test Library (STL) | Shiva Pokala, Vasista A | | | | | | | |
| Assertion Based Self-checking of Analog Circuits for Circuit Verification and Model Validation in SPICE and Co-simulation Environments | Lakshmanan Balasubramanian, Pooja Sundar, and Timothy W Fischer | | | | | | | |
| Assertion-based Verification for Analog and Mixed Signal Designs | Srinivas Aluri | | | | | | | |
| Assertion-based Verification for Analog andMixed Signal Designs | Srinivas Aluri | | | | | | | |
| Assisting Fault Injection Simulations for Functional Safety Sign-off using Formal | Pulicharla Ravindrareddy | | | | | | | |
| Assisting Fault Injection Simulations for Functional Safety Sign-off using Formal | Pulicharla Ravindrareddy | | | | | | | |
| Asynchronous Behaviors Meet Their Match with SystemVerilog Assertions | Doug Smith | | | | | | | |
| Attack Your SoCPowerChallenges with Virtual Prototyping | Stefan Thiel and Gunnar Braun | | | | | | | |
| Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor Core | Wei Foong Thoo and David A. Burgoon | | | | | | | |
| Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor Core | Wei Foong Thoo and David A. Burgoon | | | | | | | |
| Automate and Accelerate RISC-V Verification by Compositional Formal Methods | Yean-Ru Chen, Cheng-Ting Kao, Yi-Chun Kao, Tien-Yin Cheng, Chun-Sheng Ke and Chia-Hao Hsu | | | | | | | |
| Automate and Accelerate RISC-V Verification by Compositional Formal Methods | Yean-Ru Chen, Cheng-Ting Kao, Yi-Chun Kao, Tien-Yin Cheng, Chun-Sheng Ke and Chia-HaoHsu | | | | | | | |
| Automate Interrupt Checking with UVM Macros and Python | Aleksandra Dimanic, Nemanja Stevanovic, Yoav Furman, Itay Henigsberg | | | | | | | |
| Automate Interrupt Checking with UVM Macros and Python | Aleksandra Dimanic, Nemanja Stevanovic, Yoav Furman, Itay Henigsberg | | | | | | | |
| Automated approach to Register Design and Verification of complex SOC | Ballori Banerjee, Subashini Rajan, and Silpa Naidu | | | | | | | |
| Automated code generation for Early AURIX TM VP | Pratheek Mahesh and Dineshkumar Selvaraj | | | | | | | |
| Automated code generation for Early AURIX TM VP | Pratheek Mahesh and Dineshkumar Selvaraj | | | | | | | |
| Automated Comparison of Analog Behavior in a UVM Environment | Sebastian Simon, Alexander W. Rath, Volkan Esen, and Wolfgang Ecker | | | | | | | |
| Automated Comparison of Analog Behavior in a UVM Environment | Sebastian Simon | | | | | | | |
| Automated Configuration of System Level C-Based CPU Testbench in Modern SoCs : A Novel Framework | Ruchi Misra, Chetan Kulkarni, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi | | | | | | | |
| Automated Configuration of System Level C-Based CPU Testbench in Modern SoCs : A Novel Framework | Ruchi Misra, Chetan Kulkarni, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi | | | | | | | |
| Automated Configuration of Verification Environments using Specman Macros DVcon Europe 2018 – Paper number 260-OH22 | Milos Mirosavljevic, Ron Sela, Dejan Janjic and Efrat Shneydor | | | | | | | |
| Automated Configuration of Verification Environments using SpecmanMacros | Milos Mirosavljevic, Ron Sela, Dejan Janjic and Efrat Shneydor | | | | | | | |
| Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal Verification | Samantha Pandez, Christopher Geen | | | | | | | |
| Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal Verification | Samantha Pandez Christopher Geen | | | | | | | |
| Automated correct-by-construct methodology for RTL design and analog mixed-signal test bench generation: Enables early design closure of mixed-signal SoC | Lakshmanan Balasubramanian, Murugesh Prashanth Subramaniam, Atul Ramakant Lele, and Ranjit Kumar Dash | | | | | | | |
| Automated Creation of Reusable Generators for Analog IC Design with the Intelligent IP Method | Uwe Eichler, Benjamin Prautsch, Torsten Reich | | | | | | | |
| Automated Creation of Reusable Generators for Analog IC Design with the Intelligent IP Method | Uwe Eichler, Benjamin Prautsch, Torsten Reich | | | | | | | |
| Automated Floating Trash Collecting Boat | Karamalaputti Rahul, Gandham Magaraju | | | | | | | |
| Automated Formal Verification of a Highly-Configurable Register Generator | Shuhang Zhang, Bryan Olmos, Basavaraj Naik | | | | | | | |
| Automated Formal Verification of a Highly-Configurable Register Generator | Shuhang Zhang, Bryan Olmos, Basavaraj Naik Infineon Technologies AG | | | | | | | |
| Automated Generation of Interval Properties From Trace-Based Function Models | Robert Kunzelmann, Aishwarya Sridhar, Daniel Gerl, Lakshmi Vidhath Boga, Wolfgang Ecker | | | | | | | |
| Automated Generation of Interval Properties From Trace-Based Function Models | Robert Kunzelmann, Aishwarya Sridhar, Daniel Gerl, Lakshmi Vidhath Boga, Wolfgang Ecker | | | | | | | |
| Automated Generation of RAL-based UVM Sequences | Satyajit Sinari, Timothy McLean, Benjamin Applequist, Vijayakrishnan Rousseau, and Geddy Lallathin | | | | | | | |
| Automated Generation of RAL-based UVM Sequences | Vijayakrishnan Rousseau, Satyajit Sinari, Benjamin Applequist, Timothy McLean, and Geddy Lallathin | | | | | | | |
| Automated Modeling Testbench Methodology Tested with four Types of PLL Models | Jun Yan, Josh Baylor | | | | | | | |
| Automated Modeling Testbench Methodology Tested with four Types of PLL Models | Automated Modeling Testbench Methodology Tested with four Types of PLL Models | | | | | | | |
| Automated Performance Verification to Maximize your ARMv8 pulling power | Nick Heaton and Simon Rance | | | | | | | |
| Automated Performance Verification to Maximize your ARMv8 pulling power | Nick Heaton and Simon Rance | | | | | | | |
| Automated Physical Hierarchy Generation: Tools and Methodology | Ali El-Zein, Alvan Ng, Benedikt Geukes, Maya H. Safieddine, and Wolfgang Roesner | | | | | | | |
| Automated Physical Hierarchy Generation: Tools and Methodology | Ali El-Zein, Alvan Ng, Benedikt Geukes, Maya H. Safieddine, and Wolfgang Roesner | | | | | | | |
| Automated RTL Update for Abutted Design | Wonkyung Lee, Ayoung Kwon, Soyeong Kwon, Youngsik Kim, and Seonil Brian Choi | | | | | | | |
| Automated RTL Update for Abutted Design | Wonkyung Lee, Ayoung Kwon, Soyeong Kwon, Youngsik Kim, and Seonil Brian Choi | | | | | | | |
| Automated Safety Verification for Automotive Microcontrollers | H. Busch | | | | | | | |
| Automated Safety Verification for Automotive Microcontrollers | Holger Busch | | | | | | | |
| Automated Seed Selection Algorithm for an Arbitrary Test Suite | David Crutchfield, Brian Craw, Jim Sharpe, and Brandon Skaggs | | | | | | | |
| Automated Seed Selection Algorithm for an Arbitrary Test Suite | David Crutchfield, Brian Craw, Jim Sharpe, and Brandon Skaggs | | | | | | | |
| Automated Specification Driven Verification by Generation of SystemVerilog Assertions | Ferdinando Pace | | | | | | | |
| Automated Specification Driven Verification by Generation of SystemVerilog Assertions | Ferdinando Pace | | | | | | | |
| Automated SystemC Model Instantiation with modern C++ Features and sc_vector | Ralph Görgen and Philipp A. Hartmann | | | | | | | |
| Automated SystemC Model Instantiation with modern C++ Features and sc_vector | Ralph Görgen, Philipp A. Hartmann, and Wolfgang Nebel | | | | | | | |
| Automated Test Generation to Verify IP Modified for System Level Power Management | Christophe Lamard | | | | | | | |
| Automated Test Generation to Verify IP Modified for System Level Power Management | Christophe Lamard and Frederic Dupuis | | | | | | | |
| Automated Thread Evaluation of Various RISC-V Alternatives using Random Instruction Generation | Endri Kaja, Nicolas Gerlin, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker | | | | | | | |
| Automated Thread Evaluation of Various RISC-V Alternatives using Random Instruction Generators | Endri Kaja, Nicolas Gerlin, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker | | | | | | | |
| Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual Prototype | S N Ranjan and Puttaiah Jagadish | | | | | | | |
| Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual Prototype | S N Ranjan and Puttaiah Jagadish | | | | | | | |
| Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual Prototype | S N Ranjan and Puttaiah Jagadish | | | | | | | |
| Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual Prototype | S N Ranjan and Puttaiah Jagadish | | | | | | | |
| Automated traceability of requirements in the design and verification process of safety-critical mixed-signal systems | Gabriel Pachiana, Maximilian Grunwald, Thomas Markwirth, Christoph Sohrmann | | | | | | | |
| Automated Traffic Simulation Framework for SoC Performance Analysis | Diviya Jain, Tarun Kathuria | | | | | | | |
| Automated vManager regression using Jenkins | Sneha Gokarakonda | | | | | | | |
| Automated, Systematic CDC Verification Methodology Based on SDC Setup | Ashish Hari, Sulabh Kumar Khare | | | | | | | |
| Automatic Debug Down to the Line | Daniel Hansson and Patrik Granath | | | | | | | |
| Automatic Debug Down to the Line of Code | Daniel Hansson and Patrik Granath | | | | | | | |
| Automatic Diagram Creation for Design and Testbenches | Paul O’Keeffe, Jamie Beattie, and Gian Lorenzo | | | | | | | |
| Automatic Diagram Creation for Design and Testbenches | Paul O’Keeffe, Jamie Beattie and Gian Lorenzo | | | | | | | |
| Automatic Exploration of Hardware/Software Partitioning | Syed Abbas Ali Shah, Sven Alexander Horsinka, Basitan Farkas, Rolf Meyer, and Malden Berekovic | | | | | | | |
| Automatic Exploration of Hardware/Software Partitioning | Syed Abbas Ali Shah, Sven Alexander Horsinka, Basitan Farkas, Rolf Meyer, and Malden Berekovic | | | | | | | |
| Automatic Firmware Design for Application-specific Electronic Systems: Opportunities, Challenges and Solutions | Daniel Große, Joscha Benz, Vladimir Herdt, and Martin Dittrich | | | | | | | |
| Automatic Firmware Verification for Automotive Applications | Torsten Andre and Daniel Valtiner | | | | | | | |
| Automatic Firmware Verification for Automotive Applications | Torsten Andre and Daniel Valtiner | | | | | | | |
| Automatic Generation of Formal Properties for Logic Related to Clock Gating | Shuqing Zhao and Shan Yan | | | | | | | |
| Automatic Generation of Formal Properties for Logic Related to Clock Gating | Shuqing Zhao and Shan Yan | | | | | | | |
| Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDL | Nikita Gulliya, Sudhir Bisht | | | | | | | |
| Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDL | Sudhir Bisht, Nikita Gulliya | | | | | | | |
| Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDL | Sudhir Bisht | | | | | | | |
| Automatic Generation of Infineon Microcontroller Product Configurations | Prateek Chandra, Leily Zafari, Boyko Traykov | | | | | | | |
| Automatic Generation of Infineon Microcontroller Product Configurations | Prateek Chandra, Leily Zafari, Boyko Traykov | | | | | | | |
| Automatic generation of Programmer Reference Manual and Device Driver from PSS | Freddy Nunez | | | | | | | |
| Automatic generation of Programmer Reference Manual and Device Driver from PSS | Freddy Nunez | | | | | | | |
| Automatic Investigation of Power Inefficiencies | Kuo Kai Hsieh, Li C. Wang, Wen Chen, Monica Farkash, and Jayanta Bhadra | | | | | | | |
| Automatic Investigation of Power Inefficiency | Kuo-Kai Hsieh, Wen Chen, Monica Farkash, Jayanta Bhadra, and Li-C. Wang | | | | | | | |
| Automatic Netlist Modifications required by Functional Safety | Harald Lüpken, Dirk Hönicke, and Michael Rohleder | | | | | | | |
| Automatic Netlist Modifications required by Functional Safety | Harald Lüpken, Dirk Hönicke, and Michael Rohleder | | | | | | | |
| Automatic Partitioning for Multi-core HDL Simulation | Gaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra | | | | | | | |
| Automatic Partitioning for Multi-core HDL Simulation | Gaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra | | | | | | | |
| Automatic SOC Test Bench Creation | David Crutchfield, Mark Glasser, and Stephen Roe | | | | | | | |
| Automatic SOC Test Bench Creation | David Crutchfield, Mark Glasser, and Stephen Roe | | | | | | | |
| Automatic Testbench Build to Reduce Cycle Time and Forster Reuse | Joachim Geishauser and Alexander Schilling | | | | | | | |
| Automatic Testbench Build to Reduce Cycle Time and Foster Reuse | Joachim Geishauser and Alexander Schilling | | | | | | | |
| Automatic Translation of Natural Language to SystemVerilog Assertions | Abhishek Chauhan | | | | | | | |
| Automatic Translation of Natural Language to SystemVerilog Assertions | Abhishek Chauhan | | | | | | | |
| Automatic verification for Assertion Based Verification: How can a SPIRIT IP-XACT extension help? | Sofiene Mejri and Mirella Negro Marcigaglia | | | | | | | |
| Automatically Synthesizing Higher Level of Protocol Abstraction for Faster Debug and Deeper Insight Into Modern Digital Designs | Alasdair Ferro, Amar Patel, Chris Jones, Yogesh Badaya | | | | | | | |
| Automating information retrieval from EDA software reports using effective parsing algorithms | Manish Bhati | | | | | | | |
| Automating sequence creation from a microarchitecture specification | Subramoni Parameswaran and Ravi Ram | | | | | | | |
| Automating sequence creation from a Microarchitecture specification | Subramoni Parameswaran and Ravi Ram | | | | | | | |
| Automating the Integration Workflow with IP-Centric Design | Simon Butler | | | | | | | |
| Automating the Formal Verification of Firmware: A Novel Foundation and Scalable Methodology | Bryan Olmos, Sanjana Sainath, Wolfgang Kunz, Djones Lettnin | | | | | | | |
| Automating the Formal Verification of Firmware: A Novel Foundation and Scalable Methodology | Bryan Olmos, Sanjana Sainath, Wolfgang Kunz, Djones Lettnin | | | | | | | |
| Automating the formal verification sign-off flow of configurable digital IP’s | Giovanni Auditore and Giuseppe Falconeri | | | | | | | |
| Automating the formal verification sign-off flow of configurable digital IP’s | Giovanni Auditore and Giuseppe Falconeri | | | | | | | |
| Automation for Early Detection of X-propagation in Power-Aware Simulation Verification using UPF IEEE 1801 | Tony Gladvin George, Ramesh Kumar, Kyuho Shim, Karan K, Wooseong Cheong, ByungChul Yoo | | | | | | | |
| Automation for Early Detection of Xpropagation in Power-Aware Simulation Verification using UPF IEEE 1801 | Tony Gladvin George, Ramesh Kumar, Kyuho Shim, Karan K, Wooseong Cheong, ByungChul Yoo | | | | | | | |
| Automation Methodology for Bus Performance Verification using IP-XACT | Taeyoung Jeon, Gunseo Koo, Youngsik Kim, Seonil Brian Cho | | | | | | | |
| Automation Methodology for Bus Performance Verification using IP-XACT | Taeyoung Jeon, Gunseo Koo, Youngsik Kim, Seonil Brian Choi | | | | | | | |
| Automation of Power On Reset Assertion | Shang-Wei Tu, Penny Yang, Joydeep Gangopadhyay, and Amol Herlekar | | | | | | | |
| Automation of Reusable Protocol-Agnostic Performance Analysis in UVM Environments | Daniel Carrington, Alan Pippin, and Timothy Pertuit | | | | | | | |
| Automation of Reusable Protocol-Agnostic Performance Analysis in UVM Environments | D. P. Carrington, A. J. Pippin, and T. Pertuit | | | | | | | |
| Automation of Waiver and Design Collateral generation for scalable IPs | Gopalakrishnan Sridhar, Vadlamuri Venkata Sateeshm, Midhun Krishna | | | | | | | |
| Automation of Waiver and Design Collateral Generation on Scalable IPs | Gopalakrishnan Sridhar, Midhun Krishna, Vadlamuri, Venkata Sateesh | | | | | | | |
| Automotive RADAR Bitfields Verification to support Validation of Silicon bring-up | Amol Dhok, Paulraj M K | | | | | | | |
| Automotive RADAR Bitfields Verification to support Validation of Silicon bring-up | Amol Dhok, Paulraj M K | | | | | | | |
| Autonomous Verification: Are We There Yet? | Ajay Singh | | | | | | | |
| Avoiding Configuration Madness The Easy Way | Rich Edelman | | | | | | | |
| Avoiding Configuration Madness The Easy Way | Rich Edelman | | | | | | | |
| Avoiding Confounding Configurations an RDC Methodology for Configurable Designs | Eamonn Quigley, Jonathan Niven, and Kurt Takara | | | | | | | |
| Avoiding Confounding Configurations An RDC Methodology for Configurable Designs | Eamonn Quigley, Jonathan Niven, and Kurt Takara | | | | | | | |
| Back to Basics: Doing Formal “The Right Way” | Joseph Hupcey III, Saumitra Goel | | | | | | | |
| BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering Problem | Debarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, Siddhanth Dhodhi, Spandan Kachhadiya | | | | | | | |
| BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering Problem | Debarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, and Siddhanth Dhodhi | | | | | | | |
| Be a Sequence Pro to Avoid Bad Con Sequences | Mark Litterick | | | | | | | |
| Be a Sequence Pro to Avoid Bad Con Sequences | Jeff Vance, Jeff Montesano, Mark Litterick, and Jason Sprott | | | | | | | |
| Benefits of PSS coverage at SOC & its limitations | Sundararajan Haran and Saleem Khan | | | | | | | |
| Benefits of PSS Coverage at SOC and Its Limitations | Sundararajan Haran, Saleem Khan | | | | | | | |
| Best Practices in Verification Planning | Benjamin Ehlers, Carmen Vargas, and Paul Carzola | | | | | | | |
| Best Practices in Verification Planning | Benjamin Ehlers and Paul Carzola | | | | | | | |
| Better Living Through Better Class-Based SystemVerilog Debug | Rich Edelman, Raghu Ardeishar, and John Amouroux | | | | | | | |
| Better Living Through Better Class-Based SystemVerilog Debug | Rich Edelman, Raghu Ardeishar, and John Amouroux | | | | | | | |
| Between the Dialog and the Algorithm or Innovative Technological Narratives Leveraging the Idea of Authenticity in a Human Being Visualizing log files enables intuitive comprehension of complex test scenarios | Anna M. Ravitzki and Uri Feigin | | | | | | | |
| Beyond UVM: Creating Truly Reusable Protocol Layering | Janick Bergeron, Fabian Delguste, Steve Knoeck, Steve McMaster, Aron Pratt, and Amit Sharma | | | | | | | |
| Beyond UVM: Creating Truly Reusable Protocol Layering | Janick Bergeron | | | | | | | |
| Bi-Directional UVM Agents and Complex Stimulus Generation for UDN and UPF Pins | Chuck McClish | | | | | | | |
| Big Data in Verification: Making Your Engineers Smarter | David Lacey, Mike McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson | | | | | | | |
| Big Data in Verification: Making Your Engineers Smarter | David Lacey, Michael McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson | | | | | | | |
| Bit density based pre characterization of RAM cells for area critical SOC design | Dilip Kumar Ajay ([email protected]) | | | | | | | |
| Bit Density-Based Pre-Characterization of RAM Cells for Area Critical SOC Design | Dilip Kumar Ajay | | | | | | | |
| Blending multiple metrics from multiple verification engines for improved productivity | Darron May and Darren Galpin | | | | | | | |
| Boost Verification Results by Bridging the Hardware/Software Testbench Gap | Matthew Ballance | | | | | | | |
| Boost Verification Results by Bridging the Hw/Sw Testbench Gap | Matthew Ballance | | | | | | | |
| Boost your productivity in FPGA & ASIC design and verification | Bart Brosens | | | | | | | |
| Boost your productivity in FPGA & ASIC design and verification | Bart Brosens | | | | | | | |
| Boosting Debug Productivity Practical Applications of Debug Innovations in a UVM World | Joerg Richter | | | | | | | |
| Boosting Mixed-Signal Design Productivity with FPGA-Based Methods Throughout the Chip Design Process | Gabriel Rutsch, Simone Fontanesi, Steven G. Herbst, Steven Tan Hee Yeng, Andrea Possemato, Gaetano Formato, Mark Horowitz, and Wolfgang Ecker | | | | | | | |
| BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMS | Ahmed Yehia | | | | | | | |
| BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMS | Ahmed Yehia | | | | | | | |
| Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven Generation | Hoang M. Le and Rolf Drechsler | | | | | | | |
| Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven Generation | Hoang M. Le and Rolf Drechsler | | | | | | | |
| Break the SoC with Random UVM Instruction Driver | Bogdan Todea, Pravin Wilfred, Madhukar Mahadevappa, Diana Dranga | | | | | | | |
| Break the SoC with UVM Dynamically Generated Program Code | Bogdan Todea, Madhukar Mahadevappa & Pravin Wilfred | | | | | | | |
| Breaking Down Barriers: Seamless Protocol Conversion with UVM Component Layering | Santosh Mahale, Shantanu Lele | | | | | | | |
| Breaking Down Barriers: Seamless Protocol Conversion with UVM Component Layering | Santosh Mahale, Shantanu Lele | | | | | | | |
| Bridge the Portable Test and Stimulus to UVM Simulation Environment | Theta Yang and Evean Qin | | | | | | | |
| Bridge the Portable Test and Stimulus to UVM Simulation Environment | Theta Yang and Evean Qin | | | | | | | |
| Bridging the gap between system-level and chip-level performance optimization | Soniya Gupta, Vikrant Kapila & Holger Keding | | | | | | | |
| Bridging the gap between TLM-2.0 AT models and RTL – Experiments and Opportunities | Zhu Zhou, Atul Kwatra, Rajesh Gadiyar, and Paul Heraty | | | | | | | |
| Bring IP Verification Closer to SoC Scalable Methods to Bridge the Gap Between IP and SoC Verification | Gaurav Gupta, Tejbal Prasad, Rohit Goyal, Sachin Jain, Vipin Verma | | | | | | | |
| Bring IP Verification Closer to SoC Scalable Methods to Bridge the Gap Between IP and SoC Verification | Gaurav Gupta, Tejbal Prasad, Rohit Goyal, Sachin Jain, Vipin Verma | | | | | | | |
| Bringing Constrained Random into SoC SW-driven Verification | Alberto Allara and Fabio Brognara | | | | | | | |
| Bringing Constrained Random into SoC SW-driven Verification | Alberto Allara and Fabio Brognara | | | | | | | |
| BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPS | Prabal K Bhattacharya, Swapnajit Chakraborti, Donald O’Riordan, Vaibhav Bhutani, and Scott Little | | | | | | | |
| BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPS | Prabal K Bhattacharya, Swapnajit Chakraborti, Scott Little, Donald O’Riordan, and Vaibhav Bhutani | | | | | | | |
| Bringing DataPath Formal to Designers’ Footsteps | M, Achutha KiranKumar V, Disha Puri, Shriya Dharade | | | | | | | |
| Bringing Regression Systems into the 21st Century | David Crutchfield and Thom Ellis | | | | | | | |
| Bringing Regression Systems into the 21st Century | David Crutchfield | | | | | | | |
| Bringing Reset Domains and Power Domains together – Confronting issues due to UPF Instrumentation | Inayat Ali, Abdul Moyeen, Manish Bhati, Manjunatha Srinivas | | | | | | | |
| Bringing Reset Domains and Power Domains together – Non resettable registers amplifying issues in Power-Aware RDC Verification due to UPF Instrumentation | Manish Bhati, Inayat Ali | | | | | | | |
| Bringing Reset Domains and Power Domains Together – Set/Reset Flops Augmenting Complexities in Power-Aware RDC Verification. | Manish Bhati, Manjunatha Srinivas, Abdul Moyeen, Inayat Ali | | | | | | | |
| Bringing UVM to VHDL | UVVM | | | | | | | |
| Build Reliable and Efficient Reset Networks with a Comprehensive Reset Domain Crossing Verification Solution | Wanggen Shi, Yuxin You, and Kurt Takara | | | | | | | |
| Build Reliable and Efficient Reset Networks with a Comprehensive Reset Domain Crossing Verification Solution | Wanggen Shi, Yuxin You, and Kurt Takara | | | | | | | |
| Building a coherent ESL design and verification eco-system with SystemC, TLM, UVM-SystemC, and CCI | Martin Barnasconi | | | | | | | |
| Building a Comprehensive Hardware Security Methodology | Anders Nordstrom and Jagadish Nayak | | | | | | | |
| Building a Virtual Driver for Emulator | Chen Chih-Chiang | 2023 | Taiwan | Paper | | y2023 | taiwan | paper |
| Building And Modelling Reset Aware Testbench For IP Functional Verification | Naishal Shah | | | | | | | |
| Building Code Generators for Reuse – Demonstrated by a SystemC Generator | Saad Siddiqui and Ulrich Nageldinger | | | | | | | |
| Building Code Generators for Reuse – Demonstrated by a SystemC Generator | Ulrich Nageldinger and Saad Siddiqui | | | | | | | |
| Building Confidence in System level CPU Cache Coherency Verification for Complex SoC’s through a Configurable, Flexible and Portable Testbench | Ruchi Misra, Shrinidhi Rao, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi | | | | | | | |
| Building Confidence in System Level CPU Cache Coherency Verification for Complex SoCs through a Configurable Flexible and Portable Test Bench | S Shrinidhi Rao, Ruchi Misra, Alok Kumar, Garima Srivastava, YoungSik Kim, Seonil Brian Choi | | | | | | | |
| Building Configurable UVM Testbench for Configurable Design IP (Configurable TB) | Kilaru Vamsikrishna, Sushrut B Veerapur | | | | | | | |
| Building Portable Stimulus Into your IP-XACT Flow | Petri Karppa, Lauri Matilainen, and Matthew Ballance | | | | | | | |
| Building Portable Stimulus Into Your IP-XACT Flow | Petri Karppa, Lauri Matilainen, and Matthew Balance | | | | | | | |
| Building Smart SoCs Using Virtual Prototyping for the Design and SoC Integration of Deep Learning Accelerators | Holger Keding | | | | | | | |
| Building UVM Testbenches for High Quality Serial Design IPs Modelling real world scenarios | Kilaru Vamsikrishna, Sushrut B Veerapur | | | | | | | |
| Bus Trace System: Automating Bus Traffic Debugging in IP-XACT Based SoC | Wonyeong So, Yonghyun Yang, Sun-il Roe, Moonki Jang, Youngsik Kim, Seonil Brian Choi | | | | | | | |
| Bus Trace System: Automating Bus Traffic Debugging in IP-XACT Based SoC Beyond Traditional Debugging Methods | Wonyeong So, Yonghyun Yang, Sun-il Roe, Moonki Jang, Youngsik Kim, Seonil Brian Choi | | | | | | | |
| C through UVM: Effectively using C based models with UVM based Verification IP | Chris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile | | | | | | | |
| C through UVM: Effectively using C based models with UVM based Verification IP | Adiel Khan, Chris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile | | | | | | | |
| Caching Tool Run Results in Large Scale RTL Development Projects | Ashfaq Khan | | | | | | | |
| Caching Tool Run Results in Large-Scale RTL Development Projects | Ashfaq Khan | | | | | | | |
| Cadence vManager Platform and Virtuoso ADE Verifier Leading-edge technologies provide methodology for mixedsignal verification closure | Kawe Fotouhi and Walter Hartong | | | | | | | |
| Calling All Checkers: Collaboratively Utilizing SVA In UVM Based Simulation | Hui K. Zhang | | | | | | | |
| Calling All Checkers: Collaboratively Utilizing SVA in UVM Based Simulation | Hui C. K. Zhang | | | | | | | |
| CAMEL – A Flexible Cache Model for Cache Verification | Yue Liu, Fang Liu, Yunyang Song | | | | | | | |
| CAMEL: A Flexible Cache Model for Cache Verification | Yue Liu, Fang Liu, and Yunyang Song | | | | | | | |
| Can Formal Outsmart Synthesis: Improving Synthesis Quality of Results through Formal Methods | Eldon Nelson | | | | | | | |
| Can My Synthesis Compiler Do That? | Stuart Sutherland and Don Mills | | | | | | | |
| Can My Synthesis Compiler Do That? | Stuart Sutherland and Don Mills | | | | | | | |
| Can You Even Debug a 200M+ Gate Design? | Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss | | | | | | | |
| Can You Even Debug a 200M+ Gate Design? | Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss | | | | | | | |
| Case Study of Verification Planning to Coverage Closure @Block, Subsystem and System on Chip Level | Paul Kaunds, Revati Bothe, and Jesvin Johnson | | | | | | | |
| Case Study: Low-Power Verification Success Depends on Positive Pessimism | John Decker | | | | | | | |
| Case Study: Power-aware IP and Mixed-Signal Veri | Luke Lang | | | | | | | |
| Case Study: Successes and Challenges of Validation Content Reuse | Mike Chin, Jonathan Edwards, Josh Pfrimmer, and Hooi Jing Tan | | | | | | | |
| Case-study: Generating A Workload Model of the Chrome Browser from Android Execution Traces For Early Analysis of Power and Performance Trade-offs | Vikrant Kapila, Tim Kogel, Holger Keding, Amit Tara Amit Dudeja, Nishant Gautam | | | | | | | |
| Catching the low hanging fruits on intel® Graphics Designs | M, Achutha KiranKumar V, Aarti Gupta, Bindumadhava S S, Savitha Manojna, and Abhijith A Bharadwaj | | | | | | | |
| Centralized Regression Optimisation Toolkit (CROT) for expediting Regression Closure With Simulator Performance Optimisation | Harshal Kothari, Pavan M, Ajay Vamshi Krishna, Eldin Ben Jacob, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | | | |
| Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation) | Vikas Billa and Sundar Haran | | | | | | | |
| Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation) | Vikas Billa and Sundar Haran | | | | | | | |
| Challenges and Solutions for Creating Virtual Platforms of FPGA and SASIC Designs | Kalen Brunham, Jakob Engblom | | | | | | | |
| Challenges and Solutions for Creating Virtual Platforms of FPGA and SASIC Designs | Kalen Brunham, Jakob Engblom | | | | | | | |
| Challenges in Mixed Signal Verification | Amlan Chakrabarti, Sachin-Sudhakar Kulkarni | | | | | | | |
| Challenges in UVM + Python Random Verification Environment for Digital Signal Processing Datapath Design | Shabbar Vejlani and Ashok Chandran | | | | | | | |
| Challenges in UVM + Python random verification environment for Digital Signal Processing datapath design. | Shabbar Vejlani and Ashok Chandran | | | | | | | |
| Challenges of Formal Verification on Deep Learning Hardware Accelerator | Yellinidi Dasarathanaidu | | | | | | | |
| Challenges of Formal Verification on Deep Learning Hardware Accelerator | Yellinidi Dasarathanaidu | | | | | | | |
| Challenges of VHDL X-propagation Simulations | Karthik Baddam and Piyush Sukhija | | | | | | | |
| Challenges of VHDL X-propagation Simulations | Karthik Baddam and Piyush Sukhija | | | | | | | |
| Challenges with Power Aware Simulation and Verification Methodologies | Divyeshkumar Vora | | | | | | | |
| Challenges, Complexities and Advanced Verification Techniques in Stress Testing of Elastic Buffer in High Speed SERDES IPs | Kamesh Velmail, Suvadeep Bose, Ankit Garg, Parag S Lonkar, Somasunder K Sreenath | | | | | | | |
| Challenges, Complexities and Advanced Verification Techniques in Stress Testing of Elastic Buffer in High Speed SERDES IPs | Kamesh Velmail, Suvadeep Bose, Parag Lonkar, Ankit Garg | | | | | | | |
| Channel Modelling in Complex Serial IPs | Jayesh Ranjan Majhi, Saravana Balakrishnan, Navnit Kumar Kashyap | | | | | | | |
| Channel Modelling in Complex Serial IPs | Jayesh Ranjan Majhi, Saravana Balakrishnan, Navnit Kumar Kashyap | | | | | | | |
| Characterizing RF Wireless Receivers Performance in UVM Environment | Salwa Elqassas, Salwa Elqassas and Mohammed T. Abdel-Hafe | | | | | | | |
| Check Low-Power Violations by Using Machine Learning Based Classifier | Chi-Ming Lee, Chung-An Wang, Cheok-Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai | | | | | | | |
| Check Low-Power Violations by Using Machine Learning Based Classifier | Chi-Ming Lee, Chung-An Wang, Cheok-Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai | | | | | | | |
| Checking security path with formal verification tool: new application development | Julia Dushina, Saumil Shah, Joerg Mueller, and Vincent Reynolds | | | | | | | |
| Checking Security Path with Formal Verification Tool: New Application Development | Julia Dushina and Joerg Mueller | | | | | | | |
| Chef’s Special – an Efficient Verification Recipe for Maximizing Productivity While Using a Third Party Verification IP | Varun S and Bhavik Vyas | | | | | | | |
| Chiplevel Analog Regressions in Production | Yi Wang | | | | | | | |
| Choice is Yours: Either Struggle to Tame ‘X’ in the Wilderness of Multimillion Gates and Nets, OR Take it for a Walk in the RTL Park | Nitin Jaiswal, Harsh Garg, Mayank Bindal | | | | | | | |
| Cleaning Out Your Pipes – Pipeline Debug in UVM Testbenches | Rich Edelman and Neil Bulman | | | | | | | |
| Cleaning Out Your Pipes – Pipeline Debug in UVM Testbenches | Rich Edelman and Neil Bulman | | | | | | | |
| Clock Controller Unit Design Metrics: Area, Power, Software Flexibility and Congestion Impacts at System Level | Michele Chilla and Leonardo Gobbi | | | | | | | |
| CLOCK DOMAIN CROSSING CHALLENGES IN LATCH BASED DESIGNS | Madan Das, PhD, Chris Kwok, and Kurt Takara | | | | | | | |
| Clock Domain Crossing Challenges in Latch Based Designs | Madan Das, Chris Kwok, and Kurt Takara | | | | | | | |
| Clock Domain Crossing Verification in Transistor-level Design | Hyungjung Seo, KwangSun Kim, YoungRok Choi, Jihwan Kim, and Jong-Bae Lee | | | | | | | |
| Clock Tree Design Considerations in The Presence of Asymmetric Transistor Aging | Freddy Gabbay; Firas Ramadan; Majd Ganaiem | | | | | | | |
| Closed-Loop Model-First SoC Development With the Intel® Simics® Simulator | Kalen Brunham, Anthony Moore, Tobias Rozario, Wei Jun Yeap, and Jakob Engblom | | | | | | | |
| Closed-Loop Model-First SoC Development With the Intel® Simics® Simulator | Kalen Brunham, Anthony Moore, Tobias Rozario, Wei Jun Yeap, and Jakob Engblom | | | | | | | |
| Closing and Awards | Accellera Systems Initiative | | | | | | | |
| Closing Ceremony – DVCon Europe 2023 | | | | | | | | |
| Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis | Bryan Bowyer | | | | | | | |
| Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis | B. Bowyer | | | | | | | |
| Closing Functional Coverage With Deep Reinforcement Learning: A Compression Encoder Example | Eric Ohana | | | | | | | |
| Closing Functional Coverage With Deep Reinforcement Learning A Compression Encoder Example | Eric Ohana | | | | | | | |
| Closing the gap between requirement management and system design by requirement tracing | Hayri Verner Hasou, Guillermo Conde, Adrian Rolufs, Dominic Scharfe | 2022 | Europe | Paper | | y2022 | europe | paper |
| Closing the loop from requirements management to verification execution for automotive applications | Walter Tibboel and Jan Vink | | | | | | | |
| Closing the loop from requirements management to verification execution for automotive applications | Walter Tibboel and Jan Vink | | | | | | | |
| Closing with Awards | Accellera Systems Initiative | 2022 | Europe | Video | | y2022 | europe | video |
| Clustering and Classification of UVM Test Failures Using Machine Learning Techniques | Andy Truong, Daniel Hellström, Harry Duque, and Lars Viklund | | | | | | | |
| Clustering and Classification of UVM Test Failures Using Machine Learning Techniques | Andy Troung, Daniel Hellström, Harry Duque, and Lars Viklund | | | | | | | |
| Co-Design of Automotive Boardnet Topology and Architecture | Sebastian Post, Christoph Grimm | | | | | | | |
| Co-Design of Automotive Boardnet Topology and Architecture | Sebastian Post; Christoph Grimm | | | | | | | |
| Co-Developing Firmware and IP with PSS | M. Ballance | | | | | | | |
| Co-Developing IP and SoC Bring-Up Firmware with PSS | Matthew Ballance, Siemens EDA | | | | | | | |
| Co-Simulating Matlab/Simulink Models in a UVM Environment | Neal Okumura, Paul Yue, and Glenn Richards | | | | | | | |
| Co-Simulating Matlab/Simulink Models in a UVM Environment | Neal Okumura and Glenn Richards | | | | | | | |
| Code-Test-Verify all for free – Assertions + Verilator | Hemamalini Sundaram, Kasthuri Srinivas, Supriya Ummadisetty | | | | | | | |
| Code-Test-Verify all for free – Assertions + Verilator | Hemamalini Sundaram, Kasthuri Srinivas, Supriya Ummadisetty | | | | | | | |
| Coding Guidelines and Code Generation | John Aynsley and Dr. Christoph Sühnel | | | | | | | |
| Coherency Verification & Deadlock Detection Using Perspec/Portable Stimulus | Moonki Jang, Jiwoong Kim, Hyerim Chung, Phu L. Huynh, and Shai Fuss | | | | | | | |
| Coherency Verification & Deadlock Detection Using Perspec/Portable Stimulus | Moonki Jang and Phu Huynh | | | | | | | |
| Combining Simulation with Formal Techniques to Reduce the Overall Verification Cycle | Aneet Agarwal and Gaurav Gupta | | | | | | | |
| Combining Static and Dynamic Low Power Verification for the Power-Aware SoC Sign-off | Himanshu Bhatt and Prashanth M | | | | | | | |
| Combining Static and Dynamic Low Power Verification for the Power-Aware SoC Sign-off | Himanshu Bhatt, Prashanth M, and Adiel Khan | | | | | | | |
| Command Line Debug Using UVM Sequences | Mark Peryer | | | | | | | |
| Common Challenges and Solutions to Integrating a UVM Testbench | Frank Verhoorn and Mike Baird | | | | | | | |
| Common Challenges and Solutions to Integrating a UVM Testbench in Place of a Legacy Monolithic Testing Environment | Frank Verhoorn and Michael Baird | | | | | | | |
| Compact AI accelerator for embedded applications | Alexey Shchekin | | | | | | | |
| Comparison of TLM2-Quantum Keeping and TLM+-Resource Modeling with regard to Timing in Virtual Prototypes | Wolfgang Ecker, Volkan Esen, Rainer Findenigy, Thomas Leitnerz and Michael Velten | | | | | | | |
| Complementing EDA with Meta-Modeling and Code Generation | Wolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal | | | | | | | |
| Complementing EDA with Meta-Modelling & Code Generation | Wolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal | | | | | | | |
| Complementing EDA with Meta-Modelling and Code Generation | Ecker Wolfgang, Michael Velten, Ajay Goyal, and Leily Zafari | | | | | | | |
| Complementing Verification of Highly Configurable Design with Formal Techniques | Manik Tyagi, Deepak Jindal | | | | | | | |
| Complete Formal Verification of a Family of Automotive DSPs | Rafal Baranowski and Marco Trunzer | | | | | | | |
| Complete Formal Verification of a Family of Automotive DSPs | Rafal Baranowski and Marco Trunzer | | | | | | | |
| Complex Low Power Verification Challenges in NextGen SoCs : Taming the Beast! | Abhinav Nawal, Gaurav Jain, and Joachim Geishauser | | | | | | | |
| Complex Low Power Verification Challenges in NextGen SoCs: Taming the Beast! | Abhinav Nawal and Gaurav Jain | | | | | | | |
| Complex Safety Mechanisms Require Interoperability and Automation For Validation And Metric Closure | Daeseo Cha, Vedant Garg | | | | | | | |
| Complex Safety Mechanisms Require Interoperability and Automation For Validation And Metric Closure | Daeseo Cha, Vedant Garg, Ann Keffer, Arun Gogineni, James Kim, Woojoo Space Kim, Kunhyuk Kang, Seonil Brian Choi | | | | | | | |
| Complexities & Challenges of UPF Corruption Model in Low Power Emulation | Progyna Khondkar, Brad Budlong | | | | | | | |
| Compliance Driven Integrated Circuit Development Based on ISO26262 | Haridas Vilakathara and Manikandan Panchapakesan | | | | | | | |
| Compliance Driven Integrated Circuit Development Based on ISO26262 | Haridas Vilakathara, Manikantan panchapakesan | | | | | | | |
| CompMon: Ensuring Rigorous Protocol Specification and IP Compliance | Robert Adler, Sava Krstic and Erik Seligman | | | | | | | |
| Comprehensive AMS Verification using Octave, Real Number Modelling and UVM | John McGrath, Patrick Lynch, and Ali Boumaalif | | | | | | | |
| Comprehensive AMS Verification using Octave, Real Number Modelling and UVM | John McGrath, Patrick Lynch, and Ali Boumaalif | | | | | | | |
| Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain Crossings | Yossi Mirsky | | | | | | | |
| Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain Crossings | Yossi Mirsky B.Sc, M.Sc, MBA | | | | | | | |
| Comprehensive Benchmark Results: Comparing Processing-in-Memory Architecture Effectiveness using UPMEM Hardware | Ambati Rajashekar, Pranjit Das, Avi kumar Shrivastava, Partha Acharya | | | | | | | |
| Comprehensive IP to SoC CDC Verification Using Hybrid Data Model | Anwesha Choudhury and Ashish Hari | | | | | | | |
| Comprehensive IP to SoC Clock Domain Crossing Verification Using Hybrid Data Mode | Anwesha Choudhury and Ashish Hari | | | | | | | |
| Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-Chips | Ellie Burns, Gabriel Chidolue, and Guillaume Boillet | | | | | | | |
| Comprehensive Register Description Languages: The case for standardization of RDLs across design domains | David C Black and Doug Smith | | | | | | | |
| Comprehensive Systemverilog-Systemc-Vhdl Mixed-Language Design Methodology | Rudra Mukherjee, Gaurav Kumar Verma, and Sachin Kakkar | | | | | | | |
| Computational Logistics for Intelligent System Design | Simon Chang | | | | | | | |
| Compute Link Express – CXL – CXL Consortium | Narasimha Babu | | | | | | | |
| Conditional Delays for Negative Limit Timing Checks in Event Driven Simulation | Nadeem Kalil and David Roberts | | | | | | | |
| Conditional Delays for Negative Limit Timing Checks in Event Driven Simulation | N. Kalil and D. Roberts | | | | | | | |
| Confidently Sign-off Any low-Power Designs without Consequences | Madhur Bhargava, Jitesh Bansal, and Progyna Khondkar | | | | | | | |
| Confidently Sign-Off Any Low-Power Designs Without Consequences | Madhur Bharga, Jitesh Bansal and Progyna Khondkar | | | | | | | |
| Configurable Testbench (TB) for Configurable Design IP | Kilaru Vamsikrishna, Sushrut B Veerapur | | | | | | | |
| Configuration Conundrum: Managing Test Configuration with a Bite Sized Solution | Kevin Vasconcellos, Jeff McNeal | | | | | | | |
| Configuration in UVM:The Missing Manual | Mark Glasser | | | | | | | |
| Configuration in UVM: The Missing Manual | Mark Glasser | | | | | | | |
| Configuring Your Resources the UVM Way! | Parag Goel, Amit Sharma, and Rajiv Hasija | | | | | | | |
| Configuring Your Resources the UVM Way! | Parag Goel, Amit Sharma, and Rajiv Hasija | | | | | | | |
| Connecting a Company’s Verification Methodology to Standard Concepts of UVM | Frank Poppen, Marco Trunzer, and Jan‐Hendrik Oetjens | | | | | | | |
| Connecting a Company’s Verification Methodology to Standard Concepts of UVM | Frank Poppen, Marco Trunzer, and Jan‐Hendrik Oetjens | | | | | | | |
| Connecting Enterprise Applications to Metric Driven Verification | Matt Graham | | | | | | | |
| Connecting Enterprise Applications to Metric Driven Verification | Matt Graham | | | | | | | |
| CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITY | Bin Ju | | | | | | | |
| CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITY | Bin Ju | | | | | | | |
| Connecting UVM with Mixed-Signal Design | Ivica Ignjić | | | | | | | |
| CONNECTING UVM WITH MIXED-SIGNAL DESIGN | Ivica Ignjić | | | | | | | |
| Connectivity and Beyond | Shahid Ikram, Joseph DErrico, Yasmin Farhan, Jim Ellis, and Tushar Parikh | | | | | | | |
| Connectivity and Beyond | Shahid Ikram, Joseph DErrico, Yasmin Farhan, Jim Ellis, and Tushar Parikh | | | | | | | |
| Conquer the Graphics Legacy: Develop the Customized UVM VIP Embedded a Cycle-based C++ Reference Model | Roman Wang | | | | | | | |
| Conscious of Streams Managing Parallel Stimulus | Jeff Wilcox | | | | | | | |
| Conscious of Streams: Managing Parallel Stimulus | Jeffrey Wilcox and Stephen D’Onofrio | | | | | | | |
| Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL Synthesis | Rainer Findenig, Thomas Leitner, and Wolfgang Ecker | | | | | | | |
| CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTION | Jussi Mäkelä, Martin Fröjd, and Adiel Khan | | | | | | | |
| CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTION | Jussi Mäkelä, Martin Fröjd, and Adiel Khan | | | | | | | |
| CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTION | Martin Fröjd, Adiel Khan, and Jussi Mäkelä | | | | | | | |
| Context-Aware DFM Rule Analysis and Scoring Using Machine Learning | Vikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, and Jonathan Ong | | | | | | | |
| Context-Aware DFM Rule Analysis and Scoring Using Machine Learning | Vikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, and Jonathan Ong | | | | | | | |
| Control Flow Analysis for Bottom-up Portable Models Creation | Petr Bardonek; Marcela Zachariasova | | | | | | | |
| Conversion of Performance Model to Functional Model | H G Pavan Kumar, Sumail Singh Brar, Ashwani Aggarwal, Seonil Brian Choi, Woojoo Space Kim | | | | | | | |
| Counterintuitive approaches to have better communication between UVM and Python for registers with Single Controlling Algorithm | Sougata Bhattacharjee | | | | | | | |
| Coverage Acceleration and Testcase Pruning using Smart Stimuli Generator in SOC Verification | Rahul Laxkar, Naveen Srivastava, Sekhar Dangudubiyyam | | | | | | | |
| Coverage Acceleration and Testcase Pruning using Smart Stimuli Generator in SOC Verification | Rahul Laxkar, Naveen Srivastava, Sekhar Dangudubiyyam | | | | | | | |
| Coverage Closure – Is it a “Game of Dice” or “Top 10 Tests” or “Automated Closure”? | Aditya Sharma, T. Nagasundaram, M. Nitin Kumar, Nikhita Raj J | | | | | | | |
| Coverage Data Exchange is no robbery…or is it? | Darron May and Samiran Laha | | | | | | | |
| Coverage Data Exchange is no robbery…or is it? | Darron May and Samiran Laha | | | | | | | |
| Coverage Driven Distribution of Constrained Random Stimuli | Marat Teplitsky, Amit Metodi, and Raz Azaria | | | | | | | |
| Coverage Driven Distribution of Constrained Random Stimuli | Raz Azaria, Amit Metodi, and Marat Teplitsky | | | | | | | |
| Coverage Driven Signoff with Formal Verification on Power Management IPs | Baosheng Wang and Xiaolin Chen | | | | | | | |
| Coverage Driven Signoff with Formal Verification on Power Management IPs | Baosheng Wang and Xiaolin Chen | | | | | | | |
| Coverage Driven Verification of an Unmodified DUT within an OVM Testbench | Michael Baird | | | | | | | |
| Coverage Models for Formal Verification | Xiushan Feng, Xiaolin Chen, and Abhishek Muchandikar | | | | | | | |
| Coverage Models for Formal Verification | Xiushan Feng, Xiaolin Chen, and Abhishek Muchandikar | | | | | | | |
| COVERGATE: Coverage Exposed | Rich Edelman | | | | | | | |
| COVERGATE: Coverage Exposed | Rich Edelman | | | | | | | |
| Covering All the bases: Coverage-driven Formal Verification Sign-off of Pipelined Error Detection Filter | Harbaksh Gupta, Anshul Jain | | | | | | | |
| Covering All the bases: Coverage-driven Formal Verification Sign-off of Pipelined Error Detection Filter | Harbaksh Gupta, Anshul Jain | | | | | | | |
| Covering the Last Mile in SoC-Level Deadlock Verification | Jef Verdonck, Khaled Nsaibia, Sagar Dewangan, HarGovind Singh and Roger Sabbagh | | | | | | | |
| Covering the Last Mile in SoC-Level Deadlock Verification | Jef Verdonck, Dhruv Gupta, and HarGovind Singh | | | | | | | |
| Crafting a Million Instructions/Sec RISCV-DV HPC Techniques to Boost UVM Testbench Performance by Over 100x | Puneet Goel, Ritu Goel, Jyoti Dahiya | | | | | | | |
| Crafting a Million Instructions/Sec RISCV-DV HPC Techniques to Boost UVM Testbench Performance by Over 100x | Puneet Goel, Ritu Goel, Jyoti Dahiya | | | | | | | |
| CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemC | Hoang M. Le and Rolf Drechsler | | | | | | | |
| CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemC | Hoang M. Le and Rolf Drechsler | | | | | | | |
| Creating 5G Test Scenarios, the Constrained-Random way | Keshav Kannan, Eric P. Kim | | | | | | | |
| Creating 5G Test Scenarios, the Constrained-Random way | Keshav Kannan and Eric P. Kim | | | | | | | |
| Creating a Complete Low Power Verification Strategy using the Common Power Format and UVM | Robert Meyer and Joel Artmann | | | | | | | |
| Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation Requirements | David Lacey and Ed Powell | 2018 | United States | Paper | | y2018 | united-states | paper |
| Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation Requirements | David Lacey and Ed Powell | | | | | | | |
| Cross Coverage of Power States | Veeresh Vikram Singh and Awashesh Kumar | | | | | | | |
| Cross-Domain Datapath Validation Using Formal Proof Accelerators | Aarti Gupta, S. S. Bindumadhava, M. Achutha KiranKumar V, Liu Jun B | | | | | | | |
| Customizing UVM Agent Supporting Multi-Layered & TDM Protocols | Amit Pessach | | | | | | | |
| Customizing UVM Agent Supporting Multi-Layered & TDM Protocols | Amit Pessach | | | | | | | |
| CXL Verification using Portable Stimulus | Ragesh Thottathil, Karthick Gururaj | | | | | | | |
| CXL verification using portable stimulus | Karthick Gururaj | | | | | | | |
| Data Flow Based Memory IP Creation Infrastructure | Abhilash V Nair, Praveen Buddireddy, Tor Jeremiassen, Rashmi Venkatesh, and Prajakta Bhutada | | | | | | | |
| Data path verification on cross domain with formal scoreboard | Liu Jun | | | | | | | |
| Data path verification on cross domain with formal scoreboard | Liu Jun | | | | | | | |
| Data-Driven Verification: Driving the next wave of productivity improvements | Larry Melling, Chris Komar, Sharon Rosenberg, Michael Young, and Hanan Moller | | | | | | | |
| DatagenDV: Python Constrained Random Test Stimulus Framework | Jon George, James Mackenzie | | | | | | | |
| DatagenDV: Python Constrained Random Test Stimulus Framework | Jonathan George, James Mackenzie | | | | | | | |
| Day 1 Opening | Accellera Systems Initiative | | | | | | | |
| Day 2 Opening | Accellera Systems Initiative | | | | | | | |
| DDR Controller IP Evaluation Studies using Trace Based Methodology | Abhilash Nair, Amit Nene, Ritesh Sojitra, Prashant Karandikar and Prajakta Bhutada | | | | | | | |
| De-mystifying synchronization between various verification components by employing novel UVM classes | Pushpal Nautiyal and Gaurav Chugh | | | | | | | |
| De-mystifying synchronization between various verification components by employing novel UVM classes | Pushpal Nautiyal and Gaurav Chugh | | | | | | | |
| Deadlock Free Design Assurance Using Architectural Formal Verification | Bhushan Parikh, Shaman Narayana | | | | | | | |
| Deadlock Free Design Assurance Using Architectural Formal Verification | Bhushan Parikh, Shaman Narayana | | | | | | | |
| Deadlock Verification For Dummies – The Easy Way of Using SVA and Formal | Mark Eslinger, Jeremy Levitt, and Joe Hupcey III | | | | | | | |
| Deadlock Verification For Dummies – The Easy Way Using SVA and Formal | Mark Eslinger, Jeremy Levitt, and Joe Hupcey III | | | | | | | |
| Dealing with Programmable IP: Where the Rubber Meets the PSS Deployment Road | Karthick Gururaj | | | | | | | |
| Debarshi Chatterjee, Spandan Kachhadia, Chen Luo, Kumar Kushal, Siddhanth Dhodhi | Moonki Jang | | | | | | | |
| Debug APIs – next wave of innovation in DV space | Srinivasan Venkataramanan and Ajeetha Kumari | | | | | | | |
| Debug APIs – next wave of innovation in DV space | Srinivasan Venkataramanan and Ajeetha Kumari | | | | | | | |
| Debug Automation with AI | Craig Yang, Jaw Lee, Sherwin Lai | 2023 | Taiwan | Paper | | y2023 | taiwan | paper |
| Debug Challenges in Low-Power Design and Verification | Durgesh Prasad, Madhur Bhargava, Jitesh Bansal, and Chuck Seeley | | | | | | | |
| Debug Challenges in Low-Power Design and Verification | Durgesh Prasad, Madhur Bhargava, Jitesh Bansal, and Chuck Seeley | | | | | | | |
| Debug Time Reduction by Automatic Generation of Waiver List Using ML Techniques | Vardhana M, Akshay Jain, Kota Subba Rao Sajja | | | | | | | |
| Debugging Communicating Systems: The Blame Game – Blurring the Line Between Performance Analysis and Debug | Rich Edelman and Raghu Ardeishar | | | | | | | |
| Debugging Functional Coverage Models Get The Most Out of Your Cover Crosses | Mennatallah Amer and Amr Hany | | | | | | | |
| Debugging Functional Coverage Models Get The Most Out of Your Cover Crosses | Mennatallah Amer and Amr Hany | | | | | | | |
| Debugging Linux Kernel Failures on Virtual Platform | Sandeep Jain | | | | | | | |
| Deep Learning for Design and Verification Engineers | John Aynsley | | | | | | | |
| Deep Learning for Engineers | John Aynsley | | | | | | | |
| Deep Predictive Coverage Collection | Rajarshi Roy, Chinmay Duvedi, Saad Godil, and Mark Williams | | | | | | | |
| Deep Predictive Coverage Collection | Rajarshi Roy, Chinmay Duvedi, Saad Godil, and Mark Williams | | | | | | | |
| Defining TLM+ | Wolfgang Ecker, Volkan Esen, Robert Schwencker, and Michael Velten | | | | | | | |
| DeltaCov: Automated Stimulus Quality Monitoring System | Nimish Girdhar, Srinivas Badam | | | | | | | |
| Democratizing Digital-centric Mixed-signal Verification methodologies | Sumit Vishwakarma | | | | | | | |
| Democratizing Formal Verification | Tobias Ludwig, Michael Schwarz, Paulius Morkunas, Silvio Santana, Dominik Stoffel, Wolfgang Kunz | | | | | | | |
| Demystifying Formal Testbenches: Tips, Tricks, and Recommendations | Shahid Ikram, Mark Eslinger | | | | | | | |
| Demystifying Formal Testbenches: Tips, Tricks, and Recommendations | Dr. Shahid Ikram, Mark Eslinger | | | | | | | |
| Demystifying the UVM Configuration Database | Vanessa R. Cooper and Paul Marriott | | | | | | | |
| Demystifying the UVM Configuration Database | Vanessa R. Cooper and Paul Marriott | | | | | | | |
| Deploying Customized Solution for Graphics Registers with UVM1.2 RAL | Roman Wang, Nigel Wang, Lunping Guo, Robert Liu, and Jia Zhu | | | | | | | |
| Deploying Customized Solution for Graphics Registers with UVM1.2 RAL | Roman Wang, Nigel Wang, Lunping Guo, Robert Liu, and Jia Zhu | | | | | | | |
| Deploying HLS in a DO-254/ED-80 Workflow | Byron Brinson Jacob Wiltgen, David Aerne and Tammy Reeve | | | | | | | |
| Deploying HLS in a DO-254/ED-80 Workflow | Tammy Reeve, Jacob Wiltgen, Byron Brinson, and David Aerne | | | | | | | |
| Deploying Parameterized Interface with UVM | Wayne Yun and Shihua Zhang | | | | | | | |
| DEPLOYING PARAMETERIZED INTERFACE WITH UVM | Wayne Yun and Shihua Zhang | | | | | | | |
| Design & Verify Virtual Platform with reusable TLM 2.0 | Ankush Kumar | | | | | | | |
| Design and verification in ARM | Hobson Bullman | | | | | | | |
| Design and Verification of a Multichip Coherence Protocol | Shahid Ikram, Isam Akkawi, Richard Kessler, Jim Ellis, and David Asher | | | | | | | |
| Design and Verification of a Multichip Coherence Protocol | Shahid Ikram, Isam Akkawi, Richard Kessler, Jim Ellis, and David Asher | | | | | | | |
| Design and Verification of an Image Processing CPU using UVM | Milos Becvar and Greg Tumbush | | | | | | | |
| Design and Verification of an Image Processing CPU Using UVM | Greg Tumbush and Milos Becvar | | | | | | | |
| Design and Verification of the PLL using the new DCO and Its Applications to Built-In Speed Grading of Arithmetic Circuits | Yi-Sheng Wang, Hsiang-Kai Teng, Shi-Yu Huang | | | | | | | |
| Design Guidelines for Formal Verification | Anamaya Sullerey | | | | | | | |
| Design Guidelines for Formal Verification | Anamaya Sullerey | | | | | | | |
| Design Methodology for Highly Cycle Accurate SystemC Models with Better Performance | Simranjit Singh, Prasanth Sasidharan, Sameer Deshpande, and Sandeep Puttappa | | | | | | | |
| Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012 | Eldon Nelson M.S. P.E. | | | | | | | |
| Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012 | Eldon Nelson | | | | | | | |
| Design space exploration of PIM (Processing in Memory) & PNC (Processing Near Memory) based on workload characterization | Amarnath, Judhajit | | | | | | | |
| Design verification of a cascaded mmWave FMCW Radar | Shweta Pujar, Vijay M, Sainath Karlapalem, Dharani Sharavanan, Kavya P S | | | | | | | |
| Design Verification of the Quantum Control Stack | Seyed Amir Alavi, Samin Ishtiaq, Nick Johnson, Rojalin Mishra, Dwaraka O N, Asher Pearl and Jan Snoeijs | | | | | | | |
| Designers Work Less with Quality Formal Equivalence Checking | Orly Cohen, Moran Gordon, Michael Lifshits, Alexander Nadel, and Vadim Ryvchin | | | | | | | |
| Designing A PSS Reuse Strategy | Matthew Ballance | | | | | | | |
| Designing a PSS Reuse Strategy | Matthew Ballance | | | | | | | |
| Designing a PSS Reuse Strategy | Matthew Ballance | | | | | | | |
| Designing Portable UVM Test Benches for Reusable IPs | XIAONING ZHANG and BAOSHENG WANG | | | | | | | |
| Designing Portable UVM Test Benches for Reusable IPs | Xiaoning Zhang, Baosheng Wang, and Terry Li | | | | | | | |
| Designing PSS Environment Integration for Maximum Reuse | Matthew Ballance | | | | | | | |
| Designing PSS Environment Integration for Maximum Reuse | Matthew Ballance | | | | | | | |
| Designing the Future with Efficiency Guidance to Adopting SystemVerilog for Design! | Axel Scherer and Junette Tan | | | | | | | |
| Designing, Verifying and Building an Advanced L2 Cache Sub-System using SystemC | Thomas Tessier, Dr. Hai Lin, Daniel Ringoen, Eileen Hickey, and Steven Anderson | | | | | | | |
| Designing, Verifying and Building an Advanced L2 Cache Subsystem using SystemC | Steve Frank, Thomas Tessier, Dr. Hai Lin, Daniel Ringoen, Eileen Hickey, and Steven Anderson | | | | | | | |
| Detecting Circular Dependencies in Forward Progress Checkers | Saurabh Chaurdia, Arun Khurana, Naveen Kumar, Aditya Chaurasiya, Yogesh Mahajan, Prasenjit Biswas | | | | | | | |
| Detecting Harmful Race Conditions in SystemC Models Using Formal Techniques | Sven Beyer and Dominik Strasser | | | | | | | |
| Detecting Harmful Race Conditions in SystemC Models Using Formal Techniques | Sven Beyer and Dominik Strasser | | | | | | | |
| Detection of glitch-prone clock and reset propagation with automated formal analysis | Kaushal Shah, Sulabh Kumar Khare | | | | | | | |
| Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions | Kelly D. Larson | | | | | | | |
| Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions | Kelly D. Larson | | | | | | | |
| Detoxify Your Schedule With A Low-Fat UVM Environment | Nihar Shah | | | | | | | |
| Detoxify Your Schedule With A Low-Fat UVM Environment A success story on using self-checking stimulus instead of a scoreboard to reduce development time | Nihar Shah | | | | | | | |
| Developing & Testing Automotive Software on Multi SoC ECU Architectures using Virtual Prototyping | Sam Tennent | | | | | | | |
| Developing a Portable Block Testbench and Reusable SOC Verification Scenarios Using IP XACT Based Automation | Taejin Kim, Minjae Kim, Yonghyun Yang, Hyundon Kim, Daewoo Kim, Tae Hee Han, and Seonil Brian Choi | | | | | | | |
| Developing Dynamic Resource Management System in SoCEmulation | Seonchang Choi, Sangwoo Noh, Seonghee Yim and Seonil Brian Choi | | | | | | | |
| Developing Dynamic Resource Management System in SoCEmulation | Seonchang Choi and Seonghee Yim | | | | | | | |
| Development and Verification of RISC-V Based DSP Subsystem IP: Case Study | Pascal Gouedo, Damien Le Bars, Olivier Montfort, Lee Moore, Aimee Sutton, Larry Lapides | | | | | | | |
| Development of a Core-Monitor for HW/SW Co-Debugging targetting Emulation Platform | Shreya Morgansgate, Johannes Grinschgl, Djones Lettnin | | | | | | | |
| Development of Flexi Performance Analysis Platform for Multi–SoC Networking Systems | Srinivasan Reddy Devarajan, Anant Raj Gupta, IngoVolkening, Franz Josef Schaefer and Vijay Raj Franklin Paul Rajan William | | | | | | | |
| Did Power Management Break My CDC Logic? An Integrated Approach to Power Domain and Clock Domain Crossing Verification | Ashish Amonkar, Kurt Takara, and Avinash Agrawal | | | | | | | |
| Differentiating with Custom Compute and Use Case Intro | Shigehiko Ito | | | | | | | |
| Digital Eye For Aid of Blind People | Jagu Naveen Kumar, Pabbuleti Venu | | | | | | | |
| Digital mixed-signal low power verification with Unified Power Format (UPF) | Srilakshmi D R and Geeta Krishna Chaitanya Puli | | | | | | | |
| Digital mixed-signal low power verification with Unified power format (UPF) | Srilakshmi D R and Geeta Krishna Chaitanya Puli | | | | | | | |
| Digital Transformation of EDA Environments To Accelerate Semiconductor Innovation | Guru Charan Prasad Jonnalagadda | | | | | | | |
| Digitizing Mixed Signal Verification | David Brownell and Courtney Schmitt | | | | | | | |
| Digitizing Mixed Signal Verification: Digital Verification Techniques Applied to Mixed Signal and Analog Blocks on the LMA Project | David Brownell and Courtney Schmitt | | | | | | | |
| Disaggregated methodology in Multi-die SoC– A Server SoC Case Study | Rohit Kumar Sinha | | | | | | | |
| Disaggregated methodology in Multi-die SoC– A Server SoC Case Study | Rohit Kumar Sinha | | | | | | | |
| Disciplined Post Silicon Validation using ML Intelligence | Amaresh Chellapilla, Pandithurai Sangaiyah | | | | | | | |
| Discover Over-Constraints by Leveraging Formal Tool | Dongsheng Ouyang, Ray Zhang, Lucas Liu, Doris Yin, Wayne Ding | | | | | | | |
| Discover Over-Constraints by Leveraging Formal Tool | Dongsheng Ouyang, Ray Zhang, Lucas Liu, Doris Yin, Wayne Ding | | | | | | | |
| Discovering Deadlocks in a Memory Controller IP | Jef Verdonck, Emrah Armagan, Khaled Nsaibia, Slava Bulach, Pranay Gupta, Anshul Jain, Chirag Agarwal and Roger Sabbagh | | | | | | | |
| Discovering Deadlocks in a Memory Controller IP | Jef Verdonck, Emrah Armagan, Khaled Nsaibia, Slava Bulach, Pranay Gupta, Anshul Jain, Chirag Agarwal, and Roger Sabbagh | | | | | | | |
| Distributed Simulation of UVM Testbench | Theta Yang | | | | | | | |
| Distributed Simulation of UVM Testbench | Theta Yang | | | | | | | |
| Do not forget to ‘Cover’ your SystemC code with UVMC | Vishal Baskar | | | | | | | |
| Do not forget to ‘Cover’ your SystemC code with UVMC | Vishal Baskar | | | | | | | |
| Do not forget to ‘Cover’ your SystemC code with UVMC | Vishal Baskar | | | | | | | |
| Do You Know What Your Assertions Are Up To? A New Approach to Safety Critical Verification | Lee C. Smith | | | | | | | |
| Do You Know What Your Assertions Are up To? A New Approach to Safety Critical Verification | Lee C. Smith | | | | | | | |
| Do You Verify Your Verification Components? | Josh Rensch and Neil Johnson | | | | | | | |
| Does It Pay Off To Add Portable Stimulus Layer On Top Of UVM IP Block Test Bench? | Xia Wu, Jacob Sander Andersen and Ole Kristoffersen | | | | | | | |
| Does It Pay Off To Add Portable Stimulus Layer On Top Of UVM IP Block Test Bench? | Xia Wu, Jacob Sander Andersen, and Ole Kristoffersen | | | | | | | |
| Doing Funny Stuff with the UVM Register Layer: Experiences Using Front Door Sequences, Predictors, and Callbacks | John Aynsley | | | | | | | |
| Doing Funny Stuff with the UVM Register Layer: Experiences Using Front Door Sequences, Predictors, and Callbacks | John Aynsley | | | | | | | |
| Doing the Impossible: Using Formal Verification on Packet Based Data Paths | Doug Smith | | | | | | | |
| Doing the Impossible: Using Formal Verification on Packet Based Data Paths | Doug Smith | | | | | | | |
| Don’t delay catching bugs: Using UVM based architecture to model external board delays | Amit Paunikar, Saurabh Arya, Vikas Makhija, and Shaily Khare | | | | | | | |
| Don’t delay catching bugs: Using UVM based architecture to model external board delays | Amit Paunikar, Saurabh Arya, Vikas Makhija, and Shaily Khare | | | | | | | |
| Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon | Abdelouahab Ayari, Sukriti Bisht, Sulabh Kumar Khare, and Kurt Takara | | | | | | | |
| Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon | Abdelouahab Ayari, Sukriti Bisht, Sulabh Kumar Khare and Kurt Takara | | | | | | | |
| Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to Simulation | Jonathan Bromley | | | | | | | |
| Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to Simulation | Jonathan Bromley | | | | | | | |
| DPI Redux. Functionality. Speed. Optimization. | Rich Edelman, Rohit Jain, and Hui Yin | | | | | | | |
| DPI Redux. Functionality. Speed. Optimization. | Rich Edelman, Rohit Jain, and Hui Yin | | | | | | | |
| Dr. Shahid Ikram, Distinguished Engineer, Marvell Semi Mark Eslinger, Product Engineer, Siemens | Daniel Cross | | | | | | | |
| Driving Analog Stimuli from a UVM Testbench | Satvika Challa, Amlan Chakrabarti | | | | | | | |
| DSA Monitoring Framework for HW/SW Partitioning of Application Kernels leveraging VP | Christoph Hazott, Daniel Große | | | | | | | |
| DSA Monitoring Framework for HW/SW Partitioning of Application Kernels leveraging VPs | Christoph Hazott; Daniel Grosse | | | | | | | |
| DV Methodology to Model Scalable/Reusable Component to Handle IO Delays/Noise/Crosstalk in Multilane DDR PHY IF | Tapas Ranjan Jena, Gowdra Bomanna Chethan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | | | |
| DV UVM based AMS co-simulation and verification methodology for mixed signal designs | Sandeep Sharma | | | | | | | |
| DV UVM based AMS co-simulation and verification methodology for mixed signal designs | Sandeep Sharma | | | | | | | |
| DVCon EU 2014 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon EU 2015 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon EU 2016 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon EU 2017 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon EU 2018 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon EU 2019 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon EU 2020 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon EU 2020 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon EU 2021 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon Europe 2015 Road to self driving cars: View of a semiconductor company | Hans Adlkofer | | | | | | | |
| DVCon Europe 2022 Proceedings Showcase Link | Accellera Systems Initiative | | | | | | | |
| DVCon India 2021 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon India 2022 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon JP 2022 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon JP 2023 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon U.S 2021 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon U.S. 2021 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon U.S. 2022 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon US 2022 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon US 2023 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVCon USA 2023 Proceedings | Accellera Systems Initiative | | | | | | | |
| DVS Interface Element – A Novel Approach in Multi-Power Domain, Mixed-Signal Design Verification | Vijay Kumar Sankaran, Ji Du, Qingyu Lin, Arumugan A, and Badrinarayan Zanwar | | | | | | | |
| DVS Interface Element—A Novel Approach in Multi-Power Domain, Mixed-Signal Design Verification | Shekar Chetput | | | | | | | |
| Dynamic and Scalable OVM Stimulus for Accelerated Functional Coverage | Michael J Castle | | | | | | | |
| Dynamic Control Over UVM Register Backdoor Hierarchy | Roy Vincent, Unnikrishnan Nath, and Ashok Chandran | | | | | | | |
| Dynamic Fault Injection Library Approach for SystemC AMS | Thomas Markwirth, Paul Ehrlich, and Dominik Matter | | | | | | | |
| Dynamic Fault Injection Library Approach for SystemC AMS | Thomas Markwirth, Paul Ehrlich, and Dominik Matter | | | | | | | |
| Dynamic Parameter Configuration of SystemC Models | Shruti Baindur, Simranjit Singh | | | | | | | |
| Dynamic Power Automation UVM Framework | Raghavendra J N, Gudidevuni Harathi | | | | | | | |
| Dynamic Regression Suite Generation Using Coverage-Based Clustering | Shahid Ikram and Jim Ellis | | | | | | | |
| Dynamic Regression Suite Generation Using Coverage-Based Clustering | Shahid Ikram and Jim Ellis | | | | | | | |
| Dynamically Optimized Test Generation Using Machine Learning | Rajarshi Roy, Mukhdeep Singh Benipal, Saad Godil | | | | |
