A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power Intent

Today’s complex, low-power analog and mixed-signal (AMS) systems on chip (SoCs) are comprised of logic (boolean, real) and transistor-level abstractions for design implementation, verification, validation, and test readiness. This situation mandates extensive use of AMS co-simulation[1][2][3] . Such designs are increasingly becoming power managed with multiple power/multi-voltage domains by nature. There are various techniques for verification and validation of these low-power designs, but most of them either have dependencies on the block-level designer to use the right power domain for a multi-power design, or require lot of manual effort for setting up the flow, which is error prone. This paper discusses the verification of AMS SoCs in a very effective way by using the power intent information in the form of Common Power Format (CPF). We begin with discussing the traditional methods [4][5][6] used for insertion of interface elements (IEs), also called connect modules (CMs), to handle inter-discipline signal traversal, followed by how AMS-CPF based IEs proved to be very simple, straightforward, and accurate for top-level co-simulation.