DVCon Papers, Posters, Presentations
and Video Archive

DVCon brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design.

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TitleAuthor(s)YearTypeLinkevent_year_hfilterdocument_type_hfilter
“Bounded Proof” sign-off with formal coverageAbhishek Anand, Chinyu Chen, Bathri Narayanan Subramanian, Joe Hupcey2021Paper2021paper
“C” you on the faster side: Accelerating SV DPI based co-simulationParag Goel, Amit Sharma, and Hari Vinodh Balisetty2014Paper2014paper
“C” you on the faster side: Accelerating SV DPI based co-simulationHari Vinod Balisetty, Parag Goel, and Amit Sharma2014Presentation2014presentation
“In-Emulator” UVM++ Randomized Testbenches for High Performance Functional VerificationAdnan Hamid and David Kelf2022Presentation2022presentation
“Shift left” Hierarchical Low-Power Static Verification Using SAMBharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal2020Paper2020paper
“Shift left” Hierarchical Low-Power Static Verification Using SAMBharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal2020Poster2020poster
“What-If” analysis of Safety Mechanism’s impacts on ETHMAC design under Functional Safety flowUdaykrishna J, Sujatha Hiremath, Kapil Kumar, Sachin Pathak, Gaurav Goel2022Presentation2022presentation
1,2,3,…8 simple steps towards a single digital signal processing testbench supporting heterogeneous interfaces and datatypesNico Lugil2016Presentation2016presentation
1,2,3,…8 simple steps towards a single digital signal processing testbench supporting heterogeneous interfaces and datatypesNico Lugil2016Paper2016paper
5.1 Smart Verification leveraging PSS; 5.2 When Automotive FuSa Met ICDavid Hwang and Sera Gao2021Presentation2021presentation
5G – Chances and Challenges from Test & Measurement PerspectiveMeik Kottkamp2017Presentation2017presentation
5G / NR Explained From 3GPP 5G Standard Fundamentals To 5G Enabled VerticalsMichael Faerber and Kilian Roth2019Presentation2019presentation
5G for people and things Spectrum Opportunities and Challenges of 5G2017Presentation2017presentation
A 30 Minute Project Makeover Using Continuous IntegrationJL Gray2012Paper2012paper
A 30 Minute Project Makeover Using Continuous IntegrationJL Gray and Gordon McGregor2012Presentation2012presentation
A 360 Degree View of UVM EventsVikas Billa, Nagesh Kokonda2017Presentation2017presentation
A 360 Degree View of UVM Events – A Case StudyDeepak Kumar E V, Sathish Dadi, and Vikas Billa2016Paper2016paper
A 360 Degree View of UVM Events (A Case Study)Deepak Kumar E V, Sathish Dadi, and Vikas Billa2016Presentation2016presentation
A Client-Server Method for Register Design and DocumentationScott D Orangio and Julien Gagnon2016Paper2016paper
A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISC V CoreJunaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, Aashir Ahsan2022Presentation2022presentation
A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISCV CoreJunaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, and Aashir Ahsan2022Paper2022paper
A comparison of methodologies to simulate mixed-signal ICSimone Fontanesi, Karsten Einwich, Paul Ehrlich, Gaetano Formato, Andrea Possemato2021Paper2021paper
A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance AnalysisBishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel2016Poster2016poster
A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance Analysis.Bishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel2016Paper2016paper
A Comprehensive Verification Platform for RISC-V based ProcessorsEmre Karabulut, Berk Kisinbay, Abdullah Yildiz, and Rifat Demircioglu 2020Presentation2020presentation
A Comprehensive Verification Platform for RISC-V based ProcessorsEmre Karabulut, Berk Kisinbay, Abdullah Yildiz and Rifat Demircioglu2020Paper2020paper
A concept for expanding a UVM testbench to the analog-centric toplevelFelix Assmann, Axel Strobel and Hans Zander2015Paper2015paper
A concept for expanding a UVM testbenchto the analog-centric toplevelFelix Assmann, Axel Strobel and Hans Zander2015Poster2015poster
A Coverage-Driven Formal Methodology for Verification Sign-offAng Li, Hao Chen, Jason K Yu, Ee Loon Teoh, and Iswerya Prem Anand2019Paper2019paper
A Coverage-Driven Formal Methodology for Verification Sign-offAng Li, Hao Chen, Jason K Yu, Ee Loon Teoh and, Iswerya Prem Anand2019Presentation2019presentation
A Dyadic Transformation Based Methodology To Achieve Coverage Driven Verification GoalSwapnajit Mitra2017Presentation2017presentation
A Dyadic Transformation Based Methodology to Achieve Coverage Driven Verification GoalSwapnajit Mitra2017Paper2017paper
A Dynamic Approach Towards Register Coverage Generation and Collection to Reduce Compilation Overhead of Traditional UVM Register LayersSubham Banerjee2020Presentation2020presentation
A Formal Verification App Towards Efficient Chip-Wide Clock Gating VerificationProsenjit Chatterjee, Scott Fields, and Syed Suhaib2014Presentation2014presentation
A Formal Verification App Towards Efficient, Chip-Wide Clock Gating VerificationProsenjit Chatterjee, Scott Fields, and Syed Suhaib2014Paper2014paper
A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog-AMSMike Bartley, Jeganath Gandhi R2014Paper2014paper
A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog-AMSMike Bartley and Jeganath Gandhi R2014Paper2014paper
A Framework for Verification of Program Control Unit of VLIW processorsSanthosh Billava, Sharangdhar M Honwadkar2014Presentation2014presentation
A Framework for Verification of Program Control Unit of VLIW ProcessorsSanthosh Billava, Sharangdhar M Honwadkar2014Paper2014paper
A Generic Approach to Handling Sideband SignalsMarkus Brosch and Salman Tanvir2019Presentation2019presentation
A Generic Configurable Error Injection Agent for All On-Chip MemoriesNiharika Sachdeva, Arjun Suresh Kumar, Raviteja Gopagiri, Anil Deshpande, Somasunder Kattepura Sreenath, Damandeep Saini2022Presentation2022presentation
A Guide To Using Continuous Integration Within The Verification EnvironmentJason Sprott2014Presentation2014presentation
A Guide To Using Continuous Integration Within The Verification EnvironmentJason Sprott, André Winkelmann, and Gordon McGregor2014Paper2014paper
A Guide To Using Continuous Integration Within The Verification EnvironmentAndré Winkelmann, Jason Sprott, and Gordon McGregor2014Poster2014poster
A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power IntentVijay Kumar Sankaran, Lakshmanan Balasubramanian, Bharath Kumar Poluri, Venkatraman Ramakrishnan, Badrinarayan Zanwar, and Qingyu Lin2016Paper2016paper
A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power IntentQingyu Lin2016Poster2016poster
A Holistic Overview on Preventive & Corrective Action To Handle GlitchesRohit Kumar Sinha, Parimal Das2022Poster2022poster
A Holistic View of Mixed-Language IP IntegrationPankaj Singh and Gaurav Kumar Verma2010Paper2010paper
A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGAAntonis Papagrigoriou, Miltos D. Grammatikakis and Voula Piperaki2018Presentation2018presentation
A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGA*Antonis Papagrigoriou, Antonis Papagrigoriou and Voula Piperaki2018Paper2018paper
A Hybrid Verification Solution to RISC V Vector ExtensionChenghuan Li, Yanhua Feng, Liam Li2022Presentation2022presentation
A Hybrid Verification Solution to RISC-V Vector ExtensionChenghuan Li, Yanhua Feng, and Liam Li2022Paper2022paper
A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance CorrelationThomas Soong, Christopher Browne, and Chenhui Huang2022Poster2022poster
A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance CorrelationThomas Soong, Chenhui Huang, and Christopher Browne2022Paper2022paper
A Meta-Model-Based Approach for Semantic Fault Modeling on Multiple Abstraction LevelsMichael Schwarz and Moomen Chaari, Bogdan-Andrei Tabacaru2015Paper2015paper
A Meta-Model-Based Approach for Semantic Fault Modeling on Multiple Abstraction LevelsM. Schwarz M. Chaari, B.-A. Tabacaru, and W. Ecker2015Presentation2015presentation
A Meta-Modeling-Based Approach for Automatic Generation of Fault-Injection ProcessesBogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, and Thomas Kruse2014Paper2014paper
A Meta-Modeling-Based Approach for Automatic Generation of Fault-Injection ProcessesB.-A. Tabacaru, M. Chaari, W. Ecker, and T. Kruse2014Presentation2014presentation
A Method to Accelerate SoC Implementation Cycle by Automatically Generating CDC ConstraintsAshish Hari, Sulabh Kumar Khare2015Presentation2015presentation
A Methodology for Evaluating SI Artefacts in DDR4-3DS PHY using Channel ModellingAditya S Kumar, Gowdra Bomanna Chethan, Shivani Maurya, Anil Deshpande, Somasunder Kattepura Sreenath2021Paper2021paper
A Methodology for Interrupt Analysis in Virtual PlatformsPuneet Dhar2015Presentation2015presentation
A Methodology for Using Traffic Generators with Real-Time ConstraintsAvinash Mehta2015Presentation2015presentation
A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation AccelerationHorace Chan, Brian Vandegriend, and Efrat Shneydor2015Paper2015paper
A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation AccelerationHorace Chan, Brian Vandegriend, and Efrat Shneydor2015Presentation2015presentation
A Methodology to Reuse Unit Level Validation InfrastructureAshutosh Parkhi2017Presentation2017presentation
A Methodology to Verify Functionality, Security, and Trust for RISC-V CoresW. W. Chen, N. Tusinschi, and T. L. Anderson2020Presentation2020presentation
A Methodology to Verify Functionality, Security, and Trust for RISC-V CoresW. W. Chen, N. Tusinschi and T. L. Anderson2020Paper2020paper
A Metric-driven Methodology For Firmware Verification In Simulation/Emulation EnvironmentsGoran Savić2016Paper2016paper
A Mixed Signal System Design Methodology in SystemC AMS for Automotive Audio Power AmplifiersSkule Pramm, Joen Westendorp, and Quino Sandifort2019Paper2019paper
A Mutually-Exclusive Deployment of Formal and Simulation Techniques Using Proof-Core AnalysisKeerthikumara Devarajegowda, Jeroen Vliegen, Goran Petrovity, and Kawe Fotouhi2017Presentation2017presentation
A Mutually-Exclusive Deployment of Formal and Simulation Techniques Using Proof-Core AnalysisKeerthikumara Devarajegowda, Jeroen Vliegen, Goran Petrovity, and Kawe Fotouhi2017Paper2017paper
A New Approach for Generating View GeneratorsJohannes Schreiner, Felix Willgerodt, and Wolfgang Ecker2017Paper2017paper
A New Approach for Generating View GeneratorsJohannes Schreiner, Felix Willgerodt, and Wolfgang Ecker2017Poster2017poster
A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain CrossingsOmri Dassa, Yossi Mirsky2022Presentation2022presentation
A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain CrossingsOmri Dassa and Yossi (Joseph) Mirsky2022Paper2022paper
A New Approach to Low-Power Verification: Low Power AppsMadhur Bhargava and Awashesh Kumar2018Paper2018paper
A New Class Of RegistersMark Peryer and David Aerne2016Poster2016poster
A New Class Of RegistersM. Peryer and D. Aerne2016Paper2016paper
A New Epoch is Beginning: Are You Getting Ready for Stepping Into UVM-1.2?Roman Wang, Uwe Simm2014Poster2014poster
A New Epoch is Beginning: Are You Getting Ready for Stepping Into UVM-1.2?Roman Wang,Uwe Simm2014Paper2014paper
A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM DomainsSubham Banerjee and Keshava Krishna Raja2017Paper2017paper
A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM Domains2017Poster2017poster
A Novel Approach to Functional Test Development and Execution using High-Speed IOMarcus Schulze Westenhorst, Jörg Simon, Markus Bücker, Klaus Dieter Hilliges, Michael Braun2021Paper2021paper
A Novel Approach To In-System SRAM Repair Verification in Embedded SoC to Bridge Gap between Test and Functional ModeHarshal Kothari, Eldin Ben Jacob, Ajay Vamshi Krishna, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath2021Paper2021paper
A Novel Approach to Reduce Power Consumption By Bridging The Gap between Standalone Functional Scenario and Real Time Scenario at SOCEldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Poster2022poster
A Novel Approach to Reuse Firmware for Verification of Controller based Sub-Systems using PSSVishnu Ramadas, Simranjit Singh, Ashwani Aggarwal, Woojoo Space Kim , Seonil Brian Choi2021Paper2021paper
A Novel Approach to Verify CNN Based Image Processing UnitSumit K. Kulshreshtha, Raghavendra J N2021Paper2021paper
A Novel Performance Evaluation Methodology using Virtual Prototyping and EmulationWoojooSpace Kim2019Presentation2019presentation
A Novel Performance Evaluation Methodology using Virtual Prototyping and EmulationWoojoo Space Kim2018Presentation2018presentation
A Novel Processor Verification Methodology based on UVMAbhineet Bhojak, Tejbal Prasad, and Stephan Herrmann2015Paper2015paper
A Novel Variation-Aware Mixed-Signal Verification Methodology to achieve High-Sigma Variation coverage at nanometer designsTibi Galambos, Sumit Vishwakarma2021Paper2021paper
A Practical Approach to Measuring and Improving the Functional Verification of Embedded SoftwareStéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès2012Paper2012paper
A Practical Approach to Measuring and Improving the Functional Verification of Embedded SoftwareStéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès2012Presentation2012presentation
A Practical Look @ SystemVerilog Coverage – Tips, Tricks, and GotchasDoug Smith and John Aynsley2011Paper2011paper
A Pragmatic Approach Leveraging Portable Stimulus from Subsystem to SoC level and SoC EmulationKarandeep Singh, Aditya Chopra, Joachim Geishauser, Nitin Verma2019Presentation2019presentation
A Pragmatic Approach Leveraging Portable Stimulus from Subsystem to SoC level and SoC EmulationKarandeep Singh, Aditya Chopra, Joachim Geishauser, Nitin Verma2019Paper2019paper
A Pragmatic Approach to Metastability-Aware SimulationJoseph Bulone, Roger Sabbagh2014Paper2014paper
A Pragmatic Approach to Metastability-Aware SimulationJoseph Bulone, Roger Sabbagh2014Presentation2014presentation
A real world application of IP-XACT for IP packaging Bridging the usability gapPhilip Todd2014Paper2014paper
A real world application of IP-XACT for IP packaging Bridging the usability gapPhilip Todd2014Presentation2014presentation
A Real-World Clock Generator Class for UVMRhitam Datta, Ankit Somani2017Presentation2017presentation
A Recipe for swift Tape-out of Derivative SoCs: A Comprehensive Validation Approach using Formal-based Sequential Equivalence and Connectivity CheckingPriyanshu Jain, Saket Gaddagi, Sandeep Kumar and Ipshita Tripathi2022Presentation2022presentation
A Reusability Combat in UVM Callbacks vs FactoryDeepak Kumar EV, Vikas Billa, Satish Dadi, Ranganath Kempanahally2015Poster2015poster
A Reusable, Scalable Formal App for Verifying Any Configuration of 3D IC ConnectivityDaniel Han, Walter Sze, Benjamin Ting, and Darrow Chu2013Paper2013paper
A scalable framework to validate interconnect-based firewalls to enhance SoC security coverageAshutosh Mishra, Suresh Vasu2022Presentation2022presentation
A Semi-Formal Verification Methodology for Efficient Configuration Coverage of Highly Configurable Digital DesignsAman Kumar, Sebastian Simon2021Paper2021paper
A Simplified Approach Using UVM Sequence Items for Layering Protocol VerificationHaiqian Yu and Christine Thomson2017Paper2017paper
A Simplified Approach Using UVM Sequence Items for Layering Protocol VerificationChristine Thomson and Haiqian Yu2017Presentation2017presentation
A single generated UVM Register Model to handle multiple DUT configurationsSalvatore Marco Rosselli and Giuseppe Falconeri2020Presentation2020presentation
A SMART GENERATION OF DESIGN ATTRIBUTES FOR VERIFICATION CLOSURE USING SPECMANMeirav Nitzan, Yael Kinderman, and Efrat Gavish2013Poster2013poster
A Smart Synchronizer – Pragmatic way to cross asynchronous clock domainsPriyank Parakh and Steven J Kommrusch2011Paper2011paper
A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing LogicPriya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed2018Paper2018paper
A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing LogicPriya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed2018Poster2018poster
A Step Towards Zero Silicon Bugs Using Assertion Based Assumption ValidationRohit Kumar Sinha and Babu Christie2020Paper2020paper
A Step towards Zero Silicon Bugs: SVA Protocol Based Assumption ValidationRohit Kumar Sinha and Babu Christie2020Poster, Presentation2020poster presentation
A Structured Approach to verify Ties, Unconnected Signals and ParametersSaurabh Singh, Peter Limmer, and Thomas Luedeke2016Presentation2016presentation
A Structured Approach to verify Ties, Unconnected Signals and ParametersSaurabh Singh, Peter Limmer, and Thomas Luedeke2016Paper2016paper
A Systematic Approach to Power State Table (PST) DebuggingBhaskar Pal, Suman Nandan, Kaushik De, and Rajarshi Mukherjee2013Paper2013paper
A Systematic Approach to Power State Table (PST) DebuggingBhaskar Pal2013Presentation2013presentation
A Systematic Formal Reuse Methodology: From Blocks to SoC SystemsHao Chen, Yi Sun, Ang Li, and Dorry Cao2020Presentation2020presentation
A Systematic Methodology for Verifying Clock Domain Crossing ReconvergencePriya Viswanathan2017Presentation2017presentation
A Systematic Take on Addressing Dynamic CDC Verification ChallengesSukriti Bisht, Sulabh Kumar Khare, and Ashish Hari2019Paper2019paper
A Systematic Take on Addressing Dynamic CDC Verification ChallengesSukriti Bisht, Sulabh Kumar Khare, and Ashish Hari2019Presentation2019presentation
A SystemC Library for Advanced TLM VerificationMarcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen2012Paper2012paper
A SystemC Library for Advanced Verification – Towards an Enhanced OVM/UVM for SystemCMarcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen2012Presentation2012presentation
A SystemC-based UVM verification infrastructureMike Bartley and Harshavardhan Narla2015Paper2015paper
A SystemC-based UVM verification infrastructureMike Bartley and Harshavardhan Narla2015Poster2015poster
A SystemVerilog Framework for Easy Method Advice in Object-oriented Test BenchesEric Ohana2013Poster2013poster
A SystemVerilog Framework for Easy Method Advice in Object-oriented Test BenchesEric Ohana2013Paper2013paper
A SystemVerilog Framework for Efficient Randomization of Images with Complex Inter-Pixel DependenciesAxel Voss, Gabriel Jönsson, and Lars Viklund2020Presentation2020presentation
A Tale of Two Languages – SystemVerilog and SystemCDavid C Black2013Paper2013paper
A Tale of Two Languages: SystemVerilog & SystemCDavid C Black2013Presentation2013presentation
A Unified Framework for Multilanguage Verification IPs IntegrationSurinder Sood, Selvakumar Krishnamoorthy, Guarav Jalan2015Presentation2015presentation
A Unified Testbench Architecture Solution for Verifying Variants of A PLL IPDeepa Ananthanarayanan and Malathi Chikkanna2015Presentation2015presentation
A Unified Testbench Architecture Solution for Verifying Variants of the PLL IPDeepa Ananthanarayanan and Malathi Chikkanna2015Paper2015paper
A Universal DFT Verification Environment: Filling the Gap between Function Simulation and ATE TestRui Huang2016Presentation2016presentation
A Universal DFT Verification Environment: Filling the Gap between Function Simulation and ATE TestRui Huang2016Paper2016paper
A UVM Based Methodology for Processor VerificationAbhineet Bhojak, Stephan Herrmann, and TejbalPrasad2015Presentation2015presentation
A UVM Based Methodology for Processor VerificationAbhineet Bhojak, Tejbal Prasad2015Presentation2015presentation
A UVM SystemVerilog Testbench for Analog/Mixed-Signal Verification: A Digitally-Programmable Analog Filter ExampleCharles Dančak2022Paper2022paper
A UVM Testbench for Analog Verification: A Programmable Filter ExampleCharles Dančak2022Presentation2022presentation
A UVM-based Approach for Rapidly Verifying Digital Interrupt StructuresChristoph Rumpler, Alexander W. Rath, and Sebastian Simon2016Presentation2016presentation
A UVM-based Approach for Rapidly Verifying Digital Interrupt StructuresChristoph Rumpler, Alexander W. Rath, Sebastian Simon, and Heinz Endres2016Paper2016paper
A Volterra-Series Model in SystemVerilog/XMODEL for Nonlinear RF Low-Noise AmplifiersChan Young Park, Jaeha Kim2021Paper2021paper
Absolute GLS Verification An Early Simulation of Design Timing ConstraintsAteet Mishra, Deepak Mahajan, Shiva Belwal2015Presentation2015presentation
Abstract Layer for Firmware Access: A Unique Approach for SOC Functional VerificationGupta Girish Kumar, Rugmini Navia Vishnu, Choudhary Praval, Syed Mobeenuddin2021Paper2021paper
Accelerated Coverage Closure by Utilizing Local Structure in the RTL CodeRhys Buggy, Gokce Sarar, Guillaume Shippee, Han Nuou, Vishal Karna, Tushit Jain2021Paper2021paper
Accelerated simulation through design partition and HDL to C++ compilationTheta Yang2017Presentation2017presentation
Accelerated simulation through design partition and HDL to C++ compilationTheta Yang and Sga Sun2017Paper2017paper
Accelerated SOC verification Using UVM Methodology for a Mix-signal Low Power DesignGiuseppe Scata, Ashwini Padoor, Vladimir Milosevic2014Paper2014paper
Accelerated SOC Verification Using UVM Methodology for a Mixed-Signal Low Power DesignGiuseppe Scata, Ashwini Padoor, Vladimir Milosevic2014Presentation2014presentation
Accelerated, High Quality SoC Memory Map Verification using Formal TechniquesCletan Sequeira, Rajesh Kedia, Lokesh Babu Pundreeka, and Bijitendra Mittra2014Paper2014paper
Accelerated, High Quality SoC Memory Map Verification using Formal TechniquesCletan Sequeira, Rajesh Kedia, Lokesh Babu Pundreeka, and Bijitendra Mittra2014Presentation2014presentation
Accelerating and Improving FPGA Design Reviews Using Analysis ToolsAnna Tseng, Kurt Takara and Abdelouahab Ayari2020Paper2020paper
Accelerating and Improving FPGA Design Reviews Using Analysis ToolsAbdelouahab Ayari, Anna Tseng, and Kurt Takara2020Presentation2020presentation
Accelerating Automotive Ethernet validation by leveraging Synopsys Virtualizer with TraceCompassAshish Gandhi, Praveen Kumar Kondugari and Sam Tennent2020Paper2020paper
Accelerating Automotive Ethernet validation by leveraging Synopsys Virtualizer with TraceCompassAshish Gandhi, Praveen Kumar Kondugari, and Sam Tennent2020Presentation2020presentation
Accelerating CDC Verification Closure on Gate-Level DesignsAnwesha Choudhury and Ashish Hari2017Presentation2017presentation
Accelerating CDC Verification Closure on Gate-Level DesignsAnwesha Choudhury and Ashish Hari2017Paper2017paper
Accelerating Error Handling Verification Of Complex Systems: A Formal ApproachBhushan Parikh, Peter Graniello, Neha Rajendra2022Presentation2022presentation
Accelerating Error Handling Verification of Complex Systems: A Formal ApproachBhushan Parikh, Peter Graniello, and Neha Rajendra2022Paper2022paper
Accelerating Functional Verification Coverage Data Manipulation Using Map ReduceEman El Mandouh, A. Gamal, A. Khaled, B. Amr G. Wassal, and Elsayed Hemayed2017Presentation2017presentation
Accelerating Functional Verification Coverage Data Manipulation Using Map ReduceEman El Mandouh, A. Gamal, A. Khaled, T. Ibrahim, Amr G. Wassal, Elsayed Hemayed2017Paper2017paper
Accelerating ML TB Integration for Reusability Using UVM ML OASaleem Khan, Prasanna Kumar2017Presentation2017presentation
Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing ProductsYoga Priya Vadivelu, Arpan Shah, Deepinder Singh Mohoora, Ullas, and Praveen Buddireddy2022Poster2022poster
Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing ProductsYoga Priya Vadivelu, Arpan Shah, Deepinder Singh Mohoora, Ullas, and Praveen Buddireddy2022Paper2022paper
Accelerating RTL Simulation TechniquesLior Grinzaig2015Paper2015paper
Accelerating RTL Simulation TechniquesLior Grinzaig2015Presentation2015presentation
Accelerating Semiconductor Time to ISO 26262 ComplianceKirankumar Karanam2022Presentation2022presentation
Accelerating SoC Verification Signoff using Save & Restart/Dynamic Test Reload Enhanced Regression flowVanshlata B, Divya M, Garima S, Seonil Brian Choi2021Paper2021paper
Accelerating SOC Verification Using Process Automation and IntegrationSeonghee Yim, Hanna Jang, Sunchang Choi, and Seonil Brian Choi2020Paper2020paper
Accelerating the IP Design Cycle with Formal Techniques Beyond Everyday FPVBhushan Parikh, Shaman Narayana, Buck Lem, David Cassetti2021Paper2021paper
Accelerating the SoC Integration Verification Cycle Time Leveraging the Legacy Design ConfidenceAbhinav Parashar, Prasanth Kumar Narava2022Presentation2022presentation
Acceleration of Coreless SoC Design-Verification using PSS on Configurable Testbench in Multi-Link PCIe SubsystemsThanu Ganapathy, Pravin Kumar, Garima Srivastava, Seonil Brian Choi, Harish Peta2021Paper2021paper
Acceleration of product and test environment development using SystemC-TLMFlorian Barrau, Alexandre Piccini, Alexandre Nabais Moreno, Mark Burton, Luc Michel, Clement Descha2018Paper2018paper
Acceleration of product and test environment using SystemC TLMFlorian Barrau, Alexandre Piccini, Alexandre Nabais Mark Burton, Luc Michel, and Clement Deschamps2018Presentation2018presentation
Acceleration Startup Design & VerificationTim Sun, Barry Yin, and Haifeng Jiang2021Presentation2021presentation
Accellera Systems Initiative SystemC Standards UpdateBishnupriya Bhattacharya2015Presentation2015presentation
Accellera Systems InitiativeSystemC Standards UpdateMartin Barnasconi, Philipp A. Hartmann, and Stephan Schulz 2015Presentation2015presentation
Accellera Systems InitiativeSystemC Standards UpdateMartin Barnasconi, Philipp A. Hartmann, Trevor Wieman2014Presentation2014presentation
Accellera UVM-AMS Standard UpdateTom Fitzpatrick and Tim Pylant2022Presentation2022presentation
Ace’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power ConsumptionMehul Kumar, Tushar Mattu, and Amir Nilipour2016Paper2016paper
ACE’ing the Verification of a Coherent System Using UVMRomondy Luo, Ray Varghese, Parag Goel, Amit Sharma, Satyapriya Acharya, and Peer Mohammed2012Paper2012paper
ACE’ing the Verification of a Coherent System Using UVMParag Goel; Amit Sharma, Ray Varghese, Romondy Luo, Satyapriya Acharya, Peer Mohammed2012Presentation2012presentation
ACE’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power ConsumptionMehul Kumar, Shawn Honess, Amir Nilipour, and Tushar Mattu2016Poster2016poster
Achieve Complete SoC Memory Map Verification Through Efficient Combination of Formal and Simulation TechniquesClemens Roettgermann, Peter Limmer, and Michael Rohleder2015Paper2015paper
Achieve Complete SoC Memory Map Verification through Efficient Combination of Formal and Simulation TechniquesClemens Roettgermann, Peter Limmer, and Michael Rohleder2015Presentation2015presentation
Achieve Faster Debug Closure by Applying Big Data & Advanced RCA TechnologiesSundararajan Ananthakrishnan, Sundararajan PH2022Presentation2022presentation
Achieving Faster Code Coverage Closure using High-Level SynthesisSurendhar Thudukuchi Chandrapandiyan, Preetham Lakshmikanthan, Ashwani Aggarwal, Youngchan Lee, Youngsik Kim, Seonil Brian Choi2021Paper2021paper
Achieving Faster Reset Verification Closure with Intelligent Reset Domain Crossings DetectionMilanpreet Kaur and Sulabh Kumar Khare2020Paper2020paper
Achieving Faster Reset Verification Closure with Intelligent Reset Domain Crossings DetectionMilanpreet Kaur and Sulabh Kumar Khare2020Poster, Presentation2020poster presentation
Achieving First-Time Success with a UPF-based Low Power Verification FlowKjeld Svendsen, Chuck Seeley, and Erich Marschner2011Paper2011paper
Achieving Portable Stimulus with Graph-Based Verification – Tutorial2014Presentation2014presentation
Achieving Real Time Performance for Algorithms Using SOC TLM ModelSaurin Patel, Pushkar Sareen, Sharath Naidu, Baljinder S Sood2015Presentation2015presentation
Activity Trend Guided Efficient Approach to Peak Power Estimation Using EmulationGaurav Saharawat, Saurabh Jain, and Madhur Bhatia2016Presentation2016presentation
Activity Trend Guided Efficient Approach to Peak Power Estimation Using EmulationGaurav Saharawat, Saurabh Jain, and Madhur Bhatia2016Paper2016paper
Adapting the UVM Register Abstraction Layer for Burst AccessMark Villalpando2016Presentation2016presentation
Adapting the UVM Register Layer for Burst AccessM. P. Villalpando2016Paper2016paper
Adaptive Test Generation for Fast Functional Coverage ClosureAzade Nazi, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhoseini, Richard Ho2022Presentation2022presentation
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Advance Approach for Formal Verification of Configurable Pulse Width Modulation ControllerSumit K. Kulshreshtha, Raghavendra J N2021Paper2021paper
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Advanced SOC Randomization Tool for Complex SOC Level VerificationMarvin Mei, Chris Weller, Michael Sedmak, and Zhiqiang Ren2020Paper2020paper
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Advanced Usage Models for Continuous Integration in Verification EnvironmentsJohn Dickol2015Paper2015paper
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Advanced UVM Tutorial Taking Reuse to the Next LevelMark Litterick, Jason Sprott, and Jonathan Bromley2015Presentation2015presentation
Advanced UVM, Multi-Interface, Reactive Stimulus TechniquesClifford E. Cummings, Stephen DOnofrio, Jeff Wilcox, Heath Chambers2021Paper2021paper
Advanced, High Throughput Debug From Design to SiliconGordon Allan & Michael Horn2015Presentation2015presentation
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Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification CycleCharul Agrawal, Ashwin Vijayan, and Jakub Dudek2017Paper2017paper
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Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC.Nipun Bhatt2020Paper2020paper
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An Expert System Based Tool for Pre-design Chip Power EstimationBhanu Singh, Arunprasath Shankar, Francis Wolff, and Christos Papachristou2014Paper2014paper
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An Introduction to using Event-B for Cyber-Physical System Specification and DesignJohn Colley and Michael Butler2014Presentation2014presentation
An Open and Fast Virtual Platform for TriCore™-based SoCs Using QEMUBastian Koppelmann, Bernd Messidat, Markus Becker, and Christoph Kuznik2014Paper2014paper
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Analog Modelling to Suit Emulation for Hardware-Software Co-VerificationSaranya Das2020Paper2020paper
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Analog Transaction Level Modeling for Verification of Mixed-Signal-BlocksAlexander W. Rath, Volkan Esen, and Wolfgang Ecker2012Paper2012paper
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Analysis of TLM-2.0 and it’s Applicability to Non Memory Mapped InterfacesDelbergue Guillaume2016Presentation2016presentation
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Apples versus Apples HVL Comparison Finally Arrives Comparing OVM SystemVerilog to OVM eBrett Lammers and Riccardo Oddone2010Paper2010paper
Application Abstraction Layer: The Carpool Lane on the SoC Verification FreewayAbhisek Verma, Varun S, and Subramanian Kuppusamy2015Paper2015paper
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Application of SystemC/SystemC-AMS in 3G Virtual PrototypingTao Huang and Stefan Heinen2011Paper2011paper
Application Optimized HW/SW Design & Verification of a Machine Learning SoCLauro Rizzatti, Russell Klein, Stephen Bailey, and Andrew Meier2020Presentation2020presentation
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Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical PropertiesK. Selyunin, T. Nguyen, A.D. Basa, E. Bartocci, D. Nickovic, and R. Grosu2016Paper2016paper
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Applying Transaction-level Debug and Analysis Techniques to DUT Simulated Activity Using Data- Mining TechniquesLeo Chai, Bindesh Patel, and Jun Zhao2014Paper2014paper
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ARC EM Core with Safety Package – ISO 26262 CertificationVikas Bhandari2015Poster2015poster
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Architectural Formal Verification of System-Level DeadlocksMandar Munishwar1, Naveed Zaman, Anshul Jain, HarGovind Singh, and Vigyan Singhal2018Paper2018paper
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Architecturally Scalable Testbench for Complex SoCSenthilnath Subbarayan, Arulanandan Jacob, Sandeep Kumar2019Paper2019paper
Are OVM & UVM Macros Evil? A Cost-Benefit AnalysisAdam Erickson2011Paper2011paper
Are you really confident that you are getting the very best from your verification resources?Darron May and Fritz Ferstl2014Paper2014paper
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Are You Safe Yet? Safety Mechanism Insertion and ValidationPing Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen2020Paper2020paper
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Are You Smarter Than Your Testbench? With a little work you can be.Rich Edelman and Raghu Ardeishar2015Paper2015paper
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ASIC-Strength Verification in a Fast-Moving FPGA WorldBryan Murdock2013Poster2013poster
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Assertion Based Self-checking of Analog Circuits for Circuit Verification and Model Validation in SPICE and Co-simulation EnvironmentsLakshmanan Balasubramanian, Pooja Sundar, and Timothy W Fischer2011Paper2011paper
Assertion-based Verification for Analog and Mixed Signal DesignsSrinivas Aluri2017Paper2017paper
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Assisting Fault Injection Simulations for Functional Safety Sign-off using FormalPulicharla Ravindrareddy2019Presentation2019presentation
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Asynchronous Behaviors Meet Their Match with SystemVerilog AssertionsDoug Smith2010Paper2010paper
Attack Your SoCPowerChallenges with Virtual PrototypingStefan Thiel and Gunnar Braun2014Presentation2014presentation
Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor CoreWei Foong Thoo and David A. Burgoon2012Presentation2012presentation
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Automated approach to Register Design and Verification of complex SOCBallori Banerjee, Subashini Rajan, and Silpa Naidu2011Paper2011paper
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Automated Generation of RAL-based UVM SequencesVijayakrishnan Rousseau, Satyajit Sinari, Benjamin Applequist, Timothy McLean, and Geddy Lallathin2020Paper2020paper
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Automated Performance Verification to Maximize your ARMv8 pulling powerNick Heaton and Simon Rance2015Paper2015paper
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Automated Physical Hierarchy Generation: Tools and MethodologyAli El-Zein, Alvan Ng, Benedikt Geukes, Maya H. Safieddine, and Wolfgang Roesner2018Paper2018paper
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Automated RTL Update for Abutted DesignWonkyung Lee, Ayoung Kwon, Soyeong Kwon, Youngsik Kim, and Seonil Brian Choi2020Paper2020paper
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Automated Safety Verification for Automotive MicrocontrollersHolger Busch2016Presentation2016presentation
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Automated Seed Selection Algorithm for an Arbitrary Test SuiteDavid Crutchfield, Brian Craw, Jim Sharpe, and Brandon Skaggs2018Paper2018paper
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Automated Specification Driven Verification by Generation of SystemVerilog AssertionsFerdinando Pace2016Poster2016poster
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Automated SystemC Model Instantiation with modern C++ Features and sc_vectorRalph Görgen and Philipp A. Hartmann2015Paper2015paper
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Automated Test Generation to Verify IP Modified for System Level Power ManagementChristophe Lamard and Frederic Dupuis2015Presentation2015presentation
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Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual PrototypeS N Ranjan and Puttaiah Jagadish2021Presentation2021presentation
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Automated traceability of requirements in the design and verification process of safety-critical mixed-signal systemsGabriel Pachiana, Maximilian Grunwald, Thomas Markwirth, Christoph Sohrmann2021Paper2021paper
Automated Traffic Simulation Framework for SoC Performance AnalysisDiviya Jain, Tarun Kathuria 2017Presentation2017presentation
Automated vManager regression using JenkinsSneha Gokarakonda2022Poster2022poster
Automated, Systematic CDC Verification Methodology Based on SDC SetupAshish Hari, Sulabh Kumar Khare2014Paper2014paper
Automatic Debug Down to the LineDaniel Hansson and Patrik Granath2017Poster2017poster
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Automatic Diagram Creation for Design and TestbenchesPaul O’Keeffe, Jamie Beattie and Gian Lorenzo2020Paper2020paper
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Automatic Firmware Design for Application-specific Electronic Systems: Opportunities, Challenges and SolutionsDaniel Große, Joscha Benz, Vladimir Herdt, and Martin Dittrich2017Presentation2017presentation
Automatic Firmware Verification for Automotive ApplicationsTorsten Andre and Daniel Valtiner2017Paper2017paper
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Automatic Generation of Formal Properties for Logic Related to Clock GatingShuqing Zhao and Shan Yan2015Presentation2015presentation
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Automatic Generation of Infineon Microcontroller Product ConfigurationsPrateek Chandra, Leily Zafari, Boyko Traykov2019Presentation2019presentation
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Automatic Investigation of Power InefficienciesKuo Kai Hsieh, Li C. Wang, Wen Chen, Monica Farkash, and Jayanta Bhadra2017Presentation2017presentation
Automatic Investigation of Power InefficiencyKuo-Kai Hsieh, Wen Chen, Monica Farkash, Jayanta Bhadra, and Li-C. Wang2017Paper2017paper
Automatic Netlist Modifications required by Functional SafetyHarald Lüpken, Dirk Hönicke, and Michael Rohleder2014Paper2014paper
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Automatic Partitioning for Multi-core HDL SimulationGaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra2015Paper2015paper
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Automatic SOC Test Bench CreationDavid Crutchfield, Mark Glasser, and Stephen Roe2015Paper2015paper
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Automatic Testbench Build to Reduce Cycle Time and Forster ReuseJoachim Geishauser and Alexander Schilling2017Paper2017paper
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Automatic Translation of Natural Language to SystemVerilog AssertionsAbhishek Chauhan2022Presentation2022presentation
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Automatic verification for Assertion Based Verification: How can a SPIRIT IP-XACT extension help?Sofiene Mejri and Mirella Negro Marcigaglia2010Paper2010paper
Automatically Synthesizing Higher Level of Protocol Abstraction for Faster Debug and Deeper Insight Into Modern Digital DesignsAlasdair Ferro, Amar Patel, Chris Jones, Yogesh Badaya2019Paper2019paper
Automating information retrieval from EDA software reports using effective parsing algorithmsManish Bhati2022Poster2022poster
Automating sequence creation from a microarchitecture specificationSubramoni Parameswaran and Ravi Ram2016Poster2016poster
Automating sequence creation from a Microarchitecture specificationSubramoni Parameswaran and Ravi Ram2016Paper2016paper
Automating the formal verification sign-off flow of configurable digital IP’sGiovanni Auditore and Giuseppe Falconeri2019Paper2019paper
Automating the formal verification sign-off flow of configurable digital IP’sGiovanni Auditore and Giuseppe Falconeri2019Presentation2019presentation
Automation of Power On Reset AssertionShang-Wei Tu, Penny Yang, Joydeep Gangopadhyay, and Amol Herlekar2015Paper2015paper
Automation of Reusable Protocol-Agnostic Performance Analysis in UVM EnvironmentsD. P. Carrington, A. J. Pippin, and T. Pertuit2019Paper2019paper
Automation of Reusable Protocol-Agnostic Performance Analysis in UVM EnvironmentsDaniel Carrington, Alan Pippin, and Timothy Pertuit2019Presentation2019presentation
Automation of Waiver and Design Collateral generation for scalable IPsGopalakrishnan Sridhar, Vadlamuri Venkata Sateeshm, Midhun Krishna2019Paper2019paper
Automation of Waiver and Design Collateral Generation on Scalable IPsGopalakrishnan Sridhar, Midhun Krishna, Vadlamuri, Venkata Sateesh2019Presentation2019presentation
Avoiding Confounding Configurations an RDC Methodology for Configurable DesignsEamonn Quigley, Jonathan Niven, and Kurt Takara2022Poster2022poster
Avoiding Confounding Configurations An RDC Methodology for Configurable DesignsEamonn Quigley, Jonathan Niven, and Kurt Takara2022Paper2022paper
Back to Basics: Doing Formal “The Right Way”Joseph Hupcey III, Saumitra Goel 2017Presentation2017presentation
BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering ProblemDebarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, Siddhanth Dhodhi, Spandan Kachhadiya2022Presentation2022presentation
BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering ProblemDebarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, and Siddhanth Dhodhi2022Paper2022paper
Be a Sequence Pro to Avoid Bad Con SequencesMark Litterick2019Presentation2019presentation
Be a Sequence Pro to Avoid Bad Con SequencesJeff Vance, Jeff Montesano, Mark Litterick, and Jason Sprott2019Presentation2019presentation
Benefits of PSS coverage at SOC & its limitationsSundararajan Haran and Saleem Khan2019Presentation2019presentation
Benefits of PSS Coverage at SOC and Its LimitationsSundararajan Haran, Saleem Khan2019Paper2019paper
Best Practices in Verification PlanningBenjamin Ehlers, Carmen Vargas, and Paul Carzola2013Paper2013paper
Best Practices in Verification PlanningBenjamin Ehlers and Paul Carzola2013Presentation2013presentation
Better Living Through Better Class-Based SystemVerilog DebugRich Edelman, Raghu Ardeishar, and John Amouroux2012Paper2012paper
Better Living Through Better Class-Based SystemVerilog DebugRich Edelman, Raghu Ardeishar, and John Amouroux2012Presentation2012presentation
Between the Dialog and the Algorithm or Innovative Technological Narratives Leveraging the Idea of Authenticity in a Human Being Visualizing log files enables intuitive comprehension of complex test scenariosAnna M. Ravitzki and Uri Feigin2017Paper2017paper
Beyond UVM: Creating Truly Reusable Protocol LayeringJanick Bergeron, Fabian Delguste, Steve Knoeck, Steve McMaster, Aron Pratt, and Amit Sharma2013Paper2013paper
Beyond UVM: Creating Truly Reusable Protocol LayeringJanick Bergeron2013Presentation2013presentation
Bi-Directional UVM Agents and Complex Stimulus Generation for UDN and UPF PinsChuck McClish2021Paper2021paper
Big Data in Verification: Making Your Engineers SmarterDavid Lacey, Mike McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson2019Paper2019paper
Big Data in Verification: Making Your Engineers SmarterDavid Lacey, Michael McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson2019Presentation2019presentation
Bit density based pre characterization of RAM cells for area critical SOC designDilip Kumar Ajay (dajay@qti.qualcomm.com)2020Presentation2020presentation
Bit Density-Based Pre-Characterization of RAM Cells for Area Critical SOC DesignDilip Kumar Ajay2020Paper2020paper
Blending multiple metrics from multiple verification engines for improved productivityDarron May and Darren Galpin2012Paper2012paper
Boost Verification Results by Bridging the Hardware/Software Testbench GapMatthew Ballance2013Paper2013paper
Boost Verification Results by Bridging the Hw/Sw Testbench GapMatthew Ballance2013Presentation2013presentation
Boosting Debug Productivity Practical Applications of Debug Innovations in a UVM WorldJoerg Richter2017Presentation2017presentation
Boosting Mixed-Signal Design Productivity with FPGA-Based Methods Throughout the Chip Design ProcessGabriel Rutsch, Simone Fontanesi, Steven G. Herbst, Steven Tan Hee Yeng, Andrea Possemato, Gaetano Formato, Mark Horowitz, and Wolfgang Ecker2020Paper2020paper
BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMSAhmed Yehia2013Poster2013poster
BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMSAhmed Yehia2013Paper2013paper
Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven GenerationHoang M. Le and Rolf Drechsler2015Paper2015paper
Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven GenerationHoang M. Le and Rolf Drechsler2015Presentation2015presentation
Break the SoC with Random UVM Instruction DriverBogdan Todea, Pravin Wilfred, Madhukar Mahadevappa, Diana Dranga2019Paper2019paper
Bridge the Portable Test and Stimulus to UVM Simulation EnvironmentTheta Yang and Evean Qin2018Paper2018paper
Bridge the Portable Test and Stimulus to UVM Simulation EnvironmentTheta Yang and Evean Qin2018Presentation2018presentation
Bridging the gap between TLM-2.0 AT models and RTL – Experiments and OpportunitiesZhu Zhou, Atul Kwatra, Rajesh Gadiyar, and Paul Heraty2010Paper2010paper
Bring IP Verification Closer to SoC Scalable Methods to Bridge the Gap Between IP and SoC VerificationGaurav Gupta, Tejbal Prasad, Rohit Goyal, Sachin Jain, Vipin Verma2014Paper2014paper
Bring IP Verification Closer to SoC Scalable Methods to Bridge the Gap Between IP and SoC VerificationGaurav Gupta, Tejbal Prasad, Rohit Goyal, Sachin Jain, Vipin Verma2014Presentation2014presentation
Bringing Constrained Random into SoC SW-driven VerificationAlberto Allara and Fabio Brognara2013Paper2013paper
Bringing Constrained Random into SoC SW-driven VerificationAlberto Allara and Fabio Brognara2013Presentation2013presentation
BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPSPrabal K Bhattacharya, Swapnajit Chakraborti, Scott Little, Donald O’Riordan, and Vaibhav Bhutani2012Paper2012paper
BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPSPrabal K Bhattacharya, Swapnajit Chakraborti, Donald O’Riordan, Vaibhav Bhutani, and Scott Little2012Presentation2012presentation
Bringing DataPath Formal to Designers’ FootstepsM, Achutha KiranKumar V, Disha Puri, Shriya Dharade2019Paper2019paper
Bringing Regression Systems into the 21st CenturyDavid Crutchfield and Thom Ellis2014Paper2014paper
Bringing Regression Systems into the 21st CenturyDavid Crutchfield2014Poster2014poster
Bringing Reset Domains and Power Domains together – Confronting issues due to UPF InstrumentationInayat Ali, Abdul Moyeen, Manish Bhati, Manjunatha Srinivas2021Paper2021paper
Bringing Reset Domains and Power Domains together – Non resettable registers amplifying issues in Power-Aware RDC Verification due to UPF InstrumentationManish Bhati, Inayat Ali2022Presentation2022presentation
Bringing Reset Domains and Power Domains Together – Set/Reset Flops Augmenting Complexities in Power-Aware RDC Verification.Manish Bhati, Manjunatha Srinivas, Abdul Moyeen, Inayat Ali2021Paper2021paper
Bringing UVM to VHDLUVVM2022Presentation2022presentation
Build Reliable and Efficient Reset Networks with a Comprehensive Reset Domain Crossing Verification SolutionWanggen Shi, Yuxin You, and Kurt Takara2020Paper2020paper
Build Reliable and Efficient Reset Networks with a Comprehensive Reset Domain Crossing Verification SolutionWanggen Shi, Yuxin You, and Kurt Takara2020Presentation2020presentation
Building a coherent ESL design and verification eco-system with SystemC, TLM, UVM-SystemC, and CCIMartin Barnasconi2016Paper2016paper
Building a Comprehensive Hardware Security MethodologyAnders Nordstrom and Jagadish Nayak2022Presentation2022presentation
Building And Modelling Reset Aware Testbench For IP Functional VerificationNaishal Shah2019Paper2019paper
Building Code Generators for Reuse – Demonstrated by a SystemC GeneratorSaad Siddiqui and Ulrich Nageldinger2017Paper2017paper
Building Code Generators for Reuse – Demonstrated by a SystemC GeneratorUlrich Nageldinger and Saad Siddiqui2017Presentation2017presentation
Building Configurable UVM Testbench for Configurable Design IP (Configurable TB)Kilaru Vamsikrishna, Sushrut B Veerapur2022Presentation2022presentation
Building Portable Stimulus Into Your IP-XACT FlowPetri Karppa, Lauri Matilainen, and Matthew Balance2018Paper2018paper
Building Portable Stimulus Into your IP-XACT FlowPetri Karppa, Lauri Matilainen, and Matthew Ballance2018Presentation2018presentation
Building Smart SoCs Using Virtual Prototyping for the Design and SoC Integration of Deep Learning AcceleratorsHolger Keding2019Presentation2019presentation
Building UVM Testbenches for High Quality Serial Design IPs Modelling real world scenariosKilaru Vamsikrishna, Sushrut B Veerapur2022Poster2022poster
C through UVM: Effectively using C based models with UVM based Verification IPAdiel Khan, Chris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile2013Presentation2013presentation
C through UVM: Effectively using C based models with UVM based Verification IPChris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile2013Paper2013paper
Caching Tool Run Results in Large Scale RTL Development ProjectsAshfaq Khan2022Presentation2022presentation
Caching Tool Run Results in Large-Scale RTL Development ProjectsAshfaq Khan2022Paper2022paper
Cadence vManager Platform and Virtuoso ADE Verifier Leading-edge technologies provide methodology for mixedsignal verification closureKawe Fotouhi and Walter Hartong2019Presentation2019presentation
Calling All Checkers: Collaboratively Utilizing SVA In UVM Based SimulationHui K. Zhang2016Paper2016paper
Calling All Checkers: Collaboratively Utilizing SVA in UVM Based SimulationHui C. K. Zhang2016Poster2016poster
CAMEL – A Flexible Cache Model for Cache VerificationYue Liu, Fang Liu, Yunyang Song2022Presentation2022presentation
CAMEL: A Flexible Cache Model for Cache VerificationYue Liu, Fang Liu, and Yunyang Song2022Paper2022paper
Can Formal Outsmart Synthesis: Improving Synthesis Quality of Results through Formal MethodsEldon Nelson2021Paper2021paper
Can My Synthesis Compiler Do That?Stuart Sutherland and Don Mills2014Presentation2014presentation
Can My Synthesis Compiler Do That?Stuart Sutherland and Don Mills2014Paper2014paper
Can You Even Debug a 200M+ Gate Design?Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss2013Poster2013poster
Can You Even Debug a 200M+ Gate Design?Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss2013Paper2013paper
Case Study of Verification Planning to Coverage Closure @Block, Subsystem and System on Chip LevelPaul Kaunds, Revati Bothe, and Jesvin Johnson2018Presentation2018presentation
Case Study: Low-Power Verification Success Depends on Positive PessimismJohn Decker2011Paper2011paper
Case Study: Power-aware IP and Mixed-Signal VeriLuke Lang2011Paper2011paper
Case Study: Successes and Challenges of Validation Content ReuseMike Chin, Jonathan Edwards, Josh Pfrimmer, and Hooi Jing Tan2022Paper2022paper
Case-study: Generating A Workload Model of the Chrome Browser from Android Execution Traces For Early Analysis of Power and Performance Trade-offsVikrant Kapila, Tim Kogel, Holger Keding, Amit Tara Amit Dudeja, Nishant Gautam2017Presentation2017presentation
Catching the low hanging fruits on intel® Graphics DesignsM, Achutha KiranKumar V, Aarti Gupta, Bindumadhava S S, Savitha Manojna, and Abhijith A Bharadwaj2016Paper2016paper
Centralized Regression Optimisation Toolkit (CROT) for expediting Regression Closure With Simulator Performance OptimisationHarshal Kothari, Pavan M, Ajay Vamshi Krishna, Eldin Ben Jacob, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath2021Paper2021paper
Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation)Vikas Billa and Sundar Haran2018Paper2018paper
Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation)Vikas Billa and Sundar Haran2018Presentation2018presentation
Challenges in Mixed Signal VerificationAmlan Chakrabarti, Sachin-Sudhakar Kulkarni2015Presentation2015presentation
Challenges in UVM + Python Random Verification Environment for Digital Signal Processing Datapath DesignShabbar Vejlani and Ashok Chandran2016Presentation2016presentation
Challenges in UVM + Python random verification environment for Digital Signal Processing datapath design.Shabbar Vejlani and Ashok Chandran2016Paper2016paper
Challenges of Formal Verification on Deep Learning Hardware AcceleratorYellinidi Dasarathanaidu2019Presentation2019presentation
Challenges of Formal Verification on Deep Learning Hardware AcceleratorYellinidi Dasarathanaidu2019Paper2019paper
Challenges of VHDL X-propagation SimulationsKarthik Baddam and Piyush Sukhija2015Paper2015paper
Challenges of VHDL X-propagation SimulationsKarthik Baddam and Piyush Sukhija2015Presentation2015presentation
Challenges with Power Aware Simulation and Verification MethodologiesDivyeshkumar Vora2015Presentation2015presentation
Challenges, Complexities and Advanced Verification Techniques in Stress Testing of Elastic Buffer in High Speed SERDES IPsKamesh Velmail, Suvadeep Bose, Ankit Garg, Parag S Lonkar, Somasunder K Sreenath2019Presentation2019presentation
Challenges, Complexities and Advanced Verification Techniques in Stress Testing of Elastic Buffer in High Speed SERDES IPsKamesh Velmail, Suvadeep Bose, Parag Lonkar, Ankit Garg2019Paper2019paper
Channel Modelling in Complex Serial IPsJayesh Ranjan Majhi, Saravana Balakrishnan, Navnit Kumar Kashyap2022Poster2022poster
Characterizing RF Wireless Receivers Performance in UVM EnvironmentSalwa Elqassas, Salwa Elqassas and Mohammed T. Abdel-Hafe2018Paper2018paper
Checking Security Path with Formal Verification Tool: New Application DevelopmentJulia Dushina and Joerg Mueller2014Poster2014poster
Checking security path with formal verification tool: new application developmentJulia Dushina, Saumil Shah, Joerg Mueller, and Vincent Reynolds2014Paper2014paper
Chef’s Special – an Efficient Verification Recipe for Maximizing Productivity While Using a Third Party Verification IPVarun S and Bhavik Vyas2012Paper2012paper
Chiplevel Analog Regressions in ProductionYi Wang2021Paper2021paper
Choice is Yours: Either Struggle to Tame ‘X’ in the Wilderness of Multimillion Gates and Nets, OR Take it for a Walk in the RTL ParkNitin Jaiswal, Harsh Garg, Mayank Bindal2014Presentation2014presentation
Cleaning Out Your Pipes – Pipeline Debug in UVM TestbenchesRich Edelman and Neil Bulman2018Paper2018paper
Cleaning Out Your Pipes – Pipeline Debug in UVM TestbenchesRich Edelman and Neil Bulman2018Poster2018poster
Clock Controller Unit Design Metrics: Area, Power, Software Flexibility and Congestion Impacts at System LevelMichele Chilla and Leonardo Gobbi2020Paper2020paper
CLOCK DOMAIN CROSSING CHALLENGES IN LATCH BASED DESIGNSMadan Das, PhD, Chris Kwok, and Kurt Takara2018Paper2018paper
Clock Domain Crossing Challenges in Latch Based DesignsMadan Das, Chris Kwok, and Kurt Takara2018Presentation2018presentation
Clock Domain Crossing Verification in Transistor-level DesignHyungjung Seo, KwangSun Kim, YoungRok Choi, Jihwan Kim, and Jong-Bae Lee2019Poster2019poster
Closing Functional and Structural Coverage on RTL Generated by High-Level SynthesisBryan Bowyer2015Poster2015poster
Closing Functional and Structural Coverage on RTL Generated by High-Level SynthesisB. Bowyer2015Paper2015paper
Closing the loop from requirements management to verification execution for automotive applicationsWalter Tibboel and Jan Vink2015Paper2015paper
Closing the loop from requirements management to verification execution for automotive applicationsWalter Tibboel and Jan Vink2015Presentation2015presentation
Clustering and Classification of UVM Test Failures Using Machine Learning TechniquesAndy Troung, Daniel Hellström, Harry Duque, and Lars Viklund2018Presentation2018presentation
Clustering and Classification of UVM Test Failures Using Machine Learning TechniquesAndy Truong, Daniel Hellström, Harry Duque, and Lars Viklund2018Paper2018paper
Co-Developing Firmware and IP with PSSM. Ballance2022Paper2022paper
Co-Developing IP and SoC Bring-Up Firmware with PSSMatthew Ballance, Siemens EDA2022Presentation2022presentation
Co-Simulating Matlab/Simulink Models in a UVM EnvironmentNeal Okumura and Glenn Richards2015Paper2015paper
Co-Simulating Matlab/Simulink Models in a UVM EnvironmentNeal Okumura, Paul Yue, and Glenn Richards2015Presentation2015presentation
Coding Guidelines and Code GenerationJohn Aynsley and Dr. Christoph Sühnel2014Poster2014poster
Coherency Verification & Deadlock Detection Using Perspec/Portable StimulusMoonki Jang and Phu Huynh2019Presentation2019presentation
Coherency Verification & Deadlock Detection Using Perspec/Portable StimulusMoonki Jang, Jiwoong Kim, Hyerim Chung, Phu L. Huynh, and Shai Fuss2019Paper2019paper
Combining Simulation with Formal Techniques to Reduce the Overall Verification CycleAneet Agarwal and Gaurav Gupta2010Paper2010paper
Combining Static and Dynamic Low Power Verification for the Power-Aware SoC Sign-offHimanshu Bhatt and Prashanth M2014Paper2014paper
Combining Static and Dynamic Low Power Verification for the Power-Aware SoC Sign-offHimanshu Bhatt, Prashanth M, and Adiel Khan2014Presentation2014presentation
Command Line Debug Using UVM SequencesMark Peryer2011Paper2011paper
Common Challenges and Solutions to Integrating a UVM TestbenchFrank Verhoorn and Mike Baird2018Presentation2018presentation
Common Challenges and Solutions to Integrating a UVM Testbench in Place of a Legacy Monolithic Testing EnvironmentFrank Verhoorn and Michael Baird2018Paper2018paper
Comparison of TLM2-Quantum Keeping and TLM+-Resource Modeling with regard to Timing in Virtual PrototypesWolfgang Ecker, Volkan Esen, Rainer Findenigy, Thomas Leitnerz and Michael Velten2011Paper2011paper
Complementing EDA with Meta-Modeling and Code GenerationWolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal2014Paper2014paper
Complementing EDA with Meta-Modelling & Code GenerationWolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal2014Poster2014poster
Complementing EDA with Meta-Modelling and Code GenerationEcker Wolfgang, Michael Velten, Ajay Goyal, and Leily Zafari2014Presentation2014presentation
Complementing Verification of Highly Configurable Design with Formal TechniquesManik Tyagi, Deepak Jindal2015Poster2015poster
Complete Formal Verification of a Family of Automotive DSPsRafal Baranowski and Marco Trunzer2016Presentation2016presentation
Complete Formal Verification of a Family of Automotive DSPsRafal Baranowski and Marco Trunzer2016Paper2016paper
Complex Low Power Verification Challenges in NextGen SoCs : Taming the Beast!Abhinav Nawal, Gaurav Jain, and Joachim Geishauser2014Presentation2014presentation
Complex Low Power Verification Challenges in NextGen SoCs: Taming the Beast!Abhinav Nawal and Gaurav Jain2014Paper2014paper
Compliance Driven Integrated Circuit Development Based on ISO26262Haridas Vilakathara, Manikantan panchapakesan2014Presentation2014presentation
Compliance Driven Integrated Circuit Development Based on ISO26262Haridas Vilakathara and Manikandan Panchapakesan2014Paper2014paper
CompMon: Ensuring Rigorous Protocol Specification and IP ComplianceRobert Adler, Sava Krstic and Erik Seligman2011Paper2011paper
Comprehensive AMS Verification using Octave, Real Number Modelling and UVMJohn McGrath, Patrick Lynch, and Ali Boumaalif2015Paper2015paper
Comprehensive AMS Verification using Octave, Real Number Modelling and UVMJohn McGrath, Patrick Lynch, and Ali Boumaalif2015Presentation2015presentation
Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain CrossingsYossi Mirsky2017Presentation2017presentation
Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain CrossingsYossi Mirsky B.Sc, M.Sc, MBA2017Paper2017paper
Comprehensive IP to SoC CDC Verification Using Hybrid Data ModelAnwesha Choudhury and Ashish Hari2018Poster2018poster
Comprehensive IP to SoC Clock Domain Crossing Verification Using Hybrid Data ModeAnwesha Choudhury and Ashish Hari2018Paper2018paper
Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-ChipsEllie Burns, Gabriel Chidolue, and Guillaume Boillet2018Presentation2018presentation
Comprehensive Register Description Languages: The case for standardization of RDLs across design domainsDavid C Black and Doug Smith2012Paper2012paper
Comprehensive Systemverilog-Systemc-Vhdl Mixed-Language Design MethodologyRudra Mukherjee, Gaurav Kumar Verma, and Sachin Kakkar2010Paper2010paper
Computational Logistics for Intelligent System DesignSimon Chang2021Presentation2021presentation
Compute Link Express – CXL – CXL ConsortiumNarasimha Babu2022Presentation2022presentation
Conditional Delays for Negative Limit Timing Checks in Event Driven SimulationNadeem Kalil and David Roberts2015Paper2015paper
Conditional Delays for Negative Limit Timing Checks in Event Driven SimulationN. Kalil and D. Roberts2015Poster2015poster
Confidently Sign-off Any low-Power Designs without ConsequencesMadhur Bhargava, Jitesh Bansal, and Progyna Khondkar2022Poster2022poster
Confidently Sign-Off Any Low-Power Designs Without ConsequencesMadhur Bharga, Jitesh Bansal and Progyna Khondkar2022Paper2022paper
Configuration Conundrum: Managing Test Configuration with a Bite Sized SolutionKevin Vasconcellos, Jeff McNeal2021Paper2021paper
Configuration in UVM:The Missing ManualMark Glasser2014Presentation2014presentation
Configuration in UVM: The Missing ManualMark Glasser2014Paper2014paper
Configuring Your Resources the UVM Way!Parag Goel, Amit Sharma, and Rajiv Hasija2012Paper2012paper
Configuring Your Resources the UVM Way!Parag Goel, Amit Sharma, and Rajiv Hasija2012Presentation2012presentation
Connecting a Company’s Verification Methodology to Standard Concepts of UVMFrank Poppen, Marco Trunzer, and Jan‐Hendrik Oetjens2014Paper2014paper
Connecting a Company’s Verification Methodology to Standard Concepts of UVMFrank Poppen, Marco Trunzer, and Jan‐Hendrik Oetjens2014Presentation2014presentation
Connecting Enterprise Applications to Metric Driven VerificationMatt Graham2014Paper2014paper
Connecting Enterprise Applications to Metric Driven VerificationMatt Graham2014Presentation2014presentation
CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITYBin Ju2014Paper2014paper
CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITYBin Ju2014Poster2014poster
Connecting UVM with Mixed-Signal DesignIvica Ignjić2017Presentation2017presentation
CONNECTING UVM WITH MIXED-SIGNAL DESIGNIvica Ignjić2017Paper2017paper
Connectivity and BeyondShahid Ikram, Joseph DErrico, Yasmin Farhan, Jim Ellis, and Tushar Parikh2019Presentation2019presentation
Connectivity and BeyondShahid Ikram, Joseph DErrico, Yasmin Farhan, Jim Ellis, and Tushar Parikh2019Paper2019paper
Conquer the Graphics Legacy: Develop the Customized UVM VIP Embedded a Cycle-based C++ Reference ModelRoman Wang2019Poster2019poster
Conscious of Streams Managing Parallel StimulusJeff Wilcox2012Presentation2012presentation
Conscious of Streams: Managing Parallel StimulusJeffrey Wilcox and Stephen D’Onofrio2012Paper2012paper
Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL SynthesisRainer Findenig, Thomas Leitner, and Wolfgang Ecker2011Paper2011paper
CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTIONMartin Fröjd, Adiel Khan, and Jussi Mäkelä2014Paper2014paper
CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTIONJussi Mäkelä, Martin Fröjd, and Adiel Khan2014Presentation2014presentation
CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTIONJussi Mäkelä, Martin Fröjd, and Adiel Khan2014Presentation2014presentation
Context-Aware DFM Rule Analysis and Scoring Using Machine LearningVikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, and Jonathan Ong2018Paper2018paper
Context-Aware DFM Rule Analysis and Scoring Using Machine LearningVikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, and Jonathan Ong2018Poster2018poster
Conversion of Performance Model to Functional ModelH G Pavan Kumar, Sumail Singh Brar, Ashwani Aggarwal, Seonil Brian Choi, Woojoo Space Kim2021Paper2021paper
Coverage Closure – Is it a “Game of Dice” or “Top 10 Tests” or “Automated Closure”?Aditya Sharma, T. Nagasundaram, M. Nitin Kumar, Nikhita Raj J 2015Presentation2015presentation
Coverage Data Exchange is no robbery…or is it?Darron May and Samiran Laha2015Paper2015paper
Coverage Data Exchange is no robbery…or is it?Darron May and Samiran Laha2015Poster2015poster
Coverage Driven Distribution of Constrained Random StimuliRaz Azaria, Amit Metodi, and Marat Teplitsky2015Presentation2015presentation
Coverage Driven Distribution of Constrained Random StimuliMarat Teplitsky, Amit Metodi, and Raz Azaria2015Paper2015paper
Coverage Driven Signoff with Formal Verification on Power Management IPsBaosheng Wang and Xiaolin Chen2016Paper2016paper
Coverage Driven Signoff with Formal Verification on Power Management IPsBaosheng Wang and Xiaolin Chen2016Poster2016poster
Coverage Driven Verification of an Unmodified DUT within an OVM TestbenchMichael Baird2010Paper2010paper
Coverage Models for Formal VerificationXiushan Feng, Xiaolin Chen, and Abhishek Muchandikar2017Paper2017paper
Coverage Models for Formal VerificationXiushan Feng, Xiaolin Chen, and Abhishek Muchandikar2017Poster2017poster
COVERGATE: Coverage ExposedRich Edelman2020Paper2020paper
COVERGATE: Coverage ExposedRich Edelman2020Poster2020poster
Covering the Last Mile in SoC-Level Deadlock VerificationJef Verdonck, Khaled Nsaibia, Sagar Dewangan, HarGovind Singh and Roger Sabbagh2019Presentation2019presentation
Covering the Last Mile in SoC-Level Deadlock VerificationJef Verdonck, Dhruv Gupta, and HarGovind Singh2018Presentation2018presentation
CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemCHoang M. Le and Rolf Drechsler2014Paper2014paper
CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemCHoang M. Le and Rolf Drechsler2014Presentation2014presentation
Creating a Complete Low Power Verification Strategy using the Common Power Format and UVMRobert Meyer and Joel Artmann2012Paper2012paper
Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation RequirementsDavid Lacey and Ed Powell2018Paper2018paper
Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation RequirementsDavid Lacey and Ed Powell2018Poster2018poster
Cross Coverage of Power StatesVeeresh Vikram Singh and Awashesh Kumar2016Paper2016paper
Cross-Domain Datapath Validation Using Formal Proof AcceleratorsAarti Gupta, S. S. Bindumadhava, M. Achutha KiranKumar V, Liu Jun B2014Presentation2014presentation
Customizing UVM Agent Supporting Multi-Layered & TDM ProtocolsAmit Pessach2019Presentation2019presentation
Customizing UVM Agent Supporting Multi-Layered & TDM ProtocolsAmit Pessach2018Presentation2018presentation
Data Flow Based Memory IP Creation InfrastructureAbhilash V Nair, Praveen Buddireddy, Tor Jeremiassen, Rashmi Venkatesh, and Prajakta Bhutada2014Paper2014paper
Data path verification on cross domain with formal scoreboardLiu Jun2014Paper2014paper
Data path verification on cross domain with formal scoreboardLiu Jun2014Poster2014poster
Data-Driven Verification: Driving the next wave of productivity improvementsLarry Melling, Chris Komar, Sharon Rosenberg, Michael Young, and Hanan Moller2019Presentation2019presentation
DDR Controller IP Evaluation Studies using Trace Based MethodologyAbhilash Nair, Amit Nene, Ritesh Sojitra, Prashant Karandikar and Prajakta Bhutada2014Paper2014paper
De-mystifying synchronization between various verification components by employing novel UVM classesPushpal Nautiyal and Gaurav Chugh2016Poster2016poster
De-mystifying synchronization between various verification components by employing novel UVM classesPushpal Nautiyal and Gaurav Chugh2016Paper2016paper
Deadlock Verification For Dummies – The Easy Way of Using SVA and FormalMark Eslinger, Jeremy Levitt, and Joe Hupcey III2020Poster2020poster
Deadlock Verification For Dummies – The Easy Way Using SVA and FormalMark Eslinger, Jeremy Levitt, and Joe Hupcey III2020Paper2020paper
Dealing with Programmable IP: Where the Rubber Meets the PSS Deployment RoadKarthick Gururaj2020Presentation2020presentation
Debug APIs – next wave of innovation in DV spaceSrinivasan Venkataramanan and Ajeetha Kumari2017Poster2017poster
Debug APIs – next wave of innovation in DV spaceSrinivasan Venkataramanan and Ajeetha Kumari2017Paper2017paper
Debug Challenges in Low-Power Design and VerificationDurgesh Prasad, Madhur Bhargava, Jitesh Bansal, and Chuck Seeley2015Paper2015paper
Debug Challenges in Low-Power Design and VerificationDurgesh Prasad, Madhur Bhargava, Jitesh Bansal, and Chuck Seeley2015Poster2015poster
Debug Time Reduction by Automatic Generation of Waiver List Using ML TechniquesVardhana M, Akshay Jain, Kota Subba Rao Sajja2022Presentation2022presentation
Debugging Communicating Systems: The Blame Game – Blurring the Line Between Performance Analysis and DebugRich Edelman and Raghu Ardeishar2014Paper2014paper
Debugging Functional Coverage Models Get The Most Out of Your Cover CrossesMennatallah Amer and Amr Hany2018Paper2018paper
Debugging Functional Coverage Models Get The Most Out of Your Cover CrossesMennatallah Amer and Amr Hany2018Presentation2018presentation
Debugging Linux Kernel Failures on Virtual PlatformSandeep Jain2017Presentation2017presentation
Deep Learning for Design and Verification EngineersJohn Aynsley2018Presentation2018presentation
Deep Learning for EngineersJohn Aynsley2019Presentation2019presentation
Deep Predictive Coverage CollectionRajarshi Roy, Chinmay Duvedi, Saad Godil, and Mark Williams2018Paper2018paper
Deep Predictive Coverage CollectionRajarshi Roy, Chinmay Duvedi, Saad Godil, and Mark Williams2018Presentation2018presentation
Defining TLM+Wolfgang Ecker, Volkan Esen, Robert Schwencker, and Michael Velten2010Paper2010paper
DeltaCov: Automated Stimulus Quality Monitoring SystemNimish Girdhar, Srinivas Badam2021Paper2021paper
Democratizing Formal VerificationTobias Ludwig, Michael Schwarz, Paulius Morkunas, Silvio Santana, Dominik Stoffel, Wolfgang Kunz2021Paper2021paper
Demystifying the UVM Configuration DatabaseVanessa R. Cooper and Paul Marriott2014Paper2014paper
Demystifying the UVM Configuration DatabaseVanessa R. Cooper and Paul Marriott2014Poster2014poster
Deploying Customized Solution for Graphics Registers with UVM1.2 RALRoman Wang, Nigel Wang, Lunping Guo, Robert Liu, and Jia Zhu2018Paper2018paper
Deploying Customized Solution for Graphics Registers with UVM1.2 RALRoman Wang, Nigel Wang, Lunping Guo, Robert Liu, and Jia Zhu2018Presentation2018presentation
Deploying HLS in a DO-254/ED-80 WorkflowTammy Reeve, Jacob Wiltgen, Byron Brinson, and David Aerne2020Paper2020paper
Deploying HLS in a DO-254/ED-80 WorkflowByron Brinson Jacob Wiltgen, David Aerne and Tammy Reeve2020Poster, Presentation2020poster presentation
DEPLOYING PARAMETERIZED INTERFACE WITH UVMWayne Yun and Shihua Zhang2013Poster2013poster
Deploying Parameterized Interface with UVMWayne Yun and Shihua Zhang2013Paper2013paper
Design & Verify Virtual Platform with reusable TLM 2.0Ankush Kumar2015Presentation2015presentation
Design and verification in ARMHobson Bullman2016Presentation2016presentation
Design and Verification of a Multichip Coherence ProtocolShahid Ikram, Isam Akkawi, Richard Kessler, Jim Ellis, and David Asher2015Poster2015poster
Design and Verification of a Multichip Coherence ProtocolShahid Ikram, Isam Akkawi, Richard Kessler, Jim Ellis, and David Asher2015Paper2015paper
Design and Verification of an Image Processing CPU using UVMMilos Becvar and Greg Tumbush2013Paper2013paper
Design and Verification of an Image Processing CPU Using UVMGreg Tumbush and Milos Becvar2013Presentation2013presentation
Design Guidelines for Formal VerificationAnamaya Sullerey2015Presentation2015presentation
Design Guidelines for Formal VerificationAnamaya Sullerey2015Paper2015paper
Design Methodology for Highly Cycle Accurate SystemC Models with Better PerformanceSimranjit Singh, Prasanth Sasidharan, Sameer Deshpande, and Sandeep Puttappa2014Paper2014paper
Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012Eldon Nelson2016Presentation2016presentation
Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012Eldon Nelson M.S. P.E.2016Paper2016paper
Design space exploration of PIM (Processing in Memory) & PNC (Processing Near Memory) based on workload characterizationAmarnath, Judhajit2022Presentation2022presentation
Designers Work Less with Quality Formal Equivalence CheckingOrly Cohen, Moran Gordon, Michael Lifshits, Alexander Nadel, and Vadim Ryvchin2010Paper2010paper
Designing a PSS Reuse StrategyMatthew Ballance2019Presentation2019presentation
Designing a PSS Reuse StrategyMatthew Ballance2018Presentation2018presentation
Designing A PSS Reuse StrategyMatthew Ballance2019Paper2019paper
Designing Portable UVM Test Benches for Reusable IPsXiaoning Zhang, Baosheng Wang, and Terry Li2015Paper2015paper
Designing Portable UVM Test Benches for Reusable IPsXIAONING ZHANG and BAOSHENG WANG2015Poster2015poster
Designing PSS Environment Integration for Maximum ReuseMatthew Ballance2020Paper2020paper
Designing PSS Environment Integration for Maximum ReuseMatthew Ballance2020Presentation2020presentation
Designing the Future with Efficiency Guidance to Adopting SystemVerilog for Design!Axel Scherer and Junette Tan2015Paper2015paper
Designing, Verifying and Building an Advanced L2 Cache Sub-System using SystemCThomas Tessier, Dr. Hai Lin, Daniel Ringoen, Eileen Hickey, and Steven Anderson2012Paper2012paper
Designing, Verifying and Building an Advanced L2 Cache Subsystem using SystemCSteve Frank, Thomas Tessier, Dr. Hai Lin, Daniel Ringoen, Eileen Hickey, and Steven Anderson2012Presentation2012presentation
Detecting Circular Dependencies in Forward Progress CheckersSaurabh Chaurdia, Arun Khurana, Naveen Kumar, Aditya Chaurasiya, Yogesh Mahajan, Prasenjit Biswas2021Paper2021paper
Detecting Harmful Race Conditions in SystemC Models Using Formal TechniquesSven Beyer and Dominik Strasser2015Presentation2015presentation
Detecting Harmful Race Conditions in SystemC Models Using Formal TechniquesSven Beyer and Dominik Strasser2015Paper2015paper
Detection of glitch-prone clock and reset propagation with automated formal analysisKaushal Shah, Sulabh Kumar Khare2021Paper2021paper
Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog AssertionsKelly D. Larson2014Paper2014paper
Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog AssertionsKelly D. Larson2014Presentation2014presentation
Detoxify Your Schedule With A Low-Fat UVM EnvironmentNihar Shah2016Paper2016paper
Detoxify Your Schedule With A Low-Fat UVM Environment A success story on using self-checking stimulus instead of a scoreboard to reduce development time2016Poster2016poster
Developing & Testing Automotive Software on Multi SoC ECU Architectures using Virtual PrototypingSam Tennent2018Presentation2018presentation
Developing a Portable Block Testbench and Reusable SOC Verification Scenarios Using IP XACT Based AutomationTaejin Kim, Minjae Kim, Yonghyun Yang, Hyundon Kim, Daewoo Kim, Tae Hee Han, and Seonil Brian Choi2020Presentation2020presentation
Developing Dynamic Resource Management System in SoCEmulationSeonchang Choi, Sangwoo Noh, Seonghee Yim and Seonil Brian Choi2019Presentation2019presentation
Developing Dynamic Resource Management System in SoCEmulationSeonchang Choi and Seonghee Yim2018Presentation2018presentation
Development of Flexi Performance Analysis Platform for Multi–SoC Networking SystemsSrinivasan Reddy Devarajan, Anant Raj Gupta, IngoVolkening, Franz Josef Schaefer and Vijay Raj Franklin Paul Rajan William2019Presentation2019presentation
Did Power Management Break My CDC Logic? An Integrated Approach to Power Domain and Clock Domain Crossing VerificationAshish Amonkar, Kurt Takara, and Avinash Agrawal2020Presentation2020presentation
Digital mixed-signal low power verification with Unified Power Format (UPF)Srilakshmi D R and Geeta Krishna Chaitanya Puli2021Poster2021poster
Digital mixed-signal low power verification with Unified power format (UPF)Srilakshmi D R and Geeta Krishna Chaitanya Puli2021Presentation2021presentation
Digital Transformation of EDA Environments To Accelerate Semiconductor InnovationGuru Charan Prasad Jonnalagadda2022Presentation2022presentation
Digitizing Mixed Signal VerificationDavid Brownell and Courtney Schmitt2014Paper2014paper
Digitizing Mixed Signal Verification: Digital Verification Techniques Applied to Mixed Signal and Analog Blocks on the LMA ProjectDavid Brownell and Courtney Schmitt2014Presentation2014presentation
Disciplined Post Silicon Validation using ML IntelligenceAmaresh Chellapilla, Pandithurai Sangaiyah2022Presentation2022presentation
Discovering Deadlocks in a Memory Controller IPJef Verdonck, Emrah Armagan, Khaled Nsaibia, Slava Bulach, Pranay Gupta, Anshul Jain, Chirag Agarwal and Roger Sabbagh2020Paper2020paper
Discovering Deadlocks in a Memory Controller IPJef Verdonck, Emrah Armagan, Khaled Nsaibia, Slava Bulach, Pranay Gupta, Anshul Jain, Chirag Agarwal, and Roger Sabbagh2020Presentation2020presentation
Distributed Simulation of UVM TestbenchTheta Yang2016Poster2016poster
Distributed Simulation of UVM TestbenchTheta Yang2016Paper2016paper
Do You Know What Your Assertions Are up To? A New Approach to Safety Critical VerificationLee C. Smith2016Presentation2016presentation
Do You Know What Your Assertions Are Up To? A New Approach to Safety Critical VerificationLee C. Smith2016Paper2016paper
Do You Verify Your Verification Components?Josh Rensch and Neil Johnson2016Poster2016poster
Does It Pay Off To Add Portable Stimulus Layer On Top Of UVM IP Block Test Bench?Xia Wu, Jacob Sander Andersen, and Ole Kristoffersen2020Presentation2020presentation
Does It Pay Off To Add Portable Stimulus Layer On Top Of UVM IP Block Test Bench?Xia Wu, Jacob Sander Andersen and Ole Kristoffersen2020Paper2020paper
Doing Funny Stuff with the UVM Register Layer: Experiences Using Front Door Sequences, Predictors, and CallbacksJohn Aynsley2017Presentation2017presentation
Doing Funny Stuff with the UVM Register Layer: Experiences Using Front Door Sequences, Predictors, and CallbacksJohn Aynsley2017Paper2017paper
Don’t delay catching bugs: Using UVM based architecture to model external board delaysAmit Paunikar, Saurabh Arya, Vikas Makhija, and Shaily Khare2018Poster2018poster
Don’t delay catching bugs: Using UVM based architecture to model external board delaysAmit Paunikar, Saurabh Arya, Vikas Makhija, and Shaily Khare2018Paper2018paper
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in SiliconAbdelouahab Ayari, Sukriti Bisht, Sulabh Kumar Khare and Kurt Takara2019Presentation2019presentation
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in SiliconAbdelouahab Ayari, Sukriti Bisht, Sulabh Kumar Khare, and Kurt Takara2018Presentation2018presentation
Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to SimulationJonathan Bromley2015Presentation2015presentation
Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to SimulationJonathan Bromley2015Paper2015paper
DPI Redux. Functionality. Speed. Optimization.Rich Edelman, Rohit Jain, and Hui Yin2017Paper2017paper
DPI Redux. Functionality. Speed. Optimization.Rich Edelman, Rohit Jain, and Hui Yin2017Presentation2017presentation
Driving Analog Stimuli from a UVM TestbenchSatvika Challa, Amlan Chakrabarti 2015Poster2015poster
DV Methodology to Model Scalable/Reusable Component to Handle IO Delays/Noise/Crosstalk in Multilane DDR PHY IFTapas Ranjan Jena, Gowdra Bomanna Chethan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath2019Paper2019paper
DVCon EU 2014 Proceedings2014Program2014program
DVCon EU 2015 Proceedings2015Program2015program
DVCon EU 2016 Proceedings2016Program2016program
DVCon EU 2017 Proceedings2017Program2017program
DVCon EU 2018 Proceedings2018Program2018program
DVCon EU 2019 Proceedings2019Program2019program
DVCon EU 2020 Proceedings2020Program2020program
DVCon EU 2020 ProceedingsAccellera Systems Initiative2020Video2020video
DVCon EU 2021 Proceedings2021Program2021program
DVCon Europe 2015 Road to self driving cars: View of a semiconductor companyHans Adlkofer2015Presentation2015presentation
DVCon India 2021 ProceedingsAccellera Systems Initiative2021Video2021video
DVCon U.S 2021 Proceedings2021Program2021program
DVCon U.S. 2021 ProceedingsAccellera Systems Initiative2021Video2021video
DVCon U.S. 2022 Proceedings2022Video2022video
DVCon US 2022 Proceedings2022Program2022program
DVS Interface Element – A Novel Approach in Multi-Power Domain, Mixed-Signal Design VerificationVijay Kumar Sankaran, Ji Du, Qingyu Lin, Arumugan A, and Badrinarayan Zanwar2016Paper2016paper
DVS Interface Element—A Novel Approach in Multi-Power Domain, Mixed-Signal Design VerificationShekar Chetput2016Poster2016poster
Dynamic and Scalable OVM Stimulus for Accelerated Functional CoverageMichael J Castle2012Paper2012paper
Dynamic Control Over UVM Register Backdoor HierarchyRoy Vincent, Unnikrishnan Nath, and Ashok Chandran2019Poster2019poster
Dynamic Fault Injection Library Approach for SystemC AMSThomas Markwirth, Paul Ehrlich, and Dominik Matter2016Presentation2016presentation
Dynamic Fault Injection Library Approach for SystemC AMSThomas Markwirth, Paul Ehrlich, and Dominik Matter2016Paper2016paper
Dynamic Parameter Configuration of SystemC ModelsShruti Baindur, Simranjit Singh2015Presentation2015presentation
Dynamic Power Automation UVM FrameworkRaghavendra J N, Gudidevuni Harathi2015Poster2015poster
Dynamic Regression Suite Generation Using Coverage-Based ClusteringShahid Ikram and Jim Ellis2017Presentation2017presentation
Dynamic Regression Suite Generation Using Coverage-Based ClusteringShahid Ikram and Jim Ellis2017Paper2017paper
Dynamically Optimized Test Generation Using Machine LearningRajarshi Roy, Mukhdeep Singh Benipal, Saad Godil2021Paper2021paper
e/eRM to SystemVerilog/UVM: Mind the Gap, But Don’t Miss the TrainAvidan Efody and Michael Horn2012Paper2012paper
e/eRM to SystemVerilog/UVM: Mind the Gap, But Don’t Miss the TrainMichael Horn2012Presentation2012presentation
Early Design and Validation of an AI Accelerator’s System Level Performance Using an HLS Design MethodologyWenbo Zheng2021Presentation2021presentation
Early Performance Verification of Embedded Inferencing Systems using open source SystemC NVIDIA MatchLibHerbert Taucher and Russell Klein2019Presentation2019presentation
EARLY SOFTWARE DEVELOPMENT AND VERIFICATION METHODOLOGY USING HYBRID EMULATION PLATFORMWoojoo Kim, Haemin Park, Hyundon Kim, Seonil Brian Choi, and SukWon Kim2017Paper2017paper
EASI2L: A Specification Format for Automated Block Interface Generation and VerificationChintan Kaur, Ravi Narayanaswami, and Richard Ho2016Paper2016paper
Easier SystemVerilog with UVM: Taming the BeastJohn Aynsley2012Paper2012paper
Easier SystemVerilog with UVM: Taming the BeastJohn Aynsley2012Presentation2012presentation
Easier UVM – Coding Guidelines and Code GenerationJohn Aynsley and Dr. Christoph Sühnel2014Paper2014paper
Easier UVM – Making Verification Methodology More ProductiveJohn Aynsley, David Long2014Presentation2014presentation
Easier UVM – Making Verification Methodology More ProductiveJohn Aynsley and David Long2014Presentation2014presentation
Easier UVM for Functional Verification by Mainstream UsersJohn Aynsley2011Paper2011paper
Easier UVM: Learning and Using UVM with a Code GeneratorJohn Aynsley, Doulos2015Presentation2015presentation
Easy Steps Towards Virtual Prototyping using the SystemVerilog DPIDave Rich2013Paper2013paper
Easy uvm_config_db use: A simplified and reusable uvm_config_db methodology for environment developers and test writersBob Oden2015Paper2015paper
Easy uvm_config_db use: A simplified and reusable uvm_config_db methodology for environment developers and test writersBob Oden2015Poster2015poster
Effective Formal Deadlock Verification Methodologies for Interconnect designSachin Kumar, Rajesh C M2022Presentation2022presentation
Effects of Abstraction in Stimulus Generation of Layered Protocols within OVMJosh Rensch and Jesse Prusi2010Paper2010paper
Efficacious verification of Loopback and Equalization in PCIe By Using Novel approachJaydeep Suvariya, Pinal Patel2022Presentation2022presentation
Efficient and Exhaustive Floating Point Verification Using Sequential Equivalence CheckingTravis W. Pouarz and Vaibhav Agrawal2017Paper2017paper
Efficient and Exhaustive Floating Point Verification Using Sequential Equivalence CheckingTravis Pouarz and Vaibhav Agrawal2017Presentation2017presentation
Efficient and Faster Handling of CDC/RDC ViolationsAshish Kumar Gupta2017Presentation2017presentation
Efficient Bug-Hunting Techniques Using Graph-Based Stimulus ModelsNguyen Le and Mike Andrews2016Presentation2016presentation
Efficient Bug-Hunting Techniques Using Graph-Based Stimulus ModelsNguyen Le and Mike Andrews2016Paper2016paper
Efficient Clock Monitoring System for SoC Clock VerificationNam Pham Van2016Presentation2016presentation
Efficient Clock Monitoring System for SoC Clock VerificationNam Pham Van, Bernhard Braun, Dirk Moeller, and Clemens Roettgermann2016Paper2016paper
Efficient Constrained Random Generation of Address Blocks: A comparative study of simulation speedsMeenakshy Ramachandran2015Paper2015paper
Efficient Constrained Random Generation of Address Blocks: A comparative study of simulation speedsMeenakshy Ramachandran2015Poster2015poster
Efficient distribution of video frames to achieve better throughputBhavik Vyas and Suruchi Jain2012Paper2012paper
Efficient Exploration of Safety-Relevant Systems Through a Link Between Analysis and SimulationMoomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello, and Bogdan-Andrei Tabacaru2016Presentation2016presentation
Efficient Exploration of Safety-Relevant Systems Through a Link Between Analysis and SimulationMoomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello, and Bogdan-Andrei Tabacaru2016Paper2016paper
Efficient Fault Injection Methods for Safety Software Testing Based on Virtual Prototypes: Application to Powertrain ECUOns Mbarek, Dineshkumar Selvaraj, and Romero Chica Jose Miguel2018Paper2018paper
Efficient Formal strategies to verify the robustness of the designSakthivel Ramaiah2022Presentation2022presentation
Efficient hierarchical low power verification of custom designs using static and dynamic techniquesHimanshu Bhatt, Archanna Srinivasan, and Chong Lee Kuay2019Poster2019poster
Efficient methods for analog mixed signal verification Interface handling methods, trade-offs and guidelinesLakshmanan Balasubramanian, Shoeb Siddiqui, and Vijay Kumar Sankaran2014Paper2014paper
Efficient Methods for Display Power Estimation & VisualizationSrikanth Reddy Rolla and Aakash Modi2020Poster2020poster
Efficient Methods for Display Power Estimation and VisualizationSrikanth Reddy Rolla and Aakash Modi2020Paper2020paper
Efficient Regression Management with Smart Data Mining Technique Tejbal Prasad2022Presentation2022presentation
Efficient SCE-MI Usage to Accelerate TBA PerformancePonnambalam Lakshmanan, Prashantkumar Ravindra, and Rajarathinam Susaimanickam2017Paper2017paper
Efficient Simulation Based Verification by ReorderingChao Ya and Kevin Jones2010Paper2010paper
Efficient SoC Level Mixed Signal Frontend Verification using Wreal ModelsAnu Marisha, Nayana Prakash, Udit Kumar, Rajesh Tiwari, and Vijay Kumar Birange2014Paper2014paper
Efficient SoC Level Mixed Signal Frontend Verification using Wreal ModelsAnu Marisha, Nayana Prakash, Udit Kumar, and Rajesh Tiwari2014Presentation2014presentation
Efficient Standard Co-Emulation Modeling Interface (SCE-MI) Usage to Accelerate TBA PerformancePonnambalam Lakshmanan2017Presentation2017presentation
Efficient use of Virtual Prototypes in HW/SW Development and VerificationRocco Jonack and Eyck Jentzsch2018Presentation2018presentation
Efficient Verification Framework for Audio/Video InterfacesNoha Shaarawy2015Presentation2015presentation
Efficient Verification of Mixed-Signal SerDes IP Using UVMVarun R, Vinayak Hegde, Cadence Bangalore2017Presentation2017presentation
Effortless, Methodical and Exhaustive Register Verification using what you already haveAishwarya Sridhar, Pallavi Atha, and David Crutchfield2021Poster2021poster
Effortless, Methodical and Exhaustive Register Verification using what you already have.Aishwarya Sridhar, Pallavi Atha, and David Crutchfield2021Presentation2021presentation
Embedded UVMPuneet Goel2017Presentation2017presentation
Embrace Errors! Architecting UVM Testbenches for Dynamic Error Injection & HandlingSushrut B Veerapur, Kilaru Vamsikrishna2022Poster2022poster
Embracing Datapath Verification with Jasper C2RTL AppVaibhav Mittal, Sourav Roy, Anshul Singhal2022Presentation2022presentation
Embracing Formal Verification for Data Path Designs Using Golden SpecsAchutha Kirankumar V, Disha Puri, Bindumadhava S.S2017Presentation2017presentation
EMULATION BASED FULL CHIP LEVEL LOW POWER VALIDATION AT PRE-SILICON STAGEKyoungmin Park, Jaegeun Song, Hyundon Kim, Seonil Brian Choi, and Suk Won Kim2017Paper2017paper
Emulation Based Power and Performance Workloads on ML NPUsPragati Mishra, Ritu Suresh, Issac Zacharia, and Jitendra Aggarwal2022Poster2022poster
Emulation Based Power and Performance Workloads on ML NPUsPragati Mishra, Ritu Suresh, Issac Zacharia, and Jitendra Aggarwal2022Paper2022paper
Emulation based Power and Performance Workloads on ML NPUsPragati Mishra, Ritu Suresh, Issac P Zacharia, Jitendra Aggarwal2021Paper2021paper
Emulation Testbench Optimizations for better Hardware Software Co-ValidationVijayakrishnan Rousseau, Suresh Balasubramanian, Srikanth Reddy Rolla, and Mohamed Saheel Nandikotkur Hussainsaheb2019Poster2019poster
Enabling Digital Mixed-Signal Verification of Loading Effects in Power Regulation using SystemVerilog User-Defined NettypeAlvaro Caicedo and Sebastian Fritz2019Presentation2019presentation
Enabling Digital Mixed-Signal Verification of Loading Effects in Power Regulation using SystemVerilog User-Defined NettypeAlvaro Caicedo and Sebastian Fritz2018Presentation2018presentation
Enabling Energy Aware System Level Design with UPF-Based System Level Power ModelsT4A and T4B2014Presentation2014presentation
Enabling Exhaustive Reset Verification Enablement: Client PCIE Design Reset Verification Case StudyRohit Kumar Sinha, Praveen Dornala2019Presentation2019presentation
Enabling high quality design sign-off with structural and auto formal checksTimmapur, Guruprasad Haridas, Vishnu Rastogi, Mansi2022Presentation2022presentation
Enabling Shift-Left through FV Methodologies on Intel® Graphics DesignsM. Achutha KiranKumar V, Aarti Gupta Bindumadhava S S, Aishwarya R2015Presentation2015presentation
Enabling Visual Design Verification Analytics – From Prototype Visualizations to an Analytics Tool using the Unity Game EngineMarkus Borg, Andreas Brytting, and Daniel Hansson2018Paper2018paper
End to End Formal Verification Strategies for IP VerificationJacob Ryan Maas, Nirabh Regmi, Ashish Kulkarni, and Krishnan Palaniswami2017Paper2017paper
End to End Formal Verification Strategies for IP VerificationJacob Ryan Maas, Nirabh Regmi, Krishnan Palaniswami, and Ashish Kulkarni2017Poster2017poster
Engaging with IEEE through StandardsSri Chandra, Dennis Brophy2022Presentation2022presentation
Engineered SystemVerilog ConstraintsJeremy Ridgeway2015Presentation2015presentation
Engineered SystemVerilog ConstraintsJeremy Ridgeway2015Paper2015paper
Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software VerificationVictor Besyakov2022Poster2022poster
Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software VerificationVictor Besyakov2022Paper2022paper
Enhanced LDPC Codec Verification in UVMShriharsha Koila, Ganesh Shetti, Prateek Jain, Anand Shirahatti2019Paper2019paper
Enhancements of metric driven verification for the ISO26262: Recent advancements better supporting specific verification requirements including functional safetyMichael Rohleder, Clemens Röttgermann, Stephan Rüttiger, John Brennan, Matt Graham, and Riccardo Oddone2016Paper2016paper
Enhancing Productivity in Formal Testbench Generation for AHB based IPsShubham Goyal, Ishan Patil, Senthilnath Subbarayan, and Sandeep Kumar2021Poster2021poster
Enhancing Quality and Coverage of CDC Closure in Intel’s SoC DesignRohit Kumar Sinha2020Paper2020paper
Enhancing Quality and Coverage of CDC Closure in Intel’s SoC DesignRohit Kumar Sinha2020Presentation2020presentation
Enhancing The Effectiveness of a Constrained Random Test Suite Using Supervised Machine Learning AlgorithmPonnambalam Lakshmanan, Rajarathinam Susaimanickam2017Presentation2017presentation
Enriching UVM in SystemC with AMS extensions for randomization and functional coverage*Thilo Vörtler, Thomas Klotz, Karsten Einwich, Yao Li, Zhi Wang, Marie-Minerve Louërat, Jean-Paul Chaput, François Pêcheux, Ramy Iskander, and Martin Barnasconi2014Paper2014paper
Enriching UVM in SystemC with AMS extensions for randomization and functional coverage*Thilo Vörtler, Thomas Klotz, Karsten Einwich, Yao Li, Zhi Wang, Marie-Minerve Louërat, Jean-Paul Chaput, François Pêcheux, Ramy Iskander, and Martin Barnasconi2014Presentation2014presentation
Ensuring Quality of Next Generation Automotive SoC: System’s ApproachPankaj Singh2015Presentation2015presentation
Environment for efficient and reusable SystemC module level verificationFlavia Gontia2014Paper2014paper
Environment for efficient and reusable SystemC module level verificationFlavia Gonția2014Presentation2014presentation
Equivalence Validation of Analog Behavioral ModelsHardik Parekh, Manish Kumar Karna, Mohit Jain, Atul Pandey, and Sandeep Mittal2014Paper2014paper
Equivalence Validation of Analog Behavioral ModelsHardik Parekh, Manish Kumar Karna, Mohit Jain, Atul Pandey, and Sandeep Mittal2014Poster2014poster
Equivalence Validation of Analog Behavioral ModelsManish Kumar Karna, Hardik Parekh, Mohit Jain, Atul Pandey, and Sandeep Mittal2014Poster2014poster
Eradicating X-bugs and Achieving Higher Design Quality Using Static X-propagation Sign-offSanjay Thatte, Andrew Guyler, Nikhil Rahagude, and Savitha Raghunath2020Presentation2020presentation
Error Injection in a Subsystem Level Constrained Random UVM TestbenchJ. Ridgeway and H. Nguyen2018Paper2018paper
Error Injection in a Subsystem Level Constrained Random UVM TestbenchJeremy Ridgeway and Hoe Nguyen2018Presentation2018presentation
Error Injection: When Good Input Goes BadKurt Schwartz and Tim Corcoran2017Paper2017paper
Error Injection: When Good Input Goes BadKurt Schwartz and Tim Corcoran2017Presentation2017presentation
ESL Design and Modeling with SystemCAMS for Mixed-Signal IoTand Automotive ApplicationsKarsten Einwich, Martin Barnasconi, Christoph Grimm, and Torsten Mähne2017Presentation2017presentation
Essential Adjuncts of Verification InfrastructureKunal Panchal, Harshit Mehta2017Presentation2017presentation
Estimating Power Dissipation of End-User Application on RTLMagdy El-Moursy2022Presentation2022presentation
Evaluating the Feasibility of a RISC V Core for Real Time Applications Using a Virtual PrototypeJ. Santana , G. Pachiana, T. Markwirth, C. Sohrmann, B. Fischer, M. Matschnig 2022Presentation2022presentation
Evaluating the Feasibility of a RISCV Core for Real-Time Applications Using a Virtual PrototypeJuan Santana, Gabriel Pachiana, Thomas Markwirth, Christoph Sohrmann, Bernhard Fischer, and Martin Matschnig2022Paper2022paper
Every Cloud – Post-Silicon Bug Spurs Formal Verification AdoptionBlaine Hsieh, Stewart Li, and Mark Eslinger2015Presentation2015presentation
Every Cloud – Post-Silicon Bug Spurs Formal Verification AdoptionBlaine Hsieh, Stewart Li, and Mark Eslinger2015Paper2015paper
Evolution of CDC recipe: Learning through real case studies and methodology improvementsAmit Kulkarni, Suhas DS, Deepmala Sachan2021Paper2021paper
Evolution of Triage: Real-time Improvements in Debug ProductivityGordon Allan2016Paper2016paper
Exhaustive Equivalence Checking on AMD’s Next-generation Microprocessor CoreBaosheng Wang, Brian McMinn, Borhan Roohipour, Ashok Venkatachar, Arun Chandra, Richard Bartolotti, and Lerzan Celikkanat2011Paper2011paper
Exhaustive Latch Flow – Through Verification with Formal MethodsBaosheng Wang, Sean Ater, Baris Piyade, Brian McMinn, and Borhan Roohipour2012Presentation2012presentation
Exhaustive Latch Flow-through Verification with Formal MethodsBaosheng Wang, Sean Ater, Baris Piyade, Brian McMinn, and Borhan Roohipour2012Paper2012paper
Exhaustive Reset Verification Enablement: Client PCIE Design Reset Verification Case StudyRohit Kumar Sinha, Praveen Dornala2019Paper2019paper
Exhaustive validation of a cache memory controller using Formal Verification to meet performance and timing requirementsHimani Jawa, Nishant Raman, Sini Balakrishnan, Manas Karanjekar2022Presentation2022presentation
Expedite any Simulation with DMTCP and Save Decades of ComputationBalaji R, Sathish Kumar Sugumaran, Rohan Garg, Jiajun Cao2017Presentation2017presentation
Expediting the Code Coverage Closure Using Static Formal Techniques – A Proven Approach at Block and SoC Levels2015Presentation2015presentation
Expediting Verification of Critical SoC Components Using Formal MethodsNuni Srikanth, Lakshman Easwaran, Maddipatla Shankar Naidu2014Presentation2014presentation
Experience of Using Formal Verification for a Complex Memory Subsystem DesignSujeet Kumar, Vandana Goel, Hrushikesh Vaidya and Ronak Sarikhada2020Paper2020paper
Experience of using Formal Verification for a Complex Memory Subsystem DesignSujeet Kumar,Vandana Goel,Hrushikesh Vaidya, and Ronak Sarikhada2020Poster, Presentation2020poster presentation
Experience with OVM-Based Mixed-Signal Verification of the Impedance Calibration Block for a DDR InterfaceHarry Wang, Wessam El-Naji, and Kenneth Bakalar2012Paper2012paper
Experience with OVM-Based Mixed-Signal Verification of the Impedance Calibration Block for a DDR InterfaceHarry Wang, Wessam El-Naji, and Kenneth Bakalar2012Presentation2012presentation
Experiences in Migrating a Chip-Level Verification Environment from UVM EA to UVM 1.1Ashish Kumar, Dave Stang, Dudyala Sasidhar, S, Manikandan, and Thirumalai Srishan2012Paper2012paper
Experiences in Migrating a Chip-Level Verification Environment from UVM-EA to UVM-1.xAshish Kumar, S Manikandan, Sasidhar Dudyala, Srishan Thirumalai, and Dave Stang2012Presentation2012presentation
Experiencing Checkers for a Cache Controller DesignBen Cohen, Srinivasan Venkataramanan, Ajeetha Kumari, and Lisa Piper2010Paper2010paper
Exquisite modeling of verification IP: Challenges and RecommendationsAnuradha Tambad, Subashini Rajan, Shivani Upasani, Prashanth Srinivasa, Imran Ali, and Adiel Khan2012Paper2012paper
Exquisite Modeling of VIPAdiel Khan, Anuradha Tambad, Imran Ali, Prashanth Srinivasa, Shivani Upasani, and Subashini Rajan2012Presentation2012presentation
Extendable Messaging Techniques for Debugging and Analyzing UVM Testbench Structure and Transaction FlowJun Zhao, Bindesh Patel, and Rex Chen2013Presentation2013presentation
Extendable Messaging Techniques for Debugging and Analyzing UVM Testbench Structure and Transaction FlowJun Zhao, Bindesh Patel, and Rex Chen2013Paper2013paper
Extending a Traditional VIP to Solve PHY Verification ChallengesAmit Tanwar, Manoj Manu2015Presentation2015presentation
Extending functionality of UVM components by using Visitor design patternDarko M. Tomušilović2018Presentation2018presentation
Extending functionality of UVM components by using Visitor design patternDarko M. Tomušilović2018Paper2018paper
Extending Proven Digital Verification Techniques for Mixed-Signal SoCswith VCS AMSHelene Thibieroz, Adiel Khan, Pierluigi Daglio, and Gernot Koch2014Presentation2014presentation
Extending the UVM register model generation and integration flow to support user-defined scenarios and register mask valuesShuang Han, Kees van Kaam, and Martin Barnasconi2017Paper2017paper
Extending the UVM register model generation and integration flow to support user-defined scenarios and register mask valuesShuang Han, Kees van Kaam, and Martin Barnasconi2017Presentation2017presentation
Extending UVM Register Abstraction Layer for Verification of Register Access via Serial Bus InterfaceDarko M. Tomušilović2016Presentation2016presentation
Extending UVM Register Abstraction Layer for Verification of Register Access via Serial Bus InterfaceDarko Tomušilović2016Paper2016paper
Extension of the Power-Aware IP Reuse Approach to ESLAntonio Genov, Loic Leconte, Fran ç ois Verdier2022Presentation2022presentation
Fabric VerificationGalen Blake and Steve Chappell2012Presentation2012presentation
Facilitating Transactions in System Verilog and VHDLRich Edelman2020Presentation2020presentation
Facilitating Transactions in VHDL and SystemVerilogRich Edelman2020Paper2020paper
Failure Triage: The Neglected Debugging ProblemSean Safarpour, Evean Qin, Yu-Shen Yang, and Brian Keng2012Paper2012paper
Failure Triage: The Neglected Debugging ProblemSean Safarpour, Evean Qin, Yu-Sheng Yang, and Brian Keng2012Presentation2012presentation
Fast and Furious Quick Innovation from Idea to Real PrototypeSimone Fontanesi, Gaetano Formato, Thomas Arndt, and Andrea Monterastelli2018Paper2018paper
Fast and FuriousQuick Innovation from Idea to Real PrototySimone Fontanesi, Gaetano Formato, Thomas Arndt, and Andrea Monterastelli2018Presentation2018presentation
Fast forward Software Development using Advanced Hybrid TechnologiesXiaowei Pan2021Presentation2021presentation
Fast Track Formal Verification SignoffMandar Munishwar, Xiaolin Chen, Arunava Saha, and Sandeep Jana2018Poster2018poster
Fast Track Formal Verification SignoffMandar Munishwar, Xiaolin Chen, Arunava Saha, and Sandeep Jana2018Paper2018paper
Fault Campaign Framework for FuSa Verification of ISO 26262 Compliant Automotive ProductsPrashantkumar Ravindr, Mangesh Pande, and Vinay Rawat2021Presentation2021presentation
Fault Campaign Framework for FuSa Verification of ISO 26262 Compliant Automotive ProductsPrashantkumar Ravindra, Mangesh Pande, and Vinay Rawat2021Poster2021poster
Fault Effect Propagation using Verilog A for Analog Test CoverageAishwarya Prabhakaran, Ahmed Sokar, and Jaafar Mejri2018Presentation2018presentation
Fault Effect Propagation using Verilog-A for Analog Test CoverageAishwarya Prabhakaran, Ahmed Sokar and Jaafar Mejri2018Paper2018paper
Fault Injection Made Easy Unified Formal Verification of Normal and Safety FunctionsSergio Marchese, Jörg Grosse, Ashish Darbari2017Presentation2017presentation
Fault Injection Strategy to Validate ASIL-D Requirements of BMS ComponentsPraneeth Uddagiri, Veera Satya Sai Gavirni, Prashantkumar Ravindra2022Presentation2022presentation
Fault Proof: Using Formal Techniques for Safety Verification and Fault AnalysisAdrian Traskov, Thorsten Ehrenberg, Sacha Loitz, Abdelouahab Ayari, Avidan Efody, and Joseph Hupcey III2016Presentation2016presentation
Fault Proof: Using Formal Techniques for Safety Verification and Fault AnalysisAdrian Traskov,Thorsten Ehrenberg, Sacha Loitz, Abdelouahab Ayari, Avidan Efody, and Joseph Hupcey III2016Paper2016paper
Fault-Effect Analysis on Multiple Abstraction Levels in Hardware ModelingB-A. Tabacaru, M. Chaari, W. Ecker, T. Kruse, and C. Novello2016Presentation2016presentation
Fault-Effect Analysis on Multiple Abstraction Levels in Hardware ModelingBogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, and Cristiano Novello2016Paper2016paper
Filtering noise in RDC analysis by clockoff specificationAnupam Saxena, Inayat Ali, SulabhKumar Khare, and Atul Sharma2021Poster2021poster
Filtering noise in RDC analysis by clockoff specificationAnupam Saxena, Inayat Ali, Sulabh Kumar Khare and Atul Sharma2021Presentation2021presentation
Finding a Needle in a Haystack: A Novel Log Analysis Method with Test Clustering in Distributed SystemJin Choi2022Presentation2022presentation
Finding a Needle in a Haystack: A Novel Log Analysis Method with Test Clustering in Distributed SystemsJin Choi, Sangwoo Noh, Sooncheol Hong, Hanna Jang, Seonghee Yim, and Seonil Brian Choi2022Paper2022paper
Finding Hidden Bugs In Deep Cycles: Advanced Debug Methodologies for Software-first System ValidationYoucef Qassid and Andy Jolley2022Presentation2022presentation
Finding the Last Bug in a CNN DMA UnitBruno Lavigueur, Dean Ke, Eric Rao, Fergus Casey, Achin Mittal, Pallavi Kumari, Michael Thompson, and Roger Sabbagh2020Paper2020paper
Finding the Last Bug in a CNN DMA UnitBruno Lavigueur, Dean Ke, Eric Rao, Fergus Casey, Achin Mittal, Pallavi Kumari, Michael Thompson, and Roger Sabbagh2020Presentation2020presentation
Firmware Firmly under Control: New Optimization and Verification Techniques for Application Specific Electronic SystemDaniel Große, Manuel Strobel, Daniel Mueller-Gritschneder, Vladimir Herdt, and Tobias Ludwig2018Presentation2018presentation
First Reports from the UVM Trenches: User-friendly, Versatile and Malleable, or just the Emperor’s New Methodology?Jonathan Bromley2011Paper2011paper
Five Ways to Make Your Specman Environment More Reusable and ConfigurableStefan Sljukic, Nikola Knezevic, Filip Dojcinovic2021Paper2021paper
Flattening the UVM Learning Curve Automated Solutions for DSP Filter VerificationAvinash Lakshminarayana, Eric Jackowski, Eric Cigan, and Mark Lin2022Paper2022paper
Flattening the UVM Learning Curve: Automated Solutions for DSP Filter VerificationAvinash Lakshminarayana, Eric Jackowski,Eric Cigan, Mark Lin2022Presentation2022presentation
Flexible Checker: A one-stop shop for all your checkers and a methodology for elastic scoreboardingSaad Zahid, Chandra Veedhi, and Sumit Dhamanwala2019Poster2019poster
Flexible Indirect Registers with UVMUwe Simm2017Presentation2017presentation
Flexible Indirect Registers With UVMUwe Simm2017Paper2017paper
Flexible Indirect Registers With UVMUwe Simm2017Presentation2017presentation
Fnob: Command Line-Dynamic Random GeneratorHaoxiang Hu, Tuo Wang2022Presentation2022presentation
Fnob: Command Line-Dynamic Random GeneratorHaoxiang Hu and Tuo Wang2022Paper2022paper
Formal Architectural Specification and Verification of A Complex SOCShahid Ikram, Isam Akkawi, David Asher, and Jim Ellis2018Presentation2018presentation
FORMAL ARCHITECUTRAL SPECIFICATION AND VERIFICATION OF A COMPLEX SOCShahid Ikram, Isam Akkawi, David Asher, and Jim Ellis2018Paper2018paper
Formal Assisted Fault Campaign for ISO26262 CertificationNitin Ahuja, Mayank Agarwal, Sandeep Jana2019Paper2019paper
Formal Bug Hunting with “River Fishing” TechniquesMark Eslinger and Ping Yeung2019Presentation2019presentation
Formal Bug Hunting with “River Fishing” TechniquesMark Eslinger and Ping Yeung2019Paper2019paper
Formal Fault Propagation Analysis that Scales to Modern Automotive SoCsSergio Marchese and Jörg Grosse2017Paper2017paper
Formal Fault Propagation Analysis that Scales to Modern Automotive SoCsSergio Marchese2017Presentation2017presentation
Formal For Adjacencies Expanding the Scope of Formal VerificationM Achutha KiranKumar V, Bindumadhava Ss., Vichal Verma, Savitha Manojna2019Presentation2019presentation
Formal for Adjacencies Expanding the Scope of Formal VerificationM Achutha KiranKumar V, Bindumadhava Ss., Vichal Verma, Savitha Manojna2019Paper2019paper
Formal Methods to Verify the Power Manager for an Embedded Multiprocessor ClusterKesava R. Talu2010Paper2010paper
Formal Proof for GPU Resource ManagementJia Zhu, Chuanqin Yan, and Nigel Wang2017Presentation2017presentation
Formal Proof for GPU Resource ManagementJia Zhu, Chuanqin Yan, and Nigel Wang2017Paper2017paper
Formal Property Verification of the Digital Section of an Ultra-Low Current Digitizer ASICKatharina Ceesay-Seitz, Sarath Kundumattathil Mohanan, Hamza Boukabache, Daniel Perrin2021Paper2021paper
Formal Verification BootcampMike Bartley2019Presentation2019presentation
Formal Verification by The Book: Error Detection and Correction CodesK. Devarajegowda, V. Hiltl, T. Rabenalt, D. Stoffel, W. Kunz, and W. Ecker2020Presentation2020presentation
Formal Verification Experiences: Silicon Bug Hunt with “Deep Sea Fishing”Mark Handover, Abdelouahab Ayari and Ping Yeung2020Paper2020paper
Formal Verification Experiences: Silicon Bug Hunt with “Deep Sea Fishing”Ping Yeung, Mark Handover, and Abdelouahab Ayari2020Poster, Presentation2020poster presentation
Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug HuntPing Yeung, Mark Eslinger, Jin Hou2021Paper2021paper
Formal Verification in the Real WorldJonathan Bromley and Jason Sprott2018Presentation2018presentation
Formal Verification of a Highly Configurable DDR Controller IPSumit Neb, Chirag Agarwal, Deepak K. Gupta, and Roger Sabbagh2018Paper2018paper
Formal Verification of Connections at SoC-levelPenny Yang, Prasun Das, Yuya Kao, and Mingchu Kuo2018Paper2018paper
Formal Verification of Connections at SoC-levelPenny Yang, Prasun Das, Yuya Kao, and Mingchu Kuo2018Presentation2018presentation
FORMAL VERIFICATION OF FLOATING-POINT HARDWARE WITH ASSERTION-BASED VIPRavi Ram, Adam Elkins, Adnan Pratama, Sasa Stamenkovic, Sven Beyer, and Sergio Marchese2018Paper2018paper
Formal Verification of Floating-Point Hardware with Assertion-Based VIPRavi Ram, Adam Elkins, Adnan Pratama, Sasa Stamenkovic, Sven Beyer, and Sergio Marchese2018Presentation2018presentation
Formal verification of low-power RISC-V processorsAshish Darbari2019Paper2019paper
Formal verification of Macro-op cache for Arm Cortex-A77, and its successor CPUVaibhav Agrawal2020Paper2020paper
Formal Verification of Macro-op Cache for Arm Cortex-A77, and its Successor CPUVaibhav Agrawal2020Presentation2020presentation
Formal Verification of Silicon for Software Defined NetworkingSaurabh Shrivastava, Keqin Han, Anh Tran, Chirag Agarwal, Ankit Saxena, Achin Mittal, Anshul Jain, and Roger Sabbagh2018Paper2018paper
Formal Verification on Deep Learning Instructions of GPUJian (Jeffrey) Wang and Jia Zhu2018Paper2018paper
Formal Verification Tutorial Breaking Through the Knowledge BarrierSean Safarpour, Iain Singleton, Shaun Feng, Syed Suhaib, and Mandar Munishwar2018Presentation2018presentation
Formal Verificationin the Real WorldJonathan Bromley and Jason Sprott2017Presentation2017presentation
FPGA Debug Using Configuration ReadbackMike Dini 2015Presentation2015presentation
FPGA Implementation Validation and DebugRohit Goel, Rakesh Jain, Aman Rana, Ankit Goel2015Presentation2015presentation
FPGA-based Clock Domain Crossing Validation for Safety-Critical DesignsAlexander Gnusin2019Paper2019paper
FPGA-based Clock Domain Crossing Validation for Safety-Critical DesignsAlexander Gnusin2019Presentation2019presentation
Framework for Creating Performance Model of AI Algorithms for Early Architecture ExplorationAmit Dudeja, Amit Tara, Amit Garg, Tushar Jain2019Presentation2019presentation
Framework for Creating Performance Model of AI Algorithms for Early Architecture ExplorationAmit Dudeja, Amit Tara, Amit Garg, Tushar Jain2019Paper2019paper
Framework For Exploring Interconnect Level Cache CoherencyParvinder Pal Singh2017Presentation2017presentation
Framework for Holistic Assessment of Potential Performance Gains with Different Simulation Acceleration ModesParag Goel, Adiel Khan, Amit Sharma2015Presentation2015presentation
Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPFProgyna Khondkar, Ping Yeung, Gabriel Chidolue, Joe Hupcey, Rick Koster, and Madhur Bhargava2017Paper2017paper
Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPFProgyna Khondkar, Ping Yeung, Gabriel Chidolue, Joe Hupcey, Rick Koster, and Madhur Bhargava2017Poster2017poster
From Device Trees to Virtual PrototypesSakshi Arora, Vikrant Kamboj, Preeti Sharma2019Paper2019paper
From Spec to Verification Closure: a case study of applying UVM-MS for first pass success to a complex Mixed-Signal SoC designNeyaz Khan and Yaron Kashai2012Paper2012paper
From Spec to Verification Closure: A case study of applying UVM-MS for first pass success to a complex MS-SoC designNeyaz Khan and Yaron Kashai2012Presentation2012presentation
From the Magician’s Hat: Developing a Multi-Methodology PCIe Gen2 VIPAmit Sharma, Abhisek Verma, Varun S., and Anoop Kumar2011Paper2011paper
fsim_logic – A VHDL type for testing of FLYTRAPJoanne E. DeGroat, Ph.D.2013Paper2013paper
fsim_logic – A VHDL type for testing of FLYTRAPJoanne E. DeGroat, Ph.D.2013Presentation2013presentation
Full Flow Clock Domain Crossing – From Source To SiMark Litterick2016Presentation2016presentation
Full Flow Clock Domain Crossing – From Source to SiM. Litterick2016Paper2016paper
Fully Automated Functional Coverage ClosureManohar Kodi, Sagar Sudam Patil, and Ranjith Nair2019Paper2019paper
Fully Automated Functional Coverage ClosureManohar Kodi, Sagar Sudam Patil, and Ranjith Nair2019Presentation2019presentation
Fully Hierarchical CDC Analysis Using Comprehensive CDC Meta DatabaseYoungchan Lee, Youngsik Kim, Soenil Brian Choi, and Vikas Sachdeva2019Paper2019paper
Fully Hierarchical CDC Analysis Using Comprehensive CDC Meta-DatabaseYoungchan Lee, Youngsik Kim, and Seonil Brian Choi2019Presentation2019presentation
Fun with UVM Sequences – Coding and DebuggingRich Edelman2019Paper2019paper
Fun with UVM Sequences Coding and DebuggingRich Edelman2019Presentation2019presentation
Functional Coverage – without SystemVerilog!Alan Fitch and Doug Smith2010Paper2010paper
Functional Coverage Collection for Analog Circuits – Enabling Seamless Collaboration between Design and VerificationZ. Ye, H. Lin and A. M. Khan2016Paper2016paper
Functional Coverage Collection for Analog Circuits –Enabling Seamless Collaboration between Design and VerificationZhipeng Ye, Honghuang Lin and Asad Khan2016Presentation2016presentation
Functional Coverage GeneratorMunjal Mistry2017Presentation2017presentation
FUNCTIONAL COVERAGE OF REGISTER ACCESS VIA SERIAL BUS INTERFACE USING UVMDarko M. Tomušilovic2017Poster2017poster
Functional Coverage of Register Access via Serial Bus Interface using UVMD. M. Tomušilović2017Paper2017paper
Functional coverage-driven verification with SystemC on multiple level of abstractionChristoph Kuznik and Wolfgang M¨uller2011Paper2011paper
Functional Safety Verification For ISO 26262Kevin Rich, Shekhar Mahatme, and Meirav Nitzan2018Presentation2018presentation
Functional Safety Verification for ISO 26262 – Compliant Automotive DesignsJM Forey and Werner Kerscher2018Presentation2018presentation
Functional Safety Verification Methodology for ASIL-B Automotive DesignsOnkar Bhuskute2022Poster2022poster
Functional Verification of CSI2 Rx-PHY using AMS Co-simulationsRatheesh Mekkadan201