| A Novel Approach to Accelerate Latency of Assertion Simulation | Jack Yen, Felix Tung | | | | | |
| Building a Virtual Driver for Emulator | Chen Chih-Chiang | | | | | |
| Debug Automation with AI | Craig Yang, Jaw Lee, Sherwin Lai | | | | | |
| Design and Verification of the PLL using the new DCO and Its Applications to Built-In Speed Grading of Arithmetic Circuits | Yi-Sheng Wang, Hsiang-Kai Teng, Shi-Yu Huang | | | | | |
| Formal Sign-off Methodology for IP Blocks | Anna Chang, Chia-An Hsu | | | | | |
| Improve the quality of SystemC IPs through coverage-driven random verification | Trung Pham, Huy Phan, Masayuki Masuda | | | | | |
| Reducing the simulation life cycle time using Artificial Intelligence and Machine learning techniques on Big Data dataset | Darshan Sarod, Pratham Khande, Gopi Srinivas Deepala, Priyanka Gharat, Avnita Pal | | | | | |
| SAR ADC Layout Generation Using Digital Place-and-Route Tools | Yao-Hung Tsai and Shen-Iuan Liu | | | | | |
| Session 1.2: Improving UVM test benches using UVM Run time phases | Karthik Palepu, Lingkai Shi, Prosper Chen | | | | | |
| Session 1.3: Solving Memory Configurations Challenge with SVRAND Verification Flow | Kaushal Vala, Krunal Kapadiya, Joseph Bauer, Shyam Sharma | | | | | |
| Session 1.5: Exploring Token-Based Strategies to Enhance Data Security and Memory Management in PCIe Devices | Gopi Srinivas Deepala, Lakshya Miglani, Sastry Puranapanda | | | | | |
| Session 1.6: Verifying Configurable AndesCore Processors by Using Portable Testing and Stimulus Standard (PSS) | Luther Lee, Andy Lo, Brett Yeh | | | | | |
| Session 1.8: Adopts ISA-Formal On High-End Out-Of-Order Execute RISC-V Cores | Huang Yu-Tse, Wu Sheng-Jhan, Hsiao Yung-Ching | | | | | |
| Session 2.2: Trojan Horse Detection for RISC-V Cores Using Cross-Auditing | Siang-Cheng Huang, Shi-Yu Huang | | | | | |
| Session 2.3: Integrated verification ecosystem for regression management, coverage convergence, and debug automation | Ching-Yi Huang, William Huang, Craig Yang | | | | | |
| Session 2.7: Better Late Than Never – Collecting Coverage From Ones and Zeroes | Rich Edelman, Tsung-Yu Tsai | | | | | |
| Session 3.1: AutoDV: Boost SoC Verification by Automatic Construction | Robert / Chi-Kang Chen | | | | | |
| UVM Scoreboards and Checkers Memory, TLB and Cache | Rich Edelman, C. H. Liu | | | | | |
| UVM-based extended Low Power Library package with Low Power Multi-Core Architectures | Avnita Pal, Priyanka Gharat | | | | | |
| Verification Challenges & Solutions of 10BaseT1s Automotive Ethernet PHY | Harshdeep Verma, Vedansh Seth | | | | | |
