DV Methodology to Model Scalable/Reusable Component to Handle IO Delays/Noise/Crosstalk in Multilane DDR PHY IF

Author(s):

Tapas Ranjan Jena, Gowdra Bomanna Chethan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath

Type:

Paper

Download