Acceleration of Coreless SoC Design-Verification using PSS on Configurable Testbench in Multi-Link PCIe Subsystems

Author(s):
Thanu Ganapathy, Pravin Kumar, Garima Srivastava, Seonil Brian Choi, Harish Peta
Location:
United States
Year:
2021
Type:
Paper
Format:
pdf