| “Bounded Proof” sign-off with formal coverage | Abhishek Anand, Chinyu Chen, Bathri Narayanan Subramanian, Joe Hupcey | | | | | |
| “C” you on the faster side: Accelerating SV DPI based co-simulation | Parag Goel, Amit Sharma, and Hari Vinodh Balisetty | | | | | |
| “C” you on the faster side: Accelerating SV DPI based co-simulation | Hari Vinod Balisetty, Parag Goel, and Amit Sharma | | | | | |
| “In-Emulator” UVM++ Randomized Testbenches for High Performance Functional Verification | Adnan Hamid and David Kelf | | | | | |
| “Shift left” Hierarchical Low-Power Static Verification Using SAM | Bharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal | | | | | |
| “Shift left” Hierarchical Low-Power Static Verification Using SAM | Bharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal | | | | | |
| A 30 Minute Project Makeover Using Continuous Integration | JL Gray | | | | | |
| A 30 Minute Project Makeover Using Continuous Integration | JL Gray and Gordon McGregor | | | | | |
| A 360 Degree View of UVM Events – A Case Study | Deepak Kumar E V, Sathish Dadi, and Vikas Billa | | | | | |
| A 360 Degree View of UVM Events (A Case Study) | Deepak Kumar E V, Sathish Dadi, and Vikas Billa | | | | | |
| A Client-Server Method for Register Design and Documentation | Scott D Orangio and Julien Gagnon | 2016 | Paper | | y2016 | paper |
| A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISC V Core | Junaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, Aashir Ahsan | | | | | |
| A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISCV Core | Junaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, and Aashir Ahsan | | | | | |
| A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance Analysis | Bishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel | | | | | |
| A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance Analysis. | Bishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel | | | | | |
| A Comprehensive High Speed Link Verification Test Bench Harnessing Scripting to Achieve Faster Functional Coverage Closure. | Piyush Tankwal, Arnab Ghosh, Piyush Agnihotri, Mukesh Gandhi, Parag S Lonkar | | | | | |
| A Configurable, Re-usable UVM Environment Coupled with Advanced Spice Simulator for Analog and Mixed-Signal Verification of a Display PMIC | | | | | | |
| A Coverage-Driven Formal Methodology for Verification Sign-off | Ang Li, Hao Chen, Jason K Yu, Ee Loon Teoh, and Iswerya Prem Anand | | | | | |
| A Coverage-Driven Formal Methodology for Verification Sign-off | Ang Li, Hao Chen, Jason K Yu, Ee Loon Teoh and, Iswerya Prem Anand | | | | | |
| A Dyadic Transformation Based Methodology To Achieve Coverage Driven Verification Goal | Swapnajit Mitra | | | | | |
| A Dyadic Transformation Based Methodology to Achieve Coverage Driven Verification Goal | Swapnajit Mitra | | | | | |
| A Dynamic Approach Towards Register Coverage Generation and Collection to Reduce Compilation Overhead of Traditional UVM Register Layers | Subham Banerjee | | | | | |
| A Formal Verification App Towards Efficient Chip-Wide Clock Gating Verification | Prosenjit Chatterjee, Scott Fields, and Syed Suhaib | | | | | |
| A Formal Verification App Towards Efficient, Chip-Wide Clock Gating Verification | Prosenjit Chatterjee, Scott Fields, and Syed Suhaib | | | | | |
| A Guide To Using Continuous Integration Within The Verification Environment | Jason Sprott | | | | | |
| A Hardware and Software integrated power optimization approach with power aware simulations at SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A Hardware and Software Integrated Power Optimization Approach with Power Aware Simulations at SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power Intent | Vijay Kumar Sankaran, Lakshmanan Balasubramanian, Bharath Kumar Poluri, Venkatraman Ramakrishnan, Badrinarayan Zanwar, and Qingyu Lin | | | | | |
| A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power Intent | Qingyu Lin | | | | | |
| A Holistic View of Mixed-Language IP Integration | Pankaj Singh and Gaurav Kumar Verma | | | | | |
| A Hybrid Verification Solution to RISC V Vector Extension | Chenghuan Li, Yanhua Feng, Liam Li | | | | | |
| A Hybrid Verification Solution to RISC-V Vector Extension | Chenghuan Li, Yanhua Feng, and Liam Li | | | | | |
| A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation | Thomas Soong, Christopher Browne, and Chenhui Huang | | | | | |
| A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation | Thomas Soong, Chenhui Huang, and Christopher Browne | | | | | |
| A Methodology for Power and Energy Efficient Systems Design | Mohammed Fahad | | | | | |
| A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation Acceleration | Horace Chan, Brian Vandegriend, and Efrat Shneydor | | | | | |
| A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation Acceleration | Horace Chan, Brian Vandegriend, and Efrat Shneydor | | | | | |
| A New Approach for Generating View Generators | Johannes Schreiner, Felix Willgerodt, and Wolfgang Ecker | | | | | |
| A New Approach for Generating View Generators | Johannes Schreiner, Felix Willgerodt, and Wolfgang Ecker | | | | | |
| A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain Crossings | Omri Dassa, Yossi Mirsky | | | | | |
| A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain Crossings | Omri Dassa and Yossi (Joseph) Mirsky | | | | | |
| A New Class Of Registers | M. Peryer and D. Aerne | | | | | |
| A New Class Of Registers | Mark Peryer and David Aerne | | | | | |
| A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM Domains | Subham Banerjee and Keshava Krishna Raja | | | | | |
| A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM Domains | | | | | | |
| A Novel Approach to Verify CNN Based Image Processing Unit | Sumit K. Kulshreshtha, Raghavendra J N | | | | | |
| A Novel Variation-Aware Mixed-Signal Verification Methodology to achieve High-Sigma Variation coverage at nanometer designs | Tibi Galambos, Sumit Vishwakarma | | | | | |
| A Practical Approach to Measuring and Improving the Functional Verification of Embedded Software | Stéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès | | | | | |
| A Practical Approach to Measuring and Improving the Functional Verification of Embedded Software | Stéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès | | | | | |
| A Practical Look @ SystemVerilog Coverage – Tips, Tricks, and Gotchas | Doug Smith and John Aynsley | | | | | |
| A Reusable, Scalable Formal App for Verifying Any Configuration of 3D IC Connectivity | Daniel Han, Walter Sze, Benjamin Ting, and Darrow Chu | | | | | |
| A Semi-Formal Verification Methodology for Efficient Configuration Coverage of Highly Configurable Digital Designs | Aman Kumar, Sebastian Simon | | | | | |
| A Simplified Approach Using UVM Sequence Items for Layering Protocol Verification | Haiqian Yu and Christine Thomson | | | | | |
| A Simplified Approach Using UVM Sequence Items for Layering Protocol Verification | Christine Thomson and Haiqian Yu | | | | | |
| A Simulation Expert’s Guide to Formally Proving SW Status and Interrupts | Neil Johnson | | | | | |
| A Simulation Expert’s Guide to Formally Verifying Software Status and Interrupts | Neil Johnson | | | | | |
| A single generated UVM Register Model to handle multiple DUT configurations | Salvatore Marco Rosselli and Giuseppe Falconeri | | | | | |
| A SMART GENERATION OF DESIGN ATTRIBUTES FOR VERIFICATION CLOSURE USING SPECMAN | Meirav Nitzan, Yael Kinderman, and Efrat Gavish | | | | | |
| A Smart Synchronizer – Pragmatic way to cross asynchronous clock domains | Priyank Parakh and Steven J Kommrusch | | | | | |
| A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic | Priya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed | | | | | |
| A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic | Priya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed | | | | | |
| A Statistical and Model-Driven Approach for Comprehensive Fault Propagation Analysis of RISC-V Variants | Endri Kaja, Nicolas Gerlin, Ungsang Yun, Jad Al Halabi, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker | | | | | |
| A Statistical and Model-Driven Approach for Comprehensive Fault Propagation Analysis of RISC-V Variants | Endri Kaja, Nicolas Gerlin, Ungsang Yun, Jad Al Halabi, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker | | | | | |
| A Study on Virtual Prototyping based Design Verification Methodology | Woojoo Kim, Kunhyuk Kang, and Seonil Brian Choi. | | | | | |
| A Study on Virtual Prototyping based Design Verification Methodology | Woojoo Kim, Kunhyuk Kang, Seonil Brian Choi | | | | | |
| A Survey of Machine Learning Applications in Functional Verification | Dan Yu, Harry Foster, Tom Fitzpatrick | 2023 | Paper | | y2023 | paper |
| A Systematic Approach to Power State Table (PST) Debugging | Bhaskar Pal | | | | | |
| A Systematic Approach to Power State Table (PST) Debugging | Bhaskar Pal, Suman Nandan, Kaushik De, and Rajarshi Mukherjee | | | | | |
| A Systematic Formal Reuse Methodology: From Blocks to SoC Systems | Hao Chen, Yi Sun, Ang Li, and Dorry Cao | | | | | |
| A Systematic Take on Addressing Dynamic CDC Verification Challenges | Sukriti Bisht, Sulabh Kumar Khare, and Ashish Hari | | | | | |
| A Systematic Take on Addressing Dynamic CDC Verification Challenges | Sukriti Bisht, Sulabh Kumar Khare, and Ashish Hari | | | | | |
| A SystemC Library for Advanced TLM Verification | Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen | 2012 | Paper | | y2012 | paper |
| A SystemC Library for Advanced Verification – Towards an Enhanced OVM/UVM for SystemC | Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen | | | | | |
| A SystemVerilog Framework for Easy Method Advice in Object-oriented Test Benches | Eric Ohana | | | | | |
| A SystemVerilog Framework for Easy Method Advice in Object-oriented Test Benches | Eric Ohana | | | | | |
| A SystemVerilog Framework for Efficient Randomization of Images with Complex Inter-Pixel Dependencies | Axel Voss, Gabriel Jönsson, and Lars Viklund | | | | | |
| A Tale of Two Languages – SystemVerilog and SystemC | David C Black | | | | | |
| A Tale of Two Languages: SystemVerilog & SystemC | David C Black | | | | | |
| A Unified Testbench Architecture Solution for Verifying Variants of A PLL IP | Deepa Ananthanarayanan and Malathi Chikkanna | | | | | |
| A Unified Testbench Architecture Solution for Verifying Variants of the PLL IP | Deepa Ananthanarayanan and Malathi Chikkanna | | | | | |
| A Universal DFT Verification Environment: Filling the Gap between Function Simulation and ATE Test | Rui Huang | | | | | |
| A Universal DFT Verification Environment: Filling the Gap between Function Simulation and ATE Test | Rui Huang | | | | | |
| A UVM Multi-Agent Verification IP architecture to enable Next-Gen protocols with enhanced reusability, controllability and observability | Prathik R, Ramesh Madatha, Girish Gupta, Tony George | | | | | |
| A UVM Multi-Agent Verification IP architecture to enable Next-Gen protocols with enhanced reusability, controllability and observability | Prathik R, Ramesh Madatha, Girish Kumar Gupta, Tony Gladvin George | | | | | |
| A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers | Jaeha Kim | | | | | |
| A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers | Jaeha Kim | | | | | |
| A UVM SystemVerilog Testbench for Analog/Mixed-Signal Verification: A Digitally-Programmable Analog Filter Example | Charles Dančak | | | | | |
| A UVM SystemVerilog Testbench for Directed & Random Testing of an AMS LDO Voltage Regulator | Charles Dančak | | | | | |
| A UVM SystemVerilog Testbench for Directed & Random Testing of an AMS LDO Voltage Regulator | Charles Dančak | | | | | |
| A UVM SystemVerilog Testbench for Directed and Random Testing of an AMS Low-Dropout Voltage Regulator | Charles Dančak | | | | | |
| A UVM Testbench for Analog Verification: A Programmable Filter Example | Charles Dančak | | | | | |
| A UVM-based Approach for Rapidly Verifying Digital Interrupt Structures | Christoph Rumpler, Alexander W. Rath, and Sebastian Simon | | | | | |
| A UVM-based Approach for Rapidly Verifying Digital Interrupt Structures | Christoph Rumpler, Alexander W. Rath, Sebastian Simon, and Heinz Endres | | | | | |
| A Volterra-Series Model in SystemVerilog/XMODEL for Nonlinear RF Low-Noise Amplifiers | Chan Young Park, Jaeha Kim | | | | | |
| A Wholistic Approach to Optimizing Your System Verification Flow | Ross Dickson, Lance Tamura, Michael Young | | | | | |
| Abstract Layer for Firmware Access: A Unique Approach for SOC Functional Verification | Gupta Girish Kumar, Rugmini Navia Vishnu, Choudhary Praval, Syed Mobeenuddin | | | | | |
| Accelerate Coverage Closure from Day-1 with AI-driven Verification | Malay Ganai, Will Chen, Srikanth Vadanaparthi | | | | | |
| Accelerated simulation through design partition and HDL to C++ compilation | Theta Yang and Sga Sun | | | | | |
| Accelerated simulation through design partition and HDL to C++ compilation | Theta Yang | | | | | |
| Accelerated Verification of NAND Flash Memory using HW Emulator | Seyeol Yang, Byungwoo Kang, Seoyeon Bae, Choi Jaehyeon, Jintae Kim, Dongeun Lee, Junho Ahn | | | | | |
| Accelerated Verification of NAND Flash Memory using HW Emulator | Seyeol Yang, Byungwoo Kang, Seoyeon Bae, Choi Jaehyeon, Jintae Kim, Dongeun Lee, Junho Ahn | | | | | |
| Accelerated, High Quality SoC Memory Map Verification using Formal Techniques | Cletan Sequeira, Rajesh Kedia, Lokesh Babu Pundreeka, and Bijitendra Mittra | | | | | |
| Accelerated, High Quality SoC Memory Map Verification using Formal Techniques | Cletan Sequeira, Rajesh Kedia, Lokesh Babu Pundreeka, and Bijitendra Mittra | | | | | |
| Accelerating CDC Verification Closure on Gate-Level Designs | Anwesha Choudhury and Ashish Hari | | | | | |
| Accelerating CDC Verification Closure on Gate-Level Designs | Anwesha Choudhury and Ashish Hari | | | | | |
| Accelerating Error Handling Verification Of Complex Systems: A Formal Approach | Bhushan Parikh, Peter Graniello, Neha Rajendra | | | | | |
| Accelerating Error Handling Verification of Complex Systems: A Formal Approach | Bhushan Parikh, Peter Graniello, and Neha Rajendra | | | | | |
| Accelerating Functional Verification Through Stabilization of Testbench Using AI/ML | Srikanth Vadanaparthi, Pooja Ganesh, Dharmesh Mahay, Malay Ganai | | | | | |
| Accelerating Functional Verification Through Stabilization of Testbench Using AI/ML | Srikanth Vadanaparthi, Pooja Ganesh, Dharmesh Mahay, Malay Ganai | | | | | |
| Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing Products | Yoga Priya Vadivelu, Arpan Shah, Deepinder Singh Mohoora, Ullas, and Praveen Buddireddy | | | | | |
| Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing Products | Yoga Priya Vadivelu, Arpan Shah, Deepinder Singh Mohoora, Ullas, and Praveen Buddireddy | | | | | |
| Accelerating SoC Verification Signoff using Save & Restart/Dynamic Test Reload Enhanced Regression flow | Vanshlata B, Divya M, Garima S, Seonil Brian Choi | | | | | |
| Accelerating SOC Verification Using Process Automation and Integration | Seonghee Yim, Hanna Jang, Sunchang Choi, and Seonil Brian Choi | | | | | |
| Accelerating the IP Design Cycle with Formal Techniques Beyond Everyday FPV | Bhushan Parikh, Shaman Narayana, Buck Lem, David Cassetti | | | | | |
| Acceleration of Coreless SoC Design-Verification using PSS on Configurable Testbench in Multi-Link PCIe Subsystems | Thanu Ganapathy, Pravin Kumar, Garima Srivastava, Seonil Brian Choi, Harish Peta | | | | | |
| Accellera Functional Safety Working Group Update and Next Steps | Alessandra Nardi | | | | | |
| Accellera UVM-AMS Standard Update | Tom Fitzpatrick and Tim Pylant | | | | | |
| Ace’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power Consumption | Mehul Kumar, Tushar Mattu, and Amir Nilipour | | | | | |
| ACE’ing the Verification of a Coherent System Using UVM | Romondy Luo, Ray Varghese, Parag Goel, Amit Sharma, Satyapriya Acharya, and Peer Mohammed | | | | | |
| ACE’ing the Verification of a Coherent System Using UVM | Parag Goel; Amit Sharma, Ray Varghese, Romondy Luo, Satyapriya Acharya, Peer Mohammed | | | | | |
| ACE’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power Consumption | Mehul Kumar, Shawn Honess, Amir Nilipour, and Tushar Mattu | | | | | |
| Achieving End-to-End Formal Verification of Large Floating-Point Dot Product Accumulate Systolic Units | Emiliano Morini, Bill Zorn, Disha Puri, Madhurima Eranki, Shravya Jampana | | | | | |
| Achieving End-to-End Formal Verification of Large Floating-Point Dot Product Accumulate Systolic Designs | Emiliano Morini, Bill Zorn, Disha Puri, Madhurima Eranki, Shravya Jampana | | | | | |
| Achieving First-Time Success with a UPF-based Low Power Verification Flow | Kjeld Svendsen, Chuck Seeley, and Erich Marschner | | | | | |
| Activity Trend Guided Efficient Approach to Peak Power Estimation Using Emulation | Gaurav Saharawat, Saurabh Jain, and Madhur Bhatia | | | | | |
| Activity Trend Guided Efficient Approach to Peak Power Estimation Using Emulation | Gaurav Saharawat, Saurabh Jain, and Madhur Bhatia | | | | | |
| Adapting the UVM Register Abstraction Layer for Burst Access | Mark Villalpando | | | | | |
| Adapting the UVM Register Layer for Burst Access | M. P. Villalpando | | | | | |
| Adaptive Test Generation for Fast Functional Coverage Closure | Azade Nazi, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhoseini, Richard Ho | | | | | |
| Adaptive Test Generation for Fast Functional Coverage Closure | Azade Naziz, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhosseiniz, and Richard Ho | | | | | |
| Addressing Challenges in Verification of DSP based Audio IPs using a Novel Hybrid-TestBench Architecture | Suvadeep Bose, Kanak Singh Rajput, Parag S Lonkar, Somasunder K Sreenath | | | | | |
| Addressing HW/SW Interface Quality through Standards | David Murray and Sean Boyan | | | | | |
| Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail Macros | Brandon S. Skaggs | | | | | |
| Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail Macros | Brandon Skaggs | | | | | |
| Addressing the Challenges of Reset Verification in SoC Designs | Chris Kwok, Priya Viswanathan, and Ping Yeung | | | | | |
| Addressing the Challenges of Reset Verification in SoC Designs | Chris Kwok, Priya Viswanathan, and Ping Yeung | | | | | |
| Addressing the verification challenge of SERDES-based FPGAs: The performance/accuracy/efficiency trade-off | Chris Schalick | | | | | |
| Adopting Accellera’s Portable Stimulus Standard: Early Development and Validation using Virtual Prototyping | Simranjit Singh, Ashwani Aggarwal, Harshita Prabha, Vishnu Ramadas, Seonil Brian Choi, Woojoo Space Kim | | | | | |
| Advanced Digital-Centric Mixed-Signal Methodology | Michael Kontz, David Lacey, and Peter Maroni | | | | | |
| Advanced Digital-Centric Mixed-Signal Methodology | Michael Kontz, David Lacey, and Peter Maroni | | | | | |
| Advanced Functional Verification for Automotive System on a Chip | Jaein Hong, Jieun Jeong , Namyoung Kim, Hongkyu Kim, Sungcheol Park, | | | | | |
| Advanced Functional Verification for Automotive System on a Chip | Jaein Hong, Jieun Jeong, Namyoung Kim, Hongkyu Kim, and Sungcheol Park | | | | | |
| Advanced Functional Verification Methodology Using UVM for complex DSP Algorithms in Mixed Signal RF SoCs | Srinivas Aluri and Jaimin Mehta | | | | | |
| Advanced Functional Verification Methodology Using UVM For Complex DSP Algorithms In Mixed Signal RF SoCs | Srinivas Aluri and Jaimin Mehta | | | | | |
| Advanced SOC Randomization Tool for Complex SOC Level Verification | Marvin Mei, Chris Weller, Michael Sedmak, and Zhiqiang Ren | | | | | |
| Advanced Techniques for ARM L2 Cache Verification in an Accelerated Hardware and Software environment | Rob Pelt and Jay O’Donnell | | | | | |
| Advanced Techniques for AXI Fabric Verification in a Software/Hardware OVM Environment | Galen Blake and Steve Chappell | | | | | |
| Advanced Testbench Configuration with Resources | Mark Glasser | | | | | |
| Advanced UCIe-based Chiplets verification from IP to SoC | Anunay Bajaj, Moshik Rubin | | | | | |
| Advanced Usage Models for Continuous Integration in Verification Environments | John Dickol | | | | | |
| Advanced Usage Models for Continuous Integration in Verification Environments | John Dickol | | | | | |
| Advanced UVM Based Chip Verification Methodologies with Full Analog Functionality | Simul Barua, FNU Farshad, Henry Chang | | | | | |
| Advanced UVM Based Chip Verification Methodologies with Full Analog Functionality | Simul Barua, FNU Farshad, Henry Chang | | | | | |
| Advanced UVM Command Line Processor | Siddharth Krishna Kumar | | | | | |
| Advanced UVM Command Line Processor for Central Maintenance and Randomization of Control Knobs | Siddharth Krishna Kumar | | | | | |
| Advanced UVM Register Modeling | Mark Litterick and Marcus Harnisch | | | | | |
| Advanced UVM Register Modeling | Mark Litterick | | | | | |
| Advanced UVM, Multi-Interface, Reactive Stimulus Techniques | Clifford E. Cummings, Stephen DOnofrio, Jeff Wilcox, Heath Chambers | | | | | |
| Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification Cycle | Charul Agrawal, Ashwin Vijayan, and Jakub Dudek | | | | | |
| Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification Cycle | Charul Agrawal, Ashwin Vijayan, and Jakub Dudek | | | | | |
| Advancing system-level verification using UVM in SystemC | Martin Barnasconi, François Pêcheux, and Thilo Vörtler | | | | | |
| Advancing system-level verification using UVM in SystemC | Martin Barnasconi, François Pêcheux, and Thilo Vörtler | | | | | |
| Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC. | Nipun Bhatt | | | | | |
| Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC. | Nipun Bhatt | | | | | |
| AI based Media Functional Safety and Reliability verification in Safety-Critical Autonomous Systems | Suresh Vasu, Palanivel Guruvareddiar | | | | | |
| AI based Media Functional Safety and Reliability Verification in Safety-Critical Autonomous Systems | Suresh Vasu, Palanivel Guruvareddiar | | | | | |
| AI-based Algorithms to Analyze and Optimize Performance Verification Efforts | Saksham Mehra, Raghu Alamuri, Sharada Vajja | | | | | |
| All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification | Aman Kumar, Deepak Narayan Gadde Thomas Nalapat, Evgenii Rezunov, Fabio Cappellini | | | | | |
| All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification | Deepak Narayan Gadde, Aman Kumar, Thomas Nalapat, Evgenii Rezunov, Fabio Cappellini | | | | | |
| An Analytical View of Test Results Using CityScapes | Markus Borg, Andreas Brytting, and Daniel Hansson | | | | | |
| An Analytical View of Test Results Using CityScapes | Markus Borg, Andreas Brytting, and Daniel Hansson | | | | | |
| An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 Experience | Mahesha Shankarathota, Vybhava S, and Indrajit Dutta | | | | | |
| An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 Experience | Mahesha Shankarathota, Vybhava S, and Indrajit Dutta | | | | | |
| An Assertion Based Approach to Implement VHDL Functional Coverage | Michael Wazlowski, Susan Eickhoff, Michael Debole, and Tagbo Ekwueme-Okoli | | | | | |
| An Assertion Based Approach to Implement VHDL Functional Coverage | Susan Eickhoff, Michael DeBole, and Tagbo Ekwueme-Okoli | | | | | |
| An Automated Validation Framework for Power Management and Data Retention Logic Kits of Standard Cell Library | Akshay Kamath, Bharath Kumar, Sunil Aggarwal, Subramanian Parameswaran, Parag Lonkar, Debi Prasanna, Somasunder Sreenath | | | | | |
| An Automatic Visual System Performance Stress Test for TLM Designs | George F. Frazier, Neeti Bhatnagar, and Woody Larue | | | | | |
| An Easy VE/DUV Integration Approach | Uwe Simm | | | | | |
| An efficient analog fault-injection flow harnessing the power of abstraction | Renaud Gillon, Enrico Fraccaroliy, and Franco Fummi | | | | | |
| An Efficient and Modular Approach for Formally Verifying Cache Implementations | M, Achutha KiranKumar V and Abhijith A Bharadwaj | | | | | |
| An Efficient and Modular Approach for Formally Verifying Cache implementations | M Achutha KiranKumar V, Abhijith A Bharadwaj, and Bindumadhava S S | | | | | |
| An Efficient Method to Verify Dynamic IP Clock Frequency on SOC Level by Using Auto-generated Active Clock Monitor | Jaecheon Kim, Gyuhong Lee, Yeonho Jeong, Hyunsun Ahn, Daewoo Kim, Seonil Brian Choi | 2021 | Paper | | y2021 | paper |
| An Enhanced DV Approach for Effectively Verifying High Speed, Low Power MIPI-MPHY 5.0 Designs | Eldhose PM, Kuntal Pandya, Sagar Jayakrishanan, Suraj Vijay Shetty, Parag S Lonkar | | | | | |
| An Enhanced DV Approach for Effectively Verifying High Speed, Low Power MIPI-MPHY5.0 Designs | Eldhose P.M, Sagar Jayakrishnan, Suraj Vijay Shetty, Kuntal Pandya, Parag S. Lonkar | | | | | |
| An Enhanced Stimulus and Checking Mechanism on Cache Verification | Chenghuan Li, Xiaohui Zhao, and Yunyang Song | 2019 | Poster | | y2019 | poster |
| An Equivalent Modeling Approach for High-Density DRAM Array System-Level Design-Space Exploration in SystemVerilog | Seyoung Kim, Jaeha Kim | | | | | |
| An Experience of Complex Design Validation: How to Make Semiformal Verification Work | Sabih Agbaria, Dan Carmi, Orly Cohen, Dmitry Korchemny, Michael Lifshits, and Alexander Nadel | | | | | |
| An experience to finish code refinement earlier at behavioral level | Dae-Han Youn, Sik Kim, Byeong Min, and Kyu-Myung Choi | | | | | |
| An Expert System Based Tool for Pre-design Chip Power Estimation | Bhanu Singh, Arunprasath Shankar, Francis Wolff, and Christos Papachristou | | | | | |
| An Expert System Based Tool for Pre-design Chip Power Estimation | Bhanu Singh, Arunprasath Shankar, Francis Wolff, and Christos Papachristou | | | | | |
| An Innovative Methodology for RTL and Verification IP Sharing Between Two Projects | Albert Xu and Joonyoung Kim | | | | | |
| An Innovative Methodology for RTL and Verification IP Sharing Between Two Projects | Albert Xu and Joonyoung Kim | | | | | |
| An Innovative Methodology for Verifying Mixed-Signal Components | Fabian Delguste and Graeme Nunn | | | | | |
| An Integrated Framework for Power Aware Verification | Harsh Chilwal, Manish Jain, and Bhaskar Pal | | | | | |
| An Overview of Security Annotation for Electronic Design Integration (SA-EDI) Standard | Sohrab Aftabjahani | | | | | |
| Analog Transaction Level Modeling for Verification of Mixed-Signal-Blocks | Alexander W. Rath, Volkan Esen, and Wolfgang Ecker | | | | | |
| Analog Transaction Level Modeling for Verification of Mixed-Signal-Blocks | Alexander W. Rath | | | | | |
| Analysis of TLM-2.0 and it’s Applicability to Non Memory Mapped Interfaces | Guillaume Delbergue, Mark Burton, and Bertrand Le Gal and Christophe Jego | | | | | |
| Analysis of TLM-2.0 and it’s Applicability to Non Memory Mapped Interfaces | Delbergue Guillaume | | | | | |
| Apples versus Apples HVL Comparison Finally Arrives Comparing OVM SystemVerilog to OVM e | Brett Lammers and Riccardo Oddone | | | | | |
| Application Abstraction Layer: The Carpool Lane on the SoC Verification Freeway | Abhisek Verma, Varun S, and Subramanian Kuppusamy | | | | | |
| Application Abstraction Layer: The Carpool Lane on the SoC Verification Freeway | Abhisek Verma, Varun S, and Subramanian Kuppusamy | | | | | |
| Application of SystemC/SystemC-AMS in 3G Virtual Prototyping | Tao Huang and Stefan Heinen | | | | | |
| Application Optimized HW/SW Design & Verification of a Machine Learning SoC | Lauro Rizzatti, Russell Klein, Stephen Bailey, and Andrew Meier | | | | | |
| Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical Properties | K. Selyunin, T. Nguyen, A.D. Basa, E. Bartocci, D. Nickovic, and R. Grosu | | | | | |
| Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical Properties | Konstantin Selyunin, Thang Nguyen, Andrei-Daniel Basa, Ezio Bartocci, Dejan Nickovic, and Radu Grosu | | | | | |
| Applying Test-Driven Development Methods to Design Verification Software | Doug Gibson and Mike Kontz | | | | | |
| Applying Test-Driven Development Methods to Design Verification Software in UVM-e | Doug Gibson and Mike Kontz | | | | | |
| Applying Transaction-level Debug and Analysis Techniques to DUT Simulated Activity Using Data- Mining Techniques | Leo Chai, Bindesh Patel, and Jun Zhao | | | | | |
| Applying Transaction-level Debug and Analysis Techniques to DUT Simulated Activity Using Data-Mining Techniques | Leo Chai, Jun Zhao, and Bindesh Patel | | | | | |
| Architecting “Checker IP” for AMBA protocols | Srinivasan Venkataramanan and Ajeetha Kumari | | | | | |
| Architecting “Checker IP” for AMBA protocols | Ajeetha Kumari and Srinivasan Venkataramanan | | | | | |
| Architectural Evaluation Of a Programmable Accelerator For Baseband, Phy and Video Applications Using High Level Synthesis | Andy Fox, Tigran Sargsyan, and Steven Anderson | | | | | |
| Architectural Evaluation of a Programmable Accelerator for Baseband, Phy and Video Applications using High Level Synthesis | Andy Fox, Tigran Sargsyan, and Steven Anderson | | | | | |
| Architectural Formal Verification of System-Level Deadlocks | Mandar Munishwar1, Naveed Zaman, Anshul Jain, HarGovind Singh, and Vigyan Singhal | | | | | |
| Architectural Formal Verification of System-Level Deadlocks | Mandar Munishwar and Vigyan Singhal | | | | | |
| Are My Fault Campaigns Providing Accurate Results for ISO 26262 Certification? | Hyunsun Ahn, James Kim, Arun Gogineni, Ann Keffer, MyungKyoon Yim, Soobon Kim, Youngsik Kim, Seonil Brian Choi | | | | | |
| Are OVM & UVM Macros Evil? A Cost-Benefit Analysis | Adam Erickson | | | | | |
| Are you really confident that you are getting the very best from your verification resources? | Darron May and Fritz Ferstl | | | | | |
| Are you really confident that you are getting the very best from your verification resources? | Darron May and Fritz Ferstl | | | | | |
| Are You Safe Yet? Safety Mechanism Insertion and Validation | Ping Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen | | | | | |
| Are You Safe Yet? Safety Mechanism Insertion and Validation | Ping Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen | | | | | |
| Are You Smarter Than Your Testbench? With a little work you can be. | Rich Edelman and Raghu Ardeishar | | | | | |
| Are You Smarter Than Your Testbench? With a little work you could be | Rich Edelman and Raghu Ardeishar | | | | | |
| Arithmetic Overflow Verification using Formal LINT | Kaiwen Chin, Esra Sahin Basaran, Kranthi Pamarthi | | | | | |
| Arithmetic Overflow Verification using Formal LINT | Kaiwen Chin, Esra Sahin Basaran, Kranthi Pamarthi | | | | | |
| ASIC-Strength Verification in a Fast-Moving FPGA World | Bryan Murdock | | | | | |
| ASIC-Strength Verification in a Fast-Moving FPGA World | Bryan Murdock | | | | | |
| Assertion Based Self-checking of Analog Circuits for Circuit Verification and Model Validation in SPICE and Co-simulation Environments | Lakshmanan Balasubramanian, Pooja Sundar, and Timothy W Fischer | | | | | |
| Assertion-based Verification for Analog and Mixed Signal Designs | Srinivas Aluri | | | | | |
| Assertion-based Verification for Analog andMixed Signal Designs | Srinivas Aluri | | | | | |
| Asynchronous Behaviors Meet Their Match with SystemVerilog Assertions | Doug Smith | | | | | |
| Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor Core | Wei Foong Thoo and David A. Burgoon | | | | | |
| Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor Core | Wei Foong Thoo and David A. Burgoon | | | | | |
| Automated approach to Register Design and Verification of complex SOC | Ballori Banerjee, Subashini Rajan, and Silpa Naidu | | | | | |
| Automated Comparison of Analog Behavior in a UVM Environment | Sebastian Simon | | | | | |
| Automated Comparison of Analog Behavior in a UVM Environment | Sebastian Simon, Alexander W. Rath, Volkan Esen, and Wolfgang Ecker | | | | | |
| Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal Verification | Samantha Pandez, Christopher Geen | | | | | |
| Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal Verification | Samantha Pandez Christopher Geen | | | | | |
| Automated Formal Verification of a Highly-Configurable Register Generator | Shuhang Zhang, Bryan Olmos, Basavaraj Naik | | | | | |
| Automated Formal Verification of a Highly-Configurable Register Generator | Shuhang Zhang, Bryan Olmos, Basavaraj Naik Infineon Technologies AG | | | | | |
| Automated Generation of Interval Properties From Trace-Based Function Models | Robert Kunzelmann, Aishwarya Sridhar, Daniel Gerl, Lakshmi Vidhath Boga, Wolfgang Ecker | | | | | |
| Automated Generation of Interval Properties From Trace-Based Function Models | Robert Kunzelmann, Aishwarya Sridhar, Daniel Gerl, Lakshmi Vidhath Boga, Wolfgang Ecker | | | | | |
| Automated Generation of RAL-based UVM Sequences | Vijayakrishnan Rousseau, Satyajit Sinari, Benjamin Applequist, Timothy McLean, and Geddy Lallathin | | | | | |
| Automated Generation of RAL-based UVM Sequences | Satyajit Sinari, Timothy McLean, Benjamin Applequist, Vijayakrishnan Rousseau, and Geddy Lallathin | | | | | |
| Automated Modeling Testbench Methodology Tested with four Types of PLL Models | Automated Modeling Testbench Methodology Tested with four Types of PLL Models | | | | | |
| Automated Modeling Testbench Methodology Tested with four Types of PLL Models | Jun Yan, Josh Baylor | | | | | |
| Automated Performance Verification to Maximize your ARMv8 pulling power | Nick Heaton and Simon Rance | | | | | |
| Automated Performance Verification to Maximize your ARMv8 pulling power | Nick Heaton and Simon Rance | | | | | |
| Automated Physical Hierarchy Generation: Tools and Methodology | Ali El-Zein, Alvan Ng, Benedikt Geukes, Maya H. Safieddine, and Wolfgang Roesner | | | | | |
| Automated Physical Hierarchy Generation: Tools and Methodology | Ali El-Zein, Alvan Ng, Benedikt Geukes, Maya H. Safieddine, and Wolfgang Roesner | | | | | |
| Automated RTL Update for Abutted Design | Wonkyung Lee, Ayoung Kwon, Soyeong Kwon, Youngsik Kim, and Seonil Brian Choi | | | | | |
| Automated RTL Update for Abutted Design | Wonkyung Lee, Ayoung Kwon, Soyeong Kwon, Youngsik Kim, and Seonil Brian Choi | | | | | |
| Automated Safety Verification for Automotive Microcontrollers | H. Busch | | | | | |
| Automated Safety Verification for Automotive Microcontrollers | Holger Busch | | | | | |
| Automated Seed Selection Algorithm for an Arbitrary Test Suite | David Crutchfield, Brian Craw, Jim Sharpe, and Brandon Skaggs | | | | | |
| Automated Seed Selection Algorithm for an Arbitrary Test Suite | David Crutchfield, Brian Craw, Jim Sharpe, and Brandon Skaggs | | | | | |
| Automated Specification Driven Verification by Generation of SystemVerilog Assertions | Ferdinando Pace | | | | | |
| Automated Specification Driven Verification by Generation of SystemVerilog Assertions | Ferdinando Pace | | | | | |
| Automated Test Generation to Verify IP Modified for System Level Power Management | Christophe Lamard | | | | | |
| Automated Test Generation to Verify IP Modified for System Level Power Management | Christophe Lamard and Frederic Dupuis | | | | | |
| Automated Thread Evaluation of Various RISC-V Alternatives using Random Instruction Generation | Endri Kaja, Nicolas Gerlin, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker | | | | | |
| Automated Thread Evaluation of Various RISC-V Alternatives using Random Instruction Generators | Endri Kaja, Nicolas Gerlin, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker | | | | | |
| Automated traceability of requirements in the design and verification process of safety-critical mixed-signal systems | Gabriel Pachiana, Maximilian Grunwald, Thomas Markwirth, Christoph Sohrmann | | | | | |
| Automatic Debug Down to the Line | Daniel Hansson and Patrik Granath | | | | | |
| Automatic Debug Down to the Line of Code | Daniel Hansson and Patrik Granath | | | | | |
| Automatic Exploration of Hardware/Software Partitioning | Syed Abbas Ali Shah, Sven Alexander Horsinka, Basitan Farkas, Rolf Meyer, and Malden Berekovic | | | | | |
| Automatic Exploration of Hardware/Software Partitioning | Syed Abbas Ali Shah, Sven Alexander Horsinka, Basitan Farkas, Rolf Meyer, and Malden Berekovic | | | | | |
| Automatic Generation of Formal Properties for Logic Related to Clock Gating | Shuqing Zhao and Shan Yan | | | | | |
| Automatic Generation of Formal Properties for Logic Related to Clock Gating | Shuqing Zhao and Shan Yan | | | | | |
| Automatic generation of Programmer Reference Manual and Device Driver from PSS | Freddy Nunez | | | | | |
| Automatic generation of Programmer Reference Manual and Device Driver from PSS | Freddy Nunez | | | | | |
| Automatic Investigation of Power Inefficiencies | Kuo Kai Hsieh, Li C. Wang, Wen Chen, Monica Farkash, and Jayanta Bhadra | | | | | |
| Automatic Investigation of Power Inefficiency | Kuo-Kai Hsieh, Wen Chen, Monica Farkash, Jayanta Bhadra, and Li-C. Wang | | | | | |
| Automatic Partitioning for Multi-core HDL Simulation | Gaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra | | | | | |
| Automatic Partitioning for Multi-core HDL Simulation | Gaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra | | | | | |
| Automatic SOC Test Bench Creation | David Crutchfield, Mark Glasser, and Stephen Roe | | | | | |
| Automatic SOC Test Bench Creation | David Crutchfield, Mark Glasser, and Stephen Roe | | | | | |
| Automatic Translation of Natural Language to SystemVerilog Assertions | Abhishek Chauhan | | | | | |
| Automatic Translation of Natural Language to SystemVerilog Assertions | Abhishek Chauhan | | | | | |
| Automatic verification for Assertion Based Verification: How can a SPIRIT IP-XACT extension help? | Sofiene Mejri and Mirella Negro Marcigaglia | | | | | |
| Automating sequence creation from a Microarchitecture specification | Subramoni Parameswaran and Ravi Ram | | | | | |
| Automating sequence creation from a microarchitecture specification | Subramoni Parameswaran and Ravi Ram | | | | | |
| Automating the Integration Workflow with IP-Centric Design | Simon Butler | | | | | |
| Automating the Formal Verification of Firmware: A Novel Foundation and Scalable Methodology | Bryan Olmos, Sanjana Sainath, Wolfgang Kunz, Djones Lettnin | | | | | |
| Automating the Formal Verification of Firmware: A Novel Foundation and Scalable Methodology | Bryan Olmos, Sanjana Sainath, Wolfgang Kunz, Djones Lettnin | | | | | |
| Automating the formal verification sign-off flow of configurable digital IP’s | Giovanni Auditore and Giuseppe Falconeri | | | | | |
| Automating the formal verification sign-off flow of configurable digital IP’s | Giovanni Auditore and Giuseppe Falconeri | | | | | |
| Automation for Early Detection of X-propagation in Power-Aware Simulation Verification using UPF IEEE 1801 | Tony Gladvin George, Ramesh Kumar, Kyuho Shim, Karan K, Wooseong Cheong, ByungChul Yoo | | | | | |
| Automation for Early Detection of Xpropagation in Power-Aware Simulation Verification using UPF IEEE 1801 | Tony Gladvin George, Ramesh Kumar, Kyuho Shim, Karan K, Wooseong Cheong, ByungChul Yoo | | | | | |
| Automation Methodology for Bus Performance Verification using IP-XACT | Taeyoung Jeon, Gunseo Koo, Youngsik Kim, Seonil Brian Cho | | | | | |
| Automation Methodology for Bus Performance Verification using IP-XACT | Taeyoung Jeon, Gunseo Koo, Youngsik Kim, Seonil Brian Choi | | | | | |
| Automation of Power On Reset Assertion | Shang-Wei Tu, Penny Yang, Joydeep Gangopadhyay, and Amol Herlekar | | | | | |
| Automation of Reusable Protocol-Agnostic Performance Analysis in UVM Environments | Daniel Carrington, Alan Pippin, and Timothy Pertuit | | | | | |
| Automation of Reusable Protocol-Agnostic Performance Analysis in UVM Environments | D. P. Carrington, A. J. Pippin, and T. Pertuit | | | | | |
| Avoiding Configuration Madness The Easy Way | Rich Edelman | | | | | |
| Avoiding Configuration Madness The Easy Way | Rich Edelman | | | | | |
| Avoiding Confounding Configurations an RDC Methodology for Configurable Designs | Eamonn Quigley, Jonathan Niven, and Kurt Takara | | | | | |
| Avoiding Confounding Configurations An RDC Methodology for Configurable Designs | Eamonn Quigley, Jonathan Niven, and Kurt Takara | | | | | |
| BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering Problem | Debarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, Siddhanth Dhodhi, Spandan Kachhadiya | | | | | |
| BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering Problem | Debarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, and Siddhanth Dhodhi | | | | | |
| Be a Sequence Pro to Avoid Bad Con Sequences | Jeff Vance, Jeff Montesano, Mark Litterick, and Jason Sprott | | | | | |
| Best Practices in Verification Planning | Benjamin Ehlers, Carmen Vargas, and Paul Carzola | | | | | |
| Best Practices in Verification Planning | Benjamin Ehlers and Paul Carzola | | | | | |
| Better Living Through Better Class-Based SystemVerilog Debug | Rich Edelman, Raghu Ardeishar, and John Amouroux | | | | | |
| Better Living Through Better Class-Based SystemVerilog Debug | Rich Edelman, Raghu Ardeishar, and John Amouroux | | | | | |
| Beyond UVM: Creating Truly Reusable Protocol Layering | Janick Bergeron | | | | | |
| Beyond UVM: Creating Truly Reusable Protocol Layering | Janick Bergeron, Fabian Delguste, Steve Knoeck, Steve McMaster, Aron Pratt, and Amit Sharma | | | | | |
| Bi-Directional UVM Agents and Complex Stimulus Generation for UDN and UPF Pins | Chuck McClish | | | | | |
| Big Data in Verification: Making Your Engineers Smarter | David Lacey, Mike McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson | | | | | |
| Big Data in Verification: Making Your Engineers Smarter | David Lacey, Michael McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson | | | | | |
| Blending multiple metrics from multiple verification engines for improved productivity | Darron May and Darren Galpin | | | | | |
| Boost Verification Results by Bridging the Hardware/Software Testbench Gap | Matthew Ballance | | | | | |
| Boost Verification Results by Bridging the Hw/Sw Testbench Gap | Matthew Ballance | | | | | |
| BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMS | Ahmed Yehia | | | | | |
| BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMS | Ahmed Yehia | | | | | |
| Bridge the Portable Test and Stimulus to UVM Simulation Environment | Theta Yang and Evean Qin | | | | | |
| Bridge the Portable Test and Stimulus to UVM Simulation Environment | Theta Yang and Evean Qin | | | | | |
| Bridging the gap between TLM-2.0 AT models and RTL – Experiments and Opportunities | Zhu Zhou, Atul Kwatra, Rajesh Gadiyar, and Paul Heraty | | | | | |
| Bringing Constrained Random into SoC SW-driven Verification | Alberto Allara and Fabio Brognara | | | | | |
| Bringing Constrained Random into SoC SW-driven Verification | Alberto Allara and Fabio Brognara | | | | | |
| BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPS | Prabal K Bhattacharya, Swapnajit Chakraborti, Scott Little, Donald O’Riordan, and Vaibhav Bhutani | | | | | |
| BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPS | Prabal K Bhattacharya, Swapnajit Chakraborti, Donald O’Riordan, Vaibhav Bhutani, and Scott Little | | | | | |
| Bringing Regression Systems into the 21st Century | David Crutchfield | | | | | |
| Bringing Regression Systems into the 21st Century | David Crutchfield and Thom Ellis | | | | | |
| Bringing Reset Domains and Power Domains together – Confronting issues due to UPF Instrumentation | Inayat Ali, Abdul Moyeen, Manish Bhati, Manjunatha Srinivas | | | | | |
| Bringing UVM to VHDL | UVVM | | | | | |
| Building a Comprehensive Hardware Security Methodology | Anders Nordstrom and Jagadish Nayak | | | | | |
| Building Portable Stimulus Into Your IP-XACT Flow | Petri Karppa, Lauri Matilainen, and Matthew Balance | | | | | |
| Building Portable Stimulus Into your IP-XACT Flow | Petri Karppa, Lauri Matilainen, and Matthew Ballance | | | | | |
| Bus Trace System: Automating Bus Traffic Debugging in IP-XACT Based SoC | Wonyeong So, Yonghyun Yang, Sun-il Roe, Moonki Jang, Youngsik Kim, Seonil Brian Choi | | | | | |
| Bus Trace System: Automating Bus Traffic Debugging in IP-XACT Based SoC Beyond Traditional Debugging Methods | Wonyeong So, Yonghyun Yang, Sun-il Roe, Moonki Jang, Youngsik Kim, Seonil Brian Choi | | | | | |
| C through UVM: Effectively using C based models with UVM based Verification IP | Chris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile | | | | | |
| C through UVM: Effectively using C based models with UVM based Verification IP | Adiel Khan, Chris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile | | | | | |
| Caching Tool Run Results in Large Scale RTL Development Projects | Ashfaq Khan | | | | | |
| Caching Tool Run Results in Large-Scale RTL Development Projects | Ashfaq Khan | | | | | |
| Calling All Checkers: Collaboratively Utilizing SVA In UVM Based Simulation | Hui K. Zhang | | | | | |
| Calling All Checkers: Collaboratively Utilizing SVA in UVM Based Simulation | Hui C. K. Zhang | | | | | |
| CAMEL – A Flexible Cache Model for Cache Verification | Yue Liu, Fang Liu, Yunyang Song | | | | | |
| CAMEL: A Flexible Cache Model for Cache Verification | Yue Liu, Fang Liu, and Yunyang Song | | | | | |
| Can Formal Outsmart Synthesis: Improving Synthesis Quality of Results through Formal Methods | Eldon Nelson | | | | | |
| Can My Synthesis Compiler Do That? | Stuart Sutherland and Don Mills | | | | | |
| Can My Synthesis Compiler Do That? | Stuart Sutherland and Don Mills | | | | | |
| Can You Even Debug a 200M+ Gate Design? | Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss | | | | | |
| Can You Even Debug a 200M+ Gate Design? | Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss | | | | | |
| Case Study: Low-Power Verification Success Depends on Positive Pessimism | John Decker | | | | | |
| Case Study: Power-aware IP and Mixed-Signal Veri | Luke Lang | | | | | |
| Case Study: Successes and Challenges of Validation Content Reuse | Mike Chin, Jonathan Edwards, Josh Pfrimmer, and Hooi Jing Tan | | | | | |
| Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation) | Vikas Billa and Sundar Haran | | | | | |
| Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation) | Vikas Billa and Sundar Haran | | | | | |
| Challenges in UVM + Python Random Verification Environment for Digital Signal Processing Datapath Design | Shabbar Vejlani and Ashok Chandran | | | | | |
| Challenges in UVM + Python random verification environment for Digital Signal Processing datapath design. | Shabbar Vejlani and Ashok Chandran | | | | | |
| Check Low-Power Violations by Using Machine Learning Based Classifier | Chi-Ming Lee, Chung-An Wang, Cheok-Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai | | | | | |
| Check Low-Power Violations by Using Machine Learning Based Classifier | Chi-Ming Lee, Chung-An Wang, Cheok-Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai | | | | | |
| Checking security path with formal verification tool: new application development | Julia Dushina, Saumil Shah, Joerg Mueller, and Vincent Reynolds | | | | | |
| Checking Security Path with Formal Verification Tool: New Application Development | Julia Dushina and Joerg Mueller | | | | | |
| Chef’s Special – an Efficient Verification Recipe for Maximizing Productivity While Using a Third Party Verification IP | Varun S and Bhavik Vyas | | | | | |
| Cleaning Out Your Pipes – Pipeline Debug in UVM Testbenches | Rich Edelman and Neil Bulman | | | | | |
| Cleaning Out Your Pipes – Pipeline Debug in UVM Testbenches | Rich Edelman and Neil Bulman | | | | | |
| CLOCK DOMAIN CROSSING CHALLENGES IN LATCH BASED DESIGNS | Madan Das, PhD, Chris Kwok, and Kurt Takara | | | | | |
| Clock Domain Crossing Challenges in Latch Based Designs | Madan Das, Chris Kwok, and Kurt Takara | | | | | |
| Clock Domain Crossing Verification in Transistor-level Design | Hyungjung Seo, KwangSun Kim, YoungRok Choi, Jihwan Kim, and Jong-Bae Lee | | | | | |
| Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis | B. Bowyer | | | | | |
| Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis | Bryan Bowyer | | | | | |
| Closing Functional Coverage With Deep Reinforcement Learning: A Compression Encoder Example | Eric Ohana | | | | | |
| Closing Functional Coverage With Deep Reinforcement Learning A Compression Encoder Example | Eric Ohana | | | | | |
| Co-Developing Firmware and IP with PSS | M. Ballance | | | | | |
| Co-Developing IP and SoC Bring-Up Firmware with PSS | Matthew Ballance, Siemens EDA | | | | | |
| Co-Simulating Matlab/Simulink Models in a UVM Environment | Neal Okumura, Paul Yue, and Glenn Richards | | | | | |
| Co-Simulating Matlab/Simulink Models in a UVM Environment | Neal Okumura and Glenn Richards | | | | | |
| Coding Guidelines and Code Generation | John Aynsley and Dr. Christoph Sühnel | | | | | |
| Coherency Verification & Deadlock Detection Using Perspec/Portable Stimulus | Moonki Jang, Jiwoong Kim, Hyerim Chung, Phu L. Huynh, and Shai Fuss | | | | | |
| Coherency Verification & Deadlock Detection Using Perspec/Portable Stimulus | Moonki Jang and Phu Huynh | | | | | |
| Combining Simulation with Formal Techniques to Reduce the Overall Verification Cycle | Aneet Agarwal and Gaurav Gupta | | | | | |
| Command Line Debug Using UVM Sequences | Mark Peryer | | | | | |
| Common Challenges and Solutions to Integrating a UVM Testbench | Frank Verhoorn and Mike Baird | | | | | |
| Common Challenges and Solutions to Integrating a UVM Testbench in Place of a Legacy Monolithic Testing Environment | Frank Verhoorn and Michael Baird | | | | | |
| Comparison of TLM2-Quantum Keeping and TLM+-Resource Modeling with regard to Timing in Virtual Prototypes | Wolfgang Ecker, Volkan Esen, Rainer Findenigy, Thomas Leitnerz and Michael Velten | | | | | |
| Complementing EDA with Meta-Modeling and Code Generation | Wolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal | | | | | |
| Complementing EDA with Meta-Modelling & Code Generation | Wolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal | | | | | |
| Complementing EDA with Meta-Modelling and Code Generation | Ecker Wolfgang, Michael Velten, Ajay Goyal, and Leily Zafari | | | | | |
| Complex Safety Mechanisms Require Interoperability and Automation For Validation And Metric Closure | Daeseo Cha, Vedant Garg, Ann Keffer, Arun Gogineni, James Kim, Woojoo Space Kim, Kunhyuk Kang, Seonil Brian Choi | | | | | |
| Complex Safety Mechanisms Require Interoperability and Automation For Validation And Metric Closure | Daeseo Cha, Vedant Garg | | | | | |
| Complexities & Challenges of UPF Corruption Model in Low Power Emulation | Progyna Khondkar, Brad Budlong | | | | | |
| CompMon: Ensuring Rigorous Protocol Specification and IP Compliance | Robert Adler, Sava Krstic and Erik Seligman | | | | | |
| Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain Crossings | Yossi Mirsky | | | | | |
| Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain Crossings | Yossi Mirsky B.Sc, M.Sc, MBA | | | | | |
| Comprehensive IP to SoC CDC Verification Using Hybrid Data Model | Anwesha Choudhury and Ashish Hari | | | | | |
| Comprehensive IP to SoC Clock Domain Crossing Verification Using Hybrid Data Mode | Anwesha Choudhury and Ashish Hari | | | | | |
| Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-Chips | Ellie Burns, Gabriel Chidolue, and Guillaume Boillet | | | | | |
| Comprehensive Register Description Languages: The case for standardization of RDLs across design domains | David C Black and Doug Smith | | | | | |
| Comprehensive Systemverilog-Systemc-Vhdl Mixed-Language Design Methodology | Rudra Mukherjee, Gaurav Kumar Verma, and Sachin Kakkar | | | | | |
| Conditional Delays for Negative Limit Timing Checks in Event Driven Simulation | Nadeem Kalil and David Roberts | | | | | |
| Conditional Delays for Negative Limit Timing Checks in Event Driven Simulation | N. Kalil and D. Roberts | | | | | |
| Confidently Sign-off Any low-Power Designs without Consequences | Madhur Bhargava, Jitesh Bansal, and Progyna Khondkar | | | | | |
| Confidently Sign-Off Any Low-Power Designs Without Consequences | Madhur Bharga, Jitesh Bansal and Progyna Khondkar | | | | | |
| Configuration Conundrum: Managing Test Configuration with a Bite Sized Solution | Kevin Vasconcellos, Jeff McNeal | | | | | |
| Configuring Your Resources the UVM Way! | Parag Goel, Amit Sharma, and Rajiv Hasija | | | | | |
| Configuring Your Resources the UVM Way! | Parag Goel, Amit Sharma, and Rajiv Hasija | | | | | |
| CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITY | Bin Ju | | | | | |
| CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITY | Bin Ju | | | | | |
| Connecting UVM with Mixed-Signal Design | Ivica Ignjić | | | | | |
| CONNECTING UVM WITH MIXED-SIGNAL DESIGN | Ivica Ignjić | | | | | |
| Connectivity and Beyond | Shahid Ikram, Joseph DErrico, Yasmin Farhan, Jim Ellis, and Tushar Parikh | | | | | |
| Connectivity and Beyond | Shahid Ikram, Joseph DErrico, Yasmin Farhan, Jim Ellis, and Tushar Parikh | | | | | |
| Conquer the Graphics Legacy: Develop the Customized UVM VIP Embedded a Cycle-based C++ Reference Model | Roman Wang | | | | | |
| Conscious of Streams Managing Parallel Stimulus | Jeff Wilcox | | | | | |
| Conscious of Streams: Managing Parallel Stimulus | Jeffrey Wilcox and Stephen D’Onofrio | | | | | |
| Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL Synthesis | Rainer Findenig, Thomas Leitner, and Wolfgang Ecker | | | | | |
| CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTION | Martin Fröjd, Adiel Khan, and Jussi Mäkelä | | | | | |
| CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTION | Jussi Mäkelä, Martin Fröjd, and Adiel Khan | | | | | |
| CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTION | Jussi Mäkelä, Martin Fröjd, and Adiel Khan | | | | | |
| Context-Aware DFM Rule Analysis and Scoring Using Machine Learning | Vikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, and Jonathan Ong | | | | | |
| Context-Aware DFM Rule Analysis and Scoring Using Machine Learning | Vikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, and Jonathan Ong | | | | | |
| Conversion of Performance Model to Functional Model | H G Pavan Kumar, Sumail Singh Brar, Ashwani Aggarwal, Seonil Brian Choi, Woojoo Space Kim | | | | | |
| Coverage Data Exchange is no robbery…or is it? | Darron May and Samiran Laha | | | | | |
| Coverage Data Exchange is no robbery…or is it? | Darron May and Samiran Laha | | | | | |
| Coverage Driven Distribution of Constrained Random Stimuli | Raz Azaria, Amit Metodi, and Marat Teplitsky | | | | | |
| Coverage Driven Distribution of Constrained Random Stimuli | Marat Teplitsky, Amit Metodi, and Raz Azaria | | | | | |
| Coverage Driven Signoff with Formal Verification on Power Management IPs | Baosheng Wang and Xiaolin Chen | | | | | |
| Coverage Driven Signoff with Formal Verification on Power Management IPs | Baosheng Wang and Xiaolin Chen | | | | | |
| Coverage Driven Verification of an Unmodified DUT within an OVM Testbench | Michael Baird | | | | | |
| Coverage Models for Formal Verification | Xiushan Feng, Xiaolin Chen, and Abhishek Muchandikar | | | | | |
| Coverage Models for Formal Verification | Xiushan Feng, Xiaolin Chen, and Abhishek Muchandikar | | | | | |
| COVERGATE: Coverage Exposed | Rich Edelman | | | | | |
| COVERGATE: Coverage Exposed | Rich Edelman | | | | | |
| Crafting a Million Instructions/Sec RISCV-DV HPC Techniques to Boost UVM Testbench Performance by Over 100x | Puneet Goel, Ritu Goel, Jyoti Dahiya | | | | | |
| Crafting a Million Instructions/Sec RISCV-DV HPC Techniques to Boost UVM Testbench Performance by Over 100x | Puneet Goel, Ritu Goel, Jyoti Dahiya | | | | | |
| Creating 5G Test Scenarios, the Constrained-Random way | Keshav Kannan and Eric P. Kim | | | | | |
| Creating 5G Test Scenarios, the Constrained-Random way | Keshav Kannan, Eric P. Kim | | | | | |
| Creating a Complete Low Power Verification Strategy using the Common Power Format and UVM | Robert Meyer and Joel Artmann | | | | | |
| Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation Requirements | David Lacey and Ed Powell | | | | | |
| Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation Requirements | David Lacey and Ed Powell | | | | | |
| Cross Coverage of Power States | Veeresh Vikram Singh and Awashesh Kumar | | | | | |
| CXL Verification using Portable Stimulus | Ragesh Thottathil, Karthick Gururaj | | | | | |
| Data-Driven Verification: Driving the next wave of productivity improvements | Larry Melling, Chris Komar, Sharon Rosenberg, Michael Young, and Hanan Moller | | | | | |
| DatagenDV: Python Constrained Random Test Stimulus Framework | Jon George, James Mackenzie | | | | | |
| DatagenDV: Python Constrained Random Test Stimulus Framework | Jonathan George, James Mackenzie | | | | | |
| De-mystifying synchronization between various verification components by employing novel UVM classes | Pushpal Nautiyal and Gaurav Chugh | | | | | |
| De-mystifying synchronization between various verification components by employing novel UVM classes | Pushpal Nautiyal and Gaurav Chugh | | | | | |
| Deadlock Free Design Assurance Using Architectural Formal Verification | Bhushan Parikh, Shaman Narayana | | | | | |
| Deadlock Free Design Assurance Using Architectural Formal Verification | Bhushan Parikh, Shaman Narayana | | | | | |
| Deadlock Verification For Dummies – The Easy Way of Using SVA and Formal | Mark Eslinger, Jeremy Levitt, and Joe Hupcey III | | | | | |
| Deadlock Verification For Dummies – The Easy Way Using SVA and Formal | Mark Eslinger, Jeremy Levitt, and Joe Hupcey III | | | | | |
| Dealing with Programmable IP: Where the Rubber Meets the PSS Deployment Road | Karthick Gururaj | | | | | |
| Debarshi Chatterjee, Spandan Kachhadia, Chen Luo, Kumar Kushal, Siddhanth Dhodhi | Moonki Jang | | | | | |
| Debug APIs – next wave of innovation in DV space | Srinivasan Venkataramanan and Ajeetha Kumari | | | | | |
| Debug APIs – next wave of innovation in DV space | Srinivasan Venkataramanan and Ajeetha Kumari | | | | | |
| Debug Challenges in Low-Power Design and Verification | Durgesh Prasad, Madhur Bhargava, Jitesh Bansal, and Chuck Seeley | | | | | |
| Debug Challenges in Low-Power Design and Verification | Durgesh Prasad, Madhur Bhargava, Jitesh Bansal, and Chuck Seeley | | | | | |
| Debugging Communicating Systems: The Blame Game – Blurring the Line Between Performance Analysis and Debug | Rich Edelman and Raghu Ardeishar | | | | | |
| Debugging Functional Coverage Models Get The Most Out of Your Cover Crosses | Mennatallah Amer and Amr Hany | | | | | |
| Debugging Functional Coverage Models Get The Most Out of Your Cover Crosses | Mennatallah Amer and Amr Hany | | | | | |
| Deep Learning for Design and Verification Engineers | John Aynsley | | | | | |
| Deep Learning for Engineers | John Aynsley | | | | | |
| Deep Predictive Coverage Collection | Rajarshi Roy, Chinmay Duvedi, Saad Godil, and Mark Williams | | | | | |
| Deep Predictive Coverage Collection | Rajarshi Roy, Chinmay Duvedi, Saad Godil, and Mark Williams | | | | | |
| Defining TLM+ | Wolfgang Ecker, Volkan Esen, Robert Schwencker, and Michael Velten | | | | | |
| DeltaCov: Automated Stimulus Quality Monitoring System | Nimish Girdhar, Srinivas Badam | | | | | |
| Democratizing Digital-centric Mixed-signal Verification methodologies | Sumit Vishwakarma | | | | | |
| Demystifying Formal Testbenches: Tips, Tricks, and Recommendations | Shahid Ikram, Mark Eslinger | | | | | |
| Demystifying Formal Testbenches: Tips, Tricks, and Recommendations | Dr. Shahid Ikram, Mark Eslinger | | | | | |
| Demystifying the UVM Configuration Database | Vanessa R. Cooper and Paul Marriott | | | | | |
| Demystifying the UVM Configuration Database | Vanessa R. Cooper and Paul Marriott | | | | | |
| Deploying Customized Solution for Graphics Registers with UVM1.2 RAL | Roman Wang, Nigel Wang, Lunping Guo, Robert Liu, and Jia Zhu | | | | | |
| Deploying Customized Solution for Graphics Registers with UVM1.2 RAL | Roman Wang, Nigel Wang, Lunping Guo, Robert Liu, and Jia Zhu | | | | | |
| Deploying Parameterized Interface with UVM | Wayne Yun and Shihua Zhang | | | | | |
| DEPLOYING PARAMETERIZED INTERFACE WITH UVM | Wayne Yun and Shihua Zhang | | | | | |
| Design and Verification of a Multichip Coherence Protocol | Shahid Ikram, Isam Akkawi, Richard Kessler, Jim Ellis, and David Asher | | | | | |
| Design and Verification of a Multichip Coherence Protocol | Shahid Ikram, Isam Akkawi, Richard Kessler, Jim Ellis, and David Asher | | | | | |
| Design and Verification of an Image Processing CPU using UVM | Milos Becvar and Greg Tumbush | | | | | |
| Design and Verification of an Image Processing CPU Using UVM | Greg Tumbush and Milos Becvar | | | | | |
| Design Guidelines for Formal Verification | Anamaya Sullerey | | | | | |
| Design Guidelines for Formal Verification | Anamaya Sullerey | | | | | |
| Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012 | Eldon Nelson M.S. P.E. | | | | | |
| Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012 | Eldon Nelson | | | | | |
| Designers Work Less with Quality Formal Equivalence Checking | Orly Cohen, Moran Gordon, Michael Lifshits, Alexander Nadel, and Vadim Ryvchin | | | | | |
| Designing Portable UVM Test Benches for Reusable IPs | Xiaoning Zhang, Baosheng Wang, and Terry Li | | | | | |
| Designing Portable UVM Test Benches for Reusable IPs | XIAONING ZHANG and BAOSHENG WANG | | | | | |
| Designing PSS Environment Integration for Maximum Reuse | Matthew Ballance | | | | | |
| Designing PSS Environment Integration for Maximum Reuse | Matthew Ballance | | | | | |
| Designing, Verifying and Building an Advanced L2 Cache Sub-System using SystemC | Thomas Tessier, Dr. Hai Lin, Daniel Ringoen, Eileen Hickey, and Steven Anderson | | | | | |
| Designing, Verifying and Building an Advanced L2 Cache Subsystem using SystemC | Steve Frank, Thomas Tessier, Dr. Hai Lin, Daniel Ringoen, Eileen Hickey, and Steven Anderson | | | | | |
| Detecting Circular Dependencies in Forward Progress Checkers | Saurabh Chaurdia, Arun Khurana, Naveen Kumar, Aditya Chaurasiya, Yogesh Mahajan, Prasenjit Biswas | | | | | |
| Detecting Harmful Race Conditions in SystemC Models Using Formal Techniques | Sven Beyer and Dominik Strasser | | | | | |
| Detecting Harmful Race Conditions in SystemC Models Using Formal Techniques | Sven Beyer and Dominik Strasser | | | | | |
| Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions | Kelly D. Larson | | | | | |
| Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions | Kelly D. Larson | | | | | |
| Detoxify Your Schedule With A Low-Fat UVM Environment | Nihar Shah | | | | | |
| Detoxify Your Schedule With A Low-Fat UVM Environment A success story on using self-checking stimulus instead of a scoreboard to reduce development time | Nihar Shah | | | | | |
| Developing a Portable Block Testbench and Reusable SOC Verification Scenarios Using IP XACT Based Automation | Taejin Kim, Minjae Kim, Yonghyun Yang, Hyundon Kim, Daewoo Kim, Tae Hee Han, and Seonil Brian Choi | | | | | |
| Did Power Management Break My CDC Logic? An Integrated Approach to Power Domain and Clock Domain Crossing Verification | Ashish Amonkar, Kurt Takara, and Avinash Agrawal | | | | | |
| Digitizing Mixed Signal Verification | David Brownell and Courtney Schmitt | | | | | |
| Digitizing Mixed Signal Verification: Digital Verification Techniques Applied to Mixed Signal and Analog Blocks on the LMA Project | David Brownell and Courtney Schmitt | | | | | |
| Discover Over-Constraints by Leveraging Formal Tool | Dongsheng Ouyang, Ray Zhang, Lucas Liu, Doris Yin, Wayne Ding | | | | | |
| Discover Over-Constraints by Leveraging Formal Tool | Dongsheng Ouyang, Ray Zhang, Lucas Liu, Doris Yin, Wayne Ding | | | | | |
| Distributed Simulation of UVM Testbench | Theta Yang | | | | | |
| Distributed Simulation of UVM Testbench | Theta Yang | | | | | |
| Do not forget to ‘Cover’ your SystemC code with UVMC | Vishal Baskar | | | | | |
| Do not forget to ‘Cover’ your SystemC code with UVMC | Vishal Baskar | | | | | |
| Do not forget to ‘Cover’ your SystemC code with UVMC | Vishal Baskar | | | | | |
| Do You Know What Your Assertions Are Up To? A New Approach to Safety Critical Verification | Lee C. Smith | | | | | |
| Do You Know What Your Assertions Are up To? A New Approach to Safety Critical Verification | Lee C. Smith | | | | | |
| Do You Verify Your Verification Components? | Josh Rensch and Neil Johnson | | | | | |
| Doing Funny Stuff with the UVM Register Layer: Experiences Using Front Door Sequences, Predictors, and Callbacks | John Aynsley | | | | | |
| Doing Funny Stuff with the UVM Register Layer: Experiences Using Front Door Sequences, Predictors, and Callbacks | John Aynsley | | | | | |
| Doing the Impossible: Using Formal Verification on Packet Based Data Paths | Doug Smith | | | | | |
| Doing the Impossible: Using Formal Verification on Packet Based Data Paths | Doug Smith | | | | | |
| Don’t delay catching bugs: Using UVM based architecture to model external board delays | Amit Paunikar, Saurabh Arya, Vikas Makhija, and Shaily Khare | | | | | |
| Don’t delay catching bugs: Using UVM based architecture to model external board delays | Amit Paunikar, Saurabh Arya, Vikas Makhija, and Shaily Khare | | | | | |
| Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to Simulation | Jonathan Bromley | | | | | |
| Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to Simulation | Jonathan Bromley | | | | | |
| DPI Redux. Functionality. Speed. Optimization. | Rich Edelman, Rohit Jain, and Hui Yin | | | | | |
| DPI Redux. Functionality. Speed. Optimization. | Rich Edelman, Rohit Jain, and Hui Yin | | | | | |
| Dr. Shahid Ikram, Distinguished Engineer, Marvell Semi Mark Eslinger, Product Engineer, Siemens | Daniel Cross | | | | | |
| DV UVM based AMS co-simulation and verification methodology for mixed signal designs | Sandeep Sharma | | | | | |
| DV UVM based AMS co-simulation and verification methodology for mixed signal designs | Sandeep Sharma | | | | | |
| DVCon U.S 2021 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon U.S. 2021 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon U.S. 2022 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon US 2022 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon USA 2023 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon USA 2023 Proceedings | Accellera Systems Initiative | | | | | |
| DVS Interface Element – A Novel Approach in Multi-Power Domain, Mixed-Signal Design Verification | Vijay Kumar Sankaran, Ji Du, Qingyu Lin, Arumugan A, and Badrinarayan Zanwar | | | | | |
| DVS Interface Element—A Novel Approach in Multi-Power Domain, Mixed-Signal Design Verification | Shekar Chetput | | | | | |
| Dynamic and Scalable OVM Stimulus for Accelerated Functional Coverage | Michael J Castle | | | | | |
| Dynamic Control Over UVM Register Backdoor Hierarchy | Roy Vincent, Unnikrishnan Nath, and Ashok Chandran | | | | | |
| Dynamic Regression Suite Generation Using Coverage-Based Clustering | Shahid Ikram and Jim Ellis | | | | | |
| Dynamic Regression Suite Generation Using Coverage-Based Clustering | Shahid Ikram and Jim Ellis | | | | | |
| Dynamically Optimized Test Generation Using Machine Learning | Rajarshi Roy, Mukhdeep Singh Benipal, Saad Godil | | | | | |
| e/eRM to SystemVerilog/UVM: Mind the Gap, But Don’t Miss the Train | Avidan Efody and Michael Horn | | | | | |
| e/eRM to SystemVerilog/UVM: Mind the Gap, But Don’t Miss the Train | Michael Horn | | | | | |
| Early Detection of Functional Corner Case Bugs using Methodologies of the ISO 26262 | Moonki Jang, Sunil Roe, Youngsik Kim, Seonil Brian Choi | | | | | |
| EARLY SOFTWARE DEVELOPMENT AND VERIFICATION METHODOLOGY USING HYBRID EMULATION PLATFORM | Woojoo Kim, Haemin Park, Hyundon Kim, Seonil Brian Choi, and SukWon Kim | | | | | |
| EASI2L: A Specification Format for Automated Block Interface Generation and Verification | Chintan Kaur, Ravi Narayanaswami, and Richard Ho | | | | | |
| Easier SystemVerilog with UVM: Taming the Beast | John Aynsley | | | | | |
| Easier SystemVerilog with UVM: Taming the Beast | John Aynsley | | | | | |
| Easier UVM – Coding Guidelines and Code Generation | John Aynsley and Dr. Christoph Sühnel | | | | | |
| Easier UVM for Functional Verification by Mainstream Users | John Aynsley | | | | | |
| Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI | Dave Rich | | | | | |
| Easy uvm_config_db use: A simplified and reusable uvm_config_db methodology for environment developers and test writers | Bob Oden | | | | | |
| Easy uvm_config_db use: A simplified and reusable uvm_config_db methodology for environment developers and test writers | Bob Oden | | | | | |
| Effects of Abstraction in Stimulus Generation of Layered Protocols within OVM | Josh Rensch and Jesse Prusi | | | | | |
| Efficient and Exhaustive Floating Point Verification Using Sequential Equivalence Checking | Travis W. Pouarz and Vaibhav Agrawal | | | | | |
| Efficient and Exhaustive Floating Point Verification Using Sequential Equivalence Checking | Travis Pouarz and Vaibhav Agrawal | | | | | |
| Efficient application of AI algorithms for large-scale verification environments based on NoC architecture | Anna Ravitzki, Olivera Stojanovic, Nemanja Mitrovic | | | | | |
| Efficient application of AI algorithms for large-scale verification environments based on NoC architecture | Anna Ravitzki, Olivera Stojanovic, Nemanja Mitrovic | | | | | |
| Efficient Bug-Hunting Techniques Using Graph-Based Stimulus Models | Nguyen Le and Mike Andrews | | | | | |
| Efficient Bug-Hunting Techniques Using Graph-Based Stimulus Models | Nguyen Le and Mike Andrews | | | | | |
| Efficient distribution of video frames to achieve better throughput | Bhavik Vyas and Suruchi Jain | | | | | |
| Efficient hierarchical low power verification of custom designs using static and dynamic techniques | Himanshu Bhatt, Archanna Srinivasan, and Chong Lee Kuay | | | | | |
| Efficient Methods for Display Power Estimation & Visualization | Srikanth Reddy Rolla and Aakash Modi | | | | | |
| Efficient Methods for Display Power Estimation and Visualization | Srikanth Reddy Rolla and Aakash Modi | | | | | |
| Efficient SCE-MI Usage to Accelerate TBA Performance | Ponnambalam Lakshmanan, Prashantkumar Ravindra, and Rajarathinam Susaimanickam | | | | | |
| Efficient Simulation Based Verification by Reordering | Chao Ya and Kevin Jones | | | | | |
| Efficient SoC Level Mixed Signal Frontend Verification using Wreal Models | Anu Marisha, Nayana Prakash, Udit Kumar, and Rajesh Tiwari | | | | | |
| Efficient SoC Level Mixed Signal Frontend Verification using Wreal Models | Anu Marisha, Nayana Prakash, Udit Kumar, Rajesh Tiwari, and Vijay Kumar Birange | | | | | |
| Efficient Standard Co-Emulation Modeling Interface (SCE-MI) Usage to Accelerate TBA Performance | Ponnambalam Lakshmanan | | | | | |
| EMULATION BASED FULL CHIP LEVEL LOW POWER VALIDATION AT PRE-SILICON STAGE | Kyoungmin Park, Jaegeun Song, Hyundon Kim, Seonil Brian Choi, and Suk Won Kim | | | | | |
| Emulation Based Power and Performance Workloads on ML NPUs | Pragati Mishra, Ritu Suresh, Issac Zacharia, and Jitendra Aggarwal | | | | | |
| Emulation Based Power and Performance Workloads on ML NPUs | Pragati Mishra, Ritu Suresh, Issac Zacharia, and Jitendra Aggarwal | | | | | |
| Emulation Moves Into 4-State Logic and Real Number Modeling DVCon US 2024 | Brad Budlong, Michael Young, Kyoungmin Park, Nimay Shah | | | | | |
| Emulation Testbench Optimizations for better Hardware Software Co-Validation | Vijayakrishnan Rousseau, Suresh Balasubramanian, Srikanth Reddy Rolla, and Mohamed Saheel Nandikotkur Hussainsaheb | | | | | |
| Enabling True System-Level Mixed-Signal Emulation | Nimay Shah , Paul Wright , Pranav Dhayagude Raj Mitra , Adam Sherer | | | | | |
| Enabling True System-Level, Mixed-Signal Emulation | Nimay Shah, Paul Wright, Pranav Dhayagude, Raj Mitra, Adam Sherer | | | | | |
| Enabling True System-Level, Mixed-Signal Emulation | Nimay Shah, Paul Wright, Pranav Dhayagude, Raj Mitra, Adam Sherer | | | | | |
| End to End Formal Verification Strategies for IP Verification | Jacob Ryan Maas, Nirabh Regmi, Ashish Kulkarni, and Krishnan Palaniswami | | | | | |
| End to End Formal Verification Strategies for IP Verification | Jacob Ryan Maas, Nirabh Regmi, Krishnan Palaniswami, and Ashish Kulkarni | | | | | |
| Engineered SystemVerilog Constraints | Jeremy Ridgeway | | | | | |
| Engineered SystemVerilog Constraints | Jeremy Ridgeway | | | | | |
| Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software Verification | Victor Besyakov | | | | | |
| Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software Verification | Victor Besyakov | | | | | |
| Environment for efficient and reusable SystemC module level verification | Flavia Gonția | | | | | |
| Environment for efficient and reusable SystemC module level verification | Flavia Gontia | | | | | |
| Equivalence Validation of Analog Behavioral Models | Hardik Parekh, Manish Kumar Karna, Mohit Jain, Atul Pandey, and Sandeep Mittal | | | | | |
| Equivalence Validation of Analog Behavioral Models | Hardik Parekh, Manish Kumar Karna, Mohit Jain, Atul Pandey, and Sandeep Mittal | | | | | |
| Equivalence Validation of Analog Behavioral Models | Manish Kumar Karna, Hardik Parekh, Mohit Jain, Atul Pandey, and Sandeep Mittal | | | | | |
| Eradicating X-bugs and Achieving Higher Design Quality Using Static X-propagation Sign-off | Sanjay Thatte, Andrew Guyler, Nikhil Rahagude, and Savitha Raghunath | | | | | |
| Error Injection in a Subsystem Level Constrained Random UVM Testbench | Jeremy Ridgeway and Hoe Nguyen | | | | | |
| Error Injection in a Subsystem Level Constrained Random UVM Testbench | J. Ridgeway and H. Nguyen | | | | | |
| Error Injection: When Good Input Goes Bad | Kurt Schwartz and Tim Corcoran | | | | | |
| Error Injection: When Good Input Goes Bad | Kurt Schwartz and Tim Corcoran | | | | | |
| Estimating Power Dissipation of End-User Application on RTL | Magdy El-Moursy | | | | | |
| Evaluating the Feasibility of a RISC V Core for Real Time Applications Using a Virtual Prototype | J. Santana , G. Pachiana, T. Markwirth, C. Sohrmann, B. Fischer, M. Matschnig | | | | | |
| Evaluating the Feasibility of a RISCV Core for Real-Time Applications Using a Virtual Prototype | Juan Santana, Gabriel Pachiana, Thomas Markwirth, Christoph Sohrmann, Bernhard Fischer, and Martin Matschnig | | | | | |
| Every Cloud – Post-Silicon Bug Spurs Formal Verification Adoption | Blaine Hsieh, Stewart Li, and Mark Eslinger | | | | | |
| Every Cloud – Post-Silicon Bug Spurs Formal Verification Adoption | Blaine Hsieh, Stewart Li, and Mark Eslinger | | | | | |
| Evolution of CDC recipe: Learning through real case studies and methodology improvements | Amit Kulkarni, Suhas DS, Deepmala Sachan | | | | | |
| Evolution of Triage: Real-time Improvements in Debug Productivity | Gordon Allan | | | | | |
| Evolutionary and Revolutionary Innovation for Effective Verification Management & Closure | Darron May, Mark Carey, Dan Yu | | | | | |
| Exhaustive Equivalence Checking on AMD’s Next-generation Microprocessor Core | Baosheng Wang, Brian McMinn, Borhan Roohipour, Ashok Venkatachar, Arun Chandra, Richard Bartolotti, and Lerzan Celikkanat | | | | | |
| Exhaustive Latch Flow – Through Verification with Formal Methods | Baosheng Wang, Sean Ater, Baris Piyade, Brian McMinn, and Borhan Roohipour | | | | | |
| Exhaustive Latch Flow-through Verification with Formal Methods | Baosheng Wang, Sean Ater, Baris Piyade, Brian McMinn, and Borhan Roohipour | | | | | |
| Expanding role of Static Signoff in Verification Coverage | Vikas Sachdeva | | | | | |
| Expediting SoC Design Verification Closure by Accelerating Gate Level Simulations using Streamlined Smart Decentralized Testbench | Harshal Kothari, Eldin Ben Jacob, Chandrachud Murali, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | |
| Experience with OVM-Based Mixed-Signal Verification of the Impedance Calibration Block for a DDR Interface | Harry Wang, Wessam El-Naji, and Kenneth Bakalar | | | | | |
| Experience with OVM-Based Mixed-Signal Verification of the Impedance Calibration Block for a DDR Interface | Harry Wang, Wessam El-Naji, and Kenneth Bakalar | | | | | |
| Experiences in Migrating a Chip-Level Verification Environment from UVM EA to UVM 1.1 | Ashish Kumar, Dave Stang, Dudyala Sasidhar, S, Manikandan, and Thirumalai Srishan | | | | | |
| Experiences in Migrating a Chip-Level Verification Environment from UVM-EA to UVM-1.x | Ashish Kumar, S Manikandan, Sasidhar Dudyala, Srishan Thirumalai, and Dave Stang | | | | | |
| Experiencing Checkers for a Cache Controller Design | Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari, and Lisa Piper | | | | | |
| Exploring Machine Learning to assign debug priorities to improve the design quality | Vyasa Sai, Vaibhav Gupta and Fylur Rahman Sathakathulla | | | | | |
| Exploring Machine Learning to assign debug priorities to improve the design quality | Vyasa Sai, Vaibhav Gupta, Fylur Rahman | | | | | |
| Exquisite modeling of verification IP: Challenges and Recommendations | Anuradha Tambad, Subashini Rajan, Shivani Upasani, Prashanth Srinivasa, Imran Ali, and Adiel Khan | | | | | |
| Exquisite Modeling of VIP | Adiel Khan, Anuradha Tambad, Imran Ali, Prashanth Srinivasa, Shivani Upasani, and Subashini Rajan | | | | | |
| Extendable Messaging Techniques for Debugging and Analyzing UVM Testbench Structure and Transaction Flow | Jun Zhao, Bindesh Patel, and Rex Chen | | | | | |
| Extendable Messaging Techniques for Debugging and Analyzing UVM Testbench Structure and Transaction Flow | Jun Zhao, Bindesh Patel, and Rex Chen | | | | | |
| Extending the RISC-V Verification Interface for Debug Module Co-Simulation | Michael Chan, Ravi Shethwala, Richa Singhal, Lee Moore, Aimee Sutton | | | | | |
| Extending the RISC-V Verification Interface for Debug Module Co-Simulation | Lee Moore, Aimee Sutton, Michael Chan, Ravi Shethwala, Richa Singhal | | | | | |
| Extension of the Power-Aware IP Reuse Approach to ESL | Antonio Genov, Loic Leconte, Fran ç ois Verdier | | | | | |
| Fabric Verification | Galen Blake and Steve Chappell | | | | | |
| Failure Triage: The Neglected Debugging Problem | Sean Safarpour, Evean Qin, Yu-Shen Yang, and Brian Keng | | | | | |
| Failure Triage: The Neglected Debugging Problem | Sean Safarpour, Evean Qin, Yu-Sheng Yang, and Brian Keng | | | | | |
| Fast Track Formal Verification Signoff | Mandar Munishwar, Xiaolin Chen, Arunava Saha, and Sandeep Jana | | | | | |
| Fast Track Formal Verification Signoff | Mandar Munishwar, Xiaolin Chen, Arunava Saha, and Sandeep Jana | | | | | |
| Fault-Effect Analysis on Multiple Abstraction Levels in Hardware Modeling | B-A. Tabacaru, M. Chaari, W. Ecker, T. Kruse, and C. Novello | | | | | |
| Fault-Effect Analysis on Multiple Abstraction Levels in Hardware Modeling | Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, and Cristiano Novello | | | | | |
| Finding a Needle in a Haystack: A Novel Log Analysis Method with Test Clustering in Distributed System | Jin Choi | | | | | |
| Finding a Needle in a Haystack: A Novel Log Analysis Method with Test Clustering in Distributed Systems | Jin Choi, Sangwoo Noh, Sooncheol Hong, Hanna Jang, Seonghee Yim, and Seonil Brian Choi | | | | | |
| Finding Hidden Bugs In Deep Cycles: Advanced Debug Methodologies for Software-first System Validation | Youcef Qassid and Andy Jolley | | | | | |
| Finding the Last Bug in a CNN DMA Unit | Bruno Lavigueur, Dean Ke, Eric Rao, Fergus Casey, Achin Mittal, Pallavi Kumari, Michael Thompson, and Roger Sabbagh | | | | | |
| Finding the Last Bug in a CNN DMA Unit | Bruno Lavigueur, Dean Ke, Eric Rao, Fergus Casey, Achin Mittal, Pallavi Kumari, Michael Thompson, and Roger Sabbagh | | | | | |
| First Reports from the UVM Trenches: User-friendly, Versatile and Malleable, or just the Emperor’s New Methodology? | Jonathan Bromley | | | | | |
| Flattening the UVM Learning Curve Automated Solutions for DSP Filter Verification | Avinash Lakshminarayana, Eric Jackowski, Eric Cigan, and Mark Lin | | | | | |
| Flattening the UVM Learning Curve: Automated Solutions for DSP Filter Verification | Avinash Lakshminarayana, Eric Jackowski,Eric Cigan, Mark Lin | | | | | |
| Flexible Checker: A one-stop shop for all your checkers and a methodology for elastic scoreboarding | Saad Zahid, Chandra Veedhi, and Sumit Dhamanwala | | | | | |
| Flexible Indirect Registers with UVM | Uwe Simm | | | | | |
| Fnob: Command Line-Dynamic Random Generator | Haoxiang Hu, Tuo Wang | | | | | |
| Fnob: Command Line-Dynamic Random Generator | Haoxiang Hu and Tuo Wang | | | | | |
| Formal Architectural Specification and Verification of A Complex SOC | Shahid Ikram, Isam Akkawi, David Asher, and Jim Ellis | | | | | |
| FORMAL ARCHITECUTRAL SPECIFICATION AND VERIFICATION OF A COMPLEX SOC | Shahid Ikram, Isam Akkawi, David Asher, and Jim Ellis | | | | | |
| Formal Bug Hunting with “River Fishing” Techniques | Mark Eslinger and Ping Yeung | | | | | |
| Formal Bug Hunting with “River Fishing” Techniques | Mark Eslinger and Ping Yeung | | | | | |
| Formal Methods to Verify the Power Manager for an Embedded Multiprocessor Cluster | Kesava R. Talu | | | | | |
| Formal Proof for GPU Resource Management | Jia Zhu, Chuanqin Yan, and Nigel Wang | | | | | |
| Formal Proof for GPU Resource Management | Jia Zhu, Chuanqin Yan, and Nigel Wang | | | | | |
| Formal Verification Approach to Verifying Stream Decoders: Methodology & Findings | Abhishek Asi, Anshul Jain | 2024 | Paper | | y2024 | paper |
| Formal Verification Approach to Verifying Stream Decoders: Methodology & Findings | Abhishek Asi, Anshul Jain, Aarti Gupta | | | | | |
| Formal Verification Bootcamp | Mike Bartley | | | | | |
| Formal Verification by The Book: Error Detection and Correction Codes | K. Devarajegowda, V. Hiltl, T. Rabenalt, D. Stoffel, W. Kunz, and W. Ecker | | | | | |
| Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt | Ping Yeung, Mark Eslinger, Jin Hou | | | | | |
| Formal Verification Framework for Hardware Accelerator Designs | Kevin Bhensdadiya, Anmol Patel, Anshul Jain, Aarti Gupta | | | | | |
| Formal Verification Framework for Hardware Accelerator Designs | Kevin Bhensdadiya, Anmol Patel, Anshul Jain | | | | | |
| Formal Verification in the Real World | Jonathan Bromley and Jason Sprott | | | | | |
| Formal Verification of Connections at SoC-level | Penny Yang, Prasun Das, Yuya Kao, and Mingchu Kuo | | | | | |
| Formal Verification of Connections at SoC-level | Penny Yang, Prasun Das, Yuya Kao, and Mingchu Kuo | | | | | |
| FORMAL VERIFICATION OF FLOATING-POINT HARDWARE WITH ASSERTION-BASED VIP | Ravi Ram, Adam Elkins, Adnan Pratama, Sasa Stamenkovic, Sven Beyer, and Sergio Marchese | | | | | |
| Formal Verification of Floating-Point Hardware with Assertion-Based VIP | Ravi Ram, Adam Elkins, Adnan Pratama, Sasa Stamenkovic, Sven Beyer, and Sergio Marchese | | | | | |
| Formal Verification of Macro-op Cache for Arm Cortex-A77, and its Successor CPU | Vaibhav Agrawal | | | | | |
| Formal verification of Macro-op cache for Arm Cortex-A77, and its successor CPU | Vaibhav Agrawal | | | | | |
| Formal Verification of Silicon for Software Defined Networking | Saurabh Shrivastava, Keqin Han, Anh Tran, Chirag Agarwal, Ankit Saxena, Achin Mittal, Anshul Jain, and Roger Sabbagh | | | | | |
| Formal Verification on Deep Learning Instructions of GPU | Jian (Jeffrey) Wang and Jia Zhu | | | | | |
| Formal Verification Tutorial Breaking Through the Knowledge Barrier | Sean Safarpour, Iain Singleton, Shaun Feng, Syed Suhaib, and Mandar Munishwar | | | | | |
| Forward Progress Checks in Formal Verification: Liveness vs Safety | Ankit Garg | | | | | |
| Forward Progress in Formal Verification Liveness vs Safety | Ankit Garg | | | | | |
| Four Problems with Policy-Based Constraints and How to Fix Them | Dillan Mills, Chip Haldane | | | | | |
| Four Problems with Policy-Based Constraints and How to Fix Them | Dillan Mills, Chip Haldane | | | | | |
| FPGA-based Clock Domain Crossing Validation for Safety-Critical Designs | Alexander Gnusin | | | | | |
| FPGA-based Clock Domain Crossing Validation for Safety-Critical Designs | Alexander Gnusin | | | | | |
| Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF | Progyna Khondkar, Ping Yeung, Gabriel Chidolue, Joe Hupcey, Rick Koster, and Madhur Bhargava | | | | | |
| Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF | Progyna Khondkar, Ping Yeung, Gabriel Chidolue, Joe Hupcey, Rick Koster, and Madhur Bhargava | | | | | |
| From Spec to Verification Closure: a case study of applying UVM-MS for first pass success to a complex Mixed-Signal SoC design | Neyaz Khan and Yaron Kashai | | | | | |
| From Spec to Verification Closure: A case study of applying UVM-MS for first pass success to a complex MS-SoC design | Neyaz Khan and Yaron Kashai | | | | | |
| From the Magician’s Hat: Developing a Multi-Methodology PCIe Gen2 VIP | Amit Sharma, Abhisek Verma, Varun S., and Anoop Kumar | | | | | |
| fsim_logic – A VHDL type for testing of FLYTRAP | Joanne E. DeGroat, Ph.D. | | | | | |
| fsim_logic – A VHDL type for testing of FLYTRAP | Joanne E. DeGroat, Ph.D. | | | | | |
| FSM Minesweeper – Scalable Formal Verification Methodology for Detecting Hangs in Interacting FSMs | Anshul Jain, Achutha KiranKumar V M, Harbaksh Gupta, Shashwat Singh | | | | | |
| FSM Minesweeper – Scalable FV Methodology for Detecting Hangs in Interacting FSMs | Anshul Jain, Achutha KiranKumar V M, Harbaksh Gupta, Shashwat Singh | | | | | |
| Full Flow Clock Domain Crossing – From Source to Si | M. Litterick | | | | | |
| Full Flow Clock Domain Crossing – From Source To Si | Mark Litterick | | | | | |
| Fully Automated Functional Coverage Closure | Manohar Kodi, Sagar Sudam Patil, and Ranjith Nair | | | | | |
| Fully Automated Functional Coverage Closure | Manohar Kodi, Sagar Sudam Patil, and Ranjith Nair | | | | | |
| Fully Hierarchical CDC Analysis Using Comprehensive CDC Meta Database | Youngchan Lee, Youngsik Kim, Soenil Brian Choi, and Vikas Sachdeva | | | | | |
| Fully Hierarchical CDC Analysis Using Comprehensive CDC Meta-Database | Youngchan Lee, Youngsik Kim, and Seonil Brian Choi | | | | | |
| Fun with UVM Sequences – Coding and Debugging | Rich Edelman | | | | | |
| Fun with UVM Sequences Coding and Debugging | Rich Edelman | | | | | |
| Functional Coverage – without SystemVerilog! | Alan Fitch and Doug Smith | | | | | |
| Functional Coverage Closure with Python | Seokho Lee, Youngsik Kim, Suhyung Kim, Jeong Ki Lee, Wooyoung Choe, Minho Kim FuriosaAI, Seoul, Korea | 2024 | Paper | | y2024 | paper |
| Functional Coverage Closure with Python | Seokho Lee, Youngsik Kim, Suhyung Kim, Jeong Ki Lee, Wooyoung Choe, Minho Kim | | | | | |
| Functional Coverage Collection for Analog Circuits – Enabling Seamless Collaboration between Design and Verification | Z. Ye, H. Lin and A. M. Khan | | | | | |
| Functional Coverage Collection for Analog Circuits –Enabling Seamless Collaboration between Design and Verification | Zhipeng Ye, Honghuang Lin and Asad Khan | | | | | |
| Functional Coverage of Register Access via Serial Bus Interface using UVM | D. M. Tomušilović | | | | | |
| FUNCTIONAL COVERAGE OF REGISTER ACCESS VIA SERIAL BUS INTERFACE USING UVM | Darko M. Tomušilovic | | | | | |
| Functional coverage-driven verification with SystemC on multiple level of abstraction | Christoph Kuznik and Wolfgang M¨uller | | | | | |
| Functional Instruction Set Simulator (ISS) of a Neural Network Accelerator IP with native “brain float16” format | Debajyoti Mukherjee, Arpita Sahu, Arathy B S, Saranga P Pogula | | | | | |
| Functional Safety Verification For ISO 26262 | Kevin Rich, Shekhar Mahatme, and Meirav Nitzan | | | | | |
| Functional Safety Workflow of Internal IP (NPU) Within Large Automotive IC Through Analysis and Emulation Usage | Likhopoy Andrey, Kim Inhwan | | | | | |
| Functional Safety Workflow of Internal IP (NPU) Within Large Automotive IC Through Analysis and Emulation Usage for SW-based Safety Mechanisms | Andrey Likhopoy, Sangkyu Park, Hyeonuk Noh, Wonil Cho, Inhwan Kim, Robert Serphillips, Chanjin Kim, Justin Lee, James Kim, Sougata Bhattacharjee, Gulshan Kumar Sharma, Akshaya Kumar Jain | | | | | |
| Functional Verification from Chaos to Order: Using Continuous Integration for Hardware Functional Verification | Abdelouhab Ayari, Kirolos Mikhael | | | | | |
| Functional Verification from Chaos to Order: Using Continuous Integration for Hardware Functional Verification | Kirolos Mikhael, Abdelouahab Ayari | | | | | |
| Functional Verification of Analog Devices modeled using SV-RNM | Mariam Maurice | | | | | |
| Functional Verification of Analog Devices modeled using SV-RNM | Mariam Maurice | | | | | |
| Generation of Constraint Random Transactions for Verification of Mixed-Signal Blocks | Alexander W. Rath, Sebastian Simon, Volkan Esen, and Wolfgang Ecker | | | | | |
| Generic Programming in SystemVerilog | Mark Glasser | | | | | |
| Generic SCSI-Based Host Controller Verification Framework Using SystemVerilog | Mohamed Rayan, Mohamed Samy, Haytham Ashour, Ashraf Salem | | | | | |
| Getting Beyond ISA Compliance: Advanced Core/SoC Verification for RISC-V and other Beasts | Adnan Hamid | | | | | |
| Getting Rid of False Errors when Verifying LSI Designs Including Non-Determinism | Matthieu Parizy and Hiroaki Iwashita | | | | | |
| Gherkin Implementation in SystemVerilog Brings Agile Behavior-Driven Development to UVM | William L. Moore | | | | | |
| Gherkin Implementation in SystemVerilog Brings Agile Behavior-Driven Development to UVM | William L. Moore | | | | | |
| GIT for Hardware Designers | Jeffery Scott and Sanjeev Singh | | | | | |
| Git for Hardware Designers | Jeffery Scott and Sanjeev Singh | | | | | |
| Goldilocks and System Performance Modeling | Rich Edelman and Shashi Bhutada | | | | | |
| Goldilocks and System Performance Modelling A SystemVerilog Adaptive Rate Control (ARC) Stimulus Generation Methodology | Rich Edelman and Shashi Bhutada | | | | | |
| GoldMine: Automatic Assertion Generation and Coverage Closure in Design Validation | David Sheridan, Lingyi Liu, and Shobha Vasudevan | | | | | |
| Graph-IC Verification | Dennis Ramaekers and Grégory Faux | | | | | |
| Graph-IC Verification | Gregory Faux and Dennis Ramaekers | | | | | |
| GraphCov: RTL Graph Based Test Biasing for Exploring Uncharted Coverage Landscape | Debarshi Chatterjee, Spandan Kachhadia, Chen Luo, Kumar Kushal, Siddhanth Dhodhi | | | | | |
| GraphCov: RTL Graph Based Test Biasing for Exploring Uncharted Coverage Landscape | Debarshi Chatterjee, Spandan Kachhadia, Chen Luo, Kumar Kushal, Siddhanth Dhodhi | | | | | |
| Graphical Topology Info Structure for Constrained Random Verification in SoC/Subsystem Tests | Evean Qin, Richard Bell, and David Chen | | | | | |
| Graphical Topology Info Structure for Constrained Random Verification in SoC/Subsystem Tests | Evean Qin, Richard Bell, and David Chen | | | | | |
| Guaranteed Vertical Reuse – C Execution In A UVM Environment | Rachida El Idrissi and Alain Gonier | | | | | |
| Guaranteed Vertical Reuse – C Execution In a UVM Environment | Rachida El Idrissi and Alain Gonier | | | | | |
| Hardware Acceleration for UVM Based CLTs | Mohamed Saheel, Rohith M. S., and Andrew Tan | | | | | |
| Hardware Emulation: ICE vs Virtual | Lauro Rizzatti | | | | | |
| Hardware Trojan Design and Detection with Formal Verification to Deep Neural Network | Si-Han Chen, Yu-Ting Huang, Yi-Chun Kao, Yean-Ru Chen, Shang-Wei Lin, Chia-I Chen | | | | | |
| Hardware/Software co-verification using Specman and SystemC with TLM ports | Horace Chan and Brian Vandegriend | | | | | |
| Hardware/Software Co-Verification Using Specman and SystemC with TLM Ports | Horace Chan | | | | | |
| Hardware/Software Interface Formats A Discussion | Richard Weber, Jamsheed Agahi, Josh Rensch, Eric Sherk | | | | | |
| Harnessing the Power of UVM for AMS Verification with XMODEL | Jaeha Kim, Charles Dančak | | | | | |
| Hierarchical CDC and RDC closure with standard abstract models | Ping Yueng, Farhad Ahmed, Iredamola Olopade, Bill Gascoye, Sean O'Donahue, Kranthi Pamarthi, Chetan Choppali Sudaharshan, Anupam Bakshi | | | | | |
| Hierarchical UPF Design – The ‘Easy’ Way | Brandon Skaggs, Chris Turman, Joe Whitehouse | | | | | |
| Hierarchical UPF Design – The ‘Easy’ Way | Brandon Skaggs, Chris Turman, Joe Whitehouse | 2023 | Presentation | | y2023 | presentation |
| Hierarchical UPF: Uniform UPF across FE & BE | Dipankar Narendra Arya, Balaji Vishwanath Krishnamurthy, Aditi Nigam, Tahir Ali | | | | | |
| Hierarchical UPF: Uniform UPF across FE & BE | Dipankar Narendra Arya, Balaji Vishwanath Krishnamurthy, Aditi Nigam, and Ali Tahir | | | | | |
| High-Level Synthesis Walks the Talk: Synthesizing a Complete Graphics Processing Application | Thomas Bollaert | | | | | |
| High-Speed Interface IP Validation based on Virtual Emulation Platform | Jaehun Lee, DaeSeo Cha, and Sungwook Moon | | | | | |
| High-Speed Interface IP Validation based on Virtual Emulation Platform | Jaehun Lee, Daeseo Cha, and Sungwook Moon | | | | | |
| Highly Configurable UVM Environment for Parameterized IP Verification | HongLiang Liu and Karl Whiting | | | | | |
| Highly Configurable UVM Environment for Parameterized IP Verification | HongLiang Liu and Karl Whiting | | | | | |
| Holistic Approach to IO Timing Verification Using Portable Stimulus and Assertions | Amitesh Khandelwal and Praveen Kumar | | | | | |
| Holistic Approach to IO Timing Verification Using Portable Stimulus and Assertions | Amitesh Khandelwal and Praveen Kumar | | | | | |
| Holistic Automated Code Generation: No Headache with Last-Minute Changes | Klaus Strohmayer and Norbert Pramstaller | | | | | |
| Holistic Automated Code Generation: No Headache with Last-Minute Changes | Klaus Strohmayer and Norbert Pramstaller | | | | | |
| Hopscotch: A Scalable Flow-Graph Based Approach to Formally Specify and Verify Memory-Tagged Store Execution in Arm CPUs | Abhinav Sethi, Madhu Iyer, Sai Komaravelli, and Vikram Khosa | | | | | |
| Hopscotch: A Scalable Flow-Graph Based Approach to Verify CPU Store Execution | Abhinav Sethi, Madhu Iyer, Sai Komaravelli, and Vikram Khosa | | | | | |
| How Do You Verify Your Verification Components? | Josh Rensch and Neil Johnson | | | | | |
| How Far Can You Take UVM Code Generation and Why Would You Want To? | John Aynsley | | | | | |
| How Far Can You Take UVM Code Generation and Why Would You Want To? | John Aynsley | | | | | |
| How HLS and SystemC is Delivering on its Promise of Design and Verification Productivity | Stuart Swan, Mike Meredith, Matthew Bone, and Rangharajan Venkatesan | | | | | |
| How I Learned to Stop Worrying and Love Benchmarking Functional Verification! | Mike Bartley | | | | | |
| How I Learned to Stop Worrying and Love Benchmarking Functional Verification! | Mike Bartley and Mike Benjamin | | | | | |
| How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage | Mark Eslinger, Joseph V Hupcey III, and Nicolae Tusinschi | | | | | |
| How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage | Mark Eslinger, Joseph V Hupcey III, and Nicolae Tusinschi | | | | | |
| How to Create Reusable Portable Testing and Stimulus Standard (PSS) Verification IP | Sharon Rosenberg | | | | | |
| How to Kill 4 Birds with 1 Stone: Using Formal Verification to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software Specifications | Saurabh Shrivastava, Kavita Dangi, Darrow Chu, and Mukesh Sharma | | | | | |
| How to Kill 4 Birds with 1 Stone: Using Formal Verification to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software Specifications | Saurabh Shrivastava, Kavita Dangi, Darrow Chu, and Mukesh Sharma | | | | | |
| How to Overcome Editor Envy: Why Can’t My Editor Do That? | Dillan Mills, Chuck McClish | | | | | |
| How to Stay Out of the News with ISO26262-Compliant Verification | Charles Battikha and Doug Smith | | | | | |
| How to Succeed Against Increasing Pressure: Automated Techniques for Unburdening Verification Engineers | James Pascoe, Pierre Kuhn, and Steve Hobbs | | | | | |
| How to Succeed Against Increasing Pressure: Automated Techniques for Unburdening Verification Engineers | James Pascoe and Steve Hobbs | | | | | |
| How to test the whole firmware/software when the RTL can’t fit the emulator | Horace Chan and Byron Watt | | | | | |
| How to test the whole firmware/software when the RTL can’t fit the emulator | Horace Chan and Byron Watt | | | | | |
| How UPF 3.1 Reduces the Complexities of Reusing PA Macros | Madhusudhana Reddy Lebaka, Abraham Guizer, and Progyna Khondkar | | | | | |
| How UPF 3.1 Reduces the Complexities of Reusing Power Aware Macros | Madhusudhana Reddy Lebaka, Abraham Guizer, and Progyna Khondkar | | | | | |
| HSI Issues – Fake News or Not? How Hardware/Software Interface Impacts Tape-Outs | Gary Stringham, Rich Weber, and Jamsheed Agahi | | | | | |
| Hybrid Approach to Testbench and Software Driven Verification on Emulation | Debdutta Bhattacharya and Ayub Khan | | | | | |
| Hybrid Approach to Testbench and Software Driven Verification on Emulation | Debdutta Bhattacharya and Ayub Khan | | | | | |
| Hybrid Emulation: Accelerating Software Driven Verification and Debug | Issac P Zacharia and Jitendra Aggarwal | | | | | |
| Hybrid Emulation: Accelerating Software Driven Verification and Debug | Issac P Zacharia and Jitendra Aggarwal | | | | | |
| I created the Verification Gap | Ram Narayan and Tom Symons | | | | | |
| I created the Verification Gap | Ram Narayan and Tom Symons | | | | | |
| I’m Still In Love With My X! (but, do I want my X to be an optimist, a pessimist, or eliminated?) | Stuart Sutherland | | | | | |
| I’m Still In Love With My X! (but, do I want my X to be an optimist, a pessimist, or eliminated?) | Stuart Sutherland | | | | | |
| IDeALS For All – Intelligent Detection and Accurate Localization of Stalls | Pallavi Jesrani | | | | | |
| IDeALS for all – Intelligent Detection and Accurate Localization of Stalls | Pallavi Jesrani | | | | | |
| Identifying unique power scenarios with data mining techniques at full SoC level with real workloads | Amir Attarha | | | | | |
| Identifying unique power scenarios with data mining techniques at full SoC level with real workloads | Amir Attarha, Pankaj Chauhan, Diwakar Agrawal, Satish-Kumar Agrawal, Gaurav Saharawat | | | | | |
| IDEs Should be Available to Hardware Engineers Too! | Syed Daniyal Khurram and Horace Chan | | | | | |
| IDEs SHOULD BE AVAILABLE TO HARDWARE ENGINEERS TOO! | Syed Daniyal Khurram and Horace Chan | | | | | |
| IEEE 1800-2009 SystemVerilog: Assertion-based Checker Libraries | Eduard Cerny and Dmitry Korchemny | | | | | |
| IEEE 1800.2 UVM – Changes Useful UVM Tricks & Techniques | Clifford E. Cummings | | | | | |
| IEEE-Compatible UVM Reference Implementation and Verification Components | Justin Refice, Mark Strickland, Mark Peryer, Uwe Simm, and Srivatsa Vasudevan | | | | | |
| Improve Emulator Test Quality By Applying Synthesizable Functional Coverage | Hoyeon Hwang, Taesung Kim, Sanghyun Park, Yong-Kwan Cho, Dohyung Kim, Wonil Cho, Sanggyu Park | | | | | |
| Improve emulator test quality by applying synthesizable functional coverage | Hoyeon Hwang, Taeseong Kim, Sanghyun Park, Yong-Kwan Cho, Dohyung Kim, Wonil Cho, Sanggyu Park | | | | | |
| Improvement of UVM IP Validation using Portable Stimulus (PSS) | Robert R Martin, Alan M Curtis, Gopinath Narasimhan, Qingwei Zhou | | | | | |
| Improvement of UVM Scenario Generation, Control and Reproducibility using Portable Stimulus (PSS) for IP Validation | Robert R. Martin, Alan M. Curtis, Gopinath L. Narasimhan, Qingwei Zhou | | | | | |
| Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation | Eldon Nelson M.S. P.E. | | | | | |
| Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation | Eldon Nelson M.S. P.E. | | | | | |
| Improving Software Testing Speed by 100X with SystemC Virtualization in IoT Devices | David Barahona, Motaz Thiab, Isael Díaz, Joakim Urdahl, and Milica Orlandic | | | | | |
| Improving the UVM Register Model: Adding Product Feature based API for Easier Test Programming | Krishnan Balakrishnan, Courtney Fricano, and Kaushal Modi | | | | | |
| Improving the UVM Register Model: Adding Product Feature based API for Easier Test Programming | Krishnan Balakrishnan, Courtney Fricano, and Kaushal Modi | | | | | |
| Improving Verification Predictability and Efficiency Using Big Data | Darron K. May | | | | | |
| Improving Verification Predictability and Efficiency Using Big Data | Darron May | | | | | |
| In pursuit of Faster Register Abstract Layer (RAL) Model | Anmol Rana, Bhagwan Jha, and Harjeet Singh Sanga | | | | | |
| Incomplete Low-Power Verification Flow & the oncoming Internet of Things (IoT) Tsunami! | Neyaz Khan and Kamran Haqqani | | | | | |
| Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee | Thomas Ellis | | | | | |
| Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee | Thom Ellis | | | | | |
| Increasing Regression Efficiency with Portable Stimulus | Niyaz. K. Zubair and Subba Kota Rao Sajja | | | | | |
| Innovative 4-State Logic Emulation for Power-aware Verification | Kyoungmin Park, Brad Budlong, Hyundon Kim, Danny Yi, Jaehunn Lee , Chulmin Kim, Jaemin Choi, Kijung Yoo, Gibs Lee, Youngsik Kim, Yogesh Goel, Seonil Brian Choi | | | | | |
| Innovative 4-State Logic Emulation for Power-aware Verification | Kyoungmin Park, Brad Budlong, Hyundon Kim, Danny Yi, Jaehunn Lee , Chulmin Kim, Jaemin Choi, Kijung Yoo, Gibs Lee, Youngsik Kim, Yogesh Goel, Seonil Brian Choi | | | | | |
| Innovative Techniques to Solve Complex RDC Challenges | Rohit Kumar Sinha | | | | | |
| Innovative Uses of SystemVerilog Bind Statements within Formal Verification | Xiushan Feng and Christopher Starr | | | | | |
| Innovative Uses of SystemVerilog Bind Statements within Formal Verification | Xiushan Feng and Christopher Starr | | | | | |
| Integration of HDL Logic inside SystemVerilog UVM based Verification IP | Aleksandra Panajotu | | | | | |
| Integration of HDL Logic inside SystemVerilog UVM based Verification IP | Aleksandra Panajotu | | | | | |
| Interface Centric UVM Acceleration for Rapid SOC Verification | Jiwoong Kim, Yoona Lhim, Hyungjin Park, Hyunsun Ahn, and Seonil Brian Choi | | | | | |
| Interfacing Python with a Systemverilog Test Bench | Lakshay Grover and Kaushal Modi | | | | | |
| Interoperability Validation Without Direct Integration | Nicholas Nuti, Srinivasan Jambulingam | | | | | |
| Interoperability Validation Without Direct Integration | N. Nuti, S. Jambulingam | | | | | |
| INTERPRETING UPF FOR A MIXED-SIGNAL DESIGN UNDER TEST | Kenneth Bakalar and Eric Jeandeau | | | | | |
| Interpreting UPF for aMixed‐Signal Design Under Test | | | | | | |
| Introducing your team to an IDE | S. Dawson and M. Ballance | | | | | |
| Introduction to the 5 Levels of RISC-V Processor Verification | Simon Davidmann and Lee Moore | | | | | |
| Introspection Into Systemverilog Without Turning It Inside Out | Dave Rich | | | | | |
| INTROSPECTION INTO SYSTEMVERILOG WITHOUT TURNING IT INSIDE OUT. | Dave Rich | 2016 | Paper | | y2016 | paper |
| IP Security Assurance Workshop: Introduction | Mike Borza, Ambar Sarkar, Adam Sherer, and Brent Sherman (in spirit) | | | | | |
| IP-XACT based SoC Interconnect Verification Automation | YoungRae Cho, YoungSik Kim, and Seonil Brian Choi | | | | | |
| IP-XACT based SoC Interconnect Verification Automation | YoungRae Cho, YoungSik Kim, and Seonil Brian Choi | | | | | |
| IP-XACT Tutorial | Richard Weber, Anupam Bakshi | | | | | |
| IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 90 minutes! | Nikita Gulliya, Neena Chandawale, and Anupam Bakshi | | | | | |
| Ironic But Effective: How Formal Analysis Can Perfect Your Simulation Constraints | Penny Yang, Jin Hou, Yuya Kao, Nan-Sheng Huang, Ping Yeung, and Joe Hupcey | | | | | |
| Ironic But Effective: How Formal Analysis Can Perfect Your Simulation Constraints | Penny Yang, Jin Hou, Yuya Kao, Nan-Sheng Huang, Ping Yeung, and Joe Hupcey | | | | | |
| Is It a Software Bug? Is It a Hardware Bug? | Horace Chan, Mame Maria Mbaye, and Sim Ang | 2022 | Paper | | y2022 | paper |
| Is It a Software Bug? It Is a Hardware Bug? | Horace Chan, Maria Mbaye, and Sim Ang | 2022 | Presentation | | y2022 | presentation |
| Is Power State Table (PST) Golden? | Ankush Bagotra, Neha Bajaj, and Harsha Vardhan | | | | | |
| Is Power State Table Golden? | Harsha Vardhan, Ankush Bagotra, and Neha Bajaj | | | | | |
| Is Specman Still Relevant? Using UVM-ML to Take Advantage of Multiple Verification Languages | Timothy Pertuit, David Lacey, and Doug Gibson | | | | | |
| Is Specman Still Relevant? Using UVM-ML to Take Advantage of Multiple Verification Languages | Timothy Pertuit, Doug Gibson, and David Lacey | | | | | |
| Is the simulator behavior wrong for my SystemVerilog code? | Weihua Han | | | | | |
| Is The Simulator Behavior Wrong With My SystemVerilog Code | Weihua Han | | | | | |
| Is Your Hardware Dependable? | DARPA, AMD, Arm Research, and Synopsys | | | | | |
| Is your Power Aware design really x-aware? | Durgesh Prasad and Jitesh Bansal | | | | | |
| Is your Power Aware design really x-aware? | Durgesh Prasad and Jitesh Bansal | | | | | |
| Is Your System’s Security preserved? Verification of Security IP integration | Predrag Nikolic | | | | | |
| Is Your System’s Security preserved? Verification of Security IP integration | Predrag Nikolic | | | | | |
| ISO 26262 Dependent Failure Analysis using PSS | Moonki Jang, Jiwoong Kim, and Dongjoo Kim | | | | | |
| ISO 26262 Dependent Failure Analysis Using PSS | Moonki Jang | | | | | |
| It Should Just Work! Tips and Tricks for Creating Flexible, Vendor Agnostic Analog Behavioral Models | Chuck McClish | | | | | |
| It’s Not Too Late to Adopt: The Full Power of UVM | Kathleen Wittmann | | | | | |
| It’s Been 24 Hours –Should I Kill My Formal Run? | Mark Eslinger, Jin Hou, Joe Hupcey III, and Jeremy Levitt | | | | | |
| It’s Not Too Late to Adopt: The Full Power of UVM | Kathleen Wittmann | | | | | |
| JESD204B Deterministic Latency Verification with UVM Constrained Random Approaches | Girish Nadiger and Ashok Chandran | | | | | |
| JESD204B Deterministic Latency Verification with UVM Constrained Random Approaches | Girish Nadiger and Ashok Chandran | | | | | |
| Jump start your RISCV project with OpenHW | Mike Thompson, Jingliang (Leo) Wang, Steve Richmond, Lee Moore, David McConnell, Greg Tumbush | | | | | |
| Jump-Start Portable Stimulus Test Creation with SystemVerilog Reuse | Matthew Ballance | | | | | |
| Jump-Start Portable Stimulus Test Creation with SystemVerilog Reuse | Matthew Ballance | | | | | |
| Jump-Start Software-Driven Hardware Verification with a Verification Framework | Matthew Ballance | | | | | |
| Jump-Start Software-Driven Hardware Verification with a Verification Framework | Matthew Ballance | | | | | |
| Just do it! Who cares if a Structural Analysis tool is using Formal Verification | Scott Aron Bloom | | | | | |
| Keeping Score, Part 1 of 2 – Architectural Considerations for Scoreboard Design | Gordon Allan | | | | | |
| Keeping Up with Chip — the Proposed SystemVerilog 2012 Standard Makes Verifying Ever-increasing Design Complexity More Efficient | Stuart Sutherland and Tom Fitzpatrick | | | | | |
| Keeping Up with Chip — the Proposed SystemVerilog 2012 Standard Makes Verifying Ever-increasing Design Complexity More Efficient | Stuart Sutherland | | | | | |
| Keeping Your Sequences Relevant | Nicholas Zicha and Eric Combes | | | | | |
| Key Gochas in implementing CDC for various Bus Protocols | Nikita Gulliya, Mukesh Kumar Singh, and Abhishek Bora | | | | | |
| Key Gochas in implementing CDC for various Bus Protocols | Nikita Gulliya, Mukesh Kumar Singh, and Abhishek Bora | | | | | |
| Large Language Model for Verification: A Review and Its Application in Data Augmentation | Dan Yu, Eman El Mandouh, Waseem Raslan, Harry Foster, Tom Fitzpatrick | | | | | |
| Large Language Model for Verification: A Review and Its Application in Data Augmentation | Dan Yu, Eman El Mandouh, Waseem Raslan, Harry Foster, Tom Fitzpatrick | | | | | |
| Large Language Models to generate SystemC Model Code | Shravan Belagalmath, Sandeep Pendharkar, Karthick Gururaj, Santhosh Selvin | | | | | |
| Lay it On Me: Creating Layered Constraints | Bryan Morris | | | | | |
| Leaping Left: Seamless IP to SoC Hand off | Swetha Thiagarajan, Rashika Madan, Hiran Morar, and Sangeivi Sivagnanasundaram | | | | | |
| Leaping Left: Seamless IP to SoC Hand-off | Swetha Thiagarajan, Rashika Madan, Hiran Morar, and Sangeivi Sivagnanasundaram | | | | | |
| Learning From Advanced Hardware Verification for Hardware Dependent Software | Simond Davidmann and Duncan Graham | | | | | |
| Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges | Kotha Kavya and Sinha Rohit Kumar | | | | | |
| Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges | Rohit Kumar Sinha and Kavya Kotha | | | | | |
| Lessons from the field – IP/SoC integration techniques that work | David Murray and Sean Boylan | 2013 | Paper | | y2013 | paper |
| Lessons from the field IP/SoC integration techniques that work | David Murray | | | | | |
| Let’s be Formal While Talking About Verification Quality: A Novel Approach to Qualify Assertion Based VIPs | Sachin Scaria, Surinder Sood, and Erik Seligman | | | | | |
| Let’s DisCOVER Power States | Pankaj Kumar Dwivedi, Amit Srivastava, and Veeresh Vikram Singh | | | | | |
| Lets be Formal While Talking About Verification Quality: A Novel Approach Of Qualifying Assertion Based IPs | Surinder Sood, Sachin Scaria, and Erik Seligman | | | | | |
| Lets disCOVER Power States | Pankaj Kumar Dwivedi, Amit Srivastava, and Veeresh Vikram Singh | | | | | |
| Leveraging Formal to Verify SoC Register Map | Abdul Elaydi and Jose Barandiaran | | | | | |
| Leveraging Formal to Verify SoC Register Map | Abdul Elaydi and Jose Barandiaran | 2014 | Paper | | y2014 | paper |
| Leveraging Functional Safety Methodologies to Enhance Design Quality in Automotive IC | Gulshan Kumar Sharma, Sougata Bhattacharjee, James Kim, Wonil Cho, Akshaya Jain, Andrey Likhopoy, Arun Gogineni, Ann Keffer, Sangkyu Park, Hyeonuk Noh | | | | | |
| Leveraging Interface Class to Improve UVM TLM | N Goyal, J Refice | | | | | |
| Leveraging Interface Classes to Improve UVM TLM | N. Goyal, J. Refice | | | | | |
| Leveraging IP-XACT standardized IP interfaces for rapid IP integration | David Murray and Simon Rance | | | | | |
| Leveraging IP-XACT Standardized IP Interfaces for Rapid IP Integration | David Murray | | | | | |
| Leveraging Model Based Verification for Automotive SoC Development | Aswini Kumar Tata, Sanjay Chatterjee, Kamel Belhous, Surekha Kollepara, Bhanu Singh, Eric Cigan | | | | | |
| Leveraging Model Based Verification for Automotive SoC Development | Aswini Kumar Tata, Bhanu Singh, Sanjay Chatterjee, Eric Cigan, Kamel Belhous, Surekha Kollepara | | | | | |
| Leveraging more from GLS: Using metric driven GLS stimuli to boost timing verification | Sowmya Ega, Richardson Jeyapaul, and Kunal Jani | | | | | |
| Leveraging more from GLS: Using metric driven GLS stimuli to boost Timing Verification | Sowmya Ega, Richardson Jeyapaul, and Kunal Jani | | | | | |
| Leveraging Several Functional Safety Methodologies (Full Faults and SRF) to Enhance Design Quality in Automotive IC | Gulshan Kumar Sharma, Sougata Bhattacharjee, Wonil Cho, Akshaya Kumar Jain, James Kim, Sangkyu Park, Hyeonuk Noh, Andrey Likhopoy, Ann Keffer, Arun Gogineni | | | | | |
| Leveraging UVM-based Low Power Package Library to SOC Designs | Shikhadevi Katheriya, Avnita Pal, Puranapanda Sastry | | | | | |
| Leveraging UVM-based Low Power Package Library to SOC Designs | Shikhadevi Katheriya, Avnita Pal, Puranapanda Sastry | | | | | |
| Leveraging Virtual Platform ESL and TLM SystemVerification in RTL using UVM | Ashok Mehta, Albert Chiang, and Wei-Hua Han | | | | | |
| Lies, Damned Lies, and Coverage | Mark Litterick | | | | | |
| Lies, Damned Lies, and Coverage | Mark Litterick | | | | | |
| Liveness Assume-Guarantee Proof Schema: A step towards Liveness Full Proofs | Nitish Sharma, Venkata Nishanth Narisetty | | | | | |
| Low Power Apps (Shaping the Future of Low Power Verification) | Awashesh Kumar, Madhur Bhargava, Vinay Kumar Singh, and Pankaj Gairola | | | | | |
| Low Power Apps: Shaping the Future of Low Power Verification | Awashesh Kumar, Madhur Bhargava, Vinay Singh, and Pankaj Gairola | | | | | |
| Low Power Coverage: The Missing Piece in Dynamic Simulation | Progyna Khondkar, Gabriel Chidolue, and Ping Yeung | | | | | |
| Low Power Coverage: The Missing Piece in Dynamic Simulation | Progyna Khondkar | | | | | |
| Low Power SoC Verification: IP Reuse and Hierarchical Composition using UPF | Amit Srivastava, Rudra Mukherjee, Erich Marschner, and Chuck Seeley | | | | | |
| Low Power SoC Verification: IP Reuse and Hierarchical Composition using UPF | Amit Srivastava, Rudra Mukherjee, Erich Marschner, and Chuck Seeley | | | | | |
| Low Power Static Verification- Beyond Linting and Corruption Semantics | Kaustav Guha , Ankush Bagotra, and Neha Bajaj | | | | | |
| Low Power Verification with LDO | Shang-Wei Tu and Amol Herlekar | | | | | |
| Low Power Verification With LDO | Shang-Wei Tu, Amol Herlekar, and Yu-Juei Chen | | | | | |
| Low Power Verification with UPF: Principle and Practice | Jianfeng Liu, Mi-Sook Hong, Bong Hyun Lee JungYun Choi, HyoSig Won, Kyu-Myung Choi, Harsha Vardhan, and Aditya Kher | | | | | |
| Low-Power Verification at Gate Level for Zen Microprocessor Core | Baosheng Wang, Keerthi Mullangi, Raluca Stan, and Diana Irimia | | | | | |
| Low-Power Verification Automation – A Practical Approach | Shaji Kunjumohamed and Hendy Kosasih | | | | | |
| LOW-POWER VERIFICATION AUTOMATION: A PRACTICAL APPROACH | Shaji K. Kunjumohamed and Hendy Kosasih | | | | | |
| Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design Verification | Honghuang Lin, Zhipeng Ye, and Asad Khan | | | | | |
| Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design Verification | H. Lin, Z. Ye, and A. M. Khan | | | | | |
| Machine Learning Based Verification Planning Methodology Using Design and Verification Data | Hanna Jang, Seonghee Yim | | | | | |
| Machine Learning Based Verification Planning Methodology Using Design and Verification Data | Hanna Jang, Seonghee Yim, Sunchang Choi, and Seonil Brian Choi | | | | | |
| Machine Learning Driven Verification A Step Function in Productivity and Throughput | Daniel Hansson, John Rose, and Matt Graham | | | | | |
| Machine Learning-Guided Stimulus Generation for Functional Verification | S. Gogri, J. Hu, A. Tyagi, M. Quinn S. Ramachandran, F. Batool, and A. Jagadeesh | | | | | |
| Machine Learning-Guided Stimulus Generation for Functional Verification | Saumil Gogri, Jiang Hu, Aakash Tyagi, Mike Quinn, Swati Ramachandran, Fazia Batool, and Amrutha Jagadeesh | | | | | |
| Making Autonomous Cars Safer – One chip at a time | Apurva Kalia and Ann Keffer | | | | | |
| Making Formal Property Verification Mainstream: An Intel Graphics Experience | M Achutha KiranKumar V, Erik Seligman, Aarti Gupta, Ss Bindumadhava, and Abhijith Bharadwaj | | | | | |
| Making Formal Property Verification Mainstream: An Intel® Graphics Experience | M Achutha Kiran, Kumar V., Erik Seligman, Aarti Gupta, Bindumadhava S. S., and Abhijith A. Bharadwaj | | | | | |
| Making Legacy Portable with the Portable Stimulus Specification | Matthew Ballance | | | | | |
| Making Legacy Portable with the Portable Stimulus Specification | Matthew Ballance | | | | | |
| Making RAL Jump, an Introspection | Jeremy Ridgeway, Karishma Dhruv, and Manmohan Singh | | | | | |
| Making RAL Jump, an Introspection | Jeremy Ridgeway, Karishma Dhruv, and Manmohan Singh | | | | | |
| Making Security Verification “SECURE” | NAGESH RANGANATH and SUBIN THYKKOOTTATHIL | | | | | |
| Making Security Verification “SECURE” | Subin Thykkoottathil and Nagesh Ranganath | | | | | |
| Making Your DPI-C Interface a Fast River of Data | Rich Edelman | | | | | |
| MANAGING AND AUTOMATING HW/SW TESTS FROM IP TO SOC | Matthew Ballance | | | | | |
| Managing and Automating Hw/Sw Tests from IP to SoC | Matthew Ballance | | | | | |
| Managing Highly Configurable Design and Verification | Jeremy Ridgeway | | | | | |
| Managing Highly Configurable Design and Verification | J. Ridgeway | | | | | |
| Marrying Simulation and Formal Made Easier! | Lun Li, Durga Rangarajan, Christopher Starr, and James Greene | | | | | |
| Matrix Math package for VHDL | David W. Bishop | | | | | |
| Matrix Math package for VHDL | David W. Bishop | | | | | |
| Maximize Vertical Reuse, Building Module to System Verification Environments with UVM e | Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss | | | | | |
| Maximize Vertical Reuse, Building Module to System Verification Environments with UVMe | Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss | | | | | |
| Maximizing Formal ROI through Accelerated IP Verification Sign-off | Scott Peverelle, Hao Chen, Kamakshi Sarat Vallabhapurapu, Rosanna Yee, Hee Chul Kim, Johann Te, and Jacob Hotz | 2022 | Presentation | | y2022 | presentation |
| Maximizing Formal ROI through Accelerated IP Verification Sign-off | Hao Chen, Kamakshi Sarat Vallabhapurapu, Scott Peverelle, Rosanna Yee, Hee Chul Kim, Johann Te, and Jacob Hotz | | | | | |
| May the powers be with you! – Unleashing powerful new features in UPF IEEE 1801 | Srinivasan Venkataramanan and Ajeetha Kumari | | | | | |
| Mechanism to Generate FIFO VC Dependency Graph and Its Application to System Level Deadlock Verification | Debarshi Chatterjee, Chad Parsons, Siddhanth Dhodhi | | | | | |
| Media Performance Validation in Emulation and Post Silicon Using Portable Stimulus Standard | Suresh Vasu, Nithin Venkatesh, Joydeep Maitra | | | | | |
| Melioration of Enhanced Low Power Memory Retention and Low Power Feature Validation Using API’s | Nithin Venkatesh, Akula Hareesh | | | | | |
| Melting Verification Pot: Integrating RVM/VMM and UVM, a Practical Guide and Lessons Learned. | Mark A. Azadpour | | | | | |
| Melting Verification Pot: Integrating RVM/VMM and UVM, a Practical Guide and Lessons Learned. | Mark Azadpour | | | | | |
| Memory Debugging of Virtual Platforms | George F. Frazier, Neeti Bhatnagar, Qizhang Chao, and Kathy Lang | | | | | |
| Memory Debugging of Virtual Prototypes with TLM 2.0 | George F. Frazier, Qizhang Chao, Neeti Bhatnagar, and Kathy Lang | | | | | |
| Memory Subsystem Verification – Can it be taken for granted? | Shivani Upasani | | | | | |
| Memory Subsystem Verification: Can it be taken for granted? | Shivani Upasani and Prashanth Srinivasa | | | | | |
| Meta Design Framework | Sanjeev Singh and Jonathan Sadowsky | | | | | |
| Meta Design Framework: Building Designs Programmatically | Sanjeev Singh and Jonathan Sadowsky | | | | | |
| Metadata Based Testbench Generation | Daeseo Cha, Soonoh Kwon, and Ahhyung Shin | | | | | |
| Metadata Based Testbench Generation Automation | Daeseo Cha, Soonoh Kwon, Ahhyung Shin, Youngnam Youn, Youngsik Kim, and Seonil Brian Choi | | | | | |
| Method for Generating Unique Coverage Classes to Enable Meaningful Covergroup Merges Across Testbenches | Eldon Nelson, MS, PE | | | | | |
| Method for Generating Unique Coverage Classes to Enable Meaningful Covergroup Merges Across Testbenches | Eldon Nelson, M.S., P.E. | | | | | |
| Methodology for automating coverage-driven interrupt testing of instruction sets | David McConnell, Greg Tumbush | | | | | |
| Methodology for Separation of Design Concerns Using Conservative RTL Flipflop Inference | Maya H. Safieddine, Fadi A. Zaraket, and Rouwaida Kanj | | | | | |
| Methodology for Separation of Design Concerns Using Conservative RTL Flipflop Inference | Maya H. Safieddine, Fadi A. Zaraket, and Rouwaida Kanj | | | | | |
| Metric Driven Microcode Verification: Navigating Microcode Coverage Complexities | Seungyeon Yu, Damin Son, Tony Gladvin George, Kihyun Park, Dongkun An, Wooseong Cheong, ByungChul Yoo | | | | | |
| Metric Driven Microcode Verification: Navigating Microcode Coverage Complexities | Seungyeon Yu, Damin Son, Tony Gladvin George, Kihyun Park, Dongkun An, Wooseong Cheong, ByungChul Yoo | | | | | |
| Metric Driven Mixed-Signal Verification Methodology and Practices for Complex Mixed-signal ASSPs | Frank Yang, Andy Sha, Morton Zhao, and Yanping Sha | | | | | |
| Metric Driven Mixed-Signal Verification Methodology and Practices for Complex Mixed-signal ASSPs | Frank Yang, Andy Sha, Morton Zhao, and Yanping Sha | | | | | |
| Metric Driven Verification of Mixed-Signal Designs | Neyaz Khan, Yaron Kashai, and Hao Fang | | | | | |
| Metrics Driven Sign-off for SoC Specific Logic (SSL) Using Formal Techniques | Abhinav Gaur, Gaurav Jain, Ruchi Singh | | | | | |
| Metrics in SoC Verification | Andreas Meyer and Harry Foster | | | | | |
| Micro-processor verification using a C++11 sequence-based stimulus engine. | Stephan Bourduas and Chris Mikulis | | | | | |
| Micro-processor verification using a C++11 sequence-based stimulus engine. | Stephan Bourduas and Chris Mikulis | | | | | |
| Migrating from OVM to UVM The Definitive Guide | Adiel Khan | | | | | |
| Migrating from UVM to UVM-AMS | Tom Fitzpatrick, Abhijit Madhu Kumar | | | | | |
| Migrating to UVM : Conquering Legacy | Santosh Sarma, Amit Sharma, and Adiel Khan | | | | | |
| Mind the Gap(s): Creating & Closing Gaps Between Design and Verification | Chris Giles and Kurt Takara | | | | | |
| Mining Coverage Data for Test Set Coverage Efficiency | Monica Farkash, Bryan Hickerson, Mike Behm, and Balavinayagam Samynathan | | | | | |
| Mining Coverage Data for Test Set Coverage Efficiency | Bryan Hickerson, Mike Behm, Balavinayagam Samynathan, and Monica Farkash | | | | | |
| Mixed Signal Assertion-Based Verification | Prabal Bhattacharya, Don O’Riordan, and Walter Hartong | | | | | |
| Mixed Signal Design Verification: Leveraging the Best of AMS and DMS | Rock Z. Shi, Padmashree Bhinge, Preston Birdsong, Geeta Chaitanya, and Kunal Jani | | | | | |
| Mixed Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP Simulation | S. Do, J. Park, D. Kim, and J. Jang | | | | | |
| Mixed Signal Verification of a Voltage Regulator using a State Space Approach and the SV-DC extensions | Rajat Mitra | | | | | |
| Mixed Signal Verification of Dynamic Adaptive Power Management in Low Power SoC | Neyaz Khan | | | | | |
| Mixed Signal Verification of UPF based designs A Practical Example | Andrew Milne and Damian Roberts | | | | | |
| Mixed Signal Verification of UPF based designs A Practical Example | Andrew Milne and Damian Roberts | | | | | |
| Mixed-abstraction Modeling Approach with Fault Injection for Hardware-Firmware Co-design and Functional Co-verification of an Automotive Airbag System on Chip Product | Thang Nguyen, Dipl.-Ing.-Dr. and Dieter Haerle, Dipl.-Ing. | | | | | |
| Mixed-abstraction Modeling Approach with Fault Injection for Hardware-Firmware Co-design and Functional Co-verification of an Automotive Airbag System on Chip Product | Dipl.-Ing. Dr.-techn. Thang Nguyen, Dipl.-Ing. and Dieter Haerle | | | | | |
| Mixed-Signal Design Verification: Leveraging the Best of AMS and DMS | Rock Z. Shi, Padmashree Bhinge, Preston Birdsong, Geeta Chaitanya, and Kunal Jani | | | | | |
| Mixed-Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP Simulation | S. Do, J. Park, D. Kim, and J. Jang | | | | | |
| Mixed-Signal Systems-on-Chip Design Verification With Automatic Real-Number Abstraction | Nancy Qiu, Frank Yang, and Himadri De | | | | | |
| Mixed-Signal Verification Methodology to Verify Type-C USB | Varun R, Vinayak Hegde, and Somasunder Kattepura Sreenath | | | | | |
| Mixed-Signal Verification Methodology to Verify USB Type-C | Varun R, Vinayak Hegde ans Somasunder Kattepura Sreenath | | | | | |
| ML-Based Verification and Regression Automation | Abhishek Chauhan, Asif Ahmad | | | | | |
| mL: Shrinking the Verification volume using Machine Learning | Yash Phogat, Patrick Hamilton | | | | | |
| mL: Shrinking the Verification volume using Machine Learning | Yash Phogat, Patrick Hamilton | | | | | |
| mL: Shrinking the Verification volume using Machine Learning | Yash Phogat, Patrick Hamilton | | | | | |
| Modeling a Hierarchical Register Scheme with UVM | Joshua Hardy | | | | | |
| Modeling a Hierarchical Register Scheme with UVM | Joshua Hardy | | | | | |
| Modeling Analog Devices Using SV-RNM | Mariam Maurice | | | | | |
| Modeling Analog Devices using SV-RNM | Mariam Maurice | | | | | |
| Modeling Analog Systems Using Full Digital Simulations (A State Space Approach) | Rajat K Mitra | | | | | |
| Modeling Memory Coherency During Concurrent/Simultaneous Accesses | Subramoni Parameswaran | | | | | |
| Modeling Memory Coherency for concurrent/parallel accesses | Subramoni Parameswaran | | | | | |
| Modeling Memory Coherency for Concurrent/Parallel Accesses | Subramoni Parameswaran | | | | | |
| Molding Functional Coverage for Highly Configurable IP | J. Ridgeway, K. Chaturvedula, and K. Dhruv | | | | | |
| Molding Functional Coverage for Highly Configurable IP | Jeremy Ridgeway, Kavitha Chaturvedula, and Karishma Dhruv | | | | | |
| Monitors, Monitors Everywhere – Who Is Monitoring the Monitors | Rich Edelman and Raghu Ardeishar | | | | | |
| Monitors, Monitors Everywhere … | Rich Edelman and Raghu Ardeishar | | | | | |
| Moving beyond Assertions: An Innovative approach to Low-Power Checking using UPF Tcl Apps | Madhur Bhargava | | | | | |
| MS-SoC Best Practices – Advanced Modeling & Verification Techniques for first-pass success | Neyaz Khan, Greg Glennon, and Dan Romaine | | | | | |
| Multi-Domain Verification: When Clock, Power and Reset Domains Collide | Ping Yeung, Erich Marschner, and Kaowen Liu | | | | | |
| Multi-Domain Verification: When Clock, Power and Reset Domains Collide | Ping Yeung, Erich Marschner, and Kaowen Liu | | | | | |
| Multi-Language Verification: Solutions for Real World Problems | Bryan Sniderman and Vitaly Yankelevich | | | | | |
| Multi-Language Verification: Solutions for Real World Problems | Bryan Sniderman and Vitaly Yankelevich | | | | | |
| Multimedia IP DMA verification platform | Suhyung Kim, Sangkyu Park, Myungwoo Seo, Sangjin Lee, and Jiyeon Park | | | | | |
| Multimedia IP DMA verification platform | Suhyung Kim, Sangkyu Park, Myungwoo Seo, Sangjin Lee, and Jiyeon Park | | | | | |
| Multiplier-Adder-Converter Linear Piecewise Approximation for Low Power Graphics Applications | Dina M. Ellaithy, Magdy A. El-Moursy, Amal Zaki, and Abdelhalim Zekry | | | | | |
| Multithreading a UVM Testbench for Faster Simulation | Benjamin Applequist, Vijayakrishnan Rousseau, Andrew Tan, and Jayasrinivas Sesham | | | | | |
| My Testbench Used to Break! Now it Bends (Adapting to Changing Design Configurations) | Jeff Vance, Jeff Montesano, Kevin Vasconcellos, and Kevin Johnston | | | | | |
| My Testbench Used to Break! Now it Bends: Adapting to Changing Design Configurations | Jeff Vance, Jeff Montesano, Kevin Vasconcellos, and Kevin Johnston | | | | | |
| Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage Modeling | Jason Sprott, Paul Marriott, and Matt Graham | | | | | |
| Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage Modeling | Jason Sprott, Paul Marriott, and Matt Graham | | | | | |
| Never Too Late With Formal: Stepwise Guide for Applying Formal Verification in Post-Silicon Phase to Avoid Re-Spins | Anshul Jain, Aarti Gupta, Achutha KiranKumar V M, Bindumadhava Ss, Shivakumar S Kolar, and Siva Gadey NV | | | | | |
| Never Too Late with Formal: Stepwise Guide for Applying FV in Post Si Phase to Avoid Re-Spins | Anshul Jain, Aarti Gupta, Achutha KiranKumar V M, Bindumadhava Ss, Shivakumar S Kolar, Siva Gadey NV | | | | | |
| New and active ways to bind to your design | Kaiming Ho | | | | | |
| New and Active Ways to Bind to Your Designs | Kaiming Ho | | | | | |
| New Challenges in Verification of Mixed-Signal IP and SoC Design | Luke Lang and Christina Chu | | | | | |
| New Constrained Random and Metric-Driven Verification Methodology using Python | Marek Cieplucha and Witold A. Pleskacz | | | | | |
| New Constrained Random and Metric-Driven Verification Methodology using Python | Marek Ciepłucha and Witold Pleskacz | | | | | |
| New Innovative Way to Verify Package Connectivity | Mike Walsh, Jin Hou | | | | | |
| New Innovative Way to Verify Package Connectivity | Mike Walsh, Jin Hou | | | | | |
| Next Frontier in Formal Verification | Ping Yeung, Rajesh Rathi, Vaibhav Kumar, Puneet Anand, Ravindra Aneja | | | | | |
| Next Gen System Design and Verification for Transportation | David Aerne, Jacob Wiltgen, and Richard Pugh | | | | | |
| Next Generation Verification for the Era of AI/ML and 5G | Frank Schirrmeister, Pete Hardee, Larry Melling, Amit Dua, and Moshik Rubin | | | | | |
| Next-Generation Formal Property Verification: Lightweight Theorem Proving Integrated into Model Checking | Erik Seligman, Karthik Baddam, Barbara Leite Almeida, Thamara Andrade, Poliana Bueno, Carla Ferreira, Matheus Fonesca, Lars Lundgren, Raquel, Lara dos Santos Pereira, Fabiano Peixoto, Vincent Reynolds | | | | | |
| Next-Generation Formal Property Verification: Lightweight Theorem Proving Integrated into Model Checking | Erik Seligman, Karthik Baddam, Barbara Leite Almeida, Thamara Andrade, Poliana Bueno, Carla Ferreira, Matheus Fonesca, Lars Lundgren, Raquel Lara dos Santos Pereira, Fabiano Peixoto, Vincent Reynolds | | | | | |
| Next-generation Power Aware CDC Verification – What have we learned? | Kurt Takara, Chris Kwok, Naman Jain, and Ashish Hari | | | | | |
| Next-generation Power Aware CDC Verification What have we learned? | Kurt Takara, Chris Kwok, Naman Jain, and Ashish Hari | | | | | |
| No RTL Yet? No Problem UVM Testing a SystemVerilog Fabric Model | Rich Edelman | | | | | |
| No RTL Yet? No Problem UVM Testing a SystemVerilog Fabric Model | Rich Edelman | | | | | |
| Not Just for Hardware Debug: Prototype Debuggers for System Validation and Optimization | Michael Sachtjen and Joe Gaubatz | | | | | |
| NOT JUST FOR HARDWARE DEBUG: PROTOTYPE DEBUGGERS FOR SYSTEM VALIDATION AND OPTIMIZATION | Michael Sachtjen and Joe Gaubatz | | | | | |
| Novel Approach to ASIC Prototyping | Mohamed Saheel, Suresh Balasubramanian, and Vijayakrishnan Rousseau | | | | | |
| Novel Approach to Automate Design Verification Cycle Using Continuous Integration-Continuous Deployment Platform | Juilly Sunilrao Videkar, Sri Harsha Reddy Kaliki, Shaik Babjan Sohail, Kannusamy Mariappan | | | | | |
| Novel Approaches for C vs. RTL Formal Verification of Vertex Attribute Address Generator Unit | Nianchen Wu, Christopher Starr, and Xiushan Feng | | | | | |
| Novel GUI Based UVM Test Bench Template Builder | Vignesh Manoharan | | | | | |
| Novel GUI Based UVM Test Bench Template Builder | Vignesh Manoharan | | | | | |
| Novel Method To Speed-Up UVM Testbench Development | Nimay Shah, Prashant Ravindra, Barry Briscoe, Miguel Castillo | | | | | |
| Novel Method To Speed-Up UVM Testbench Development | Prashantkumar Ravindra, Barry Briscoe, Miguel Castillo, Nimay Shah | | | | | |
| Novel Mixed Signal Verification Methodology Using Complex UDNs | Rakesh Dama, Ravi Reddy, and Andy Vitek | | | | | |
| Novel Mixed Signal Verification Methodology using complex UDNs | Rakesh Dama, Ravi Reddy, and Andy Vitek | 2019 | Paper | | y2019 | paper |
| Novel Paradigm in Formally Verifying Complex Algorithms | M Achutha KiranKumar V, Disha Puri, Mohit Choradia, Paras Gupta | | | | | |
| Novel Test Case Design Techniques for Logical Specifications of Safety Critical Systems Software in Aerial Vehicle | Lakshmi KVNS and Sanjeev Kumar | | | | | |
| Novel Verification Techniques for ARM A15 Multi-core Subsystem Using IEEE 1647 | Vaibhav Mahimkar, Akshit Dayal, Tomas Huynh, Van Huynh, and Erwin Hermanto. | | | | | |
| Novel Verification Techniques for ARM A15 Multi-core Subsystem Using IEEE 1647 | Vaibhav Mahimkar, Akshit Dayal, Tomas Huynh, Van Huynh, and Erwin Hermanto | | | | | |
| Novelty-Driven Verification: Using Machine Learning to Identify Novel Stimuli and Close Coverage | Tim Blackmore, Rhys Hodson, Sebastian Schaal | | | | | |
| NVMe Development and Debug for a 16 x Multicore System | Soummya Mallick, Raj Mathur, Arindam Guha, and Frank Schirrmeister | | | | | |
| Of Camels and Committees | Tom Fitzpatrick and Dave Rich | | | | | |
| Of Camels and Committees: Standardization Should Enable Innovation, Not Strangle It | Tom Fitzpatrick and Dave Rich | | | | | |
| Off To The Races With Your Accelerated SystemVerilog Testbench (A Methodology for Hardware-Assisted Acceleration of SystemVerilog Testbenches) | Hans van der Schoot, Anoop Saha, Ankit Garg, and Krishnamurthy Suresh | | | | | |
| On Analysis of RDC issues for identifying reset tree design bugs and further strategies for noise | Farhad Ahmed, Lyle Benson, Manish Bhati | | | | | |
| On analysis of RDC issues for identifying reset tree design bugs and further strategies for noise reduction | Farhad Ahmed, Lyle Benson, Manish Bhati | | | | | |
| On Verification Coverage Metrics in Formal Verification and Speeding Verification Closure with UCIS Coverage Interoperability Standard | Rajeev Ranjan, PhD, Ross Weber, and Ziyad Hanna, PhD | | | | | |
| One Compile to Rule Them All: An Elegant Solution for OVM/UVM Testbench Topologies | Galen Blake and Steve Chappell | | | | | |
| One Compile to Rule them All: An elegant solution for OVM/UVM Testbench Topologies | Galen Blake and Steve Chappell | | | | | |
| One Stop Solution for DFT Register Modelling in UVM | Rui Huang | | | | | |
| One Stop Solution of DFT Register Modelling in UVM | Rui Huang | | | | | |
| Open-source Framework for Co-emulation using PYNQ | Ioana-Cătălina Cristea, Dragoș Dospinescu | | | | | |
| Optimal Usage of the Computer Farm for Regression Testing | Daniel Hansson and Patrik Granath | | | | | |
| Optimal Usage of the Computer Farm for Regression Testing | Daniel Hansson and Patrik Granath | | | | | |
| Optimizing Area and Power Using Formal Method | Alan Carlin, Chris Komar Cadence, and Anuj Singhania | | | | | |
| Optimizing Random Test Constraints Using Machine Learning Algorithms | Stan Sokorac | | | | | |
| Optimizing Random Test Constraints Using Machine Learning Algorithms | Stan Sokorac | | | | | |
| Optimizing Turnaround Times In A CI Flow Using a Scheduler Implementation | Robert Strong | | | | | |
| Optimizing Turnaround Times in a Continuous Integration Flow Using a Scheduler Based Implementation | Robert Strong | | | | | |
| OS aware IP Development Methodology | Hyunjae Woo, Woojoo Kim, Youngsik Kim, and Seonil Brian Choi | | | | | |
| OS-aware IP Development Methodology | Hyunjae Woo, Woojoo Kim, Youngsik Kim, and Seonil Brian Choi | | | | | |
| OS-aware Performance and Power Analysis Methodology | Hyunjae Woo, HojinJo, Woojoo Kim, and Seonil Brian Choi | | | | | |
| Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath Scoreboards | Bochra El-Meray and Jörg Müller | | | | | |
| Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath Scoreboards | Bochra Elmaray and Joerg Mueller | | | | | |
| OVM & UVM Techniques for On-the-fly Reset | Muralidhara Ramalingaiah and Boobalan Anantharaman | | | | | |
| OVM & UVM Techniques for On-the-fly Reset | Muralidhara Ramalingaiah and Boobalan Anantharaman | | | | | |
| OVM & UVM Techniques for Terminating Tests | Clifford E. Cummings and Tom Fitzpatrick | | | | | |
| OVM TO UVM DEFINITIVE GUIDE PART 1 | Adiel Khan, Justin Refice, and Warren Stapleton | | | | | |
| PA-APIs: Looking beyond power intent specification formats | Amit Srivastava and Awashesh Kumar | | | | | |
| PA-APIs: Looking beyond power intent specification formats | Amit Srivastava and Awashesh Kumar | | | | | |
| Panning for Gold in RTL Using Transactions | Rich Edelman, Raghu Ardeishar, Akshay Sarup, and Suman Kasam | | | | | |
| Parallel Computing for Functional Verification and Compute Farms: The Holy Matrimony | Amit Sharma, Shekhar Basavanna, and Srinivasan Venkataramanan | | | | | |
| Parameter Passing From SystemVerilog to SystemC | Bishnupriya Bhattacharya, Samik Das, Zhiting Duan, Chandra Sekhar Katuri, and Pradipta Laha | | | | | |
| Parameter Passing from SystemVerilog to SystemC for Highly Configurable Mixed-Language Designs | Bishnupriya Bhattacharya, Samik Das, Zhiting Duan, Chandra Sekhar Katuri, and Pradipta Laha | | | | | |
| Parameterize Like a Pro: Handling Parameterized RTL in your UVM Testbench | Jeff Montesano | | | | | |
| Parameterized and Re-usable Jitter Model for Serial and Parallel Interfaces | Amlan Chakrabarti and Malathi Chikkanna | | | | | |
| Parameterized and Re-usable Jitter Model for Serial and Parallel Interfaces | Malathi Chikkanna and Amlan Chakrabarti | | | | | |
| Parameters and OVM — Can’t They Just Get Along? | Bryan Ramirez and Michael Horn | | | | | |
| Parameters, UVM, Coverage & Emulation – Take Two and Call Me in the Morning | Michael Horn, Bryan Ramirez, and Hans van der Schoot | | | | | |
| Path-based UPF Strategies: Optimally Manage Power on your Designs | Progyna Khondkar | | | | | |
| Path-Based UPF Strategies: Optimally Manage Power on Your Designs | Progyna Khondkar | | | | | |
| Pay Me Now or Pay Me Later Exploring the Implementation and Analysis Cost Trade-Offs of Coverage Model Design | Paul Graykowski and Andrew Piziali | | | | | |
| Plan & Metric Driven Mixed-Signal Verification for Medical Devices | Gregg Sarkinen | | | | | |
| Plugging the Holes: SystemC and VHDL Functional Coverage Methodology | Pankaj Singh and Gaurav Kumar Verma | | | | | |
| Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication bridge | Andrei Vintila and Ionut Tolea | | | | | |
| Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication bridge | Andrei Vintila and Ionut Tolea | | | | | |
| Portable Stimulus Models for C/SystemC, UVM and Emulation | Mike Andrews and Boris Hristov | | | | | |
| Portable Stimulus Models for C/SystemC, UVM and Emulation | Mike Andrews and Boris Hristov | | | | | |
| Portable Stimulus Standard Update: PSS in the Real World | Accellera Portable Stimulus Working Group | | | | | |
| Portable Stimulus Standard: The Promises and Pitfalls of Early Adoption | Mike Bartley | | | | | |
| Portable Stimulus Standard’s Hardware Software Interface (HSI) to validate 4G 5G Forward Error Correction Encoder/Decoder IP in Emulation Silicon | Joydeep Maitra, Suresh Vasu, Nithin Venkatesh, Suhas Reddy, Luis Campos, Vinit Shenoy | | | | | |
| Portable Stimulus Tutorial | Adnan Hamid, Tom Fitzpatrick, Matthew Ballance, Sergey Khaikin, Prabhat Gupta | | | | | |
| Portable Stimulus vs Formal vs UVM: A Comparative Analysis of Verification Methodologies Throughout the Life of an IP Block | Gaurav Bhatnagar | | | | | |
| Portable Stimulus vs Formal vs UVM: A Comparative Analysis of Verification Methodologies Throughout the Life of an IP Block | Gaurav Bhatnagar and David Brownell | | | | | |
| Portable Stimulus: What’s Coming in 1.1 and What it Means For You | Portable Stimulus Working Group | | | | | |
| Portable Test and Stimulus: The Next Level of Verification Productivity is Here | Accellera Portable Stimulus Working Group | | | | | |
| Post Silicon Performance Validation Using PSS | Dayoung Kim, Jaehun Lee, Daeseo Cha, Phu L. Huynh, and Jake Kim | | | | | |
| Post-Silicon Performance Validation Using PSS | Dayoung Kim, Jaehun Lee, and Daeseo Cha | | | | | |
| Power Aware CDC Analysis at Top Level Using SOC Abstract Flow | Venkatesh Ranga and Pramod Rajan K S | | | | | |
| Power Aware CDC Analysis at Top Level Using SOC Abstract Flow | Venkatesh Ranga and Pramod Rajan K S | | | | | |
| Power Aware Verification Strategy for SoCs | Boobalan Anantharaman and Arunkumar Narayanamurthy | | | | | |
| Power Aware Verification Strategy for SoCs | Boobalan Anantharaman and Arunkumar Narayanamurthy | | | | | |
| Power estimation – what to expect what not to expect | Prakash Parikh | | | | | |
| Power Estimation Techniques – what to expect, what not to expect | Prakash Parikh | | | | | |
| Power Management Verification for SOC ICs | David Akselrod, Alex Miretsky, Sergey Golubkov, Pearl Liu, Afshin Parvaresh, Shu Wang, and Feng Yan | | | | | |
| Power Management Verification for SoC ICs | David Akselrod, Alex Miretsky, Sergey Golubkov, Pearl Liu, Afshin Parvaresh, Shu Wang, and Feng Yan | | | | | |
| Power models & Terminal Boundary: Get your IP Ready for Low Power | Progyna K., William W., Phil G., Brandon S. | | | | | |
| Power Models and Terminal Boundary: Get your IP Ready for Low Power | Progyna Khondkar, William Winkeler, Phil Giangarra and Brandon Skaggs | | | | | |
| Power State to PST Conversion: Simplifying static analysis and debugging of power aware designs | Madhur Bhargava and Pankaj Gairola | | | | | |
| Power State to PST Conversion: Simplifying static analysis and debugging of power aware designs | Madhur Bhargava and Pankaj Gairola | | | | | |
| Practical Applications of the Portable Testing and Stimulus Standard (PSS) | Sharon Rosenberg | | | | | |
| Practical Approach Using a Formal App to Detect X-Optimism-Related RTL Bugs | Shuqing Zhao, Shan Yan, and Yafang Feng | | | | | |
| Practical Approach Using a Formal App to Detect X-Optimism-Related RTL Bugs | Shuqing Zhao, Shan Yan, and Yafang Feng | | | | | |
| Practical Asynchronous SystemVerilog Assertions | Doug Smith | | | | | |
| Practical Asynchronous SystemVerilog Assertions | Doug Smith | | | | | |
| Practical Considerations for Real Valued Modeling of High Performance Analog Systems | Dushyant Juneja, Siddharth Prabhu, and Syam Veluri | | | | | |
| Practical Considerations for Real Valued Modeling of High Performance Analog Systems | Dushyant Juneja, Siddharth Prabhu, and Syam Veluri | | | | | |
| Practical Considerations for Real Valued Modeling of High Performance Analog Systems | Dushyant Juneja, Siddharth Prabhu, and Syam Veluri | | | | | |
| Practical Considerations for Real Valued Modeling of High Performance Analog Systems | Dushyant Juneja, Siddharth Prabhu, and Syam Veluri | | | | | |
| Practical Issues in Implementing Fast and Accurate SystemC-Constructed Virtual Platform Simulation | Yu-Fu Yeh and Chung-Yang (Ric) Huang | | | | | |
| Practical Issues in Implementing Fast and Accurate SystemC-Constructed Virtual Platform Simulation | Yu-Fu Yeh and Chung-Yang (Ric) Huang | | | | | |
| Practical Scheme to Enhance Verification Turn-Around-Time by Using Reusable Harness Interface (RHI) | Jong pil Jung, Hyunju Lee, Jaejin Ha, and Yonghee Im | | | | | |
| Practical Scheme to Enhance Verification Turn-Around-Time by Using Reusable Harness Interface (RHI) | Jongpil Jung, Hyunju Lee, Jaejin Ha, and Yonghee Im | | | | | |
| Practical Schemes to Enhance Vertical, Horizontal and Platform Reusability of Verification Components in AMBA Based SoC Design | Ieryung Park, Nara Cho and Yonghee Im | | | | | |
| PRACTICAL SCHEMES TO ENHANCE VERTICAL, HORIZONTAL AND PLATFORM REUSABILITY OF VERIFICATION COMPONENTS IN AMBA BASED SOC DESIGN | Ieryung Park, Nara Cho, and Yonghee Im | | | | | |
| Pragmatic Formal Verification of Sequential Error Detection and Correction Codes (ECCs) used in Safety-Critical Design | Aman Kumar | | | | | |
| Pragmatic Formal Verification of Sequential Error Detection and Correction Codes (ECCs) used in Safety-Critical Design | Aman Kumar | | | | | |
| Pragmatic Verification Reuse in a Vertical World | Mark Litterick | | | | | |
| Pragmatic Verification Reuse in a Vertical World | Mark Litterick | | | | | |
| Pre-Silicon Power Management Verification of Complex SOCs: Experiences with Intel Moorefield | Rajeev Muralidhar, Nivedha Krishnakumar, Bryan Morgan, Robert Karas, Billy Dennie, and Neil Rosenberg | | | | | |
| Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads using Hybrid System Level Emulation SoC Platform | Neeraj Gupta, Reddaiah Yedoti, Dixit Sethi, and Sarvesh Kumar Pandey | | | | | |
| Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads Using Hybrid System Level Emulation SoC Platform | Neeraj Gupta, Reddaiah Yedoti, Dixit Sethi, and Sarvesh Kumar Pandey | | | | | |
| Predicting Bad Commits | Christian Graber, Daniel Hansson, and Adam Tornhill | | | | | |
| Preventing Chip-Killing Glitches on CDC Paths with Automated Formal Analysis | Jackie Hsiung, Ashish Hari, and Sulabh Kumar Khare | | | | | |
| Preventing Chip-Killing Glitches on CDC Paths with Automated Formal Analysis | Jackie Hsiung, Sulabh Kumar Khare, and Ashish Hari | | | | | |
| Preventing Glitch Nightmares on CDC Paths: The Three Witches | Jian-Hua Yan, Ping Yeung, Stewart Li, Sulabh-Kumar Khare | | | | | |
| Primary, Anonymous, or What? The Destiny of Ports from Design Top that Ultimately are Driven from Off-Chip… | Brandon Skaggs, Progyna Khondkar | | | | | |
| Problematic Bi-Directional Port Connections: How Well is Your Simulator Filling the UPF LRM Void? | Brandon Skaggs | | | | | |
| Problematic Bi-Directional Port Connections: How Well Is Your Simulator Filling the UPF LRM Void? | Brandon Skaggs | | | | | |
| Product Life Cycle of an Interconnect Bus: A Portable Stimulus Methodology for Performance Modeling, Design Verification, and Post-Silicon Validation | Gaurav Bhatnagar and Courtney Fricano | | | | | |
| Product Life Cycle of Interconnect Bus:A Portable Stimulus Methodology for Performance Modeling, Design Verification, and Post-Silicon Validation | Gaurav Bhatnagar and Courtney Fricano | | | | | |
| Programming Model Inheritance and Sequence Reuse | Aji Varghese | | | | | |
| Proper Probing: Flexibility on the TLM Level | Gergö Vékony | | | | | |
| Proper probing: Flexibility on the TLM level | Gergő V kony | | | | | |
| Property-Driven Development of a RISC-V CPU | Tobias Ludwig, Michael Schwarz, Joakim Urdahl, Lucas Deutschmann, Salaheddin Hetalani, Dominik Stoffel, and Wolfgang Kunz | | | | | |
| Property-Driven Development of a RISC-V CPU | Tobias Ludwig | | | | | |
| Proven Strategies for Better Verification Planning: DVCon 2022 Workshop | Paul Marriott, Jeff Vance, and Jeff McNeal | | | | | |
| PSL/SVA Assertions in SPICE | Donald O’Riordan and Prabal Bhattacharya | | | | | |
| PSS Action Sequence Modeling Using Machine Learning | Moonki Jang | | | | | |
| PSS Action Sequence Modeling Using Machine Learning | Moonki Jang, Myeongwhan Hyun, Hyunkyu Ahn, Jiwoong Kim, Yunwhan Kim, and Dongjoo Kim | | | | | |
| PSS: The Promises and Pitfalls of Early Adoption | Mike Bartley | | | | | |
| Pushbutton Complete IP Generation | Freddy Nunez | | | | | |
| PyRDV: a Python-based solution to the requirements traceability problem | Fernando Gabriel Orge | | | | | |
| PyRDV: a Python-based solution to the requirements traceability problem | Fernando Gabriel Orge, | | | | | |
| Qualification of Formal Properties for Productive Automotive Microcontroller Verification | Holger Busch | | | | | |
| Quantification of Formal Properties for Productive Automotive Microcontroller Verification | Holger Busch | | | | | |
| Raising the level of Formal Signoff with End to End Checking Methodology | Ping Yeung, Arun Khurana, Dhruv Gupta, Ashutosh Prasad, Achin Mittal | | | | | |
| Raising the Level of Formal Signoff with End-to-End Checking Methodology | Ping Yeung, Arun Khurana, Dhruv Gupta, Ashutosh Prasad, and Achin Mittal | | | | | |
| Random Directed Low Power Coverage Methodology: A Smart Approach to Power Aware Verification Closure | Awashesh Kumar and Madhur Bhargava | | | | | |
| Random Directed Low Power Coverage Methodology:(A Smart Approach to Power Aware Verification Closure) | Awashesh Kumar and Madhur Bhargava | | | | | |
| Random Testcase Generation and Verification of Debug Unit for a RISC-V Processor Core | Sneha Mishra, Lu Hao, Ajay Sharma, Afshan Anjum, Lucia Franco, Sourav Roy, Jeff Scott | | | | | |
| Random Testcase Generation and Verification of Debug Unit for a RISC-V Processor Core | Sneha Mishra, Lu Hao, Ajay Sharma, Afshan Anjum, Lucia Franco, Sourav Roy, Jeff Scott | | | | | |
| Randomizing UVM Config DB Parameters | Jeremy Ridgeway | | | | | |
| Randomizing UVM Config DB Parameters | Jeremy Ridgeway | | | | | |
| Real Number Modeling | Tom Cole, Wes Queen, Mark Kautzman, and Dan Romaine | | | | | |
| Real Number Modeling Enables Fast, Accurate Functional Verification | Wes Queen, Tom Cole, and Dan Romaine | | | | | |
| Real Number Modeling for RF Circuits | Jakub Dudek, Joshua Nekl and Keith O’Donoghue | | | | | |
| Real Number Modeling of RF Circuits | Jakub Dudek, Joshua Nekl, and Keith O’Donoghue | | | | | |
| Recipe for bug hunting: Tips & Tricks for Low power silicon sign-off | Monika Rawat, Dipankar Narendra Arya, Anuroop R, Deepmala Sachan | | | | | |
| RegAnalyzer – A tool for programming analysis and debug for verification and validation | Suresh Vasu | | | | | |
| RegAnalyzer -A tool for programming analysis and debug for verification and validation | Suresh Vasu | | | | | |
| Register This! Experiences Applying UVM Registers | Sharon Rosenberg | | | | | |
| Register This! Experiences Applying UVM Registers | Kathleen Meade | | | | | |
| Register Verification: Do We Have Reliable Specification? | NamDo Kim, Junhyuk Park, Byeong Min, and Wesley Park | | | | | |
| Register Verification: Do We Have Reliable Specification? | NamDo Kim, Junhyuk Park, Byeong Min, and Wesley Park | | | | | |
| Registering the standard: Migrating to the UVM_REG code base | Sachin Patel, Amit Sharma, and Adiel Khan | | | | | |
| Regressions in the 21st Century – Tools for Global Surveillance | David Crutchfield, Tushar Grupta, Frank Roberts, and Venkataramanan Srinivasan | | | | | |
| Regressions in the 21st Century – Tools for Global Surveillance | David Crutchfield, Tushar Grupta, Frank Roberts, and Venkataramanan Srinivasan | | | | | |
| Regvue Modern Hardware/Software Interface (HSI) Documentation | Rob Donnelly, Josh Geden | | | | | |
| Regvue Modern Hardware/Software Interface Documentation | Rob Donnelly, Josh Geden | | | | | |
| Relieving the Parameterized Coverage Headache | Christine Lovett, Bryan Ramirez, Stacey Secatch, and Michael Horn | | | | | |
| Relieving the Parameterized Coverage Headache | Christine Lovett | | | | | |
| Requirements Recognition for Verification IP Design Using Large Language Models | Siarhei Zalivaka | | | | | |
| Requirements Recognition for Verification IP Design Using Large Language Models | S. S. Zalivaka | | | | | |
| Reset and Initialization, the Good, the Bad and the Ugly | Ping Yeung and Kaowen Liu | | | | | |
| Reset and Initialization, the Good, the Bad and the Ugly | Ping Yeung and Kaowen Liu | | | | | |
| Reset and Initialization: the Good, the Bad and the Ugly | Ping Yeung and Kaowen Liu | | | | | |
| Reset Domain Crossing for designs with set-reset flops | Abdul Moyeen, Inayat Ali | | | | | |
| Resetting Anytime with the Cadence UVM Reset Package | Courtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm | | | | | |
| Resetting Anytime with the Cadence UVM Reset Package | Courtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm | | | | | |
| Results Checking Strategies with Portable Stimulus | Tom Fitzpatrick and Matthew Ballance | | | | | |
| Results Checking Strategies with Portable Stimulus | Tom Fitzpatrick and Matthew Balance | | | | | |
| Reusable System-Level Power-Aware IP Modeling Approach | Antonio Genov, Francois Verdier, and Loic Leconte | 2022 | Paper | | y2022 | paper |
| REUSABLE UPF: Transitioning from RTL to Gate Level Verification | Durgesh Prasad, Jitesh Bansal, and Madhur Bhargava | | | | | |
| REUSABLE UPF: Transitioning from RTL to Gate Level Verification | Durgesh Prasad, Jitesh Bansal, and Madhur Bhargava | | | | | |
| Reuse C test and UVM sequence utilizing TLM2, register model and interrupt handler | Liu HongLiang and Gao Teng-Fei | | | | | |
| Reuse C test and UVM sequence utilizing TLM2, register model and interrupt handler | HongLiang Liu and Teng-Fei Gao | | | | | |
| Reusing Testbench Components in a Hybrid Simulation-Formal Environment | Ritero Chi and Xiaolin Chen | | | | | |
| Reusing UVM Test Benches in a Cycle Simulator | Kristina Hager, Carter Alvord, Andrew Lynch, and Umer Yousafzai | | | | | |
| Reusing UVM Testbenches in a Cycle Simulator | Kristina Hager, Andrew Lynch, Umer Yousafzai, and Carter Alvord | | | | | |
| Richard Weber, Jamsheed Agahi, Josh Rensch, Eric Sherk | Pratik Parvati | | | | | |
| RISC-V Core Verification: A New Normal in Verification Techniques | Adnan Hamid, John Sotiropoulos | | | | | |
| RISC-V Processor Verification: Case Study | Adi Maymon, Shay Harari, Lee Moore, Larry Lapides | | | | | |
| RISC-V Security Verification using Perspec/Portable Stimulus | Junxia Wang, Siyan. Li, Leven. Li, A T S Prasad, Kiran Kumar Palla, Yung Cheng Chen | | | | | |
| RISC-V Testing – status and current state of the art | Jon Taylor | | | | | |
| RISC-V Testing Status and current state of the art | Jon Taylor | | | | | |
| Robust Physical Layer IP Verification for DDR4-3DS Memory by Channel Modelling | Aditya S Kumar, Gowdra Bomanna Chethan, Shivani Maurya, Kumar Rajeev Ranjan, Anil Deshpande, Somasunder Kattepura Sreenath | | | | | |
| Rockin’ the Polymorphism for an Elegant UVM Testbench Architecture | Mike Baird and Frank Verhoorn | | | | | |
| Rockin’ the polymorphism for an Elegant UVM testbench Architecture for a Scalable, Highly Configurable, Extensible DUT | Michael Baird and Frank Verhoorn | | | | | |
| Role of AI in SoC Performance Verification(PV) | Sharada Vajja, Raghu Alamuri, Saksham Mehra | | | | | |
| Rolling the dice with random instructions is the safe bet on RISC-V verification | Simon Davidmann and Lee Moore, Richard Ho and Tao Liu, and Doug Letcher and Aimee Sutton | | | | | |
| RTL Transformation Methods to Achieve Order of Magnitude TAT Improvement in VLSI Design | Ashfaq Khan, Shuhui Lin, Dan Standring, Adam Cajiao Campos, Soowan Suh, Satish Venkatesan | | | | | |
| RTL Transformation Methods to Achieve Order of Magnitude TAT Improvement in VLSI Design | Ashfaq Khan, Shuhui Lin, Dan Standring, Adam Cajiao Campos, Soowan Suh, Satish Venkatesan | | | | | |
| Run-time Configuration of a Verification Environment – A Novel Use of the OVM/UVM Analysis Pattern | Paul Marriott and Mark Ronan | | | | | |
| Run-Time Configuration of a Verification Environment: A Novel Use of the OVM/UVM Analysis Pattern | Paul Marriott | | | | | |
| Run-Time Phasing in UVM: Ready for the Big Time or Dead in the Water? | John Aynsley | | | | | |
| Run-Time Phasing in UVM: Ready for the Big Time or Dead in the Water? | John Aynsley | | | | | |
| Safety and Security Aware Pre-silicon Concurrent Software Development and Verification | Frank Schirrmeister, Joe Fabbre, and Max Hinson | | | | | |
| Safety and Security Aware Pre-silicon Concurrent Software Development and Verification | Frank Schirrmeister, Joe Fabbre, and Max Hinson | | | | | |
| Saving and Restoring Simulation Methodology using UVM Factory Overriding to Reduce Simulation Turnaround Time | Ahhyung Shin, Yungi Um, Youngsik Kim, and Seonil Brian Choi | | | | | |
| Saving and Restoring Simulation Methodology using UVM Factory Overriding to Reduce Simulation Turnaround Time | Ahhyung Shin, Yungi Um, Youngsik Kim, and Seonil Brian Choi | | | | | |
| Scalable Functional Verification using Portable Stimulus Standard | Santosh Kumar, Yogish Kumar Raja, Geetika Agrawal, Karthikeyan S, Arjun Ashok V, Tommy Brunansky | | | | | |
| Scalable Functional Verification using PSS | Santosh Kumar, Yogish Kumar Raja, Geetika Agrawal, Karthikeyan S, Arjun Ashok V, Tommy Brunansky | | | | | |
| Scalable Reset Domain Crossing Verification Using Hierarchical Data Model | Soumya Palit, Anwesha Choudhury, and Kurt Takara | | | | | |
| SCALABLE, RE-USABLE UVM DMS AMS BASED VERIFICATION METHODOLOGY FOR MIXED-SIGNAL SOCS | Nilesh Sonara, Noorulla Mohammad, Poonam Singh, David Stoops, Joseph Fernando, and Kartik Sudarshana | | | | | |
| Scalable, Re-usable UVM DMS AMS based Verification Methodology for Mixed-Signal SOCs | Nilesh Sonara, Noorulla Mohammad, Poonam Singh, David Stoops, Joseph Fernando, and Kartik Sudarshana | | | | | |
| Second Generation Completeness Analysis of Formal Assertions on Compatibility of RISC-V Cores | Wayne Yun | | | | | |
| Security Verification using Perspec/Portable Stimulus | Junxia Wang, Leven Li, Siyan Li, A T S Prasad, Kiran Kumar Palla, Yung Cheng Chen | | | | | |
| Security Verification Using Portable Stimulus Driven Test Suite Synthesis | Adnan Hamid and David Kelf | | | | | |
| See the Forest for the Trees – How to Effectively Model and Randomize a Directed Rooted Tree Structure | Harry Duque and Lars Viklund | | | | | |
| See the Forest for the Trees – How to Effectively Model and Randomize a DRT Structure | Harry Duque, Lars Viklund | | | | | |
| Sequence, Sequence on the Wall – Who’s the Fairest of Them All? | Rich Edelman and Raghu Ardeishar | | | | | |
| Seven Separate Sequence Styles Speed Stimulus Scenarios | Mark Peryer | | | | | |
| Seven Separate Sequence Styles Speed Stimulus Scenarios | Mark Peryer | | | | | |
| SGEN2: Evolution of a Sequence-Based Stimulus Engine for Micro-Processor Verification | Stephan Bourduas and Christopher Mikulis | | | | | |
| SGEN2: Evolution of a sequence-based stimulus engine for micro-processor verification. | Stephan Bourduas and Chris Mikulis | | | | | |
| Shaping Formal Traces without Constraints: A Case Study in Closing Code Coverage on a Crypto Engine Using Formal Verification | David N. Goldberg, Adriana Maggiore, and David J. Simpson | | | | | |
| Shaping Formal Traces without Constraints: A Case Study in Closing Code Coverage on a Crypto Engine using Formal Verification | David N. Goldberg, Adriana Maggiore, and David J. Simpson | | | | | |
| Sharing Generic Class Libraries in SystemVerilog Makes Coding Fun Again | Keisuke Shimizu | | | | | |
| Sharing Generic Class Libraries in SystemVerilog Makes Coding Fun Again | Keisuke Shimizu | | | | | |
| Shift-Left on Timing Constraints Verification: Beyond Typical Front-End Execution | Vineeth B, Deepmala Sachan, Ritesh Jain | | | | | |
| Shift-Left on Timing Constraints Verification: Beyond Typical Front-End Execution | Vineeth B, Deepmala Sachan, Ritesh Jain | | | | | |
| Sign-off with Bounded Formal Verification Proofs | NamDo Kim, Junhyuk Park, HarGovind Singh, and Vigyan Singhal | | | | | |
| Sign-off with Bounded Formal Verification Proofs | NAMDO KIM, JUNHYUK PARK, HARGOVIND SINGH, and VIGYAN SINGHAL | | | | | |
| Simple & Rapid Design Verification using SystemVerilog Testbench on Intel’s Next-Generation Microprocessor | Thomas Alsop, Wayne Clift, Luke Hood, and Jeff Gray | | | | | |
| Simpler Register Model | Sanjeev Singh | | | | | |
| Simpler Register Model Package for UVM Testbenches. | Sanjeev Singh | | | | | |
| Simulation Acceleration with ZeBu to Speed IP and Platform Verification | Hillel Miller and Wei-Hua Han | | | | | |
| Simulation Runtime Optimization of Constrained Random Verification using Machine Learning Algorithms | Sarath Mohan Ambalakkat and Eldon Nelson | | | | | |
| Simulation Runtime Optimization of Constrained Random Verification using Machine Learning Algorithms | Sarath Mohan Ambalakkat M.S. and Eldon Nelson M.S. P.E. | | | | | |
| Single Source Register Sequencing Toolkit and Methodology for FW and Verification Co-Development | Josh Loo, Anthony Cabrera, Kiel Boyle, and Scott R. Nelson | | | | | |
| Slaying the UVM Reuse Dragon | Mike Baird and Bob Oden | | | | | |
| Slaying the UVM Reuse Dragon Issues and Strategies for Achieving UVM Reuse | Mike Baird and Bob Oden | | | | | |
| Smart Formal for Scalable Verification | Ashish Darbari | | | | | |
| Smart Formal for Scalable Verification | Ashish Darbari | | | | | |
| So There’s My Bug! Debugging Universal Verification Methodology (UVM) Environments | Mike Floyd | | | | | |
| So you think you have good stimulus: System-level distributed metrics analysis and results | Andreas Meyer | | | | | |
| So you think you have good stimulus: System-level distributed metrics analysis and results | Andreas Meyer | | | | | |
| SoC Firmware Debugging Tracer in Emulation Platform | Kubendra Kumbar, Sandeep Vallabhaneni, Ken Joseph Kannampuzha, Hojun Shim, and Byung Chul Yoo | | | | | |
| SoC Firmware Debugging Tracer in Emulation Platform | Kubendra Kumbar, Sandeep Vallabhaneni, Ken Joseph Kannampuzha, Hojun Shim, and Byung Chul Yoo | | | | | |
| SoC Verification of Analog IP Integration through Automated, Formal-Based, Rule-driven Spec Generation | Murugesh Palaniswamy, Ravi Kalyanaraman, Gargi Sharma, and Bharat Baliga-Savel | | | | | |
| SoC Verification of Analog IP Integration through Automated, Formal-Based, Rule-driven Spec Generation | Murugesh Palaniswamy, Ravi Kalyanaraman, Gargi Sharma, and Bharat Baliga-Savel | | | | | |
| SoC Verification Speed – More is Better | Fernanda Braga, John Rose, William Winkeler, Sharon Rosenberg, and Frank Schirrmeister | | | | | |
| SoC Verification using OVM : Leveraging OVM Constructs to Perform Processor Centric Verification | Cedric Macadangdang and Paul Yue | | | | | |
| Soft Constraints in SV: Semantics and Challenges | Mark Strickland | | | | | |
| Soft Constraints in SystemVerilog Semantics and Challenges | Mark Strickland, Joseph Hanli Zhang, Jason Chen, Dhiraj Goswami, and Alex Wakefield | | | | | |
| Solving Next Generation IP Configurability | David Murray and Simon Rance | | | | | |
| Solving Next Generation IP Configurability | David Murray and Simon Rance | | | | | |
| Source Control…$100 Regression Script…$500 Good Automated Release Steps…$Priceless | Jeffrey Wren | | | | | |
| Specification Driven Analog and Mixed-Signal Verification | Henry Chang and Ken Kundert | | | | | |
| Specification Driven Analog and Mixed-Signal Verification | Henry Chang and Ken Kundert | | | | | |
| Standard Regression Testing Does not Work | Daniel Hansson | | | | | |
| Standard Regression Testing Does Not Work | Daniel Hansson | | | | | |
| Static power-management verification of Cypress’s PSoC® Programmable System-on-Chip for embedded systems | Johnie Au and Prapanna Tiwari | | | | | |
| Static Sign-Off Best Practices Learnings and Experiences from Industry Use Cases | Vikas Sachdeva | | | | | |
| Statically Dynamic or Dynamically Static? Exploring the power of classes and enumerations in SystemVerilog Assertions for reusability and scalability | Sachin Scaria, Sreenu Yerabolu, and Don Mills | | | | | |
| Statically Dynamic or Dynamically Static? Exploring the power of classes and enumerations in SystemVerilog Assertions for reusability and scalability | Sachin Scaria and Sreenu Yerabolu | | | | | |
| Stepping into UPF 2.1 world: Easy solution to complex Power Aware Verification | Amit Srivastava and Madhur Bhargava | | | | | |
| Stepping into UPF 2.1 world: Easy solution to complex Power Aware Verification | Amit Srivastava and Madhur Bhargava | | | | | |
| Stepwise Refinement and Reuse: The Key to ESL | Ashok B. Mehta, Mark Glasser, Shabtay Matalon, and Dan Gardner | | | | | |
| Stimulating Scenarios in the OVM and VMM | JL Gray and Scott Roland | | | | | |
| Strategies and Methods of using PSS2.0 high level modeling techniques to augment UVM verification | Swami Venkatesan | | | | | |
| Strategies on CDC False Alarm Rapid Location | Jianhua Yan, Meiling Qi, Yunyang Song | | | | | |
| Strategies to Maximize Reusability of UVM Test Scenarios in SoC Verification | Hyeonman Park, Namyoung Kim, Kyoungmin Lee, Hongkyu Kim, Jaein Hong, Kiseok Bae | | | | | |
| Strategies to Maximize Reusability of UVM Test Scenarios in SoC Verification | Namyoung Kim, Hyeonman Park, Kyoungmin Lee, Hongkyu Kim, Jaein Hong, Kiseok Bae | | | | | |
| Strategy and Environment for SOC Mixed-Signal Validation: A Case Study | Erik A McShane and Intel | | | | | |
| Streamlining Low Power Verification: From UPF to Signoff | Godwin Maben, Santhana Krishnan, Neeraj Mishra, Nishant Patel, Bhaumik Matholia | | | | | |
| Sub-design Interface Aware Top Only Static Low Power Verification | Heichang Lee, Nikhil Amin, Jianfeng Liu, Minyoung Mo, and Dongkwan Han | | | | | |
| Successes and Challenges of Validation Content Reuse | Mike Chin, Jonathan Edwards, Josh Pfrimmer, and Hooi Jing Tan | | | | | |
| Successive Refinement – An Approach to Decouple Front End and Back End Power Intent | Sinha Rohit Kumar and Kotha Kavya | | | | | |
| Successive Refinement – An Approach to Decouple Front Front-End and Back Back-End Power Intent | Kotha Kavya and Sinha Rohit Kumar | | | | | |
| Successive Refinement of UPF Power Switches | Prabhakar Satya Ayyagari, William G Crocco | | | | | |
| Successive Refinement: A Methodology for Incremental Specification of Power Intent | Adnan Khan, John Biggs, Eamonn Quigley, and Erich Marschner | | | | | |
| Successive Refinement: A Methodology for Incremental Specification of Power Intent | Adnan Khan, Eamonn Quigley, John Biggs, and Erich Marschner | | | | | |
| Successive Refinement: A Methodology for Incremental Specification of Power Intent | Adnan Khan, Eamonn Quigley, John Biggs, and Erich Marschner | | | | | |
| Supercharge Your Verification Using Rapid Expression Coverage as the Basis of a MC/DC-Compliant Coverage Methodology | Gaurav Kumar Verma and Doug Warmke | | | | | |
| Supercharge Your Verification Using Rapid Expression Coverage as the Basis of a MC/DC-Compliant Coverage Methodology | Gaurav Kumar Verma and Doug Warmke | | | | | |
| Supplementing Simulation of a Microcontroller Flash Memory Subsystem with Formal Veri cation | Othmane Bahlous and Abdelouahab Ayari | | | | | |
| Supplementing Simulation of a Microcontroller Flash Memory Subsystem with Formal Verification | Othmane Bahlous and Abdel Ayari | | | | | |
| Supply network connectivity: An imperative part in low power gate-level verification | Gabriel Chidolue, Vinay Singh, and Divyeshkumar Dhanjibhaiv Vora | | | | | |
| Supply network connectivity: An imperative part in low power gate-level verification | Vinay Kumar Singh and Gabriel Chidolue | | | | | |
| Supporting root cause analysis of inaccurate bug prediction based on machine learning – Lessons learned when interweaving training data and source code | Oscar Werneman, Markus Borg, Daniel Hansson | | | | | |
| Survey of Machine Learning (ML) Applications in Functional Verification (FV) | Dan Yu, Harry Foster, Tom Fitzpatrick | | | | | |
| SV_LUT: A SystemVerilog Look Up Table package for developing complex AMS Real Number Modeling | FNU Farshad, Shafaitul Islam Surush, Simul Barua | | | | | |
| SV_LUT: A SystemVerilog Look Up Table package for developing complex AMS Real Number Modeling | FNU Farshad, Shafaitul Islam Surush, Simul Barua | | | | | |
| SVA Encapsulation in UVM: enabling phase and configuration aware assertions | Mark Litterick | | | | | |
| SVA Encapsulation in UVM: enabling phase and configuration aware assertions | Mark Litterick | | | | | |
| Switch the Gears of the UVM Register Package to cruise through the street named “Register Verification”. | Amit Sharma, Varun S, Abhisek Verma, and Gaurav Gupta | | | | | |
| Switch the Gears of the UVM Register Package to cruise through the street named “Register Verification”. | Parag Goel, Amit Sharma, Varun S, Abhisek Verma, and Gaurav Gupta | | | | | |
| Synchronicity: Bringing Order to SystemVerilog/UVM Synchronizing Chaos | Bryan Morris and P. Eng | | | | | |
| Synchronicity: Bringing Order to the SystemVerilog/UVM Synchronizing Chaos | Bryan Morris | | | | | |
| Synthesis of Decoder Tables using Formal Verification Tools | Keerthikumara Devarajegowda, Johannes Schreiner, and Wolfgang Ecker | | | | | |
| Synthesis of Decoder Tables using Formal Verification Tools | Keerthikumara Devarajegowda, Johannes Schreiner, and Wolfgang Ecker | | | | | |
| Synthesis of Decoder Tables Using Formal Verification Tools | Keerthikumara Devarajegowda, Johannes Schreiner, and Wolfgang Ecker | | | | | |
| Synthesizable Random Testbench for Multimedia IP Verification | Sanggyu Park | | | | | |
| Synthetic Traffic based SOC Performance Verification Methodology | Jeonggu Lee, Taewon Park, Hyungtae Park, Taeyoung Jeon, Hyunjae Woo, Youngsik Kim, Seonil Brian Choi | | | | | |
| Synthetic Traffic based SOC Performance Verification Methodology | Jeonggu Lee, Taewon Park, Hyungtae Park, Taeyoung Jeon, Hyunjae Woo, Youngsik Kim, Seonil Brian Choi | | | | | |
| SYSTEM LEVEL FAULT INJECTION SIMULATION USING SIMULINK | Wai Yuen Tang, Marcelo Mizuki, Mitch Norcross, and Fengying Qiao | | | | | |
| System Level Fault Injection Simulation Using Simulink | Wai Yuen Tang, Marcelo Mizuki, Mitch Norcross, and Fengying Qiao | | | | | |
| System level random verification: How it should be done | Madhusudan Rathi and Ashok Chandran | | | | | |
| System Model – A Testbench Library Component Aided for Emulating User Interaction | Hussain Wadia | | | | | |
| System Responsiveness Verification of large Multi Processor System Configurations using Micro Benchmarks and a Multi Level Analysis | Dr. Ralf Winkelmann, Edward Chencinski, Hanno Eichelberger, Michael Fee, Carsten Otte, and Christoph Raisch | | | | | |
| System Responsiveness Verification of large Multi-Processor System Configurations using Micro-Benchmarks and a Multi-Level Analysis | Dr. Ralf Winkelmann, Edward Chencinski, Hanno Eichelberger, Michael Fee, Carsten Otte, Christoph Raisch | | | | | |
| System to catch Implementation gotchas in the RTL Restructuring process | Anmol Rattan, Satinder Malhi, and Balwinder Soni | | | | | |
| System to catch Implementation gotchas in the RTL Restructuring process | Anmol Rattan, Satinder Singh Malhi, Balwinder Singh Soni, Anuj Kumar, Navneet Chaurasia, and Sami Akhtar | | | | | |
| System Verification with MatchLib | Russell Klein | | | | | |
| System Verilog Assertion Linting: Closing Potentially Critical Verification Holes | Erik Seligman, Laurence Bisht, and Dmitry Korchemny | | | | | |
| System-Level Power Estimation of SSDs under Real Workloads using Emulation | Sangmin Kim, Kwanghyo Ahn, Changhoon Han, Hyunsik Kim, Jaewoo Im | | | | | |
| System-Level Power Estimation of SSDs under Real Workloads using Emulation | Sangmin Kim, Kwanghyo Ahn, Changhoon Han, Hyunsik Kim, Jaewoo Im | | | | | |
| System-Level Random Verification: How it should be done | Madhusudan Rathi and Ashok Chandran | | | | | |
| System-Level Security Verification Starts with the Hardware Root of Trust | Dr. Jason Oberg | | | | | |
| Systematic Application of UCIS to Improve the Automation on Verification Closure | Christoph Kuznik, Marcio F. S. Oliveira, Gilles Bertrand Defo, and Wolfgang Mueller | | | | | |
| Systematic Application of UCIS to Improve the Automation on Verification Closure | Christoph Kuznik, Marcio F. S. Oliveira, Gilles Bertrand Defo, and Wolfgang Mueller | | | | | |
| Systematic Constraint Relaxation (SCR): Hunting for Over Constrained Stimulus | Debarshi Chatterjee, Spandan Kachhadia, Ismet Bayraktaroglu, Siddhanth Dhodhi | | | | | |
| Systematic Constraint Relaxation (SCR): Hunting for Over-Constrained Stimulus | Debarshi Chatterjee, Spandan Kachhadiya, Ismet Bayraktaroglu, and Siddhanth Dhodhi | | | | | |
| Systematic Speedup Techniques for Functional CDC Verification Closure | Sulabh Kumar Khare and Ashish Hari | | | | | |
| Systematic Speedup Techniques for Functional CDC Verification Closure | Sulabh Kumar Khare and Ashish Hari | | | | | |
| Systematically Achieving CDC Verification Closure based on Coverage Models and Coverage Metrics | Ashish Hari and Yogesh Badaya | | | | | |
| Systematically Achieving CDC Verification Closure based on Coverage Models and Coverage Metrics | Ashish Hari and Yogesh Badaya | | | | | |
| SystemC FMU for Verification of Advanced Driver Assistance Systems | Keroles Khalil and Magdy A. El-Moursy | | | | | |
| SystemC Virtual Prototype: Ride the Earliest Train for Time-To-Market | Shweta Saxena and Mahantesh Danagouda | | | | | |
| SystemC Virtual Prototype: Ride the earliest train for Time-To-Market! | Shweta Saxena and Mahantesh Danagouda | | | | | |
| SystemC: Focusing on High Level Synthesis and Functional Coverage for SystemC | Dragos Dospinescu, Frederic Doucet, Mike Meredith, Bob Condon, Dragos Dospinescu and Mike Meredith | | | | | |
| SystemRDL to PSS BASIC TO PRO | Anupam Bakshi and Amanjyot Kaur | | | | | |
| SystemVerilog Assertion Linting: Closing Potentially Critical Verification Holes | Laurence S. Bisht, Dmitry Korchemny, and Erik Seligman | | | | | |
| SystemVerilog Assertions for Clock-Domain-Crossing Data Paths | Don Mills | | | | | |
| SystemVerilog Assertions for Clock-Domain-Crossing Data Paths | Don Mills | | | | | |
| SystemVerilog Checkers: Key Building Blocks for Verification IP | Laurence Bisht, Dmitry Korchemny, and Erik Seligman | | | | | |
| SystemVerilog Configurations and Tool Flow Using SCons (an Improved Make) | Don Mills and Dillan Mills | | | | | |
| SystemVerilog Constraint Layering via Reusable Randomization Policy Classes | John Dickol | | | | | |
| SystemVerilog Constraint Layering via Reusable Randomization Policy Classes | John Dickol | | | | | |
| SystemVerilog Constraints: Appreciating What You Forgot In School to Get Better Results | Dave Rich | | | | | |
| SystemVerilog Format of Portable Stimulus | Wayne Yun, David Chen, Theta Yang, and Evean Qin | | | | | |
| SystemVerilog FrameWorksTM Scoreboard: An Open Source Implementation Using UVM | Ambar Sarkar | | | | | |
| SystemVerilog Interface Classes – More Useful Than You Thought | Stan Sokorac | | | | | |
| SystemVerilog Interface Classes More Useful Than You Thought | Stan Sokorac | | | | | |
| SystemVerilog Interface Cookbook | Paul Egan and Kathleen Otten | | | | | |
| SystemVerilog Interface Cookbook | Paul Egan and Kathleen Otten | | | | | |
| SystemVerilog Meets C++: Re-use of Existing C/C++ Models Just Got Easier | John Aynsley | | | | | |
| SystemVerilog Real Models for an InMemory Compute Design | Daniel Cross | | | | | |
| SystemVerilog-2009 Enhancements: Priority/Unique/Unique | Clifford E. Cummings | | | | | |
| SystemVerilog, Batteries Included: A Programmer’s Utility Library for SystemVerilog | Jonathan Bromley and André Winkelmann | | | | | |
| SystemVerilog, Batteries Included: A Programmer’s Utility Library for SystemVerilog | Jonathan Bromley and André Winkelmann | | | | | |
| Table-based Functional Coverage Management for SOC Protocols | Shahid Ikram, Jack Perveiler, Isam Akkawi, Jim Ellis, and David Asher | | | | | |
| Table-based Functional Coverage Management for SOC Protocols | Shahid Ikram, Jack Perveiler, Isam Akkawi, Jim Ellis, and David Asher | | | | | |
| Tackling Missing Bins: Refining Functional Coverage in SystemVerilog for Deterministic Coverage Closure | Jikjoo Lee, Tony Gladvin George, Kihyun Park, Dongkun An, Wooseong Cheong, ByungChul Yoo | | | | | |
| Tackling Missing Bins: Refining Functional Coverage in SystemVerilog for Deterministic Coverage Closure | Jikjoo Lee, Tony Gladvin George, Kihyun Park, Dongkun An, Wooseong Cheong, ByungChul Yood | | | | | |
| Tackling Random Blind Spots with Strategy-Driven Generation | Matthew Ballance | | | | | |
| Tackling Random Blind Spots with Strategy-Driven Stimulus Generation | Matthew Ballance | | | | | |
| Tackling Register Aliasing Verification Challenges in Complex ASIC Design | Shan Yan, Jie Wu, and Jing Li | | | | | |
| Tackling Register Aliasing Verification Challenges in Complex ASIC Design | Shan Yan, Jie Wu, and Jing Li | | | | | |
| Tackling the challenge of simulating multi-rail macros in a power aware flow | Himanshu Bhatt, Amol Herlekar, Vikas Grover, and Subhadip Nath | | | | | |
| Tackling the challenge of simulating multi-rail macros in a power-aware flow | Himanshu Bhatt, Amol Herlekar, Vikas Grover, and Subhadip Nath | | | | | |
| Tackling the Complexity Problem in Control and Datapath Designs with Formal Verification | Ravindra Aneja, Ashish Darbari, Nitin Mhaske, and Per Bjesse | | | | | |
| Take AIM! Introducing the Analog Information Model | Chuck McClish | | | | | |
| Take AIM! Introducing the Analog Information Model | Chuck McClish | | | | | |
| Taking Real-Value Modeling to the next level: Power-aware verification of mixed-signal designs | Subin Thykkoottathil, Jakub Dudek, Nagesh Ranganath, Nimay Shah, and Santosh Singh | | | | | |
| Taking RNM Model to the Next Level: Power-Aware Verification of Mixed-Signal Designs | Subin Thykkoottathil, Nagesh Ranganath, Santosh Singh, Jakub Dudek, and Nimay Shah | | | | | |
| Taming a Complex UVM Environment | Manjunath Shetty, and Ramamurthy Gorti | | | | | |
| Taming a Complex UVM Environment | Manjunath Shetty and Ramamurthy Gorti | | | | | |
| Taming the beast: A smart generation of Design Attributes (Parameters) for Verification Closure Using Specman | Meirav Nitzan, Yael Kinderman, and Efrat Gavish | | | | | |
| Test driving Portable Stimulus at AMD | Prabhat Gupta and Matan Vax | | | | | |
| Test Parameter Tuning with Blackbox Optimization: A Simple Yet Effective Way to Improve Coverage | Qijing Huang*, Hamid Shojaei, Fred Zyda, Azade Nazi, Shobha Vasudevan, Sat Chatterjee, Richard Ho | | | | | |
| Test Parameter Tuning with Blackbox Optimization: A Simple Yet Effective Way to Improve Coverage | Qijing Huang, Hamid Shojaei, Fred Zyda, Azade Nazi, Shobha Vasudevan, Sat Chatterjee, Richard Ho | | | | | |
| Test-driving PSS for System Low-Power Validation | Prabhat Gupta and Matan Vax | | | | | |
| Testbench Configuration Mantra | Stephen D’Onofrio | | | | | |
| Testing the Testbench | Stan Sokorac | | | | | |
| Testing the Testbench | Stan Sokorac | | | | | |
| Testpoint Synthesis Using Symbolic Simulation | Kai-Hui Chang, Yen-Ting Liu and Chris Browy | | | | | |
| Testpoint Synthesis Using Symbolic Simulation | Kai-Hui Chang, Yen-Ting Liu and Chris Browy | | | | | |
| The Art of Portable and Reusable UVM Shared System Memory Model Verification Methodology across Multiple Verification Platforms | Roman Wang, Thomas Bodmer, and Beryl Chen | | | | | |
| The Art of Portable and Reusable UVM Shared System Memory Model Verification Methodology Across Multiple Verification Platforms | Roman Wang, Thomas Bodmer, and Beryl Chen | | | | | |
| The beginning of new norm: CDC/RDC constraints signoff through functional simulation | Suhas D S, Ponsankar Arumugam, Deepmala Sachan, Ritesh Jain | | | | | |
| The beginning of new norm: CDC/RDC constraints signoff through functional simulation | Suhas D S, Ponsankar Arumugam, Deepmala Sachan, Ritesh Jain | | | | | |
| The Best Verification Strategy You’ve Never Heard Of | David Aerne, Amir Attarha, Harry Foster, and Kurt Takara | | | | | |
| The Big Brain Theory – Visualizing SoC Design & Verification Data | Gordon Allan | | | | | |
| The Big Brain Theory: Visualizing SoC Design & Verification Data | Gordon Allan | | | | | |
| The Case for Low-Power Simulation-to-Implementation Equivalence Checking | Himanshu Bhatt, John Decker, and Hiral Desai | | | | | |
| The Case for Low-Power Simulation-to-Implementation Equivalence Checking | Himanshu Bhatt, John Decker, and Hiral Desai | | | | | |
| The CHIPS ACT and Its Impact On The Design & Verification Markets | BOB SMITH | | | | | |
| The Cost of SoC Bugs | Ken Albin | | | | | |
| The Cost of SoC Bugs | Ken Albin | | | | | |
| The Evolution of RISC-V Processor Verification | Aimee Sutton, Lee Moore, Mike Thompson | | | | | |
| The Evolution of RISC-V Processor Verification: Open Standards and Verification IP | Lee Moore, Aimee Sutton, Mike Thompson | | | | | |
| The Evolution of Triage – Real-time Improvements in Debug Productivity | Gordon Allan | | | | | |
| The Exascale Debug Challenge: Time to advance your emulation debug game | Ribhu Mittal and Melvyn Goveas | | | | | |
| The Finer Points of UVM: Tasting Tips for the Connoisseur | John Aynsley | | | | | |
| The Finer Points of UVM: Tasting Tips for the Connoisseur | John Aynsley | | | | | |
| The future of formal model checking is NOW! | Ram Narayan | | | | | |
| The Future of Formal Model Checking is NOW! | Ram Narayan | | | | | |
| The Growing Need for End-to-end Protocol Verification for IP to Multi-die Systems | Varun Agrawal, Shakir Ali | | | | | |
| The Importance of Complete Signoff Methodology for Formal Verification | Iain Singleton, Mahesh Parmer, and Geogy Jacob | | | | | |
| The Importance of Complete Signoff Methodology for Formal Verification | Mahesh Parmar, Iain Singleton, Geogy Jacob | | | | | |
| The Life of a SystemVerilog Variable | Dave Rich | | | | | |
| The Missing Link: The Testbench to DUT Connection | David Rich | | | | | |
| The Need for Speed: Understanding design factors that make multi-core parallel simulations efficient | Shobana Sudhakar and Rohit K Jain | | | | | |
| The Need for Speed: Understanding design factors that make multi-core parallel simulations efficient | Shobana Sudhakar and Rohit K Jain | | | | | |
| The OVM-VMM Interoperability Library: Bridging the Gap | Tom Fitzpatrick and Adam Erickson | | | | | |
| The Problems with Lack of Multiple Inheritance in SystemVerilog and a Solution | David Rich | | | | | |
| The Process and Proof for Formal Sign-Off –A Live Case Study | Ipshita Tripathi, Ankit Saxena, Anant Verma, and Prashant Aggarwal | | | | | |
| The Process and Proof for Formal Sign-off A Live Case Study | Ipshita Tripathi, Ankit Saxena, Anant Verma, and Prashant Aggarwal | | | | | |
| The Untapped Power of UVM Resources and Why Engineers Should Use the uvm_resource_db API | Clifford E. Cummings, Heath Chambers, Mark Glasser | | | | | |
| The Untapped Power of UVM Resources and Why Engineers Should Use the uvm_resource_db API | Clifford E. Cummings, Heath Chambers, Mark Glasser | | | | | |
| The UPF 2.1 Library Commands: Truly Unifying the Power Specification Formats | Amit Srivastava, Awashesh Kumar, and Vinay Singh | | | | | |
| The UPF 2.1 library commands: Truly unifying the power specification formats | Amit Srivastava, Awashesh Kumar, and Vinay Singh | | | | | |
| THE VERIFICATION COCKPIT – A ONE-STOP SHOP FOR YOUR VERIFICATION DATA | Alia Shah, Eugene Rotter, Avi Ziv, Raviv Gal, and Divya Joshi | | | | | |
| There’s something wrong between Sally Sequencer and Dirk Driver – why UVM sequencers and drivers need some relationship counselling | Mark Peryer | | | | | |
| There’s something wrong between Sally Sequencer and Dirk Driver (Why UVM sequencers and drivers need some relationship counseling) | Mark Peryer | | | | | |
| Timing Coverage: An Approach to Analyzing Performance Holes | Surbhi Kalia, Shubhadeep Karmakar, Vikas Makhija, and Apoorva Mathur | | | | | |
| Tips for Developing Performance Efficient Verification Environments | Prashanth Srinivasa, Sarath Chandrababu Valapala, and Varun S | | | | | |
| Title: Using Test-IP Based Verification Techniques in a UVM Environment | Vidya Bellippady, Sundar Haran, and Jay O’Donnell | | | | | |
| TLM-2.0 in SystemVerilog | Mark Glasser and Janick Bergeron, | | | | | |
| To Infinity And Beyond – Streaming Data Sequences in UVM | Mark Litterick, Jeff Vance, Jeff Montesano | | | | | |
| Tough Verification Challenges: Data Visualization to the Rescue | Shaji Kunjumohamed | | | | | |
| Towards Efficient Design Verification – PyUVM & PyVSC | Deepak Narayan Gadde, Suruchi Kumari, Aman Kumar | | | | | |
| Towards Efficient Design Verification – Constrained Random Verification using PyUVM | Deepak Narayan Gadde, Suruchi Kumari, Aman Kumar | | | | | |
| Towards Provable Protocol Conformance of Serial Automotive Communication IP | Jens E. Becker, Oliver Sander, Alexander Klimm, J¨urgen Becker, Katharina Weinberger, and Slava Bulach | | | | | |
| Traditional top level static low power rule check | | | | | | |
| Traffic Profiling and Performance Instrumentation For On-Chip Interconnects | Mark Peryer and Bruce Mathewson | | | | | |
| Traffic Profiling and Performance Instrumentation For On-Chip Interconnects | Mark Peryer | | | | | |
| Transaction Recording Anywhere Anytime | Rich Edelman | | | | | |
| Transaction-Based Acceleration—Strong Ammunition In Any Verification Arsenal | Chandrasekhar Poorna, Varun Gupta, and Raj Mathur | | | | | |
| Transaction-Level Friending: An Open-Source, Standards-Based Library for Connecting TLM Models in SystemC and SystemVerilog | Adam Erickson | | | | | |
| Transaction-Level State Charts in UML and SystemC with Zero-Time Evaluation | Rainer Findenig , Thomas Leitner, Michael Velten, and Wolfgang Ecker | | | | | |
| Translating and Adapting to the “real” world: SerDes Mixed Signal Verification using UVM | Akhila Madhu Kumar and Karl Herterich | | | | | |
| Translating and Adapting to the “real” world: SerDesMixed Signal Verification using UVM | Akhila Madhu Kumar and Karl Herterich | | | | | |
| Transparent SystemC Model Factory for Scripting Languages | Rolf Meyer, Bastian Farkas, Syed Abbas Ali Shah, and Mladen Berekovic | | | | | |
| Transparent SystemC Model Factory for Scripting Languages | Rolf Meyer, Bastian Farkas, Syed Abbas Ali Shah, and Mladen Berekovic | | | | | |
| Transparently Checkpointing Software Test Benches to Improve Productivity of SOC Verification in an Emulation Environment | Ankit Garg, K. Suresh, Jeff Evans, Gene Cooperman, and Rohan Garg | | | | | |
| Transparently Checkpointing Software Test Benches to Improve Productivity of SoC Verification in an Emulation Environment | Ankit Garg, K. Suresh, Gene Cooperman, Rohan Garg, and Jeff Evans | | | | | |
| Traversing the Interconnect: Automating Configurable Verification Environment Development | Prashanth Srinivasa and Mathew Roy | | | | | |
| Tree Data Framework for Code Generation: Application of Generating UVM Testbench for Complex Designs | Chenhui Huang, Yu Sun, Divyang Agrawal | | | | | |
| Tree Data Framework for Code Generation: Application of Generating UVM Testbench for Complex Designs | Chenhui Huang, Yu Sun, Divyang Agrawal | | | | | |
| Trends in Functional Verification: A 2016 Industry Study | Harry D. Foster | | | | | |
| Trends in Functional Verification: A 2016 Industry Study | Harry D. Foster | | | | | |
| Tried and Tested Speedups for SW-driven SoC Simulation | Gordon Allan | | | | | |
| Tried/Tested speedups for SW-driven SoC Simulation | Gordon Allan | | | | | |
| Tweak-Free Reuse Using OVM | Sharon Rosenberg | | | | | |
| Two Stage Framework for Corner Case Stimuli Generation Using Transformer and Reinforcement Learning | Chung An Wang, Chiao Hua Tseng, Chia Cheng Tsai, Tung Yu Lee, Yen Her Chen, Chien Hsin Yeh, Chia Shun Yeh, Chin Tang Lai MediaTek, Hsinchu, Taiwan | | | | | |
| Two-Stage Framework for Corner Case Stimuli Generation Using Transformer and Reinforcement Learning | Chung-An Wang, Chiao-Hua Tseng, Chia-Cheng Tsai, Tung-Yu Lee, Yen-Her Chen, Chien-Hsin Yeh, Chia-Shun Yeh, and Chin-Tang Lai | | | | | |
| UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process | Ahmed Yehia | | | | | |
| UCIS APPLICATIONS: IMPROVING VERIFICATION PRODUCTIVITY, SIMULATION THROUGHPUT, AND COVERAGE CLOSURE PROCESS | Ahmed Yehia | | | | | |
| Ultimate Shift Left: Unleash the Power of UVM Virtual LAB Methodology upon SoC Verification | Roman Wang | | | | | |
| Ultimate Shift Left: Unleash the Power of UVM Virtual LAB Methodology upon SoC Verification | Roman Wang | | | | | |
| Unconstrained UVM SystemVerilog Performance | Wes Queen and Justin Sprague | | | | | |
| Unconstrained UVM SystemVerilog Performance | Wes Queen | | | | | |
| Understanding the Low Power Abstract | Gary Delp, Erich Marschner, and Kenneth Bakalar | | | | | |
| Understanding the RISC-V Verification Ecosystem | imon Davidmann, Aimee Sutton, Lee Moore | | | | | |
| Unifying Hardware-Assisted Verification and Validation Using UVM and Emulation | Hemant Sharma, Hans van der Schoot, and Achutam Murarka | | | | | |
| Unifying Hardware-Assisted Verification and Validation Using UVM and Emulation | Hemant Sharma, Hans van der Schoot, and Achutam Murarka | | | | | |
| Unique Verification Case Studies of Low Power Mixed Signal Chips | Venkatesh Ranga, Madhusudhan Subramanya, Anand Shirwal, Pramod Rajan K S, and Jeff Goswick | | | | | |
| Unique Verification Case Studies of Low Power Mixed Signal Chips | Jeff Goswick, Venkatesh Ranga, Madhusudhan Subramanya, Anand Shirwal, and Pramod Rajan K S | | | | | |
| Unleashing Portable Stimulus Productivity with a PSS Reuse Strategy | M. Ballance | | | | | |
| Unleashing Portable Stimulus Productivity with a Reuse Strategy | Matthew Balance | | | | | |
| Unleashing the Full Power of UPF Power States | Erich Marschner and John Biggs | | | | | |
| Unleashing the Full Power of UPF Power States | Erich Marschner and John Biggs | | | | | |
| Unleashing the Power of Whisper for block-level verification in high performance RISC-V | Chenhui Huang, Yu Sun ysun, Joe Rahmeh | | | | | |
| Unleashing the Power of Whisper for block-level verification in high performance RISC-V CPU | Chenhui Huang, Yu Sun, Joe Rahmeh | | | | | |
| Unraveling the Complexities of Functional Coverage: An advanced guide to simplify your use model | Thomas Ellis and Rohit Jain | | | | | |
| Unraveling the Complexities of Functional Coverage: An advanced guide to simplify your use model | Thom Ellis and Rohit Jain | | | | | |
| Unveil the Mystery of Code Coverage in Low Power Designs (Achieving Power Aware Verification Closure) | Madhur Bhargava, Durgesh Prasad, and Pavan Rangudu | | | | | |
| Unveil the Mystery of Code Coverage in Low-Power Designs: Achieving Power Aware Verification Closure | Madhur Bhargava, Durgesh Prasad, and Pavan Rangudu | | | | | |
| UPF 1.0, UPF 2.0, UPF 2.1, UPF 3.0, and now UPF 3.1: The big Q “Which is the Right Standard for My Design”? | Madhur Bhargava | | | | | |
| UPF Code Coverage and Corresponding Power Domain Hierarchical Tree for Debugging | Shang-Wei Tu, Tom Lin, Archie Feng, and Chen Ya Ping | | | | | |
| UPF GENERIC REFERENCES: UNLEASHING THE FULL POTENTIAL | Durgesh Prasad and Jitesh Bansal | | | | | |
| UPF Generic References: Unleashing the Full Potential | Jitesh Bansal and Durgesh Prasad | | | | | |
| Use of Aliasing in SystemVerilog Verification Environment | Evean Qin | | | | | |
| Use of Aliasing in SystemVerilog Verification Environment | Evean Qin | | | | | |
| Use of Portable Stimulus to Verify Task Dispatching and Scheduling Functions in an LTE Switch | Adnan Hamid | | | | | |
| User Experiences with the Portable Stimulus Standard | Tom Fitzpatrick, Prabhat Gupta, Mike Chin | | | | | |
| User Experiences with the Portable Stimulus Standard | Tom Fitzpatrick, Prabhat Gupta, Mike Chin | | | | | |
| USF-based FMEDA-driven Functional Safety Verification | Francesco Lertora, Mangesh Mukundrao Pande, Pete Hardee | | | | | |
| Using a modern build system to speed up complex hardware design | Varun Koyyalagunta | | | | | |
| Using a modern software build system to speed up complex hardware design | Varun Koyyalagunta | | | | | |
| Using Advanced OOP Concepts To Integrate Templatized Algorithms for Standard Protocols With UVM | Anunay Bajaj and Gaurav Chugh | | | | | |
| Using Advanced OOP Concepts To Integrate Templatized Algorithms for Standard Protocols With UVM | Anunay Bajaj and Gaurav Chugh | | | | | |
| Using Assertions in an Active W ay to Design and Verify Interface between Analog and Digital B locks | HyunDon Kim, Jiang Long, Wesley Park, ChiHo Cha, JaeBeom Kim, Byeong Min, and KyuMyung Choi | | | | | |
| Using Automation to Close the Loop Between Functional Requirements and Their Verification | Brian Craw, David Crutchfield, Martin Oberkoenig, Markus Heigl, and Martin O’Keeffe | | | | | |
| Using Automation to Close the Loop Between Functional Requirements and Their Verification | Brian Craw, David Crutchfield, Martin Oberkoenig, Markus Heigl, and Martin O’Keeffe | | | | | |
| Using Formal Applications to Create Pristine IPs | Lee Burns, David Crutchfield, and Hithesh Velkooru | | | | | |
| Using Formal Applications to Create Pristine IPs | Lee Burns, David Crutchfield, Bob Metzler, and Hithesh Velkooru | | | | | |
| Using Formal Techniques to Verify SoC Reset Schemes | Kaowen Liu, Penny Yang, Mark Eslinger, Jeremy Levitt, and Matt Berman | | | | | |
| Using Formal Techniques to Verify System on Chip Reset Schemes | Kaowen Liu, Penny Yang, Jeremy Levitt, Matt Berman, and Mark Eslinger | | | | | |
| Using Formal to Exaustively Determine Unsafe Clock Ratios Between Asynchronous Blocks | Eric Hendrickson, Bill Au, Richard Llaca, and Joe Hupcey III | | | | | |
| Using Formal to Exhaustively Determine Unsafe Clock Ratios Between Asynchronous Blocks | Eric Hendrickson, Bill Au, Richard Llaca, and Joe Hupcey III | | | | | |
| Using Formal Verification to Exhaustively Verify SoC Assemblies | Kenny Ranerup and Mark Handover | | | | | |
| Using Formal Verification to Exhaustively Verify SoC Assemblies | Mark Handover and Kenny Ranerup | | | | | |
| Using Machine Learning in Register Automation and Verification | Nikita Gulliya, Abhishek Bora, Nitin Chaudhary, and Amanjyot Kaur | | | | | |
| Using Machine Learning in Register Automation and Verification | Nikita Gulliya, Abhishek Bora, Nitin Chaudhary, and Amanjyot Kaur | | | | | |
| Using Modal Analysis to Increase Clock Domain Crossing (CDC) Analysis Efficiency and Accuracy | Kurt Takara, Gargi Sharma, Ajay Thadhlani, and Bhrugurajsinh Chudasama | | | | | |
| Using Modal Analysis to Increase Clock Domain Crossing (CDC) Analysis Efficiency and Accuracy | Kurt Takara, Gargi Sharma, Ajay Thadhlani, and Bhrugurajsinh Chudasama | | | | | |
| Using Model Checking to Prove Constraints of Combinational Equivalence Checking | Xiushan Feng, Joseph Gutierrez, Mel Pratt, Mark Eslinger, and Noam Farkash | | | | | |
| Using Mutation Coverage for Advanced Bug Hunting | Vladislav Palfy and Nicolae Tusinschi | | | | | |
| Using Portable Stimulus to Verify an ARMv8 Sub-System SoC Integration | Mike Baird and Aileen Honess | | | | | |
| Using Portable Stimulus to Verify an LTE Base-Station Switch | Adnan Hamid | | | | | |
| Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC | Adnan Hamid, David Koogler, and Thomas L. Anderson | | | | | |
| Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC | Adnan Hamid and Raja Pantangi | | | | | |
| Using PSS-2.0 Hardware-Software Interface to validate 4G/5G Forward Error Correction Encoder/Decoder IP in Emulation & Silicon | Vinit Shenoy, Suresh Vasu, Nithin Venkatesh, Suhas Reddy, Joydeep Maitra | | | | | |
| Using Save/Restore is Easy, Right? A User’s Perspective on Deploying Save/Restore in a Mature Verification Methodology | Ed Powell, Ron Thurgood, and Aneesh Samudrala | | | | | |
| Using Save/Restore is easy, Right?A User’s Perspective on Deploying Save/Restore | Ron Thurgood, Ed Powell, and Aneesh Samudrala | | | | | |
| Using Static RTL Analysis to Accelerate Satellite FPGA Verification | Adam Taylor and Dave Wallace | | | | | |
| Using SystemVerilog “Interfaces” as Object-Oriented RTL Modules | Geoff Barnes | | | | | |
| Using SystemVerilog Interfaces and Structs for RTL Design | Tom Symons and Nihar Shah | | | | | |
| Using SystemVerilog Interfaces and Structs for RTL Design | Tom Symons and Nihar Shah | | | | | |
| Using SystemVerilog Packages in Real Verification Proj | Kaiming Ho | | | | | |
| Using Test-IP Based Verification Techniques in a UVM Environment | Vidya Bellippady, Sundar Haran, and Jay O’Donnell | | | | | |
| Using UPF Information Model APIs to write re-usable Low Power Testbenches and customized coverage models for Low Power | Shreedhar Ramachandra and Himanshu Bhatt | | | | | |
| Using UVM Virtual Sequencers & Virtual Sequences | Clifford E. Cummings and Janick Bergeron | | | | | |
| Using UVM: The Condensed Guide For Designers, Debuggers, Test-Writers And Other Skeptics | Gordon Allan | | | | | |
| Using UVM: The Condensed Guide For Designers, Debuggers, Test-Writers And Other Skeptics | Gordon Allan | | | | | |
| Utilizing Technology Implementation Data in blended hardware/software power optimization. | Theodore Wilson and Frank Schirrmeister | | | | | |
| UVM – Stop Hitting Your Brother Coding Guidelines | Rich Edelman and Chris Spear | | | | | |
| UVM – Stop Hitting Your Brother Coding Guidelines | Chris Spear and Rich Edelman | | | | | |
| UVM Acceleration using Hardware Emulator at Pre-silicon Stage | Sunil Roe, YunGi Um, Hyunwoo Koh, Hyunsun Ahn, Youngsik Kim, and Seonil Brian Choi | | | | | |
| UVM Acceleration Using Hardware Emulator at Pre-silicon Stage | Sunil Roe, YunGi Um, Hyunwoo Koh, Hyunsun Ahn, Youngsik Kim, and Seonil Brian Choi | | | | | |
| UVM and C – Perfect Together | Rich Edelman | | | | | |
| UVM and C – Perfect Together | Rich Edelman | | | | | |
| UVM and SystemC Transactions – An Update | David Long and John Aynsley | | | | | |
| UVM and SystemC Transactions – An Update | David Long | | | | | |
| UVM and UPF: an application of UPF Information Model | Amit Srivastava, Harsh Chilwal, and Srivatsa Vasudevan | | | | | |
| UVM and UPF: an application of UPF Information Model | Amit Srivastava, Harsh Chilwal, and Srivatsa Vasudevan | | | | | |
| UVM Based Approach To Model Validation For SV-RNM Behavioral Models | Donald Lewis and Courtney Fricano | | | | | |
| UVM Based Approach To Model Validation For SV-RNM Behavioral Models | Donald Lewis and Courtney Fricano | | | | | |
| UVM Based Mixed-Signal Verification of a Display PMIC Designed for OLED Display Applications | Vijay Kumar & Adnan Malik | | | | | |
| UVM Based Mixed-Signal Verification of a Display PMIC Designed for OLED Display Applications | Vijay Kumar & Adnan Malik | | | | | |
| UVM Do’s and Don’ts for Effective Verification | Kathleen Meade and Sharon Rosenberg | | | | | |
| UVM for HLS: An Expedient Approach to the Functional Verification of HLS Designs | Dave Burgoon and Robert Havlik | | | | | |
| UVM for HLS: An Expedient Approach to the Functional Verification of HLS Designs | Dave Burgoon and Robert Havlik | | | | | |
| UVM IEEE Shiny Object | Rich Edelman | | | | | |
| UVM IEEE Shiny Object | Rich Edelman and Moses Satyasekaran | | | | | |
| UVM Interactive Debug Library: Shortening the Debug Turnaround Time | Horace Chan | | | | | |
| UVM Interactive Debug Library: Shortening the Debug Turnaround Time | Horace Chan | | | | | |
| UVM Layering for Protocol Modeling Using State Pattern | Tony George, Girish Gupta, Shim Hojun, and Byung C. Yoo | | | | | |
| UVM Random Stability | Avidan Efody | | | | | |
| UVM Rapid Adoption: A Practical Subset of UVM | Stuart Sutherland and Tom Fitzpatrick | | | | | |
| UVM Rapid Adoption: A Practical Subset of UVM | Stuart Sutherland and Tom Fitzpatrick | | | | | |
| UVM Reactive Stimulus Techniques | Cliff Cummings, Heath Chambers, and Stephen Donofrio | | | | | |
| UVM Register Modelling at the Integration- Level Testbench | Wayne Yun | | | | | |
| UVM Sans UVM An approach to automating UVM testbench writing | Rich Edelman and Shashi Bhutada | | | | | |
| UVM Sans UVM: An approach to automating UVM testbench writing | Rich Edelman and Shashi Bhutada | | | | | |
| UVM SchmooVM – I Want My C Tests! | Rich Edelman and Raghu Ardeishar | | | | | |
| UVM SchmooVM! – I Want My C Tests! | Rich Edelman and Raghu Ardeishar | | | | | |
| UVM Testbench Automation for AMS Designs | Jonathan David, Henry Chang | | | | | |
| UVM Testbench Automation for AMS Designs | J. B. David, H. Chang | | | | | |
| UVM Testbench Considerations for Acceleration | Kathleen A Meade | | | | | |
| UVM Testbench Considerations for Acceleration | Kathleen A Meade | | | | | |
| UVM testbench design for ISA functional verification of a microprocessor | Gabriel Wang, Hongtao Ma, and Maoduo Sun | | | | | |
| UVM testbench design for ISA functional verification of a microprocessor | Gabriel Wang, Hongtao Ma, and Maoduo Sun | | | | | |
| UVM Transaction Recording Enhancements | Rex Chen, Bindesh Patel, and Jun Zhao | | | | | |
| UVM Update | Srivatsa Vasudevan | | | | | |
| UVM Verification Environment Based on Software Design Patterns | Darko M. Tomušilović and Hagai Arbel | | | | | |
| UVM Verification Environment Based on Software Design Patterns | D. M. Tomušilović and H. J. Arbel | | | | | |
| UVM Working Group Releases 1800.2-2020-2.0 Library | Srivatsa Vasudevan, Jamsheed Agahi, Mark Strickland | | | | | |
| UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer | Marcela Zachariasova, Lubos Moravec, John Stickley, Hans van der Schoot, and Shakeel Jeeawoody | | | | | |
| UVM-based verification of a RISC-V Processor Core Using a Golden predictor model and a Configuration Layer | Marcela Zachariasova, Lubos Moravec, John Stickley, Hans van der Schoot, and Shakeel Jeeawoody | | | | | |
| UVM-FM: Reusable Extension Layer for UVM to Simplify Functional Modeling | Ahmed Kamal | | | | | |
| UVM-FM: Reusable Extension Layer for UVMto Simplify Functional Modeling | Ahmed Kamal | | | | | |
| UVM-SV Feedback Loop – The Foundation of Self-Improving Testbenches | Andrei Vintila, Sergiu Duda | | | | | |
| UVM-SV Feedback Loop – The foundation of Self-Improving Testbenches | Andrei Vintila, Sergiu Duda | | | | | |
| UVM: Conquering Legacy | Santosh Sarma, Amit Sharma, and Adiel Khan | | | | | |
| UVM’s MAM to the Rescue | Michael Baird | | | | | |
| UVM’s MAM to the Rescue | Michael Baird | | | | | |
| UVM/SystemVerilog based infrastructure and testbench automation using scripts | Prakash Parikh | | | | | |
| UVM/SystemVerilog based infrastructure and testbench automation using scripts | Prakash Parikh | | | | | |
| Variation-Aware Modeling Method for MRAM Behavior Model using System-Verilog | S. Do, S. Shin, J. Jang, D. Kim | | | | | |
| Variation-Aware Modeling Method for MRAM Behavior Model using System-Verilog | S. Do, S. Shin, J. Jang, D. Kim | | | | | |
| Verification 2.0 – Multi-Engine, Multi-Run AI Driven Verification | Matt Graham | | | | | |
| Verification Environment Automation from RTL | Zhidong Chen, Yunyang Song, Wenting Hou, Junna Qiao, Junxia Wang, Ling Bai, and Kei-Wang Yiu | | | | | |
| Verification Environment Automation from RTL | Zhidong Chen, Yunyang Song, Wenting Hou, Junna Qiao, Junxia Wang, Ling Bai, and Kei-Wang Yiu | | | | | |
| Verification Learns a New Language: – An IEEE 1800.2 Implementation | Ray Salemi, Tom Fitzpatrick | | | | | |
| Verification Macros: Maintain the integrity of verifiable IP UPF through integration | Amit Srivastava, Shreedhar Ramachandra | | | | | |
| Verification Macros: Maintain the integrity of verifiable IP UPF through integration | Amit Srivastava, Shreedhar Ramachandra | | | | | |
| Verification Mind Games | Jeffrey Montesano and Mark Litterick | | | | | |
| Verification Mind Games | Jeffrey Montesano and Mark Litterick | | | | | |
| Verification of Accelerators in System Context | Russell A. Klein | | | | | |
| Verification of an Image Processing Mixed-Signal ASIC | Kevin Buescher, Milos Becvar, Greg Tumbush, and David Jenkins | | | | | |
| Verification of Clock Domain Crossing Jitter and Metastability Tolerance using Emulation | Ashish Hari, Suresh Krishnamurthy, Amit Jain, and Yogesh Badaya | | | | | |
| Verification of Inferencing Algorithm Accelerators | Russell Klein, Petri Solanti | | | | | |
| Verification Patterns – Taking Reuse to the Next Level | Harry Foster, Michael Horn, Bob Oden, Pradeep Salla, and Hans van der Schoot | | | | | |
| Verification Patterns in the Multicore SoC Domain | Gordon Allan | | | | | |
| Verification Plan in Requirements Management Tool: Simple Traceability and Automated Interface to Regression Manager | Jan Kreisinger, Sanjay Chatterjee | | | | | |
| Verification Plan in Requirements Management Tool: Simple Traceability and Automated Interface to Regression Manager | Jan Kreisinger, Sanjay Chatterjee Allegro MicroSystems | | | | | |
| Verification Reuse for a Non-Transaction Based Design across Multiple Platforms | Luis Li, Pablo Salazar, and Andrés Cordero | | | | | |
| Verification strategy for pipeline type of design | Djuro Grubor | | | | | |
| Verification Strategy for Pipeline Type of Design | Djuro Grubor | | | | | |
| Verification with multi-core parallel simulations: Have you found your sweet spot yet? | Rohit K Jain and Shobana Sudhakar | | | | | |
| Verification with multi-core parallel simulations: Have you found your sweet spot yet? | Rohit K Jain and Shobana Sudhakar | | | | | |
| Verifying clock-domain crossing at RTL IP level using coverage-driven methodology | Jean-François Vizier, Dennis Ramaekers, and Zheng Hai Zhou | | | | | |
| Verifying functionality is simply not enough | Rajesh Bawankule | | | | | |
| Verifying functionality is simply not enough | Rajesh Bawankule | | | | | |
| Verifying Layered Protocols – Leveraging Advanced UVM Capabilities | Parag Goel and Amit Sharma | | | | | |
| Verifying Layered Protocols – Leveraging Advanced UVM Capabilities | Parag Goel | | | | | |
| Verifying Multiple DUV Representations with a Single UVM-e Testbench | Matt Graham | | | | | |
| Verifying Multiple DUV Representations with a Single UVM-e Testbench | Matt Graham | | | | | |
| Verifying RO registers: Challenges and the solution | Ivana Dobrilovic | | | | | |
| Verifying RO registers: Challenges and the solution | Ivana Dobrilovic | | | | | |
| Versatile UVM Scoreboarding | Jacob Andersen, Peter Jensen, and Kevin Steffensen | | | | | |
| Versatile UVM Scoreboarding | Jacob Andersen, Peter Jensen, and Kevin Steffensen | | | | | |
| VHDL 2018 New and Noteworthy | Hendrik Eeckhaut and Lieven Lemiengre | | | | | |
| VHDL 2018: New and Noteworthy | L. Lemiengre and H. Eeckhaut | | | | | |
| VIP Shielding | Jeremy Ridgeway and Karishma Dhruv | | | | | |
| VIP Shielding | Jeremy Ridgeway and Karishma Dhruv | | | | | |
| Virtual Platforms to Shift-Left Software Development and System Verification | Ross Dickson and Pankaj Kakkar | | | | | |
| Virtual Sequencers & Virtual Sequences | Clifford E. Cummings and Janick Bergeron | | | | | |
| Virtual Test: Simulating ATE Vectors in a SystemVerilog Testbench for Faster Time to Market | John Mackintosh, Matthew Borto, Cecil Stone, David Brownell, and Courtney Fricano | | | | | |
| Virtual Test: Simulating ATE Vectors in a SystemVerilog Testbench for Faster Time to Market | John Mackintosh, Matthew Borto, Cecil Stone, David Brownell, and Courtney Fricano | | | | | |
| Want a Boost in your Regression Throughput? Simulate common setup phase only once. | Rohit K Jain and Shobana Sudhakar | | | | | |
| Want a Boost in your Regression Throughput? Simulate common setup phase only once. | Rohit K Jain and Shobana Sudhakar | | | | | |
| Watch Out! Generating Coordinated Random Traffic in UVM | Nigasan Ragunathan, Christine Thomson | | | | | |
| Weathering the Verification Storm: Methodology Enhancements used on a Next Generation Weather Satellite C&DH Program | Michael Donnelly and Michael Horn | | | | | |
| Weathering the Verification Storm: Methodology Enhancements used on a Next Generation Weather Satellite CDH Program | Michael Horn | | | | | |
| What Does The Sequence Say? Powering Productivity with Polymorphism | Rich Edelman | | | | | |
| What Does The Sequence Say? Powering Productivity with Polymorphism | Rich Edelman | | | | | |
| What Ever Happened to AOP? | James Strober, P.Eng, and Corey Goss | | | | | |
| What Ever Happened to AOP? | James Strober, P.Eng, and Corey Goss | | | | | |
| What I Wish My Regression Run Manager’s Vendor Knew! | David Crutchfield, Brian Craw, Jason Lambirth | | | | | |
| What I Wish My Regression Run Manager’s Vendor Knew! | Brian Craw, David Crutchfield, Jason Lambirth | | | | | |
| What is new in IP-XACT Std. IEEE 1685-2022? | Richard Weber, Edwin Dankert | | | | | |
| What Time Is It: Implementing a SystemVerilog Object-Oriented Wrapper for Interacting with the C Library time | Eldon Nelson M.S. P.E. | | | | | |
| What Time Is It: Implementing a SystemVerilog Object-Oriented Wrapper for Interacting with the C Library time | Eldon Nelson M.S. P.E. | | | | | |
| What Your Software Team Would Like the RTL Team to Know. | Josh Rensch | | | | | |
| What’s Next for SystemVerilog in the Upcoming IEEE 1800 standard | Dave Rich | | | | | |
| What’s Next for SystemVerilog in the Upcoming IEEE 1800 standard | Dave Rich | | | | | |
| Where OOP Falls Short of Hardware Verification Needs | Matan Vax | | | | | |
| Who’s Watching the Watchmen? The Time has Come to Objectively Measure the Quality of Your Verification | David Brownell | | | | | |
| Who’s Watching the Watchmen? The Time has Come to Objectively Measure the Quality of Your Verification Environment | David Brownell | | | | | |
| Whose Fault Is It Formally? Formal Techniques for Optimizing ISO 26262 Fault Analysis. | Ping Yeung, Doug Smith, and Abdelouahab Ayari | | | | | |
| Whose Fault Is It Formally? Formal Techniques for Optimizing ISO 26262 Fault Analysis. | Ping Yeung, Doug Smith, and Abdelouahab Ayari | | | | | |
| Whose fault is it? Advanced techniques for optimizing ISO 26262 fault analysis | Avidan Efody | | | | | |
| Whose fault is it? Advanced techniques for optimizing ISO 26262 fault analysis | Avidan Efody | | | | | |
| Why Not “Connect” Using UVM Connect: Mixed Language Communication Got Easier with UVMC | Vishal Baskar | | | | | |
| Why Not “Connect” Using UVM Connect: Mixed Language Communication Got Easier with UVMC | Vishal Baskar | | | | | |
| Wiretap your SoC | Avidan Efody | | | | | |
| Wiretap your SoC: Why scattering Verification IPs throughout your design is a smart thing to do | Avidan Efody | | | | | |
| With Great Power Comes Great Responsibility A method to verify PMICs with UVM-MS | Dor Spigel and Moshik Hershcovitch | | | | | |
| With great power comes great responsibility: A method to verify PMICs using UVM-MS | Dor Spigel and Moshik Hershcovitch | | | | | |
| Without Objection – Touring the uvm_objection implementations – uses and improvements | Rich Edelman | | | | | |
| Without Objection – Touring the uvm_objection implementation – uses and improvements | Rich Edelman | | | | | |
| Working within the Parameters that System Verilog has constrained us to | Salman Tanvir, David Crutchfield, Markus Brosch | | | | | |
| Working within the Parameters that SystemVerilog has constrained us to | Salman Tanvir, David Crutchfield | | | | | |
| Wrapping Verilog Bus Functional Model (BFM) and RTL as Drivers in Customized UVM VIP Using Abstract Classes | Roman Wang and Thomas Bodmer | | | | | |
| Wrapping Verilog Bus Functional Model (BFM) and RTL as Drivers in Customized UVM VIP Using Abstract Classes | Roman Wang and Thomas Bodmer | | | | | |
| X-Propagation Woes: Masking Bugs at RTL and Unnecessary Debug at the Netlist | Lisa Piper and Vishnu Vimjam | | | | | |
| X-propagation Woes: Masking Bugs at RTL and Unnecessary Debug at the Netlist | Lisa Piper | | | | | |
| YAMM Yet Another Memory Manager | Andrei Vintila, Ionut Tolea, and Teodor Vasilache | | | | | |
| Yet Another Memory Manager (YAMM) | Ionut Tolea, Andrei Vintila, and Cosmin-Teodor Vasilache | | | | | |
| Yikes! Why is My SystemVerilog Still So Slooooow? | Cliff Cummings, John Rose, and Adam Sherer | | | | | |
| Yikes! Why is My SystemVerilog Testbench So Slooooow? | Frank Kampf | | | | | |
| Yikes! Why is my SystemVerilog Testbench So Slooooow? | Justin Sprague | | | | | |
| You Are In a Maze of Twisty Little Sequences, All Alike – or Layering Sequences for Stimulus Abstraction | Rich Edelman, Adam Rose, Andreas Meyer, Raghu Ardeishar, and Jason Polychronopoulos | | | | | |
| Your SoC, Your Topology: Interconnects used within SoCs | Ami Pathak, Matt Mangan | | | | | |
