| “Bounded Proof” sign-off with formal coverage | Abhishek Anand, Chinyu Chen, Bathri Narayanan Subramanian, Joe Hupcey | | | | | |
| “C” you on the faster side: Accelerating SV DPI based co-simulation | Parag Goel, Amit Sharma, and Hari Vinodh Balisetty | | | | | |
| “C” you on the faster side: Accelerating SV DPI based co-simulation | Hari Vinod Balisetty, Parag Goel, and Amit Sharma | | | | | |
| “In-Emulator” UVM++ Randomized Testbenches for High Performance Functional Verification | Adnan Hamid and David Kelf | | | | | |
| “Shift left” Hierarchical Low-Power Static Verification Using SAM | Bharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal | | | | | |
| “Shift left” Hierarchical Low-Power Static Verification Using SAM | Bharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal | | | | | |
| “What-If” analysis of Safety Mechanism’s impacts on ETHMAC design under Functional Safety flow | Udaykrishna J, Sujatha Hiremath, Kapil Kumar, Sachin Pathak, Gaurav Goel | | | | | |
| 1,2,3,…8 simple steps towards a single digital signal processing testbench supporting heterogeneous interfaces and datatypes | Nico Lugil | | | | | |
| 1,2,3,…8 simple steps towards a single digital signal processing testbench supporting heterogeneous interfaces and datatypes | Nico Lugil | | | | | |
| 5.1 Smart Verification leveraging PSS; 5.2 When Automotive FuSa Met IC | David Hwang and Sera Gao | | | | | |
| 5G – Chances and Challenges from Test & Measurement Perspective | Meik Kottkamp | | | | | |
| 5G / NR Explained From 3GPP 5G Standard Fundamentals To 5G Enabled Verticals | Michael Faerber and Kilian Roth | | | | | |
| 5G for people and things Spectrum Opportunities and Challenges of 5G | | | | | | |
| A 30 Minute Project Makeover Using Continuous Integration | JL Gray and Gordon McGregor | | | | | |
| A 30 Minute Project Makeover Using Continuous Integration | JL Gray | 2012 | Paper | | y2012 | paper |
| A 360 Degree View of UVM Events | Vikas Billa, Nagesh Kokonda | | | | | |
| A 360 Degree View of UVM Events – A Case Study | Deepak Kumar E V, Sathish Dadi, and Vikas Billa | | | | | |
| A 360 Degree View of UVM Events (A Case Study) | Deepak Kumar E V, Sathish Dadi, and Vikas Billa | | | | | |
| A Client-Server Method for Register Design and Documentation | Scott D Orangio and Julien Gagnon | | | | | |
| A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISC V Core | Junaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, Aashir Ahsan | | | | | |
| A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISCV Core | Junaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, and Aashir Ahsan | | | | | |
| A comparison of methodologies to simulate mixed-signal IC | Simone Fontanesi, Karsten Einwich, Paul Ehrlich, Gaetano Formato, Andrea Possemato | | | | | |
| A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance Analysis | Bishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel | | | | | |
| A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance Analysis. | Bishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel | | | | | |
| A Comprehensive Verification Platform for RISC-V based Processors | Emre Karabulut, Berk Kisinbay, Abdullah Yildiz and Rifat Demircioglu | | | | | |
| A Comprehensive Verification Platform for RISC-V based Processors | Emre Karabulut, Berk Kisinbay, Abdullah Yildiz, and Rifat Demircioglu | 2020 | Presentation | | y2020 | presentation |
| A concept for expanding a UVM testbench to the analog-centric toplevel | Felix Assmann, Axel Strobel and Hans Zander | | | | | |
| A concept for expanding a UVM testbenchto the analog-centric toplevel | Felix Assmann, Axel Strobel and Hans Zander | | | | | |
| A Coverage-Driven Formal Methodology for Verification Sign-off | Ang Li, Hao Chen, Jason K Yu, Ee Loon Teoh, and Iswerya Prem Anand | | | | | |
| A Coverage-Driven Formal Methodology for Verification Sign-off | Ang Li, Hao Chen, Jason K Yu, Ee Loon Teoh and, Iswerya Prem Anand | | | | | |
| A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMS | Muhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, Daniel Große | | | | | |
| A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMS | Muhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, Daniel Große | | | | | |
| A Dyadic Transformation Based Methodology To Achieve Coverage Driven Verification Goal | Swapnajit Mitra | | | | | |
| A Dyadic Transformation Based Methodology to Achieve Coverage Driven Verification Goal | Swapnajit Mitra | | | | | |
| A Dynamic Approach Towards Register Coverage Generation and Collection to Reduce Compilation Overhead of Traditional UVM Register Layers | Subham Banerjee | | | | | |
| A Faster and Efficient Timing Constraint Verification Methodology for GFX SOCs | Vineeth B, Deepmala Sachan | | | | | |
| A Faster and Efficient Timing Constraint Verification Methodology for GFX SOCs | Vineeth B, Deepmala Sachan | | | | | |
| A Formal Verification App Towards Efficient Chip-Wide Clock Gating Verification | Prosenjit Chatterjee, Scott Fields, and Syed Suhaib | | | | | |
| A Formal Verification App Towards Efficient, Chip-Wide Clock Gating Verification | Prosenjit Chatterjee, Scott Fields, and Syed Suhaib | | | | | |
| A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog-AMS | Mike Bartley and Jeganath Gandhi R | | | | | |
| A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog-AMS | Mike Bartley, Jeganath Gandhi R | | | | | |
| A Framework for the Execution of Python Tests in SystemC and Specman Testbenches | Christoph Tietz, Sebastian Stieber , Najdet Charaf, Diana Göhringer | | | | | |
| A Framework for the Execution of Python Tests in SystemC and Specman Testbenches | Christoph Tietz, Sebastian Stieber, Najdet Charaf, Diana Göhringer | | | | | |
| A Framework for Verification of Program Control Unit of VLIW processors | Santhosh Billava, Sharangdhar M Honwadkar | | | | | |
| A Framework for Verification of Program Control Unit of VLIW Processors | Santhosh Billava, Sharangdhar M Honwadkar | | | | | |
| A Generic Approach to Handling Sideband Signals | Markus Brosch and Salman Tanvir | | | | | |
| A Generic Configurable Error Injection Agent for On-Chip Memories | Niharika Sachdeva, Arjun Suresh Kumar, Damandeep Saini, Anil Deshpande, Ravi Teja Gopagiri, Somasunder KS, Jaechul Park | | | | | |
| A Generic Configurable Error Injection Agent for All On-Chip Memories | Niharika Sachdeva, Arjun Suresh Kumar, Raviteja Gopagiri, Anil Deshpande, Somasunder Kattepura Sreenath, Damandeep Saini | | | | | |
| A Generic Configurable Error Injection Agent for All On-Chip Memories | Anil Deshpande, Jaechul Park, Niharika Sachdeva, Arjun Suresh Kumar, Raviteja Gopagiri, Somasund Kattepura Sreenath, Damandeep Saini | | | | | |
| A Generic Configurable Error Injection Agent for On-Chip Memories | Niharika Sachdeva, Arjun Suresh Kumar, Raviteja Gopagiri, Anil Deshpande, Somasunder Kattepura Sreenath | | | | | |
| A Generic Verification Methodology for Chip to Chip Interrupt Handling in a Multi-Chip SoC (3DIC) | Vignesh Adiththan, Padma Vutukuru, Lalithraj Mailappa, Sekhar Dangudubiyyam | | | | | |
| A Generic Verification Methodology for Chip to Chip Interrupt Handling in a Multi-Chip SoC (3DIC) | Vignesh Adiththan, Padma Vutukuru, Lalithraj Mailappa, Sekhar Dangudubiyyam | | | | | |
| A Guide To Using Continuous Integration Within The Verification Environment | Jason Sprott | | | | | |
| A Guide To Using Continuous Integration Within The Verification Environment | Jason Sprott, André Winkelmann, and Gordon McGregor | | | | | |
| A Guide To Using Continuous Integration Within The Verification Environment | André Winkelmann, Jason Sprott, and Gordon McGregor | | | | | |
| A Hardware and Software integrated power optimization approach with power aware simulations at SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A Hardware and Software Integrated Power Optimization Approach with Power Aware Simulations at SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power Intent | Vijay Kumar Sankaran, Lakshmanan Balasubramanian, Bharath Kumar Poluri, Venkatraman Ramakrishnan, Badrinarayan Zanwar, and Qingyu Lin | | | | | |
| A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power Intent | Qingyu Lin | | | | | |
| A Holistic Overview on Preventive & Corrective Action To Handle Glitches | Rohit Kumar Sinha, Parimal Das | | | | | |
| A Holistic View of Mixed-Language IP Integration | Pankaj Singh and Gaurav Kumar Verma | | | | | |
| A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGA | Antonis Papagrigoriou, Miltos D. Grammatikakis and Voula Piperaki | | | | | |
| A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGA* | Antonis Papagrigoriou, Antonis Papagrigoriou and Voula Piperaki | | | | | |
| A Hybrid Verification Solution to RISC V Vector Extension | Chenghuan Li, Yanhua Feng, Liam Li | | | | | |
| A Hybrid Verification Solution to RISC-V Vector Extension | Chenghuan Li, Yanhua Feng, and Liam Li | | | | | |
| A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation | Thomas Soong, Christopher Browne, and Chenhui Huang | | | | | |
| A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation | Thomas Soong, Chenhui Huang, and Christopher Browne | | | | | |
| A Meta-Model-Based Approach for Semantic Fault Modeling on Multiple Abstraction Levels | Michael Schwarz and Moomen Chaari, Bogdan-Andrei Tabacaru | | | | | |
| A Meta-Model-Based Approach for Semantic Fault Modeling on Multiple Abstraction Levels | M. Schwarz M. Chaari, B.-A. Tabacaru, and W. Ecker | | | | | |
| A Meta-Modeling-Based Approach for Automatic Generation of Fault-Injection Processes | Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, and Thomas Kruse | | | | | |
| A Meta-Modeling-Based Approach for Automatic Generation of Fault-Injection Processes | B.-A. Tabacaru, M. Chaari, W. Ecker, and T. Kruse | | | | | |
| A Method to Accelerate SoC Implementation Cycle by Automatically Generating CDC Constraints | Ashish Hari, Sulabh Kumar Khare | | | | | |
| A Methodology for Evaluating SI Artefacts in DDR4-3DS PHY using Channel Modelling | Aditya S Kumar, Gowdra Bomanna Chethan, Shivani Maurya, Anil Deshpande, Somasunder Kattepura Sreenath | | | | | |
| A Methodology for Interrupt Analysis in Virtual Platforms | Puneet Dhar | | | | | |
| A Methodology for Power and Energy Efficient Systems Design | Mohammed Fahad | | | | | |
| A Methodology for Using Traffic Generators with Real-Time Constraints | Avinash Mehta | | | | | |
| A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation Acceleration | Horace Chan, Brian Vandegriend, and Efrat Shneydor | | | | | |
| A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation Acceleration | Horace Chan, Brian Vandegriend, and Efrat Shneydor | | | | | |
| A Methodology to Reuse Unit Level Validation Infrastructure | Ashutosh Parkhi | | | | | |
| A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores | W. W. Chen, N. Tusinschi and T. L. Anderson | | | | | |
| A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores | W. W. Chen, N. Tusinschi, and T. L. Anderson | | | | | |
| A Metric-driven Methodology For Firmware Verification In Simulation/Emulation Environments | Goran Savić | | | | | |
| A Mixed Signal System Design Methodology in SystemC AMS for Automotive Audio Power Amplifiers | Skule Pramm, Joen Westendorp, and Quino Sandifort | | | | | |
| A Mutually-Exclusive Deployment of Formal and Simulation Techniques Using Proof-Core Analysis | Keerthikumara Devarajegowda, Jeroen Vliegen, Goran Petrovity, and Kawe Fotouhi | | | | | |
| A Mutually-Exclusive Deployment of Formal and Simulation Techniques Using Proof-Core Analysis | Keerthikumara Devarajegowda, Jeroen Vliegen, Goran Petrovity, and Kawe Fotouhi | | | | | |
| A New Approach for Generating View Generators | Johannes Schreiner, Felix Willgerodt, and Wolfgang Ecker | | | | | |
| A New Approach for Generating View Generators | Johannes Schreiner, Felix Willgerodt, and Wolfgang Ecker | | | | | |
| A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain Crossings | Omri Dassa and Yossi (Joseph) Mirsky | | | | | |
| A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain Crossings | Omri Dassa, Yossi Mirsky | | | | | |
| A New Approach to Low-Power Verification: Low Power Apps | Madhur Bhargava and Awashesh Kumar | | | | | |
| A New Class Of Registers | M. Peryer and D. Aerne | | | | | |
| A New Class Of Registers | Mark Peryer and David Aerne | | | | | |
| A New Epoch is Beginning: Are You Getting Ready for Stepping Into UVM-1.2? | Roman Wang,Uwe Simm | | | | | |
| A New Epoch is Beginning: Are You Getting Ready for Stepping Into UVM-1.2? | Roman Wang, Uwe Simm | | | | | |
| A NOVEL AND EFFICIENT METHODOLOGY TO EXPEDITE COMPLEX SOC DV CLOSURE BY LEVERAGING MODULARLY ARCHITECTURED SCALABLE ENVIRONMENT | Vinay Swargam, Guttapalem Yatisha, Ayush Agrawal, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A Novel Approach to Accelerate Latency of Assertion Simulation | Jack Yen, Felix Tung | | | | | |
| A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM Domains | Subham Banerjee and Keshava Krishna Raja | | | | | |
| A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM Domains | | | | | | |
| A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoC | Harshal Kothari, Manishadevi Satyanarayana Cheernam, Vignesh Adiththan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | |
| A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoC | Harshal Kothari, Manishadevi Satyanarayana Cheernam, Vignesh Adiththan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | |
| A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoC | Harshal Kothari, Manishadevi Satyanarayana Cheernam, Vignesh Adiththan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | |
| A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development | Harshal Kothari, Vinay Swargam, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development | Harshal Kothari, Vinay Swargam, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development | Harshal Kothari, Vinay Swargam, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A Novel Approach to Functional Test Development and Execution using High-Speed IO | Marcus Schulze Westenhorst, Jörg Simon, Markus Bücker, Klaus Dieter Hilliges, Michael Braun | | | | | |
| A NOVEL APPROACH TO HARDWARE CONTROLLED POWER AWARE VERIFICATION WITH OPTIMISED POWER CONSUMPTION TECHNIQUES AT SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A NOVEL APPROACH TO HARDWARE CONTROLLED POWER AWARE VERIFICATION WITH OPTIMISED POWER CONSUMPTION TECHNIQUES AT SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A Novel Approach to Hardware Controlled Power Aware Verification with Optimized Power Consumption Techniques at SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A Novel Approach To In-System SRAM Repair Verification in Embedded SoC to Bridge Gap between Test and Functional Mode | Harshal Kothari, Eldin Ben Jacob, Ajay Vamshi Krishna, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | |
| A Novel Approach to Reduce Power Consumption By Bridging The Gap between Standalone Functional Scenario and Real Time Scenario at SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A Novel Approach to Reuse Firmware for Verification of Controller based Sub-Systems using PSS | Vishnu Ramadas, Simranjit Singh, Ashwani Aggarwal, Woojoo Space Kim , Seonil Brian Choi | | | | | |
| A novel approach to standardize reusable Modular Plug and Play Skeleton Structure (MPPSS) to expedite verification closure | Himanshu Dixit, Chandrachud Murali, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A novel approach to standardize reusable Modular Plug and Play Skeleton Structure (MPPSS) to expedite verification closure | Chandrachud Murali, Himanshu Dixit, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A Novel Approach to Verify CNN Based Image Processing Unit | Sumit K. Kulshreshtha, Raghavendra J N | | | | | |
| A Novel Performance Evaluation Methodology using Virtual Prototyping and Emulation | Woojoo Space Kim | | | | | |
| A Novel Performance Evaluation Methodology using Virtual Prototyping and Emulation | WoojooSpace Kim | | | | | |
| A Novel Processor Verification Methodology based on UVM | Abhineet Bhojak, Tejbal Prasad, and Stephan Herrmann | | | | | |
| A Novel Variation-Aware Mixed-Signal Verification Methodology to achieve High-Sigma Variation coverage at nanometer designs | Tibi Galambos, Sumit Vishwakarma | | | | | |
| A Practical Approach to Measuring and Improving the Functional Verification of Embedded Software | Stéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès | | | | | |
| A Practical Approach to Measuring and Improving the Functional Verification of Embedded Software | Stéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès | | | | | |
| A Practical Look @ SystemVerilog Coverage – Tips, Tricks, and Gotchas | Doug Smith and John Aynsley | | | | | |
| A Pragmatic Approach Leveraging Portable Stimulus from Subsystem to SoC level and SoC Emulation | Karandeep Singh, Aditya Chopra, Joachim Geishauser, Nitin Verma | | | | | |
| A Pragmatic Approach Leveraging Portable Stimulus from Subsystem to SoC level and SoC Emulation | Karandeep Singh, Aditya Chopra, Joachim Geishauser, Nitin Verma | | | | | |
| A Pragmatic Approach to Metastability-Aware Simulation | Joseph Bulone, Roger Sabbagh | | | | | |
| A Pragmatic Approach to Metastability-Aware Simulation | Joseph Bulone, Roger Sabbagh | | | | | |
| A real world application of IP-XACT for IP packaging Bridging the usability gap | Philip Todd | | | | | |
| A real world application of IP-XACT for IP packaging Bridging the usability gap | Philip Todd | | | | | |
| A Real-World Clock Generator Class for UVM | Rhitam Datta, Ankit Somani | | | | | |
| A Recipe for swift Tape-out of Derivative SoCs: A Comprehensive Validation Approach using Formal-based Sequential Equivalence and Connectivity Checking | Priyanshu Jain, Saket Gaddagi, Sandeep Kumar and Ipshita Tripathi | | | | | |
| A Reconfigurable And Fully Automated SRAM Environment Generation Flow for Robust Verification And To Accelerate DV Closure | Vinay Swargam, Lakshmana Kumar Arumugasamy, Sriram Kazhiyur Sounderrajan | | | | | |
| A Reconfigurable Interface Architecture to Protect System IP | Arshad Riazuddin, Shoab A. Khan | | | | | |
| A Reconfigurable Interface Architecture to Protect System IP | Arshad Riazuddin, Shoab A. Khan | | | | | |
| A Reusability Combat in UVM Callbacks vs Factory | Deepak Kumar EV, Vikas Billa, Satish Dadi, Ranganath Kempanahally | | | | | |
| A Reusable, Scalable Formal App for Verifying Any Configuration of 3D IC Connectivity | Daniel Han, Walter Sze, Benjamin Ting, and Darrow Chu | | | | | |
| A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage | Ashutosh Mishra, Suresh Vasu | | | | | |
| A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage | Ashutosh Mishra, Suresh Vasu | | | | | |
| A Semi-Formal Verification Methodology for Efficient Configuration Coverage of Highly Configurable Digital Designs | Aman Kumar, Sebastian Simon | | | | | |
| A Shift-left Methodology for an Early Power Closure Using EDCs and Power Analysis | Mohammed Fahad | | | | | |
| A shift-left Methodology for an early power closure using PowerPro | Mohammed Fahad | | | | | |
| A Simplified Approach Using UVM Sequence Items for Layering Protocol Verification | Haiqian Yu and Christine Thomson | | | | | |
| A Simplified Approach Using UVM Sequence Items for Layering Protocol Verification | Christine Thomson and Haiqian Yu | | | | | |
| A Simulation Expert’s Guide to Formally Proving SW Status and Interrupts | Neil Johnson | | | | | |
| A Simulation Expert’s Guide to Formally Verifying Software Status and Interrupts | Neil Johnson | | | | | |
| A single generated UVM Register Model to handle multiple DUT configurations | Salvatore Marco Rosselli and Giuseppe Falconeri | | | | | |
| A SMART GENERATION OF DESIGN ATTRIBUTES FOR VERIFICATION CLOSURE USING SPECMAN | Meirav Nitzan, Yael Kinderman, and Efrat Gavish | | | | | |
| A Smart Synchronizer – Pragmatic way to cross asynchronous clock domains | Priyank Parakh and Steven J Kommrusch | | | | | |
| A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic | Priya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed | | | | | |
| A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic | Priya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed | | | | | |
| A Step Towards Zero Silicon Bugs Using Assertion Based Assumption Validation | Rohit Kumar Sinha and Babu Christie | | | | | |
| A Step towards Zero Silicon Bugs: SVA Protocol Based Assumption Validation | Rohit Kumar Sinha and Babu Christie | | | | | |
| A streamlined approach to validate FP matrix multiplication with formal | Gerardo Nahum, Nicolae Tusinschi, Seiya Nakagawa | | | | | |
| A Structured Approach to verify Ties, Unconnected Signals and Parameters | Saurabh Singh, Peter Limmer, and Thomas Luedeke | | | | | |
| A Structured Approach to verify Ties, Unconnected Signals and Parameters | Saurabh Singh, Peter Limmer, and Thomas Luedeke | | | | | |
| A Study on Virtual Prototyping based Design Verification Methodology | Woojoo Kim, Kunhyuk Kang, Seonil Brian Choi | | | | | |
| A Study on Virtual Prototyping based Design Verification Methodology | Woojoo Kim, Kunhyuk Kang, and Seonil Brian Choi. | | | | | |
| A Survey of Machine Learning Applications in Functional Verification | Dan Yu, Harry Foster, Tom Fitzpatrick | | | | | |
| A Systematic Approach to Power State Table (PST) Debugging | Bhaskar Pal | | | | | |
| A Systematic Approach to Power State Table (PST) Debugging | Bhaskar Pal, Suman Nandan, Kaushik De, and Rajarshi Mukherjee | | | | | |
| A Systematic Formal Reuse Methodology: From Blocks to SoC Systems | Hao Chen, Yi Sun, Ang Li, and Dorry Cao | | | | | |
| A Systematic Methodology for Verifying Clock Domain Crossing Reconvergence | Priya Viswanathan | | | | | |
| A Systematic Take on Addressing Dynamic CDC Verification Challenges | Sukriti Bisht, Sulabh Kumar Khare, and Ashish Hari | | | | | |
| A Systematic Take on Addressing Dynamic CDC Verification Challenges | Sukriti Bisht, Sulabh Kumar Khare, and Ashish Hari | | | | | |
| A SystemC Library for Advanced TLM Verification | Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen | | | | | |
| A SystemC Library for Advanced Verification – Towards an Enhanced OVM/UVM for SystemC | Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen | | | | | |
| A SystemC-based UVM verification infrastructure | Mike Bartley and Harshavardhan Narla | | | | | |
| A SystemC-based UVM verification infrastructure | Mike Bartley and Harshavardhan Narla | | | | | |
| A SystemVerilog Framework for Easy Method Advice in Object-oriented Test Benches | Eric Ohana | | | | | |
| A SystemVerilog Framework for Easy Method Advice in Object-oriented Test Benches | Eric Ohana | | | | | |
| A SystemVerilog Framework for Efficient Randomization of Images with Complex Inter-Pixel Dependencies | Axel Voss, Gabriel Jönsson, and Lars Viklund | | | | | |
| A Tale of Two Languages – SystemVerilog and SystemC | David C Black | | | | | |
| A Tale of Two Languages: SystemVerilog & SystemC | David C Black | | | | | |
| A Unified Framework for Multilanguage Verification IPs Integration | Surinder Sood, Selvakumar Krishnamoorthy, Guarav Jalan | | | | | |
| A Unified Testbench Architecture Solution for Verifying Variants of A PLL IP | Deepa Ananthanarayanan and Malathi Chikkanna | | | | | |
| A Unified Testbench Architecture Solution for Verifying Variants of the PLL IP | Deepa Ananthanarayanan and Malathi Chikkanna | | | | | |
| A Universal DFT Verification Environment: Filling the Gap between Function Simulation and ATE Test | Rui Huang | | | | | |
| A Universal DFT Verification Environment: Filling the Gap between Function Simulation and ATE Test | Rui Huang | | | | | |
| A UVM Based Methodology for Processor Verification | Abhineet Bhojak, Stephan Herrmann, and TejbalPrasad | | | | | |
| A UVM Based Methodology for Processor Verification | Abhineet Bhojak, Tejbal Prasad | | | | | |
| A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers | Jaeha Kim | | | | | |
| A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers | Jaeha Kim | | | | | |
| A UVM SystemVerilog Testbench for 5G/LTE Multi-Standard RF Transceiver | Byeong Kyu Kim, Jaeha Kim | | | | | |
| A UVM SystemVerilog Testbench for 5G/LTE Multi-Standard RF Transceiver | ByeongKyu Kim, Jaeha Kim | | | | | |
| A UVM SystemVerilog Testbench for Analog/Mixed-Signal Verification: A Digitally-Programmable Analog Filter Example | Charles Dančak | | | | | |
| A UVM Testbench for Analog Verification: A Programmable Filter Example | Charles Dančak | | | | | |
| A UVM-based Approach for Rapidly Verifying Digital Interrupt Structures | Christoph Rumpler, Alexander W. Rath, and Sebastian Simon | | | | | |
| A UVM-based Approach for Rapidly Verifying Digital Interrupt Structures | Christoph Rumpler, Alexander W. Rath, Sebastian Simon, and Heinz Endres | | | | | |
| A Volterra-Series Model in SystemVerilog/XMODEL for Nonlinear RF Low-Noise Amplifiers | Chan Young Park, Jaeha Kim | | | | | |
| A Wholistic Approach to Optimizing Your System Verification Flow | Ross Dickson, Lance Tamura, Michael Young | | | | | |
| Absolute GLS Verification An Early Simulation of Design Timing Constraints | Ateet Mishra, Deepak Mahajan, Shiva Belwal | | | | | |
| Abstract Layer for Firmware Access: A Unique Approach for SOC Functional Verification | Gupta Girish Kumar, Rugmini Navia Vishnu, Choudhary Praval, Syed Mobeenuddin | | | | | |
| Accelerate Coverage Closure from Day-1 with AI-driven Verification | Malay Ganai, Will Chen, Srikanth Vadanaparthi | | | | | |
| Accelerated Coverage Closure by Utilizing Local Structure in the RTL Code | Rhys Buggy, Gokce Sarar, Guillaume Shippee, Han Nuou, Vishal Karna, Tushit Jain | 2021 | Paper | | y2021 | paper |
| Accelerated simulation through design partition and HDL to C++ compilation | Theta Yang | | | | | |
| Accelerated simulation through design partition and HDL to C++ compilation | Theta Yang and Sga Sun | | | | | |
| Accelerated SOC verification Using UVM Methodology for a Mix-signal Low Power Design | Giuseppe Scata, Ashwini Padoor, Vladimir Milosevic | | | | | |
| Accelerated SOC Verification Using UVM Methodology for a Mixed-Signal Low Power Design | Giuseppe Scata, Ashwini Padoor, Vladimir Milosevic | | | | | |
| Accelerated Verification of NAND Flash Memory using HW Emulator | Seyeol Yang, Byungwoo Kang, Seoyeon Bae, Choi Jaehyeon, Jintae Kim, Dongeun Lee, Junho Ahn | | | | | |
| Accelerated Verification of NAND Flash Memory using HW Emulator | Seyeol Yang, Byungwoo Kang, Seoyeon Bae, Choi Jaehyeon, Jintae Kim, Dongeun Lee, Junho Ahn | | | | | |
| Accelerated, High Quality SoC Memory Map Verification using Formal Techniques | Cletan Sequeira, Rajesh Kedia, Lokesh Babu Pundreeka, and Bijitendra Mittra | 2014 | Paper | | y2014 | paper |
| Accelerated, High Quality SoC Memory Map Verification using Formal Techniques | Cletan Sequeira, Rajesh Kedia, Lokesh Babu Pundreeka, and Bijitendra Mittra | 2014 | Presentation | | y2014 | presentation |
| Accelerating and Improving FPGA Design Reviews Using Analysis Tools | Anna Tseng, Kurt Takara and Abdelouahab Ayari | | | | | |
| Accelerating and Improving FPGA Design Reviews Using Analysis Tools | Abdelouahab Ayari, Anna Tseng, and Kurt Takara | | | | | |
| Accelerating Automotive Ethernet validation by leveraging Synopsys Virtualizer with TraceCompass | Ashish Gandhi, Praveen Kumar Kondugari, and Sam Tennent | | | | | |
| Accelerating Automotive Ethernet validation by leveraging Synopsys Virtualizer with TraceCompass | Ashish Gandhi, Praveen Kumar Kondugari and Sam Tennent | | | | | |
| Accelerating CDC Verification Closure on Gate-Level Designs | Anwesha Choudhury and Ashish Hari | | | | | |
| Accelerating CDC Verification Closure on Gate-Level Designs | Anwesha Choudhury and Ashish Hari | | | | | |
| Accelerating Error Handling Verification of Complex Systems: A Formal Approach | Bhushan Parikh, Peter Graniello, and Neha Rajendra | | | | | |
| Accelerating Error Handling Verification Of Complex Systems: A Formal Approach | Bhushan Parikh, Peter Graniello, Neha Rajendra | | | | | |
| Accelerating Functional Verification Through Stabilization of Testbench Using AI/ML | Srikanth Vadanaparthi, Pooja Ganesh, Dharmesh Mahay, Malay Ganai | | | | | |
| Accelerating Functional Verification Coverage Data Manipulation Using Map Reduce | Eman El Mandouh, A. Gamal, A. Khaled, B. Amr G. Wassal, and Elsayed Hemayed | | | | | |
| Accelerating Functional Verification Coverage Data Manipulation Using Map Reduce | Eman El Mandouh, A. Gamal, A. Khaled, T. Ibrahim, Amr G. Wassal, Elsayed Hemayed | | | | | |
| Accelerating Functional Verification Through Stabilization of Testbench Using AI/ML | Srikanth Vadanaparthi, Pooja Ganesh, Dharmesh Mahay, Malay Ganai | | | | | |
| Accelerating ML TB Integration for Reusability Using UVM ML OA | Saleem Khan, Prasanna Kumar | | | | | |
| Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing Products | Yoga Priya Vadivelu, Arpan Shah, Deepinder Singh Mohoora, Ullas, and Praveen Buddireddy | | | | | |
| Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing Products | Yoga Priya Vadivelu, Arpan Shah, Deepinder Singh Mohoora, Ullas, and Praveen Buddireddy | | | | | |
| Accelerating RTL Simulation Techniques | Lior Grinzaig | | | | | |
| Accelerating RTL Simulation Techniques | Lior Grinzaig | | | | | |
| Accelerating Semiconductor Time to ISO 26262 Compliance | Kirankumar Karanam | | | | | |
| Accelerating SoC Sensor Network Verification Sign-off through Dynamic and Formal Synergy | Vinod Usha, Shreeram Hegde, Prasad Reddy | | | | | |
| Accelerating SoC Sensor Network Verification Sign-off through Dynamic and Formal Synergy | Vinod Usha, Shreeram Hegde, Prasad Reddy | | | | | |
| Accelerating SoC Verification Signoff using Save & Restart/Dynamic Test Reload Enhanced Regression flow | Vanshlata B, Divya M, Garima S, Seonil Brian Choi | | | | | |
| Accelerating SOC Verification Using Process Automation and Integration | Seonghee Yim, Hanna Jang, Sunchang Choi, and Seonil Brian Choi | | | | | |
| Accelerating SOC Verification, Reducing Simulation Turnaround Time & Diskspace Optimization using Dynamic Test Reload (DTR) | Prashant Hota & Shekhar Jha | | | | | |
| Accelerating the IP Design Cycle with Formal Techniques Beyond Everyday FPV | Bhushan Parikh, Shaman Narayana, Buck Lem, David Cassetti | | | | | |
| Accelerating the SoC Integration Verification Cycle Time Leveraging the Legacy Design Confidence | Abhinav Parashar, Prasanth Kumar Narava | | | | | |
| Accelerating the SoC Integration Verification Cycle Time Leveraging the Legacy Design Confidence | Abhinav Parashar, Prasanth Kumar Narava | | | | | |
| Acceleration of Coreless SoC Design-Verification using PSS on Configurable Testbench in Multi-Link PCIe Subsystems | Thanu Ganapathy, Pravin Kumar, Garima Srivastava, Seonil Brian Choi, Harish Peta | | | | | |
| Acceleration of product and test environment development using SystemC-TLM | Florian Barrau, Alexandre Piccini, Alexandre Nabais Moreno, Mark Burton, Luc Michel, Clement Descha | | | | | |
| Acceleration of product and test environment using SystemC TLM | Florian Barrau, Alexandre Piccini, Alexandre Nabais Mark Burton, Luc Michel, and Clement Deschamps | | | | | |
| Acceleration Startup Design & Verification | Tim Sun, Barry Yin, and Haifeng Jiang | | | | | |
| Accellera FS WG Update | Alessandra Nardi, Ghani Kanawati | | | | | |
| Accellera PSS being adopted in real projects Tutorial | Accellera Systems Initiative | | | | | |
| Accellera Systems Initiative SystemC Standards Update | Bishnupriya Bhattacharya | | | | | |
| Accellera Systems InitiativeSystemC Standards Update | Martin Barnasconi, Philipp A. Hartmann, Trevor Wieman | | | | | |
| Accellera Systems InitiativeSystemC Standards Update | Martin Barnasconi, Philipp A. Hartmann, and Stephan Schulz | | | | | |
| Accellera Update | Lu Dai | | | | | |
| Accellera UVM-AMS Standard Update | Tom Fitzpatrick and Tim Pylant | | | | | |
| Accellera, Standards, and Semiconductor Supply Chain | Lu Dai | | | | | |
| Ace’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power Consumption | Mehul Kumar, Tushar Mattu, and Amir Nilipour | | | | | |
| ACE’ing the Verification of a Coherent System Using UVM | Romondy Luo, Ray Varghese, Parag Goel, Amit Sharma, Satyapriya Acharya, and Peer Mohammed | | | | | |
| ACE’ing the Verification of a Coherent System Using UVM | Parag Goel; Amit Sharma, Ray Varghese, Romondy Luo, Satyapriya Acharya, Peer Mohammed | | | | | |
| ACE’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power Consumption | Mehul Kumar, Shawn Honess, Amir Nilipour, and Tushar Mattu | | | | | |
| Achieve Complete SoC Memory Map Verification Through Efficient Combination of Formal and Simulation Techniques | Clemens Roettgermann, Peter Limmer, and Michael Rohleder | | | | | |
| Achieve Complete SoC Memory Map Verification through Efficient Combination of Formal and Simulation Techniques | Clemens Roettgermann, Peter Limmer, and Michael Rohleder | | | | | |
| Achieve Faster Debug Closure by Applying Big Data & Advanced RCA Technologies | Sundararajan Ananthakrishnan, Sundararajan PH | | | | | |
| Achieving Faster Code Coverage Closure using High-Level Synthesis | Surendhar Thudukuchi Chandrapandiyan, Preetham Lakshmikanthan, Ashwani Aggarwal, Youngchan Lee, Youngsik Kim, Seonil Brian Choi | | | | | |
| Achieving Faster Reset Verification Closure with Intelligent Reset Domain Crossings Detection | Milanpreet Kaur and Sulabh Kumar Khare | | | | | |
| Achieving Faster Reset Verification Closure with Intelligent Reset Domain Crossings Detection | Milanpreet Kaur and Sulabh Kumar Khare | | | | | |
| Achieving First-Time Success with a UPF-based Low Power Verification Flow | Kjeld Svendsen, Chuck Seeley, and Erich Marschner | | | | | |
| Achieving Portable Stimulus with Graph-Based Verification – Tutorial | Josef Derner, Holger Horbach, Frederic Krampac, Staffan Berg | | | | | |
| Achieving Real Time Performance for Algorithms Using SOC TLM Model | Saurin Patel, Pushkar Sareen, Sharath Naidu, Baljinder S Sood | | | | | |
| Achieving system dependability: the role of automation and scalability | Alessandra Nardi | | | | | |
| Achieving system dependability: the role of automation and scalability | Teo Cupaiuolo, Paul Baron, Ghani Kanawati | | | | | |
| Activity Trend Guided Efficient Approach to Peak Power Estimation Using Emulation | Gaurav Saharawat, Saurabh Jain, and Madhur Bhatia | | | | | |
| Activity Trend Guided Efficient Approach to Peak Power Estimation Using Emulation | Gaurav Saharawat, Saurabh Jain, and Madhur Bhatia | | | | | |
| Adapting the UVM Register Abstraction Layer for Burst Access | Mark Villalpando | | | | | |
| Adapting the UVM Register Layer for Burst Access | M. P. Villalpando | | | | | |
| Adaptive Test Generation for Fast Functional Coverage Closure | Azade Nazi, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhoseini, Richard Ho | | | | | |
| Adaptive Test Generation for Fast Functional Coverage Closure | Azade Naziz, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhosseiniz, and Richard Ho | | | | | |
| Adaptive UVM AMOD Testbench for Configurable DSI IP | Krishnapal Singh, Pavan Yeluri, Ranjith Nair | | | | | |
| Adding Agility to Hardware Design-Verification using UVM & Assertions | Francois Cerisier, Ajeetha Kumari, Gurubasappa, Srujana Reddy | | | | | |
| Addressing Asynchronous FIFO Verification Challenge | Anchal Gupta, Ashish Hari, Sulabh Kumar Khare | | | | | |
| Addressing Asynchronous FIFO Verification Challenge | Anchal Gupta, Ashish Hari and Sulabh Kumar Khare | | | | | |
| Addressing Challenges in Verification of DSP based Audio IPs using a Novel Hybrid-TestBench Architecture | Suvadeep Bose, Kanak Singh Rajput, Parag S Lonkar, Somasunder K Sreenath | | | | | |
| Addressing HW/SW Interface Quality through Standards | David Murray and Sean Boyan | | | | | |
| Addressing Renewed Gate Level Simulation Needs for 10nm-28nm and Below | Gagandeep Singh | | | | | |
| Addressing Shared IP Instances in a Multi-CPU System Using Fabric Switch A Comprehensive Solution | Priyanka Gharat, Avnita Pal, Sastry Puranapanda | | | | | |
| Addressing Shared IP Instances in a MultiCPU System Using Fabric Switch | Priyanka Gharat, Avnita Pal, Sastry Puranapanda | | | | | |
| Addressing the Challenges of ABV in Complex SOCs | Rithin A N, Arif M, Rupinjeet Singh, Jeevan | | | | | |
| Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail Macros | Brandon Skaggs | | | | | |
| Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail Macros | Brandon S. Skaggs | | | | | |
| Addressing the Challenges of Reset Verification in SoC Designs | Chris Kwok, Priya Viswanathan, and Ping Yeung | | | | | |
| Addressing the Challenges of Reset Verification in SoC Designs | Chris Kwok, Priya Viswanathan, and Ping Yeung | | | | | |
| Addressing the Complex Challenges in Low-Power Design and Verification | Madhur Bhargava, Durgesh Prasad, Jitesh Bansal, and Gabriel Chidolue | | | | | |
| Addressing the Complex Challenges in Low-Power Design and Verification | Madhur Bhargava, Durgesh Prasad, and Jitesh Bansal | | | | | |
| Addressing the verification challenge of SERDES-based FPGAs: The performance/accuracy/efficiency trade-off | Chris Schalick | | | | | |
| Adopting Accellera’s Portable Stimulus Standard: Early Development and Validation using Virtual Prototyping | Simranjit Singh, Ashwani Aggarwal, Harshita Prabha, Vishnu Ramadas, Seonil Brian Choi, Woojoo Space Kim | | | | | |
| Adopting UVM for FPGA Verification | Kamalesh Vikramasimhan, Shridevi Biradar | | | | | |
| Adopting UVM for safety Verification requirements | Srinivasan Venkatarmanan, Hemakiran Kolli, Gurubasappa Kinagi, and Satinder Paul Singh | | | | | |
| Adopting UVM for safety Verification requirements | Srinivasan Venkatarmanan, Hema Kiran, and Satinder Paul Singh | | | | | |
| Advance Approach for Formal Verification of Configurable Pulse Width Modulation Controller | Sumit K. Kulshreshtha, Raghavendra J N | | | | | |
| Advance your Design and Verification Flow Using IP XACT | Edwin Dankert, Maximilian Albrecht and Vincent Thibaut | | | | | |
| Advanced Digital-Centric Mixed-Signal Methodology | Michael Kontz, David Lacey, and Peter Maroni | | | | | |
| Advanced Digital-Centric Mixed-Signal Methodology | Michael Kontz, David Lacey, and Peter Maroni | | | | | |
| Advanced Functional Verification for Automotive System on a Chip | Jaein Hong, Jieun Jeong, Namyoung Kim, Hongkyu Kim, and Sungcheol Park | | | | | |
| Advanced Functional Verification for Automotive System on a Chip | Jaein Hong, Jieun Jeong , Namyoung Kim, Hongkyu Kim, Sungcheol Park, | | | | | |
| Advanced Functional Verification Methodology Using UVM For Complex DSP Algorithms In Mixed Signal RF SoCs | Srinivas Aluri and Jaimin Mehta | | | | | |
| Advanced Functional Verification Methodology Using UVM for complex DSP Algorithms in Mixed Signal RF SoCs | Srinivas Aluri and Jaimin Mehta | | | | | |
| Advanced RISC-V Verification Technique Learnings for SoC Validation | David Kelf, Nambi Ju | | | | | |
| Advanced RISC-V Verification Technique Learnings for SoC Validation | David Kelf, Nambi Ju | | | | | |
| Advanced SOC Randomization Tool for Complex SOC Level Verification | Marvin Mei, Chris Weller, Michael Sedmak, and Zhiqiang Ren | | | | | |
| Advanced specification driven methodology for quick and accurate RDC signoff | Sai Jagadeesh Ambati, Sulabh Kumar Khare, Atul Sharma | | | | | |
| Advanced Techniques for ARM L2 Cache Verification in an Accelerated Hardware and Software environment | Rob Pelt and Jay O’Donnell | | | | | |
| Advanced Techniques for AXI Fabric Verification in a Software/Hardware OVM Environment | Galen Blake and Steve Chappell | | | | | |
| Advanced Techniques to Accomplish Power Aware CDC Verification | Rohit K Sinha, Ashish Hari and Sulabh Kumar Khare | | | | | |
| Advanced Testbench Configuration with Resources | Mark Glasser | | | | | |
| Advanced Usage Models for Continuous Integration in Verification Environments | John Dickol | | | | | |
| Advanced Usage Models for Continuous Integration in Verification Environments | John Dickol | | | | | |
| Advanced UVM Coding Techniques | David Long | | | | | |
| Advanced UVM Command Line Processor | Siddharth Krishna Kumar | | | | | |
| Advanced UVM Command Line Processor for Central Maintenance and Randomization of Control Knobs | Siddharth Krishna Kumar | | | | | |
| Advanced UVM in the real world ‐ Tutorial | Mark Litterick, Jason Sprott, Jonathan Bromley, and Vanessa Cooper | | | | | |
| Advanced UVM Register Modeling | Mark Litterick and Marcus Harnisch | | | | | |
| Advanced UVM Register Modeling | Mark Litterick | | | | | |
| Advanced UVM Tutorial Taking Reuse to the Next Level | Mark Litterick, Jason Sprott, and Jonathan Bromley | | | | | |
| Advanced UVM, Multi-Interface, Reactive Stimulus Techniques | Clifford E. Cummings, Stephen DOnofrio, Jeff Wilcox, Heath Chambers | | | | | |
| Advanced, High Throughput Debug From Design to Silicon | Gordon Allan & Michael Horn | | | | | |
| Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IP | Eldhose P.M, Sagar Jayakrishnan, Suraj Vijay Shetty, Kuntal Pandya, Parag S. Lonkar | | | | | |
| Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IP | Eldhose P.M, Sagar Jayakrishnan, Suraj Vijay Shetty, Kuntal Pandya, Parag S. Lonkar | | | | | |
| Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification Cycle | Charul Agrawal, Ashwin Vijayan, and Jakub Dudek | | | | | |
| Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification Cycle | Charul Agrawal, Ashwin Vijayan, and Jakub Dudek | | | | | |
| Advancing system-level verification using UVM in SystemC | Martin Barnasconi, François Pêcheux, and Thilo Vörtler | | | | | |
| Advancing system-level verification using UVM in SystemC | Martin Barnasconi, François Pêcheux, and Thilo Vörtler | | | | | |
| Advancing the SystemC Ecosystem | Philipp A Hartmann, Jerome Cornet, Martin Scnierginger, and Frederic Doucet | | | | | |
| Advancing traceability and consistency in Verification and Validation | Walter Tibboel and Martin Barnasconi | | | | | |
| Advancing traceability and consistency in Verification and Validation | Walter Tibboel and Martin Barnasconi | | | | | |
| Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC. | Nipun Bhatt | | | | | |
| Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC. | Nipun Bhatt | | | | | |
| Agile and dynamic functional coverage using SQL on the cloud | Filip Dojcinovic and Mihailo Ivanovic | | | | | |
| Agile and dynamic functional coverage using SQL on the cloud | Filip Dojcinovic and Mihailo Ivanovic | | | | | |
| Agile Approaches to ASIC Verification (A3V) – A Novel Agile Flow in Functional Verification | Adithya Rangan, Vidyasagar Kantamneni, Vishal Dalal | | | | | |
| Agile Approaches to ASIC Verification (A3V) – A Novel Agile Flow in Functional Verification | Adithya Rangan CK, Vidyasagar Kantamneni, Vishal Dalal | | | | | |
| Agnostic UVM-XX Testbench Generation | Jacob Andersen, Stephan Gerth, and Filippo Dughetti | | | | | |
| Agnostic UVM-XX Testbench Generation Replace XX (almost) as you see fit! | Jacob Andersen, Stephan Gerth, and Filippo Dughetti | | | | | |
| AI Driven Verification | Curtis Tsai | | | | | |
| Algorithm Verification with Open Source and System Verilog | Andra Socianu and Daniel Ciupitu | | | | | |
| AMS Verification at SoC Level: A Practical Approach for Using VAMS vs SPICE Views | Nitin Pant, Gautham Harinarayan, Manmohan Rana | | | | | |
| AMS Verification in a UVM Environment | Silvia Strähle | | | | | |
| AMS Verification in a UVM Environment | Silvia Strähle | | | | | |
| An Accelerated System Level CPU Verification through Simulation-Emulation Co-Existence | Ruchi Misra, Samridh Deva, Sai Krishna Pallekonda, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi | | | | | |
| An Accelerated System Level CPU Verification through Simulation-Emulation Co-Existence | Ruchi Misra, Samridh Deva, P Sai Krishna, Alok Kumar, Garima Srivastava YoungSik Kim, Seonil Brian Choi | | | | | |
| An Analysis of Stimulus Techniques for Efficient Functional Coverage Closure | Caglayan Yalein, Aileen McCabe | | | | | |
| An Analytical View of Test Results Using CityScapes | Markus Borg, Andreas Brytting, and Daniel Hansson | | | | | |
| An Analytical View of Test Results Using CityScapes | Markus Borg, Andreas Brytting, and Daniel Hansson | | | | | |
| An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 Experience | Mahesha Shankarathota, Vybhava S, and Indrajit Dutta | | | | | |
| An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 Experience | Mahesha Shankarathota, Vybhava S, and Indrajit Dutta | | | | | |
| An Assertion Based Approach to Implement VHDL Functional Coverage | Michael Wazlowski, Susan Eickhoff, Michael Debole, and Tagbo Ekwueme-Okoli | | | | | |
| An Assertion Based Approach to Implement VHDL Functional Coverage | Susan Eickhoff, Michael DeBole, and Tagbo Ekwueme-Okoli | | | | | |
| An Automated Formal Verification Flow for Safety Registers | Holger Busch | | | | | |
| An Automated Formal Verification Flow for Safety Registers | Holger Busch | | | | | |
| An Automated Pre-silicon IP Trustworthiness Assessment for Hardware Assurance | John Hallman, David Landoll, Sergio Marchese, Sven Beyer, Garrett Chan, Salam Zantout and Vikram Rao | | | | | |
| An Automated Pre-silicon IP Trustworthiness Assessment for Hardware Assurance | J. Hallman, D. Landoll, S. Marchese, S. Beyer, G. Chan, S. Zantout, and V. Rao | | | | | |
| An Automated Systematic CDC Verification Methodology based on SDC Setup | Ashish Hari, Sulabh Kumar Khare | | | | | |
| An Automated Validation Framework for Power Management and Data Retention Logic Kits of Standard Cell Library | Akshay Kamath, Bharath Kumar, Sunil Aggarwal, Subramanian Parameswaran, Parag Lonkar, Debi Prasanna, Somasunder Sreenath | | | | | |
| An Automatic Visual System Performance Stress Test for TLM Designs | George F. Frazier, Neeti Bhatnagar, and Woody Larue | | | | | |
| An Easy VE/DUV Integration Approach | Uwe Simm | | | | | |
| An Easy VE/DUV Integration Approach | Uwe Simm | | | | | |
| An Easy VE/DUV Integration Approach | Uwe Simm | | | | | |
| An Effective Design and Verification Methodology for Digital PLL | Biju Viswanathan, Rajagopal P.C, Ramya Nair S. R, Joseph J Vettickatt, and Jobin Cyriac | | | | | |
| An Effective Design and Verification Methodology for Digital PLL | Biju Viswanathan, Rajagopal P.C, Ramya Nair S. R, Joseph J Vettickatt, and Jobin Cyriac | | | | | |
| An efficient analog fault-injection flow harnessing the power of abstraction | Renaud Gillon, Enrico Fraccaroliy, and Franco Fummi | | | | | |
| An Efficient and Modular Approach for Formally Verifying Cache Implementations | M, Achutha KiranKumar V and Abhijith A Bharadwaj | | | | | |
| An Efficient and Modular Approach for Formally Verifying Cache implementations | M Achutha KiranKumar V, Abhijith A Bharadwaj, and Bindumadhava S S | | | | | |
| An Efficient Method to Verify Dynamic IP Clock Frequency on SOC Level by Using Auto-generated Active Clock Monitor | Jaecheon Kim, Gyuhong Lee, Yeonho Jeong, Hyunsun Ahn, Daewoo Kim, Seonil Brian Choi | | | | | |
| An Efficient Methodology for Mutation-Coverage-Collection of Formal-Property-Checking | Holger Busch | | | | | |
| An Efficient Methodology for Mutation-Coverage-Collection of Formal-Property-Checking | Holger Busch | | | | | |
| An efficient requirements-driven and scenario-driven verification flow | Heino van Orsouw | | | | | |
| An efficient requirements-driven and scenario-driven verification flow | Walter Tibboel, Heino van Orsouw, and Shuang Han | | | | | |
| An Efficient Verification Framework for Audio/Video Interface Protocols | Noha Shaarawy, Mustafa Khairallah, Khaled Khalifa, Hany Salah, Amr Salah and Maged Ghoneima | | | | | |
| An Efficient Verification Methodology to Achieve DV Sign-off with Emphasis on Quality and Quicker DV Cycle | Piyush Agnihotri, Nirmal Kumar, Arnab Ghosh, Parag S Lonkar | | | | | |
| An Efficient Verification Methodology to Achieve DV Sign-off with Emphasis on Quality and Quicker DV Cycle | Piyush Agnihotri, Nirmal Kumar, Arnab Ghosh, Parag S Lonkar | | | | | |
| An end-to-end approach to Design and Verify Battery Management Systems: from Requirements to Virtual Field Testing | Irina Costachescu, Marius-Lucian Andrei, Manuel Fedou, Conrado Ramirez Garcia, | | | | | |
| An end-to-end approach to Design and Verify BMS: from Requirements to Virtual Field Testing | Conrado Ramirez, Irina Costachescu, Marius Andrei, Carlos Villegas | | | | | |
| An Enhanced DV Approach for Effectively Verifying High Speed, Low Power MIPI-MPHY 5.0 Designs | Eldhose PM, Kuntal Pandya, Sagar Jayakrishanan, Suraj Vijay Shetty, Parag S Lonkar | | | | | |
| An Enhanced DV Approach for Effectively Verifying High Speed, Low Power MIPI-MPHY5.0 Designs | Eldhose P.M, Sagar Jayakrishnan, Suraj Vijay Shetty, Kuntal Pandya, Parag S. Lonkar | | | | | |
| An Enhanced Stimulus and Checking Mechanism on Cache Verification | Chenghuan Li, Xiaohui Zhao, and Yunyang Song | | | | | |
| An Equivalent Modeling Approach for High-Density DRAM Array System-Level Design-Space Exploration in SystemVerilog | Seyoung Kim, Jaeha Kim | | | | | |
| An Experience of Complex Design Validation: How to Make Semiformal Verification Work | Sabih Agbaria, Dan Carmi, Orly Cohen, Dmitry Korchemny, Michael Lifshits, and Alexander Nadel | | | | | |
| An experience to finish code refinement earlier at behavioral level | Dae-Han Youn, Sik Kim, Byeong Min, and Kyu-Myung Choi | | | | | |
| An Expert System Based Tool for Pre-design Chip Power Estimation | Bhanu Singh, Arunprasath Shankar, Francis Wolff, and Christos Papachristou | | | | | |
| An Expert System Based Tool for Pre-design Chip Power Estimation | Bhanu Singh, Arunprasath Shankar, Francis Wolff, and Christos Papachristou | | | | | |
| An Industry Proven UVM Reuse Methodology for Coverage Driven Block Level Verification to SW Driven Chip Level Verification Across Simulation & Emulation | Pradeep Salla, Keshav Joshi | | | | | |
| An Innovative Methodology for RTL and Verification IP Sharing Between Two Projects | Albert Xu and Joonyoung Kim | | | | | |
| An Innovative Methodology for RTL and Verification IP Sharing Between Two Projects | Albert Xu and Joonyoung Kim | | | | | |
| An Innovative Methodology for Verifying Mixed-Signal Components | Fabian Delguste and Graeme Nunn | | | | | |
| An Integrated Framework for Power Aware Verification | Harsh Chilwal, Manish Jain, and Bhaskar Pal | | | | | |
| An Introduction to the Accellera Portable Stimulus Standard | Srivatsa Vasudevan, Pradeep Salla, Sharon Rosenberg, Adnan Hamid, Karthick Gururaj, Srivatsa Vasudevan, Bishnupriya Bhattacharya | | | | | |
| An Introduction to using Event-B for Cyber-Physical System Specification and Design | John Colley and Michael Butler | | | | | |
| An Open and Fast Virtual Platform for TriCore™-based SoCs Using QEMU | Bastian Koppelmann, Bernd Messidat, Markus Becker, and Christoph Kuznik | | | | | |
| An Open and Fast Virtual Platform for TriCore™-based SoCs Using QEMU | Bastian Koppelmann | | | | | |
| An open and flexible SystemC to VHDL workflow for rapid prototyping | Bastian Farkas, Syed Abbas Ali Shah, Jan Wagner, Rolf Meyer, Rainer Buchty, and Mladen Berekovic | | | | | |
| An open and flexible SystemC to VHDL workflow for rapid prototyping | Bastian Farkas | | | | | |
| An Overview of Ethernet 10Base-T1S in Automotive SoC and its Verification | Bipul Halder, Jagtar Singh, Sahana S, Pushpal Nautiyal, Gaurav Chugh | | | | | |
| An Overview of Security Annotation for Electronic Design Integration (SA-EDI) Standard | Sohrab Aftabjahani | | | | | |
| Analog Modelling to Suit Emulation for Hardware-Software Co-Verification | Saranya Das | | | | | |
| Analog Modelling to Suit Emulation for Hardware-Software Co-Verification | Saranya Das | | | | | |
| Analog Transaction Level Modeling for Verification of Mixed-Signal-Blocks | Alexander W. Rath, Volkan Esen, and Wolfgang Ecker | | | | | |
| Analog Transaction Level Modeling for Verification of Mixed-Signal-Blocks | Alexander W. Rath | | | | | |
| Analysis of TLM-2.0 and it’s Applicability to Non Memory Mapped Interfaces | Guillaume Delbergue, Mark Burton, and Bertrand Le Gal and Christophe Jego | | | | | |
| Analysis of TLM-2.0 and it’s Applicability to Non Memory Mapped Interfaces | Delbergue Guillaume | | | | | |
| Apples versus Apples HVL Comparison Finally Arrives Comparing OVM SystemVerilog to OVM e | Brett Lammers and Riccardo Oddone | | | | | |
| Application Abstraction Layer: The Carpool Lane on the SoC Verification Freeway | Abhisek Verma, Varun S, and Subramanian Kuppusamy | | | | | |
| Application Abstraction Layer: The Carpool Lane on the SoC Verification Freeway | Abhisek Verma, Varun S, and Subramanian Kuppusamy | | | | | |
| Application of SystemC/SystemC-AMS in 3G Virtual Prototyping | Tao Huang and Stefan Heinen | | | | | |
| Application Optimized HW/SW Design & Verification of a Machine Learning SoC | Lauro Rizzatti, Russell Klein, Stephen Bailey, and Andrew Meier | | | | | |
| Applying Big Data to Next-Generation Coverage Analysis and Closure | Tom Fitzpatrick, Darron May, Thom Ellis, Athira Panicker and Francisco Chen | | | | | |
| Applying Design Patterns to accelerate development of reusable, configurable and portable UVCs. | | | | | | |
| Applying Design Patterns to Maximize Verification Reuse at Block, Subsystem and System on Chip Level | Paul Kaunds, Revati Bothe and Jesvin Johnson | | | | | |
| Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical Properties | K. Selyunin, T. Nguyen, A.D. Basa, E. Bartocci, D. Nickovic, and R. Grosu | | | | | |
| Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical Properties | Konstantin Selyunin, Thang Nguyen, Andrei-Daniel Basa, Ezio Bartocci, Dejan Nickovic, and Radu Grosu | | | | | |
| Applying Test-Driven Development Methods to Design Verification Software | Doug Gibson and Mike Kontz | | | | | |
| Applying Test-Driven Development Methods to Design Verification Software in UVM-e | Doug Gibson and Mike Kontz | | | | | |
| Applying Transaction-level Debug and Analysis Techniques to DUT Simulated Activity Using Data- Mining Techniques | Leo Chai, Bindesh Patel, and Jun Zhao | | | | | |
| Applying Transaction-level Debug and Analysis Techniques to DUT Simulated Activity Using Data-Mining Techniques | Leo Chai, Jun Zhao, and Bindesh Patel | | | | | |
| ARC EM Core with Safety Package – ISO 26262 Certification | Vikas Bhandari | | | | | |
| Architecting “Checker IP” for AMBA protocols | Srinivasan Venkataramanan and Ajeetha Kumari | | | | | |
| Architecting “Checker IP” for AMBA protocols | Ajeetha Kumari and Srinivasan Venkataramanan | | | | | |
| Architectural Evaluation Of a Programmable Accelerator For Baseband, Phy and Video Applications Using High Level Synthesis | Andy Fox, Tigran Sargsyan, and Steven Anderson | | | | | |
| Architectural Evaluation of a Programmable Accelerator for Baseband, Phy and Video Applications using High Level Synthesis | Andy Fox, Tigran Sargsyan, and Steven Anderson | | | | | |
| Architectural Formal Verification of System-Level Deadlocks | Mandar Munishwar and Vigyan Singhal | | | | | |
| Architectural Formal Verification of System-Level Deadlocks | Mandar Munishwar1, Naveed Zaman, Anshul Jain, HarGovind Singh, and Vigyan Singhal | | | | | |
| Architecturally Scalable Testbench for Complex SoC | Senthilnath Subbarayan, Arulanandan Jacob, Sandeep Kumar | | | | | |
| Architectures to tradeoff performance vs debug for software development on emulation platforms | Loganath Ramachandran, Ragavendar Swamisai, Makato Ikeda | | | | | |
| Architectures to Tradeoff Performance vs. Debug for Software Development on Emulation Platform | Loganath Ramachandran, Ragavendar Swamisai, Makato Ikeda | | | | | |
| Are OVM & UVM Macros Evil? A Cost-Benefit Analysis | Adam Erickson | | | | | |
| Are you really confident that you are getting the very best from your verification resources? | Darron May and Fritz Ferstl | | | | | |
| Are you really confident that you are getting the very best from your verification resources? | Darron May and Fritz Ferstl | | | | | |
| Are You Safe Yet? Safety Mechanism Insertion and Validation | Ping Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen | | | | | |
| Are You Safe Yet? Safety Mechanism Insertion and Validation | Ping Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen | | | | | |
| Are You Smarter Than Your Testbench? With a little work you can be. | Rich Edelman and Raghu Ardeishar | | | | | |
| Are You Smarter Than Your Testbench? With a little work you could be | Rich Edelman and Raghu Ardeishar | | | | | |
| ASIC-Strength Verification in a Fast-Moving FPGA World | Bryan Murdock | | | | | |
| ASIC-Strength Verification in a Fast-Moving FPGA World | Bryan Murdock | | | | | |
| ASIL B/D Fault Campaign Strategy for Computer Vision core using Soft Test Library (STL) | Shiva Pokala, Vasista A | | | | | |
| Assertion Based Self-checking of Analog Circuits for Circuit Verification and Model Validation in SPICE and Co-simulation Environments | Lakshmanan Balasubramanian, Pooja Sundar, and Timothy W Fischer | | | | | |
| Assertion-based Verification for Analog and Mixed Signal Designs | Srinivas Aluri | | | | | |
| Assertion-based Verification for Analog andMixed Signal Designs | Srinivas Aluri | | | | | |
| Assisting Fault Injection Simulations for Functional Safety Sign-off using Formal | Pulicharla Ravindrareddy | | | | | |
| Assisting Fault Injection Simulations for Functional Safety Sign-off using Formal | Pulicharla Ravindrareddy | | | | | |
| Asynchronous Behaviors Meet Their Match with SystemVerilog Assertions | Doug Smith | | | | | |
| Attack Your SoCPowerChallenges with Virtual Prototyping | Stefan Thiel and Gunnar Braun | | | | | |
| Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor Core | Wei Foong Thoo and David A. Burgoon | | | | | |
| Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor Core | Wei Foong Thoo and David A. Burgoon | | | | | |
| Automate and Accelerate RISC-V Verification by Compositional Formal Methods | Yean-Ru Chen, Cheng-Ting Kao, Yi-Chun Kao, Tien-Yin Cheng, Chun-Sheng Ke and Chia-HaoHsu | | | | | |
| Automate and Accelerate RISC-V Verification by Compositional Formal Methods | Yean-Ru Chen, Cheng-Ting Kao, Yi-Chun Kao, Tien-Yin Cheng, Chun-Sheng Ke and Chia-Hao Hsu | | | | | |
| Automate Interrupt Checking with UVM Macros and Python | Aleksandra Dimanic, Nemanja Stevanovic, Yoav Furman, Itay Henigsberg | | | | | |
| Automate Interrupt Checking with UVM Macros and Python | Aleksandra Dimanic, Nemanja Stevanovic, Yoav Furman, Itay Henigsberg | | | | | |
| Automated approach to Register Design and Verification of complex SOC | Ballori Banerjee, Subashini Rajan, and Silpa Naidu | | | | | |
| Automated code generation for Early AURIX TM VP | Pratheek Mahesh and Dineshkumar Selvaraj | | | | | |
| Automated code generation for Early AURIX TM VP | Pratheek Mahesh and Dineshkumar Selvaraj | | | | | |
| Automated Comparison of Analog Behavior in a UVM Environment | Sebastian Simon | | | | | |
| Automated Comparison of Analog Behavior in a UVM Environment | Sebastian Simon, Alexander W. Rath, Volkan Esen, and Wolfgang Ecker | | | | | |
| Automated Configuration of System Level C-Based CPU Testbench in Modern SoCs : A Novel Framework | Ruchi Misra, Chetan Kulkarni, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi | | | | | |
| Automated Configuration of System Level C-Based CPU Testbench in Modern SoCs : A Novel Framework | Ruchi Misra, Chetan Kulkarni, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi | | | | | |
| Automated Configuration of Verification Environments using Specman Macros DVcon Europe 2018 – Paper number 260-OH22 | Milos Mirosavljevic, Ron Sela, Dejan Janjic and Efrat Shneydor | | | | | |
| Automated Configuration of Verification Environments using SpecmanMacros | Milos Mirosavljevic, Ron Sela, Dejan Janjic and Efrat Shneydor | | | | | |
| Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal Verification | Samantha Pandez, Christopher Geen | | | | | |
| Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal Verification | Samantha Pandez Christopher Geen | | | | | |
| Automated correct-by-construct methodology for RTL design and analog mixed-signal test bench generation: Enables early design closure of mixed-signal SoC | Lakshmanan Balasubramanian, Murugesh Prashanth Subramaniam, Atul Ramakant Lele, and Ranjit Kumar Dash | | | | | |
| Automated Creation of Reusable Generators for Analog IC Design with the Intelligent IP Method | Uwe Eichler, Benjamin Prautsch, Torsten Reich | | | | | |
| Automated Creation of Reusable Generators for Analog IC Design with the Intelligent IP Method | Uwe Eichler, Benjamin Prautsch, Torsten Reich | | | | | |
| Automated Floating Trash Collecting Boat | Karamalaputti Rahul, Gandham Magaraju | | | | | |
| Automated Generation of RAL-based UVM Sequences | Satyajit Sinari, Timothy McLean, Benjamin Applequist, Vijayakrishnan Rousseau, and Geddy Lallathin | | | | | |
| Automated Generation of RAL-based UVM Sequences | Vijayakrishnan Rousseau, Satyajit Sinari, Benjamin Applequist, Timothy McLean, and Geddy Lallathin | | | | | |
| Automated Modeling Testbench Methodology Tested with four Types of PLL Models | Jun Yan, Josh Baylor | | | | | |
| Automated Modeling Testbench Methodology Tested with four Types of PLL Models | Automated Modeling Testbench Methodology Tested with four Types of PLL Models | | | | | |
| Automated Performance Verification to Maximize your ARMv8 pulling power | Nick Heaton and Simon Rance | | | | | |
| Automated Performance Verification to Maximize your ARMv8 pulling power | Nick Heaton and Simon Rance | | | | | |
| Automated Physical Hierarchy Generation: Tools and Methodology | Ali El-Zein, Alvan Ng, Benedikt Geukes, Maya H. Safieddine, and Wolfgang Roesner | | | | | |
| Automated Physical Hierarchy Generation: Tools and Methodology | Ali El-Zein, Alvan Ng, Benedikt Geukes, Maya H. Safieddine, and Wolfgang Roesner | | | | | |
| Automated RTL Update for Abutted Design | Wonkyung Lee, Ayoung Kwon, Soyeong Kwon, Youngsik Kim, and Seonil Brian Choi | | | | | |
| Automated RTL Update for Abutted Design | Wonkyung Lee, Ayoung Kwon, Soyeong Kwon, Youngsik Kim, and Seonil Brian Choi | | | | | |
| Automated Safety Verification for Automotive Microcontrollers | H. Busch | | | | | |
| Automated Safety Verification for Automotive Microcontrollers | Holger Busch | | | | | |
| Automated Seed Selection Algorithm for an Arbitrary Test Suite | David Crutchfield, Brian Craw, Jim Sharpe, and Brandon Skaggs | | | | | |
| Automated Seed Selection Algorithm for an Arbitrary Test Suite | David Crutchfield, Brian Craw, Jim Sharpe, and Brandon Skaggs | | | | | |
| Automated Specification Driven Verification by Generation of SystemVerilog Assertions | Ferdinando Pace | | | | | |
| Automated Specification Driven Verification by Generation of SystemVerilog Assertions | Ferdinando Pace | | | | | |
| Automated SystemC Model Instantiation with modern C++ Features and sc_vector | Ralph Görgen and Philipp A. Hartmann | | | | | |
| Automated SystemC Model Instantiation with modern C++ Features and sc_vector | Ralph Görgen, Philipp A. Hartmann, and Wolfgang Nebel | | | | | |
| Automated Test Generation to Verify IP Modified for System Level Power Management | Christophe Lamard | | | | | |
| Automated Test Generation to Verify IP Modified for System Level Power Management | Christophe Lamard and Frederic Dupuis | | | | | |
| Automated Thread Evaluation of Various RISC-V Alternatives using Random Instruction Generation | Endri Kaja, Nicolas Gerlin, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker | | | | | |
| Automated Thread Evaluation of Various RISC-V Alternatives using Random Instruction Generators | Endri Kaja, Nicolas Gerlin, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker | | | | | |
| Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual Prototype | S N Ranjan and Puttaiah Jagadish | | | | | |
| Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual Prototype | S N Ranjan and Puttaiah Jagadish | | | | | |
| Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual Prototype | S N Ranjan and Puttaiah Jagadish | | | | | |
| Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual Prototype | S N Ranjan and Puttaiah Jagadish | | | | | |
| Automated traceability of requirements in the design and verification process of safety-critical mixed-signal systems | Gabriel Pachiana, Maximilian Grunwald, Thomas Markwirth, Christoph Sohrmann | | | | | |
| Automated Traffic Simulation Framework for SoC Performance Analysis | Diviya Jain, Tarun Kathuria | | | | | |
| Automated vManager regression using Jenkins | Sneha Gokarakonda | | | | | |
| Automated, Systematic CDC Verification Methodology Based on SDC Setup | Ashish Hari, Sulabh Kumar Khare | | | | | |
| Automatic Debug Down to the Line | Daniel Hansson and Patrik Granath | | | | | |
| Automatic Debug Down to the Line of Code | Daniel Hansson and Patrik Granath | | | | | |
| Automatic Diagram Creation for Design and Testbenches | Paul O’Keeffe, Jamie Beattie and Gian Lorenzo | | | | | |
| Automatic Diagram Creation for Design and Testbenches | Paul O’Keeffe, Jamie Beattie, and Gian Lorenzo | | | | | |
| Automatic Exploration of Hardware/Software Partitioning | Syed Abbas Ali Shah, Sven Alexander Horsinka, Basitan Farkas, Rolf Meyer, and Malden Berekovic | | | | | |
| Automatic Exploration of Hardware/Software Partitioning | Syed Abbas Ali Shah, Sven Alexander Horsinka, Basitan Farkas, Rolf Meyer, and Malden Berekovic | | | | | |
| Automatic Firmware Design for Application-specific Electronic Systems: Opportunities, Challenges and Solutions | Daniel Große, Joscha Benz, Vladimir Herdt, and Martin Dittrich | | | | | |
| Automatic Firmware Verification for Automotive Applications | Torsten Andre and Daniel Valtiner | | | | | |
| Automatic Firmware Verification for Automotive Applications | Torsten Andre and Daniel Valtiner | | | | | |
| Automatic Generation of Formal Properties for Logic Related to Clock Gating | Shuqing Zhao and Shan Yan | | | | | |
| Automatic Generation of Formal Properties for Logic Related to Clock Gating | Shuqing Zhao and Shan Yan | | | | | |
| Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDL | Nikita Gulliya, Sudhir Bisht | | | | | |
| Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDL | Sudhir Bisht, Nikita Gulliya | | | | | |
| Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDL | Sudhir Bisht | | | | | |
| Automatic Generation of Infineon Microcontroller Product Configurations | Prateek Chandra, Leily Zafari, Boyko Traykov | | | | | |
| Automatic Generation of Infineon Microcontroller Product Configurations | Prateek Chandra, Leily Zafari, Boyko Traykov | | | | | |
| Automatic Investigation of Power Inefficiencies | Kuo Kai Hsieh, Li C. Wang, Wen Chen, Monica Farkash, and Jayanta Bhadra | | | | | |
| Automatic Investigation of Power Inefficiency | Kuo-Kai Hsieh, Wen Chen, Monica Farkash, Jayanta Bhadra, and Li-C. Wang | | | | | |
| Automatic Netlist Modifications required by Functional Safety | Harald Lüpken, Dirk Hönicke, and Michael Rohleder | | | | | |
| Automatic Netlist Modifications required by Functional Safety | Harald Lüpken, Dirk Hönicke, and Michael Rohleder | | | | | |
| Automatic Partitioning for Multi-core HDL Simulation | Gaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra | | | | | |
| Automatic Partitioning for Multi-core HDL Simulation | Gaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra | | | | | |
| Automatic SOC Test Bench Creation | David Crutchfield, Mark Glasser, and Stephen Roe | | | | | |
| Automatic SOC Test Bench Creation | David Crutchfield, Mark Glasser, and Stephen Roe | | | | | |
| Automatic Testbench Build to Reduce Cycle Time and Forster Reuse | Joachim Geishauser and Alexander Schilling | | | | | |
| Automatic Testbench Build to Reduce Cycle Time and Foster Reuse | Joachim Geishauser and Alexander Schilling | | | | | |
| Automatic Translation of Natural Language to SystemVerilog Assertions | Abhishek Chauhan | | | | | |
| Automatic Translation of Natural Language to SystemVerilog Assertions | Abhishek Chauhan | | | | | |
| Automatic verification for Assertion Based Verification: How can a SPIRIT IP-XACT extension help? | Sofiene Mejri and Mirella Negro Marcigaglia | | | | | |
| Automatically Synthesizing Higher Level of Protocol Abstraction for Faster Debug and Deeper Insight Into Modern Digital Designs | Alasdair Ferro, Amar Patel, Chris Jones, Yogesh Badaya | | | | | |
| Automating information retrieval from EDA software reports using effective parsing algorithms | Manish Bhati | | | | | |
| Automating sequence creation from a Microarchitecture specification | Subramoni Parameswaran and Ravi Ram | | | | | |
| Automating sequence creation from a microarchitecture specification | Subramoni Parameswaran and Ravi Ram | | | | | |
| Automating the formal verification sign-off flow of configurable digital IP’s | Giovanni Auditore and Giuseppe Falconeri | | | | | |
| Automating the formal verification sign-off flow of configurable digital IP’s | Giovanni Auditore and Giuseppe Falconeri | | | | | |
| Automation for Early Detection of X-propagation in Power-Aware Simulation Verification using UPF IEEE 1801 | Tony Gladvin George, Ramesh Kumar, Kyuho Shim, Karan K, Wooseong Cheong, ByungChul Yoo | | | | | |
| Automation for Early Detection of Xpropagation in Power-Aware Simulation Verification using UPF IEEE 1801 | Tony Gladvin George, Ramesh Kumar, Kyuho Shim, Karan K, Wooseong Cheong, ByungChul Yoo | | | | | |
| Automation Methodology for Bus Performance Verification using IP-XACT | Taeyoung Jeon, Gunseo Koo, Youngsik Kim, Seonil Brian Cho | | | | | |
| Automation Methodology for Bus Performance Verification using IP-XACT | Taeyoung Jeon, Gunseo Koo, Youngsik Kim, Seonil Brian Choi | | | | | |
| Automation of Power On Reset Assertion | Shang-Wei Tu, Penny Yang, Joydeep Gangopadhyay, and Amol Herlekar | | | | | |
| Automation of Reusable Protocol-Agnostic Performance Analysis in UVM Environments | Daniel Carrington, Alan Pippin, and Timothy Pertuit | | | | | |
| Automation of Reusable Protocol-Agnostic Performance Analysis in UVM Environments | D. P. Carrington, A. J. Pippin, and T. Pertuit | | | | | |
| Automation of Waiver and Design Collateral generation for scalable IPs | Gopalakrishnan Sridhar, Vadlamuri Venkata Sateeshm, Midhun Krishna | | | | | |
| Automation of Waiver and Design Collateral Generation on Scalable IPs | Gopalakrishnan Sridhar, Midhun Krishna, Vadlamuri, Venkata Sateesh | | | | | |
| Automotive RADAR Bitfields Verification to support Validation of Silicon bring-up | Amol Dhok, Paulraj M K | | | | | |
| Automotive RADAR Bitfields Verification to support Validation of Silicon bring-up | Amol Dhok, Paulraj M K | | | | | |
| Autonomous Verification: Are We There Yet? | Ajay Singh | | | | | |
| Avoiding Configuration Madness The Easy Way | Rich Edelman | | | | | |
| Avoiding Configuration Madness The Easy Way | Rich Edelman | | | | | |
| Avoiding Confounding Configurations an RDC Methodology for Configurable Designs | Eamonn Quigley, Jonathan Niven, and Kurt Takara | | | | | |
| Avoiding Confounding Configurations An RDC Methodology for Configurable Designs | Eamonn Quigley, Jonathan Niven, and Kurt Takara | | | | | |
| Back to Basics: Doing Formal “The Right Way” | Joseph Hupcey III, Saumitra Goel | | | | | |
| BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering Problem | Debarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, Siddhanth Dhodhi, Spandan Kachhadiya | | | | | |
| BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering Problem | Debarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, and Siddhanth Dhodhi | | | | | |
| Be a Sequence Pro to Avoid Bad Con Sequences | Mark Litterick | | | | | |
| Be a Sequence Pro to Avoid Bad Con Sequences | Jeff Vance, Jeff Montesano, Mark Litterick, and Jason Sprott | | | | | |
| Benefits of PSS coverage at SOC & its limitations | Sundararajan Haran and Saleem Khan | | | | | |
| Benefits of PSS Coverage at SOC and Its Limitations | Sundararajan Haran, Saleem Khan | | | | | |
| Best Practices in Verification Planning | Benjamin Ehlers, Carmen Vargas, and Paul Carzola | | | | | |
| Best Practices in Verification Planning | Benjamin Ehlers and Paul Carzola | | | | | |
| Better Living Through Better Class-Based SystemVerilog Debug | Rich Edelman, Raghu Ardeishar, and John Amouroux | | | | | |
| Better Living Through Better Class-Based SystemVerilog Debug | Rich Edelman, Raghu Ardeishar, and John Amouroux | | | | | |
| Between the Dialog and the Algorithm or Innovative Technological Narratives Leveraging the Idea of Authenticity in a Human Being Visualizing log files enables intuitive comprehension of complex test scenarios | Anna M. Ravitzki and Uri Feigin | | | | | |
| Beyond UVM: Creating Truly Reusable Protocol Layering | Janick Bergeron, Fabian Delguste, Steve Knoeck, Steve McMaster, Aron Pratt, and Amit Sharma | | | | | |
| Beyond UVM: Creating Truly Reusable Protocol Layering | Janick Bergeron | | | | | |
| Bi-Directional UVM Agents and Complex Stimulus Generation for UDN and UPF Pins | Chuck McClish | | | | | |
| Big Data in Verification: Making Your Engineers Smarter | David Lacey, Mike McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson | | | | | |
| Big Data in Verification: Making Your Engineers Smarter | David Lacey, Michael McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson | | | | | |
| Bit density based pre characterization of RAM cells for area critical SOC design | Dilip Kumar Ajay ([email protected]) | | | | | |
| Bit Density-Based Pre-Characterization of RAM Cells for Area Critical SOC Design | Dilip Kumar Ajay | | | | | |
| Blending multiple metrics from multiple verification engines for improved productivity | Darron May and Darren Galpin | | | | | |
| Boost Verification Results by Bridging the Hardware/Software Testbench Gap | Matthew Ballance | | | | | |
| Boost Verification Results by Bridging the Hw/Sw Testbench Gap | Matthew Ballance | | | | | |
| Boost your productivity in FPGA & ASIC design and verification | Bart Brosens | | | | | |
| Boost your productivity in FPGA & ASIC design and verification | Bart Brosens | | | | | |
| Boosting Debug Productivity Practical Applications of Debug Innovations in a UVM World | Joerg Richter | | | | | |
| Boosting Mixed-Signal Design Productivity with FPGA-Based Methods Throughout the Chip Design Process | Gabriel Rutsch, Simone Fontanesi, Steven G. Herbst, Steven Tan Hee Yeng, Andrea Possemato, Gaetano Formato, Mark Horowitz, and Wolfgang Ecker | | | | | |
| BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMS | Ahmed Yehia | | | | | |
| BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMS | Ahmed Yehia | | | | | |
| Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven Generation | Hoang M. Le and Rolf Drechsler | | | | | |
| Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven Generation | Hoang M. Le and Rolf Drechsler | | | | | |
| Break the SoC with Random UVM Instruction Driver | Bogdan Todea, Pravin Wilfred, Madhukar Mahadevappa, Diana Dranga | | | | | |
| Breaking Down Barriers: Seamless Protocol Conversion with UVM Component Layering | Santosh Mahale, Shantanu Lele | | | | | |
| Breaking Down Barriers: Seamless Protocol Conversion with UVM Component Layering | Santosh Mahale, Shantanu Lele | | | | | |
| Bridge the Portable Test and Stimulus to UVM Simulation Environment | Theta Yang and Evean Qin | | | | | |
| Bridge the Portable Test and Stimulus to UVM Simulation Environment | Theta Yang and Evean Qin | | | | | |
| Bridging the gap between TLM-2.0 AT models and RTL – Experiments and Opportunities | Zhu Zhou, Atul Kwatra, Rajesh Gadiyar, and Paul Heraty | | | | | |
| Bring IP Verification Closer to SoC Scalable Methods to Bridge the Gap Between IP and SoC Verification | Gaurav Gupta, Tejbal Prasad, Rohit Goyal, Sachin Jain, Vipin Verma | | | | | |
| Bring IP Verification Closer to SoC Scalable Methods to Bridge the Gap Between IP and SoC Verification | Gaurav Gupta, Tejbal Prasad, Rohit Goyal, Sachin Jain, Vipin Verma | | | | | |
| Bringing Constrained Random into SoC SW-driven Verification | Alberto Allara and Fabio Brognara | | | | | |
| Bringing Constrained Random into SoC SW-driven Verification | Alberto Allara and Fabio Brognara | | | | | |
| BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPS | Prabal K Bhattacharya, Swapnajit Chakraborti, Donald O’Riordan, Vaibhav Bhutani, and Scott Little | | | | | |
| BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPS | Prabal K Bhattacharya, Swapnajit Chakraborti, Scott Little, Donald O’Riordan, and Vaibhav Bhutani | | | | | |
| Bringing DataPath Formal to Designers’ Footsteps | M, Achutha KiranKumar V, Disha Puri, Shriya Dharade | | | | | |
| Bringing Regression Systems into the 21st Century | David Crutchfield | | | | | |
| Bringing Regression Systems into the 21st Century | David Crutchfield and Thom Ellis | | | | | |
| Bringing Reset Domains and Power Domains together – Confronting issues due to UPF Instrumentation | Inayat Ali, Abdul Moyeen, Manish Bhati, Manjunatha Srinivas | | | | | |
| Bringing Reset Domains and Power Domains together – Non resettable registers amplifying issues in Power-Aware RDC Verification due to UPF Instrumentation | Manish Bhati, Inayat Ali | | | | | |
| Bringing Reset Domains and Power Domains Together – Set/Reset Flops Augmenting Complexities in Power-Aware RDC Verification. | Manish Bhati, Manjunatha Srinivas, Abdul Moyeen, Inayat Ali | | | | | |
| Bringing UVM to VHDL | UVVM | | | | | |
| Build Reliable and Efficient Reset Networks with a Comprehensive Reset Domain Crossing Verification Solution | Wanggen Shi, Yuxin You, and Kurt Takara | | | | | |
| Build Reliable and Efficient Reset Networks with a Comprehensive Reset Domain Crossing Verification Solution | Wanggen Shi, Yuxin You, and Kurt Takara | | | | | |
| Building a coherent ESL design and verification eco-system with SystemC, TLM, UVM-SystemC, and CCI | Martin Barnasconi | | | | | |
| Building a Comprehensive Hardware Security Methodology | Anders Nordstrom and Jagadish Nayak | | | | | |
| Building a Virtual Driver for Emulator | Chen Chih-Chiang | | | | | |
| Building And Modelling Reset Aware Testbench For IP Functional Verification | Naishal Shah | | | | | |
| Building Code Generators for Reuse – Demonstrated by a SystemC Generator | Saad Siddiqui and Ulrich Nageldinger | | | | | |
| Building Code Generators for Reuse – Demonstrated by a SystemC Generator | Ulrich Nageldinger and Saad Siddiqui | | | | | |
| Building Confidence in System level CPU Cache Coherency Verification for Complex SoC’s through a Configurable, Flexible and Portable Testbench | Ruchi Misra, Shrinidhi Rao, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi | | | | | |
| Building Confidence in System Level CPU Cache Coherency Verification for Complex SoCs through a Configurable Flexible and Portable Test Bench | S Shrinidhi Rao, Ruchi Misra, Alok Kumar, Garima Srivastava, YoungSik Kim, Seonil Brian Choi | | | | | |
| Building Configurable UVM Testbench for Configurable Design IP (Configurable TB) | Kilaru Vamsikrishna, Sushrut B Veerapur | | | | | |
| Building Portable Stimulus Into your IP-XACT Flow | Petri Karppa, Lauri Matilainen, and Matthew Ballance | | | | | |
| Building Portable Stimulus Into Your IP-XACT Flow | Petri Karppa, Lauri Matilainen, and Matthew Balance | | | | | |
| Building Smart SoCs Using Virtual Prototyping for the Design and SoC Integration of Deep Learning Accelerators | Holger Keding | | | | | |
| Building UVM Testbenches for High Quality Serial Design IPs Modelling real world scenarios | Kilaru Vamsikrishna, Sushrut B Veerapur | | | | | |
| C through UVM: Effectively using C based models with UVM based Verification IP | Chris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile | | | | | |
| C through UVM: Effectively using C based models with UVM based Verification IP | Adiel Khan, Chris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile | | | | | |
| Caching Tool Run Results in Large Scale RTL Development Projects | Ashfaq Khan | | | | | |
| Caching Tool Run Results in Large-Scale RTL Development Projects | Ashfaq Khan | | | | | |
| Cadence vManager Platform and Virtuoso ADE Verifier Leading-edge technologies provide methodology for mixedsignal verification closure | Kawe Fotouhi and Walter Hartong | | | | | |
| Calling All Checkers: Collaboratively Utilizing SVA In UVM Based Simulation | Hui K. Zhang | | | | | |
| Calling All Checkers: Collaboratively Utilizing SVA in UVM Based Simulation | Hui C. K. Zhang | | | | | |
| CAMEL – A Flexible Cache Model for Cache Verification | Yue Liu, Fang Liu, Yunyang Song | | | | | |
| CAMEL: A Flexible Cache Model for Cache Verification | Yue Liu, Fang Liu, and Yunyang Song | | | | | |
| Can Formal Outsmart Synthesis: Improving Synthesis Quality of Results through Formal Methods | Eldon Nelson | | | | | |
| Can My Synthesis Compiler Do That? | Stuart Sutherland and Don Mills | | | | | |
| Can My Synthesis Compiler Do That? | Stuart Sutherland and Don Mills | | | | | |
| Can You Even Debug a 200M+ Gate Design? | Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss | | | | | |
| Can You Even Debug a 200M+ Gate Design? | Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss | | | | | |
| Case Study of Verification Planning to Coverage Closure @Block, Subsystem and System on Chip Level | Paul Kaunds, Revati Bothe, and Jesvin Johnson | | | | | |
| Case Study: Low-Power Verification Success Depends on Positive Pessimism | John Decker | | | | | |
| Case Study: Power-aware IP and Mixed-Signal Veri | Luke Lang | | | | | |
| Case Study: Successes and Challenges of Validation Content Reuse | Mike Chin, Jonathan Edwards, Josh Pfrimmer, and Hooi Jing Tan | | | | | |
| Case-study: Generating A Workload Model of the Chrome Browser from Android Execution Traces For Early Analysis of Power and Performance Trade-offs | Vikrant Kapila, Tim Kogel, Holger Keding, Amit Tara Amit Dudeja, Nishant Gautam | | | | | |
| Catching the low hanging fruits on intel® Graphics Designs | M, Achutha KiranKumar V, Aarti Gupta, Bindumadhava S S, Savitha Manojna, and Abhijith A Bharadwaj | | | | | |
| Centralized Regression Optimisation Toolkit (CROT) for expediting Regression Closure With Simulator Performance Optimisation | Harshal Kothari, Pavan M, Ajay Vamshi Krishna, Eldin Ben Jacob, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | |
| Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation) | Vikas Billa and Sundar Haran | | | | | |
| Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation) | Vikas Billa and Sundar Haran | | | | | |
| Challenges and Solutions for Creating Virtual Platforms of FPGA and SASIC Designs | Kalen Brunham, Jakob Engblom | | | | | |
| Challenges and Solutions for Creating Virtual Platforms of FPGA and SASIC Designs | Kalen Brunham, Jakob Engblom | | | | | |
| Challenges in Mixed Signal Verification | Amlan Chakrabarti, Sachin-Sudhakar Kulkarni | | | | | |
| Challenges in UVM + Python Random Verification Environment for Digital Signal Processing Datapath Design | Shabbar Vejlani and Ashok Chandran | | | | | |
| Challenges in UVM + Python random verification environment for Digital Signal Processing datapath design. | Shabbar Vejlani and Ashok Chandran | | | | | |
| Challenges of Formal Verification on Deep Learning Hardware Accelerator | Yellinidi Dasarathanaidu | | | | | |
| Challenges of Formal Verification on Deep Learning Hardware Accelerator | Yellinidi Dasarathanaidu | | | | | |
| Challenges of VHDL X-propagation Simulations | Karthik Baddam and Piyush Sukhija | | | | | |
| Challenges of VHDL X-propagation Simulations | Karthik Baddam and Piyush Sukhija | | | | | |
| Challenges with Power Aware Simulation and Verification Methodologies | Divyeshkumar Vora | | | | | |
| Challenges, Complexities and Advanced Verification Techniques in Stress Testing of Elastic Buffer in High Speed SERDES IPs | Kamesh Velmail, Suvadeep Bose, Ankit Garg, Parag S Lonkar, Somasunder K Sreenath | | | | | |
| Challenges, Complexities and Advanced Verification Techniques in Stress Testing of Elastic Buffer in High Speed SERDES IPs | Kamesh Velmail, Suvadeep Bose, Parag Lonkar, Ankit Garg | | | | | |
| Channel Modelling in Complex Serial IPs | Jayesh Ranjan Majhi, Saravana Balakrishnan, Navnit Kumar Kashyap | | | | | |
| Channel Modelling in Complex Serial IPs | Jayesh Ranjan Majhi, Saravana Balakrishnan, Navnit Kumar Kashyap | | | | | |
| Characterizing RF Wireless Receivers Performance in UVM Environment | Salwa Elqassas, Salwa Elqassas and Mohammed T. Abdel-Hafe | | | | | |
| Check Low-Power Violations by Using Machine Learning Based Classifier | Chi-Ming Lee, Chung-An Wang, Cheok-Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai | | | | | |
| Check Low-Power Violations by Using Machine Learning Based Classifier | Chi-Ming Lee, Chung-An Wang, Cheok-Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai | | | | | |
| Checking security path with formal verification tool: new application development | Julia Dushina, Saumil Shah, Joerg Mueller, and Vincent Reynolds | | | | | |
| Checking Security Path with Formal Verification Tool: New Application Development | Julia Dushina and Joerg Mueller | | | | | |
| Chef’s Special – an Efficient Verification Recipe for Maximizing Productivity While Using a Third Party Verification IP | Varun S and Bhavik Vyas | | | | | |
| Chiplevel Analog Regressions in Production | Yi Wang | | | | | |
| Choice is Yours: Either Struggle to Tame ‘X’ in the Wilderness of Multimillion Gates and Nets, OR Take it for a Walk in the RTL Park | Nitin Jaiswal, Harsh Garg, Mayank Bindal | | | | | |
| Cleaning Out Your Pipes – Pipeline Debug in UVM Testbenches | Rich Edelman and Neil Bulman | | | | | |
| Cleaning Out Your Pipes – Pipeline Debug in UVM Testbenches | Rich Edelman and Neil Bulman | | | | | |
| Clock Controller Unit Design Metrics: Area, Power, Software Flexibility and Congestion Impacts at System Level | Michele Chilla and Leonardo Gobbi | | | | | |
| CLOCK DOMAIN CROSSING CHALLENGES IN LATCH BASED DESIGNS | Madan Das, PhD, Chris Kwok, and Kurt Takara | | | | | |
| Clock Domain Crossing Challenges in Latch Based Designs | Madan Das, Chris Kwok, and Kurt Takara | | | | | |
| Clock Domain Crossing Verification in Transistor-level Design | Hyungjung Seo, KwangSun Kim, YoungRok Choi, Jihwan Kim, and Jong-Bae Lee | | | | | |
| Closing and Awards | Accellera Systems Initiative | | | | | |
| Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis | Bryan Bowyer | | | | | |
| Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis | B. Bowyer | | | | | |
| Closing Functional Coverage With Deep Reinforcement Learning: A Compression Encoder Example | Eric Ohana | | | | | |
| Closing Functional Coverage With Deep Reinforcement Learning A Compression Encoder Example | Eric Ohana | | | | | |
| Closing the gap between requirement management and system design by requirement tracing | Hayri Verner Hasou, Guillermo Conde, Adrian Rolufs, Dominic Scharfe | | | | | |
| Closing the loop from requirements management to verification execution for automotive applications | Walter Tibboel and Jan Vink | | | | | |
| Closing the loop from requirements management to verification execution for automotive applications | Walter Tibboel and Jan Vink | | | | | |
| Closing with Awards | Accellera Systems Initiative | | | | | |
| Clustering and Classification of UVM Test Failures Using Machine Learning Techniques | Andy Truong, Daniel Hellström, Harry Duque, and Lars Viklund | | | | | |
| Clustering and Classification of UVM Test Failures Using Machine Learning Techniques | Andy Troung, Daniel Hellström, Harry Duque, and Lars Viklund | | | | | |
| Co-Developing Firmware and IP with PSS | M. Ballance | | | | | |
| Co-Developing IP and SoC Bring-Up Firmware with PSS | Matthew Ballance, Siemens EDA | | | | | |
| Co-Simulating Matlab/Simulink Models in a UVM Environment | Neal Okumura and Glenn Richards | | | | | |
| Co-Simulating Matlab/Simulink Models in a UVM Environment | Neal Okumura, Paul Yue, and Glenn Richards | | | | | |
| Code-Test-Verify all for free – Assertions + Verilator | Hemamalini Sundaram, Kasthuri Srinivas, Supriya Ummadisetty | | | | | |
| Code-Test-Verify all for free – Assertions + Verilator | Hemamalini Sundaram, Kasthuri Srinivas, Supriya Ummadisetty | | | | | |
| Coding Guidelines and Code Generation | John Aynsley and Dr. Christoph Sühnel | | | | | |
| Coherency Verification & Deadlock Detection Using Perspec/Portable Stimulus | Moonki Jang and Phu Huynh | | | | | |
| Coherency Verification & Deadlock Detection Using Perspec/Portable Stimulus | Moonki Jang, Jiwoong Kim, Hyerim Chung, Phu L. Huynh, and Shai Fuss | | | | | |
| Combining Simulation with Formal Techniques to Reduce the Overall Verification Cycle | Aneet Agarwal and Gaurav Gupta | | | | | |
| Combining Static and Dynamic Low Power Verification for the Power-Aware SoC Sign-off | Himanshu Bhatt and Prashanth M | | | | | |
| Combining Static and Dynamic Low Power Verification for the Power-Aware SoC Sign-off | Himanshu Bhatt, Prashanth M, and Adiel Khan | | | | | |
| Command Line Debug Using UVM Sequences | Mark Peryer | | | | | |
| Common Challenges and Solutions to Integrating a UVM Testbench | Frank Verhoorn and Mike Baird | | | | | |
| Common Challenges and Solutions to Integrating a UVM Testbench in Place of a Legacy Monolithic Testing Environment | Frank Verhoorn and Michael Baird | | | | | |
| Compact AI accelerator for embedded applications | Alexey Shchekin | | | | | |
| Comparison of TLM2-Quantum Keeping and TLM+-Resource Modeling with regard to Timing in Virtual Prototypes | Wolfgang Ecker, Volkan Esen, Rainer Findenigy, Thomas Leitnerz and Michael Velten | | | | | |
| Complementing EDA with Meta-Modeling and Code Generation | Wolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal | | | | | |
| Complementing EDA with Meta-Modelling & Code Generation | Wolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal | | | | | |
| Complementing EDA with Meta-Modelling and Code Generation | Ecker Wolfgang, Michael Velten, Ajay Goyal, and Leily Zafari | | | | | |
| Complementing Verification of Highly Configurable Design with Formal Techniques | Manik Tyagi, Deepak Jindal | | | | | |
| Complete Formal Verification of a Family of Automotive DSPs | Rafal Baranowski and Marco Trunzer | | | | | |
| Complete Formal Verification of a Family of Automotive DSPs | Rafal Baranowski and Marco Trunzer | | | | | |
| Complex Low Power Verification Challenges in NextGen SoCs : Taming the Beast! | Abhinav Nawal, Gaurav Jain, and Joachim Geishauser | | | | | |
| Complex Low Power Verification Challenges in NextGen SoCs: Taming the Beast! | Abhinav Nawal and Gaurav Jain | | | | | |
| Complex Safety Mechanisms Require Interoperability and Automation For Validation And Metric Closure | Daeseo Cha, Vedant Garg | | | | | |
| Complex Safety Mechanisms Require Interoperability and Automation For Validation And Metric Closure | Daeseo Cha, Vedant Garg, Ann Keffer, Arun Gogineni, James Kim, Woojoo Space Kim, Kunhyuk Kang, Seonil Brian Choi | | | | | |
| Compliance Driven Integrated Circuit Development Based on ISO26262 | Haridas Vilakathara, Manikantan panchapakesan | | | | | |
| Compliance Driven Integrated Circuit Development Based on ISO26262 | Haridas Vilakathara and Manikandan Panchapakesan | | | | | |
| CompMon: Ensuring Rigorous Protocol Specification and IP Compliance | Robert Adler, Sava Krstic and Erik Seligman | | | | | |
| Comprehensive AMS Verification using Octave, Real Number Modelling and UVM | John McGrath, Patrick Lynch, and Ali Boumaalif | | | | | |
| Comprehensive AMS Verification using Octave, Real Number Modelling and UVM | John McGrath, Patrick Lynch, and Ali Boumaalif | | | | | |
| Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain Crossings | Yossi Mirsky B.Sc, M.Sc, MBA | | | | | |
| Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain Crossings | Yossi Mirsky | | | | | |
| Comprehensive Benchmark Results: Comparing Processing-in-Memory Architecture Effectiveness using UPMEM Hardware | Ambati Rajashekar, Pranjit Das, Avi kumar Shrivastava, Partha Acharya | | | | | |
| Comprehensive IP to SoC CDC Verification Using Hybrid Data Model | Anwesha Choudhury and Ashish Hari | | | | | |
| Comprehensive IP to SoC Clock Domain Crossing Verification Using Hybrid Data Mode | Anwesha Choudhury and Ashish Hari | | | | | |
| Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-Chips | Ellie Burns, Gabriel Chidolue, and Guillaume Boillet | | | | | |
| Comprehensive Register Description Languages: The case for standardization of RDLs across design domains | David C Black and Doug Smith | | | | | |
| Comprehensive Systemverilog-Systemc-Vhdl Mixed-Language Design Methodology | Rudra Mukherjee, Gaurav Kumar Verma, and Sachin Kakkar | | | | | |
| Computational Logistics for Intelligent System Design | Simon Chang | | | | | |
| Compute Link Express – CXL – CXL Consortium | Narasimha Babu | | | | | |
| Conditional Delays for Negative Limit Timing Checks in Event Driven Simulation | Nadeem Kalil and David Roberts | | | | | |
| Conditional Delays for Negative Limit Timing Checks in Event Driven Simulation | N. Kalil and D. Roberts | | | | | |
| Confidently Sign-off Any low-Power Designs without Consequences | Madhur Bhargava, Jitesh Bansal, and Progyna Khondkar | | | | | |
| Confidently Sign-Off Any Low-Power Designs Without Consequences | Madhur Bharga, Jitesh Bansal and Progyna Khondkar | | | | | |
| Configurable Testbench (TB) for Configurable Design IP | Kilaru Vamsikrishna, Sushrut B Veerapur | | | | | |
| Configuration Conundrum: Managing Test Configuration with a Bite Sized Solution | Kevin Vasconcellos, Jeff McNeal | | | | | |
| Configuration in UVM:The Missing Manual | Mark Glasser | | | | | |
| Configuration in UVM: The Missing Manual | Mark Glasser | | | | | |
| Configuring Your Resources the UVM Way! | Parag Goel, Amit Sharma, and Rajiv Hasija | | | | | |
| Configuring Your Resources the UVM Way! | Parag Goel, Amit Sharma, and Rajiv Hasija | | | | | |
| Connecting a Company’s Verification Methodology to Standard Concepts of UVM | Frank Poppen, Marco Trunzer, and Jan‐Hendrik Oetjens | | | | | |
| Connecting a Company’s Verification Methodology to Standard Concepts of UVM | Frank Poppen, Marco Trunzer, and Jan‐Hendrik Oetjens | | | | | |
| Connecting Enterprise Applications to Metric Driven Verification | Matt Graham | | | | | |
| Connecting Enterprise Applications to Metric Driven Verification | Matt Graham | | | | | |
| CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITY | Bin Ju | | | | | |
| CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITY | Bin Ju | | | | | |
| CONNECTING UVM WITH MIXED-SIGNAL DESIGN | Ivica Ignjić | | | | | |
| Connecting UVM with Mixed-Signal Design | Ivica Ignjić | | | | | |
| Connectivity and Beyond | Shahid Ikram, Joseph DErrico, Yasmin Farhan, Jim Ellis, and Tushar Parikh | | | | | |
| Connectivity and Beyond | Shahid Ikram, Joseph DErrico, Yasmin Farhan, Jim Ellis, and Tushar Parikh | | | | | |
| Conquer the Graphics Legacy: Develop the Customized UVM VIP Embedded a Cycle-based C++ Reference Model | Roman Wang | | | | | |
| Conscious of Streams Managing Parallel Stimulus | Jeff Wilcox | | | | | |
| Conscious of Streams: Managing Parallel Stimulus | Jeffrey Wilcox and Stephen D’Onofrio | | | | | |
| Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL Synthesis | Rainer Findenig, Thomas Leitner, and Wolfgang Ecker | | | | | |
| CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTION | Martin Fröjd, Adiel Khan, and Jussi Mäkelä | | | | | |
| CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTION | Jussi Mäkelä, Martin Fröjd, and Adiel Khan | | | | | |
| CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTION | Jussi Mäkelä, Martin Fröjd, and Adiel Khan | | | | | |
| Context-Aware DFM Rule Analysis and Scoring Using Machine Learning | Vikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, and Jonathan Ong | | | | | |
| Context-Aware DFM Rule Analysis and Scoring Using Machine Learning | Vikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, and Jonathan Ong | | | | | |
| Conversion of Performance Model to Functional Model | H G Pavan Kumar, Sumail Singh Brar, Ashwani Aggarwal, Seonil Brian Choi, Woojoo Space Kim | | | | | |
| Counterintuitive approaches to have better communication between UVM and Python for registers with Single Controlling Algorithm | Sougata Bhattacharjee | | | | | |
| Coverage Acceleration and Testcase Pruning using Smart Stimuli Generator in SOC Verification | Rahul Laxkar, Naveen Srivastava, Sekhar Dangudubiyyam | | | | | |
| Coverage Acceleration and Testcase Pruning using Smart Stimuli Generator in SOC Verification | Rahul Laxkar, Naveen Srivastava, Sekhar Dangudubiyyam | | | | | |
| Coverage Closure – Is it a “Game of Dice” or “Top 10 Tests” or “Automated Closure”? | Aditya Sharma, T. Nagasundaram, M. Nitin Kumar, Nikhita Raj J | | | | | |
| Coverage Data Exchange is no robbery…or is it? | Darron May and Samiran Laha | | | | | |
| Coverage Data Exchange is no robbery…or is it? | Darron May and Samiran Laha | | | | | |
| Coverage Driven Distribution of Constrained Random Stimuli | Marat Teplitsky, Amit Metodi, and Raz Azaria | | | | | |
| Coverage Driven Distribution of Constrained Random Stimuli | Raz Azaria, Amit Metodi, and Marat Teplitsky | | | | | |
| Coverage Driven Signoff with Formal Verification on Power Management IPs | Baosheng Wang and Xiaolin Chen | | | | | |
| Coverage Driven Signoff with Formal Verification on Power Management IPs | Baosheng Wang and Xiaolin Chen | | | | | |
| Coverage Driven Verification of an Unmodified DUT within an OVM Testbench | Michael Baird | | | | | |
| Coverage Models for Formal Verification | Xiushan Feng, Xiaolin Chen, and Abhishek Muchandikar | | | | | |
| Coverage Models for Formal Verification | Xiushan Feng, Xiaolin Chen, and Abhishek Muchandikar | | | | | |
| COVERGATE: Coverage Exposed | Rich Edelman | | | | | |
| COVERGATE: Coverage Exposed | Rich Edelman | | | | | |
| Covering All the bases: Coverage-driven Formal Verification Sign-off of Pipelined Error Detection Filter | Harbaksh Gupta, Anshul Jain | | | | | |
| Covering All the bases: Coverage-driven Formal Verification Sign-off of Pipelined Error Detection Filter | Harbaksh Gupta, Anshul Jain | | | | | |
| Covering the Last Mile in SoC-Level Deadlock Verification | Jef Verdonck, Khaled Nsaibia, Sagar Dewangan, HarGovind Singh and Roger Sabbagh | | | | | |
| Covering the Last Mile in SoC-Level Deadlock Verification | Jef Verdonck, Dhruv Gupta, and HarGovind Singh | | | | | |
| CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemC | Hoang M. Le and Rolf Drechsler | | | | | |
| CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemC | Hoang M. Le and Rolf Drechsler | | | | | |
| Creating 5G Test Scenarios, the Constrained-Random way | Keshav Kannan and Eric P. Kim | | | | | |
| Creating 5G Test Scenarios, the Constrained-Random way | Keshav Kannan, Eric P. Kim | | | | | |
| Creating a Complete Low Power Verification Strategy using the Common Power Format and UVM | Robert Meyer and Joel Artmann | | | | | |
| Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation Requirements | David Lacey and Ed Powell | | | | | |
| Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation Requirements | David Lacey and Ed Powell | | | | | |
| Cross Coverage of Power States | Veeresh Vikram Singh and Awashesh Kumar | | | | | |
| Cross-Domain Datapath Validation Using Formal Proof Accelerators | Aarti Gupta, S. S. Bindumadhava, M. Achutha KiranKumar V, Liu Jun B | | | | | |
| Customizing UVM Agent Supporting Multi-Layered & TDM Protocols | Amit Pessach | | | | | |
| Customizing UVM Agent Supporting Multi-Layered & TDM Protocols | Amit Pessach | | | | | |
| CXL verification using portable stimulus | Karthick Gururaj | | | | | |
| Data Flow Based Memory IP Creation Infrastructure | Abhilash V Nair, Praveen Buddireddy, Tor Jeremiassen, Rashmi Venkatesh, and Prajakta Bhutada | | | | | |
| Data path verification on cross domain with formal scoreboard | Liu Jun | | | | | |
| Data path verification on cross domain with formal scoreboard | Liu Jun | | | | | |
| Data-Driven Verification: Driving the next wave of productivity improvements | Larry Melling, Chris Komar, Sharon Rosenberg, Michael Young, and Hanan Moller | | | | | |
| DatagenDV: Python Constrained Random Test Stimulus Framework | Jon George, James Mackenzie | | | | | |
| DatagenDV: Python Constrained Random Test Stimulus Framework | Jonathan George, James Mackenzie | | | | | |
| Day 1 Opening | Accellera Systems Initiative | | | | | |
| Day 2 Opening | Accellera Systems Initiative | | | | | |
| DDR Controller IP Evaluation Studies using Trace Based Methodology | Abhilash Nair, Amit Nene, Ritesh Sojitra, Prashant Karandikar and Prajakta Bhutada | 2014 | Paper | | y2014 | paper |
| De-mystifying synchronization between various verification components by employing novel UVM classes | Pushpal Nautiyal and Gaurav Chugh | | | | | |
| De-mystifying synchronization between various verification components by employing novel UVM classes | Pushpal Nautiyal and Gaurav Chugh | | | | | |
| Deadlock Free Design Assurance Using Architectural Formal Verification | Bhushan Parikh, Shaman Narayana | | | | | |
| Deadlock Free Design Assurance Using Architectural Formal Verification | Bhushan Parikh, Shaman Narayana | | | | | |
| Deadlock Verification For Dummies – The Easy Way of Using SVA and Formal | Mark Eslinger, Jeremy Levitt, and Joe Hupcey III | | | | | |
| Deadlock Verification For Dummies – The Easy Way Using SVA and Formal | Mark Eslinger, Jeremy Levitt, and Joe Hupcey III | | | | | |
| Dealing with Programmable IP: Where the Rubber Meets the PSS Deployment Road | Karthick Gururaj | | | | | |
| Debarshi Chatterjee, Spandan Kachhadia, Chen Luo, Kumar Kushal, Siddhanth Dhodhi | Moonki Jang | | | | | |
| Debug APIs – next wave of innovation in DV space | Srinivasan Venkataramanan and Ajeetha Kumari | | | | | |
| Debug APIs – next wave of innovation in DV space | Srinivasan Venkataramanan and Ajeetha Kumari | | | | | |
| Debug Automation with AI | Craig Yang, Jaw Lee, Sherwin Lai | | | | | |
| Debug Challenges in Low-Power Design and Verification | Durgesh Prasad, Madhur Bhargava, Jitesh Bansal, and Chuck Seeley | | | | | |
| Debug Challenges in Low-Power Design and Verification | Durgesh Prasad, Madhur Bhargava, Jitesh Bansal, and Chuck Seeley | | | | | |
| Debug Time Reduction by Automatic Generation of Waiver List Using ML Techniques | Vardhana M, Akshay Jain, Kota Subba Rao Sajja | | | | | |
| Debugging Communicating Systems: The Blame Game – Blurring the Line Between Performance Analysis and Debug | Rich Edelman and Raghu Ardeishar | | | | | |
| Debugging Functional Coverage Models Get The Most Out of Your Cover Crosses | Mennatallah Amer and Amr Hany | | | | | |
| Debugging Functional Coverage Models Get The Most Out of Your Cover Crosses | Mennatallah Amer and Amr Hany | | | | | |
| Debugging Linux Kernel Failures on Virtual Platform | Sandeep Jain | | | | | |
| Deep Learning for Design and Verification Engineers | John Aynsley | | | | | |
| Deep Learning for Engineers | John Aynsley | | | | | |
| Deep Predictive Coverage Collection | Rajarshi Roy, Chinmay Duvedi, Saad Godil, and Mark Williams | | | | | |
| Deep Predictive Coverage Collection | Rajarshi Roy, Chinmay Duvedi, Saad Godil, and Mark Williams | | | | | |
| Defining TLM+ | Wolfgang Ecker, Volkan Esen, Robert Schwencker, and Michael Velten | | | | | |
| DeltaCov: Automated Stimulus Quality Monitoring System | Nimish Girdhar, Srinivas Badam | | | | | |
| Democratizing Digital-centric Mixed-signal Verification methodologies | Sumit Vishwakarma | | | | | |
| Democratizing Formal Verification | Tobias Ludwig, Michael Schwarz, Paulius Morkunas, Silvio Santana, Dominik Stoffel, Wolfgang Kunz | | | | | |
| Demystifying Formal Testbenches: Tips, Tricks, and Recommendations | Shahid Ikram, Mark Eslinger | | | | | |
| Demystifying Formal Testbenches: Tips, Tricks, and Recommendations | Dr. Shahid Ikram, Mark Eslinger | | | | | |
| Demystifying the UVM Configuration Database | Vanessa R. Cooper and Paul Marriott | | | | | |
| Demystifying the UVM Configuration Database | Vanessa R. Cooper and Paul Marriott | | | | | |
| Deploying Customized Solution for Graphics Registers with UVM1.2 RAL | Roman Wang, Nigel Wang, Lunping Guo, Robert Liu, and Jia Zhu | | | | | |
| Deploying Customized Solution for Graphics Registers with UVM1.2 RAL | Roman Wang, Nigel Wang, Lunping Guo, Robert Liu, and Jia Zhu | | | | | |
| Deploying HLS in a DO-254/ED-80 Workflow | Byron Brinson Jacob Wiltgen, David Aerne and Tammy Reeve | | | | | |
| Deploying HLS in a DO-254/ED-80 Workflow | Tammy Reeve, Jacob Wiltgen, Byron Brinson, and David Aerne | | | | | |
| Deploying Parameterized Interface with UVM | Wayne Yun and Shihua Zhang | | | | | |
| DEPLOYING PARAMETERIZED INTERFACE WITH UVM | Wayne Yun and Shihua Zhang | | | | | |
| Design & Verify Virtual Platform with reusable TLM 2.0 | Ankush Kumar | | | | | |
| Design and verification in ARM | Hobson Bullman | | | | | |
| Design and Verification of a Multichip Coherence Protocol | Shahid Ikram, Isam Akkawi, Richard Kessler, Jim Ellis, and David Asher | | | | | |
| Design and Verification of a Multichip Coherence Protocol | Shahid Ikram, Isam Akkawi, Richard Kessler, Jim Ellis, and David Asher | | | | | |
| Design and Verification of an Image Processing CPU using UVM | Milos Becvar and Greg Tumbush | | | | | |
| Design and Verification of an Image Processing CPU Using UVM | Greg Tumbush and Milos Becvar | | | | | |
| Design and Verification of the PLL using the new DCO and Its Applications to Built-In Speed Grading of Arithmetic Circuits | Yi-Sheng Wang, Hsiang-Kai Teng, Shi-Yu Huang | | | | | |
| Design Guidelines for Formal Verification | Anamaya Sullerey | | | | | |
| Design Guidelines for Formal Verification | Anamaya Sullerey | | | | | |
| Design Methodology for Highly Cycle Accurate SystemC Models with Better Performance | Simranjit Singh, Prasanth Sasidharan, Sameer Deshpande, and Sandeep Puttappa | | | | | |
| Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012 | Eldon Nelson M.S. P.E. | | | | | |
| Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012 | Eldon Nelson | | | | | |
| Design space exploration of PIM (Processing in Memory) & PNC (Processing Near Memory) based on workload characterization | Amarnath, Judhajit | | | | | |
| Design verification of a cascaded mmWave FMCW Radar | Shweta Pujar, Vijay M, Sainath Karlapalem, Dharani Sharavanan, Kavya P S | | | | | |
| Designers Work Less with Quality Formal Equivalence Checking | Orly Cohen, Moran Gordon, Michael Lifshits, Alexander Nadel, and Vadim Ryvchin | | | | | |
| Designing a PSS Reuse Strategy | Matthew Ballance | | | | | |
| Designing a PSS Reuse Strategy | Matthew Ballance | | | | | |
| Designing A PSS Reuse Strategy | Matthew Ballance | | | | | |
| Designing Portable UVM Test Benches for Reusable IPs | Xiaoning Zhang, Baosheng Wang, and Terry Li | | | | | |
| Designing Portable UVM Test Benches for Reusable IPs | XIAONING ZHANG and BAOSHENG WANG | | | | | |
| Designing PSS Environment Integration for Maximum Reuse | Matthew Ballance | | | | | |
| Designing PSS Environment Integration for Maximum Reuse | Matthew Ballance | | | | | |
| Designing the Future with Efficiency Guidance to Adopting SystemVerilog for Design! | Axel Scherer and Junette Tan | | | | | |
| Designing, Verifying and Building an Advanced L2 Cache Sub-System using SystemC | Thomas Tessier, Dr. Hai Lin, Daniel Ringoen, Eileen Hickey, and Steven Anderson | | | | | |
| Designing, Verifying and Building an Advanced L2 Cache Subsystem using SystemC | Steve Frank, Thomas Tessier, Dr. Hai Lin, Daniel Ringoen, Eileen Hickey, and Steven Anderson | | | | | |
| Detecting Circular Dependencies in Forward Progress Checkers | Saurabh Chaurdia, Arun Khurana, Naveen Kumar, Aditya Chaurasiya, Yogesh Mahajan, Prasenjit Biswas | | | | | |
| Detecting Harmful Race Conditions in SystemC Models Using Formal Techniques | Sven Beyer and Dominik Strasser | | | | | |
| Detecting Harmful Race Conditions in SystemC Models Using Formal Techniques | Sven Beyer and Dominik Strasser | | | | | |
| Detection of glitch-prone clock and reset propagation with automated formal analysis | Kaushal Shah, Sulabh Kumar Khare | | | | | |
| Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions | Kelly D. Larson | | | | | |
| Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions | Kelly D. Larson | | | | | |
| Detoxify Your Schedule With A Low-Fat UVM Environment | Nihar Shah | | | | | |
| Detoxify Your Schedule With A Low-Fat UVM Environment A success story on using self-checking stimulus instead of a scoreboard to reduce development time | Nihar Shah | | | | | |
| Developing & Testing Automotive Software on Multi SoC ECU Architectures using Virtual Prototyping | Sam Tennent | | | | | |
| Developing a Portable Block Testbench and Reusable SOC Verification Scenarios Using IP XACT Based Automation | Taejin Kim, Minjae Kim, Yonghyun Yang, Hyundon Kim, Daewoo Kim, Tae Hee Han, and Seonil Brian Choi | | | | | |
| Developing Dynamic Resource Management System in SoCEmulation | Seonchang Choi, Sangwoo Noh, Seonghee Yim and Seonil Brian Choi | | | | | |
| Developing Dynamic Resource Management System in SoCEmulation | Seonchang Choi and Seonghee Yim | | | | | |
| Development and Verification of RISC-V Based DSP Subsystem IP: Case Study | Pascal Gouedo, Damien Le Bars, Olivier Montfort, Lee Moore, Aimee Sutton, Larry Lapides | | | | | |
| Development of a Core-Monitor for HW/SW Co-Debugging targetting Emulation Platform | Shreya Morgansgate, Johannes Grinschgl, Djones Lettnin | | | | | |
| Development of Flexi Performance Analysis Platform for Multi–SoC Networking Systems | Srinivasan Reddy Devarajan, Anant Raj Gupta, IngoVolkening, Franz Josef Schaefer and Vijay Raj Franklin Paul Rajan William | | | | | |
| Did Power Management Break My CDC Logic? An Integrated Approach to Power Domain and Clock Domain Crossing Verification | Ashish Amonkar, Kurt Takara, and Avinash Agrawal | | | | | |
| Differentiating with Custom Compute and Use Case Intro | Shigehiko Ito | | | | | |
| Digital Eye For Aid of Blind People | Jagu Naveen Kumar, Pabbuleti Venu | | | | | |
| Digital mixed-signal low power verification with Unified Power Format (UPF) | Srilakshmi D R and Geeta Krishna Chaitanya Puli | | | | | |
| Digital mixed-signal low power verification with Unified power format (UPF) | Srilakshmi D R and Geeta Krishna Chaitanya Puli | | | | | |
| Digital Transformation of EDA Environments To Accelerate Semiconductor Innovation | Guru Charan Prasad Jonnalagadda | | | | | |
| Digitizing Mixed Signal Verification | David Brownell and Courtney Schmitt | | | | | |
| Digitizing Mixed Signal Verification: Digital Verification Techniques Applied to Mixed Signal and Analog Blocks on the LMA Project | David Brownell and Courtney Schmitt | | | | | |
| Disaggregated methodology in Multi-die SoC– A Server SoC Case Study | Rohit Kumar Sinha | | | | | |
| Disaggregated methodology in Multi-die SoC– A Server SoC Case Study | Rohit Kumar Sinha | | | | | |
| Disciplined Post Silicon Validation using ML Intelligence | Amaresh Chellapilla, Pandithurai Sangaiyah | | | | | |
| Discover Over-Constraints by Leveraging Formal Tool | Dongsheng Ouyang, Ray Zhang, Lucas Liu, Doris Yin, Wayne Ding | | | | | |
| Discover Over-Constraints by Leveraging Formal Tool | Dongsheng Ouyang, Ray Zhang, Lucas Liu, Doris Yin, Wayne Ding | | | | | |
| Discovering Deadlocks in a Memory Controller IP | Jef Verdonck, Emrah Armagan, Khaled Nsaibia, Slava Bulach, Pranay Gupta, Anshul Jain, Chirag Agarwal, and Roger Sabbagh | | | | | |
| Discovering Deadlocks in a Memory Controller IP | Jef Verdonck, Emrah Armagan, Khaled Nsaibia, Slava Bulach, Pranay Gupta, Anshul Jain, Chirag Agarwal and Roger Sabbagh | | | | | |
| Distributed Simulation of UVM Testbench | Theta Yang | | | | | |
| Distributed Simulation of UVM Testbench | Theta Yang | | | | | |
| Do not forget to ‘Cover’ your SystemC code with UVMC | Vishal Baskar | | | | | |
| Do not forget to ‘Cover’ your SystemC code with UVMC | Vishal Baskar | | | | | |
| Do not forget to ‘Cover’ your SystemC code with UVMC | Vishal Baskar | | | | | |
| Do You Know What Your Assertions Are up To? A New Approach to Safety Critical Verification | Lee C. Smith | | | | | |
| Do You Know What Your Assertions Are Up To? A New Approach to Safety Critical Verification | Lee C. Smith | | | | | |
| Do You Verify Your Verification Components? | Josh Rensch and Neil Johnson | | | | | |
| Does It Pay Off To Add Portable Stimulus Layer On Top Of UVM IP Block Test Bench? | Xia Wu, Jacob Sander Andersen and Ole Kristoffersen | | | | | |
| Does It Pay Off To Add Portable Stimulus Layer On Top Of UVM IP Block Test Bench? | Xia Wu, Jacob Sander Andersen, and Ole Kristoffersen | | | | | |
| Doing Funny Stuff with the UVM Register Layer: Experiences Using Front Door Sequences, Predictors, and Callbacks | John Aynsley | | | | | |
| Doing Funny Stuff with the UVM Register Layer: Experiences Using Front Door Sequences, Predictors, and Callbacks | John Aynsley | | | | | |
| Doing the Impossible: Using Formal Verification on Packet Based Data Paths | Doug Smith | | | | | |
| Doing the Impossible: Using Formal Verification on Packet Based Data Paths | Doug Smith | | | | | |
| Don’t delay catching bugs: Using UVM based architecture to model external board delays | Amit Paunikar, Saurabh Arya, Vikas Makhija, and Shaily Khare | | | | | |
| Don’t delay catching bugs: Using UVM based architecture to model external board delays | Amit Paunikar, Saurabh Arya, Vikas Makhija, and Shaily Khare | | | | | |
| Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon | Abdelouahab Ayari, Sukriti Bisht, Sulabh Kumar Khare and Kurt Takara | | | | | |
| Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon | Abdelouahab Ayari, Sukriti Bisht, Sulabh Kumar Khare, and Kurt Takara | | | | | |
| Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to Simulation | Jonathan Bromley | | | | | |
| Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to Simulation | Jonathan Bromley | | | | | |
| DPI Redux. Functionality. Speed. Optimization. | Rich Edelman, Rohit Jain, and Hui Yin | | | | | |
| DPI Redux. Functionality. Speed. Optimization. | Rich Edelman, Rohit Jain, and Hui Yin | | | | | |
| Dr. Shahid Ikram, Distinguished Engineer, Marvell Semi Mark Eslinger, Product Engineer, Siemens | Daniel Cross | | | | | |
| Driving Analog Stimuli from a UVM Testbench | Satvika Challa, Amlan Chakrabarti | | | | | |
| DV Methodology to Model Scalable/Reusable Component to Handle IO Delays/Noise/Crosstalk in Multilane DDR PHY IF | Tapas Ranjan Jena, Gowdra Bomanna Chethan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | |
| DVCon EU 2014 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon EU 2015 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon EU 2016 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon EU 2017 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon EU 2018 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon EU 2019 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon EU 2020 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon EU 2020 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon EU 2021 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon Europe 2015 Road to self driving cars: View of a semiconductor company | Hans Adlkofer | | | | | |
| DVCon Europe 2022 Proceedings Showcase Link | Accellera Systems Initiative | | | | | |
| DVCon India 2021 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon India 2022 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon JP 2022 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon JP 2023 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon U.S 2021 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon U.S. 2021 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon U.S. 2022 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon US 2022 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon US 2023 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon USA 2023 Proceedings | Accellera Systems Initiative | | | | | |
| DVS Interface Element – A Novel Approach in Multi-Power Domain, Mixed-Signal Design Verification | Vijay Kumar Sankaran, Ji Du, Qingyu Lin, Arumugan A, and Badrinarayan Zanwar | | | | | |
| DVS Interface Element—A Novel Approach in Multi-Power Domain, Mixed-Signal Design Verification | Shekar Chetput | | | | | |
| Dynamic and Scalable OVM Stimulus for Accelerated Functional Coverage | Michael J Castle | | | | | |
| Dynamic Control Over UVM Register Backdoor Hierarchy | Roy Vincent, Unnikrishnan Nath, and Ashok Chandran | | | | | |
| Dynamic Fault Injection Library Approach for SystemC AMS | Thomas Markwirth, Paul Ehrlich, and Dominik Matter | | | | | |
| Dynamic Fault Injection Library Approach for SystemC AMS | Thomas Markwirth, Paul Ehrlich, and Dominik Matter | | | | | |
| Dynamic Parameter Configuration of SystemC Models | Shruti Baindur, Simranjit Singh | | | | | |
| Dynamic Power Automation UVM Framework | Raghavendra J N, Gudidevuni Harathi | | | | | |
| Dynamic Regression Suite Generation Using Coverage-Based Clustering | Shahid Ikram and Jim Ellis | | | | | |
| Dynamic Regression Suite Generation Using Coverage-Based Clustering | Shahid Ikram and Jim Ellis | | | | | |
| Dynamically Optimized Test Generation Using Machine Learning | Rajarshi Roy, Mukhdeep Singh Benipal, Saad Godil | | | | | |
| e/eRM to SystemVerilog/UVM: Mind the Gap, But Don’t Miss the Train | Avidan Efody and Michael Horn | | | | | |
| e/eRM to SystemVerilog/UVM: Mind the Gap, But Don’t Miss the Train | Michael Horn | | | | | |
| Early Design and Validation of an AI Accelerator’s System Level Performance Using an HLS Design Methodology | Wenbo Zheng | | | | | |
| Early Detection of Functional Corner Case Bugs using Methodologies of the ISO 26262 | Moonki Jang, Sunil Roe, Youngsik Kim, Seonil Brian Choi | | | | | |
| Early Performance Verification of Embedded Inferencing Systems using open source SystemC NVIDIA MatchLib | Herbert Taucher and Russell Klein | | | | | |
| EARLY SOFTWARE DEVELOPMENT AND VERIFICATION METHODOLOGY USING HYBRID EMULATION PLATFORM | Woojoo Kim, Haemin Park, Hyundon Kim, Seonil Brian Choi, and SukWon Kim | | | | | |
| EASI2L: A Specification Format for Automated Block Interface Generation and Verification | Chintan Kaur, Ravi Narayanaswami, and Richard Ho | | | | | |
| Easier SystemVerilog with UVM: Taming the Beast | John Aynsley | | | | | |
| Easier SystemVerilog with UVM: Taming the Beast | John Aynsley | | | | | |
| Easier UVM – Coding Guidelines and Code Generation | John Aynsley and Dr. Christoph Sühnel | | | | | |
| Easier UVM – Making Verification Methodology More Productive | John Aynsley and David Long | | | | | |
| Easier UVM – Making Verification Methodology More Productive | John Aynsley, David Long | | | | | |
| Easier UVM for Functional Verification by Mainstream Users | John Aynsley | | | | | |
| Easier UVM: Learning and Using UVM with a Code Generator | John Aynsley, Doulos | | | | | |
| Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI | Dave Rich | | | | | |
| Easy Testbench Evolution – Styling Sequences and Drivers | Rich Edelman, Kento Nishizawa | | | | | |
| Easy Testbench Evolution Styling Sequences and Drivers | Rich Edelman, Kento Nishizawa | | | | | |
| Easy uvm_config_db use: A simplified and reusable uvm_config_db methodology for environment developers and test writers | Bob Oden | | | | | |
| Easy uvm_config_db use: A simplified and reusable uvm_config_db methodology for environment developers and test writers | Bob Oden | | | | | |
| Effective Formal Deadlock Verification Methodologies for Interconnect design | Sachin Kumar, Rajesh C M | | | | | |
| Effects of Abstraction in Stimulus Generation of Layered Protocols within OVM | Josh Rensch and Jesse Prusi | | | | | |
| Efficacious Verification of Irreproachable and Steady Data Transfer Protocol for high-speed die-to-die communication on a 3DIC Chip | Varun Kumar C, Jyoti Verma, Sekhar Dangudubiyyam | | | | | |
| Efficacious Verification of Irreproachable and Steady Data Transfer Protocol for high-speed die-to-die communication on a 3DIC Chip | Varun Kumar C, Jyoti Verma, Sekhar Dangudubiyyam | | | | | |
| Efficacious verification of Loopback and Equalization in PCIe By Using Novel approach | Jaydeep Suvariya, Pinal Patel | | | | | |
| Efficient and Exhaustive Floating Point Verification Using Sequential Equivalence Checking | Travis Pouarz and Vaibhav Agrawal | | | | | |
| Efficient and Exhaustive Floating Point Verification Using Sequential Equivalence Checking | Travis W. Pouarz and Vaibhav Agrawal | | | | | |
| Efficient and Faster Handling of CDC/RDC Violations | Ashish Kumar Gupta | | | | | |
| Efficient Bug-Hunting Techniques Using Graph-Based Stimulus Models | Nguyen Le and Mike Andrews | | | | | |
| Efficient Bug-Hunting Techniques Using Graph-Based Stimulus Models | Nguyen Le and Mike Andrews | | | | | |
| Efficient Clock Monitoring System for SoC Clock Verification | Nam Pham Van, Bernhard Braun, Dirk Moeller, and Clemens Roettgermann | | | | | |
| Efficient Clock Monitoring System for SoC Clock Verification | Nam Pham Van | | | | | |
| Efficient Constrained Random Generation of Address Blocks: A comparative study of simulation speeds | Meenakshy Ramachandran | | | | | |
| Efficient Constrained Random Generation of Address Blocks: A comparative study of simulation speeds | Meenakshy Ramachandran | | | | | |
| Efficient distribution of video frames to achieve better throughput | Bhavik Vyas and Suruchi Jain | | | | | |
| Efficient Exploration of Safety-Relevant Systems Through a Link Between Analysis and Simulation | Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello, and Bogdan-Andrei Tabacaru | | | | | |
| Efficient Exploration of Safety-Relevant Systems Through a Link Between Analysis and Simulation | Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello, and Bogdan-Andrei Tabacaru | | | | | |
| Efficient Fault Injection Methods for Safety Software Testing Based on Virtual Prototypes: Application to Powertrain ECU | Ons Mbarek, Dineshkumar Selvaraj, and Romero Chica Jose Miguel | | | | | |
| Efficient Formal strategies to verify the robustness of the design | Sakthivel Ramaiah | | | | | |
| Efficient Formal strategies to verify the robustness of the design | Sakthivel Ramaiah | | | | | |
| Efficient hierarchical low power verification of custom designs using static and dynamic techniques | Himanshu Bhatt, Archanna Srinivasan, and Chong Lee Kuay | | | | | |
| Efficient Loosely-Timed SystemC TLM-2.0 Modeling: A Hands-On Tutorial | Nils Bosbach, Lukas Junger, Rainer Leupers | | | | | |
| Efficient Loosely-Timed SystemC TLM-2.0 Modeling: A Hands-On Tutorial | Nils Bosbach, Lukas Jünger, Rainer Leupers | | | | | |
| Efficient methodology to uncover common root causes for RDC violations using intelligent data analytics | Manish Bhati, Rajagopal Anantharaman, Inayat Ali | | | | | |
| Efficient methods for analog mixed signal verification Interface handling methods, trade-offs and guidelines | Lakshmanan Balasubramanian, Shoeb Siddiqui, and Vijay Kumar Sankaran | | | | | |
| Efficient Methods for Display Power Estimation & Visualization | Srikanth Reddy Rolla and Aakash Modi | | | | | |
| Efficient Methods for Display Power Estimation and Visualization | Srikanth Reddy Rolla and Aakash Modi | | | | | |
| Efficient Regression Management with Smart Data Mining Technique | Tejbal Prasad | | | | | |
| Efficient Regression Management with Smart Data Mining Technique | Tejbal Prasad | | | | | |
| Efficient SCE-MI Usage to Accelerate TBA Performance | Ponnambalam Lakshmanan, Prashantkumar Ravindra, and Rajarathinam Susaimanickam | | | | | |
| Efficient Simulation Based Verification by Reordering | Chao Ya and Kevin Jones | | | | | |
| Efficient SoC Level Mixed Signal Frontend Verification using Wreal Models | Anu Marisha, Nayana Prakash, Udit Kumar, Rajesh Tiwari, and Vijay Kumar Birange | | | | | |
| Efficient SoC Level Mixed Signal Frontend Verification using Wreal Models | Anu Marisha, Nayana Prakash, Udit Kumar, and Rajesh Tiwari | | | | | |
| Efficient Standard Co-Emulation Modeling Interface (SCE-MI) Usage to Accelerate TBA Performance | Ponnambalam Lakshmanan | | | | | |
| Efficient use of Virtual Prototypes in HW/SW Development and Verification | Rocco Jonack and Eyck Jentzsch | | | | | |
| Efficient Verification Framework for Audio/Video Interfaces | Noha Shaarawy | | | | | |
| Efficient Verification of Arbitration Design with a Generic Model | Kevin Kotadiya, Ishita Agrawal | | | | | |
| Efficient Verification of Arbitration Design with a Generic Model | Kevin Kotadiya, Ishita Agrawal | | | | | |
| Efficient Verification of Mixed-Signal SerDes IP Using UVM | Varun R, Vinayak Hegde, Cadence Bangalore | | | | | |
| Effortless, Methodical and Exhaustive Register Verification using what you already have | Aishwarya Sridhar, Pallavi Atha, and David Crutchfield | | | | | |
| Effortless, Methodical and Exhaustive Register Verification using what you already have. | Aishwarya Sridhar, Pallavi Atha, and David Crutchfield | | | | | |
| Embedded UVM | Puneet Goel | | | | | |
| Embrace Errors! Architecting UVM Testbenches for Dynamic Error Injection & Handling | Sushrut B Veerapur, Kilaru Vamsikrishna | | | | | |
| Embracing Datapath Verification with Jasper C2RTL App | Vaibhav Mittal, Sourav Roy, Anshul Singhal | | | | | |
| Embracing Formal Verification for Data Path Designs Using Golden Specs | Achutha Kirankumar V, Disha Puri, Bindumadhava S.S | | | | | |
| EMULATION BASED FULL CHIP LEVEL LOW POWER VALIDATION AT PRE-SILICON STAGE | Kyoungmin Park, Jaegeun Song, Hyundon Kim, Seonil Brian Choi, and Suk Won Kim | | | | | |
| Emulation based Power and Performance Workloads on ML NPUs | Pragati Mishra, Ritu Suresh, Issac P Zacharia, Jitendra Aggarwal | | | | | |
| Emulation Based Power and Performance Workloads on ML NPUs | Pragati Mishra, Ritu Suresh, Issac Zacharia, and Jitendra Aggarwal | | | | | |
| Emulation Based Power and Performance Workloads on ML NPUs | Pragati Mishra, Ritu Suresh, Issac Zacharia, and Jitendra Aggarwal | | | | | |
| Emulation Testbench Optimizations for better Hardware Software Co-Validation | Vijayakrishnan Rousseau, Suresh Balasubramanian, Srikanth Reddy Rolla, and Mohamed Saheel Nandikotkur Hussainsaheb | | | | | |
| Enabling Digital Mixed-Signal Verification of Loading Effects in Power Regulation using SystemVerilog User-Defined Nettype | Alvaro Caicedo and Sebastian Fritz | | | | | |
| Enabling Digital Mixed-Signal Verification of Loading Effects in Power Regulation using SystemVerilog User-Defined Nettype | Alvaro Caicedo and Sebastian Fritz | | | | | |
| Enabling Energy Aware System Level Design with UPF-Based System Level Power Models | T4A and T4B | | | | | |
| Enabling Exhaustive Reset Verification Enablement: Client PCIE Design Reset Verification Case Study | Rohit Kumar Sinha, Praveen Dornala | | | | | |
| Enabling high quality design sign-off with Jasper structural and auto formal checks | Vishnu Haridas, Mansi Rastogi, Guruprasad Timmapur | | | | | |
| Enabling high quality design sign-off with structural and auto formal checks | Timmapur, Guruprasad Haridas, Vishnu Rastogi, Mansi | | | | | |
| Enabling Shift-Left through FV Methodologies on Intel® Graphics Designs | M. Achutha KiranKumar V, Aarti Gupta Bindumadhava S S, Aishwarya R | | | | | |
| Enabling Visual Design Verification Analytics – From Prototype Visualizations to an Analytics Tool using the Unity Game Engine | Markus Borg, Andreas Brytting, and Daniel Hansson | | | | | |
| End to End Formal Verification Strategies for IP Verification | Jacob Ryan Maas, Nirabh Regmi, Ashish Kulkarni, and Krishnan Palaniswami | | | | | |
| End to End Formal Verification Strategies for IP Verification | Jacob Ryan Maas, Nirabh Regmi, Krishnan Palaniswami, and Ashish Kulkarni | | | | | |
| Engaging with IEEE through Standards | Sri Chandra, Dennis Brophy | | | | | |
| Engineered SystemVerilog Constraints | Jeremy Ridgeway | | | | | |
| Engineered SystemVerilog Constraints | Jeremy Ridgeway | | | | | |
| Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software Verification | Victor Besyakov | | | | | |
| Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software Verification | Victor Besyakov | | | | | |
| Enhanced LDPC Codec Verification in UVM | Shriharsha Koila, Ganesh Shetti, Prateek Jain, Anand Shirahatti | | | | | |
| Enhancements of metric driven verification for the ISO26262: Recent advancements better supporting specific verification requirements including functional safety | Michael Rohleder, Clemens Röttgermann, Stephan Rüttiger, John Brennan, Matt Graham, and Riccardo Oddone | | | | | |
| Enhancing Productivity in Formal Testbench Generation for AHB based IPs | Shubham Goyal, Ishan Patil, Senthilnath Subbarayan, and Sandeep Kumar | | | | | |
| Enhancing Quality and Coverage of CDC Closure in Intel’s SoC Design | Rohit Kumar Sinha | | | | | |
| Enhancing Quality and Coverage of CDC Closure in Intel’s SoC Design | Rohit Kumar Sinha | | | | | |
| Enhancing The Effectiveness of a Constrained Random Test Suite Using Supervised Machine Learning Algorithm | Ponnambalam Lakshmanan, Rajarathinam Susaimanickam | | | | | |
| Enriching UVM in SystemC with AMS extensions for randomization and functional coverage* | Thilo Vörtler, Thomas Klotz, Karsten Einwich, Yao Li, Zhi Wang, Marie-Minerve Louërat, Jean-Paul Chaput, François Pêcheux, Ramy Iskander, and Martin Barnasconi | | | | | |
| Enriching UVM in SystemC with AMS extensions for randomization and functional coverage* | Thilo Vörtler, Thomas Klotz, Karsten Einwich, Yao Li, Zhi Wang, Marie-Minerve Louërat, Jean-Paul Chaput, François Pêcheux, Ramy Iskander, and Martin Barnasconi | | | | | |
| Ensuring Quality of Next Generation Automotive SoC: System’s Approach | Pankaj Singh | | | | | |
| Environment for efficient and reusable SystemC module level verification | Flavia Gontia | | | | | |
| Environment for efficient and reusable SystemC module level verification | Flavia Gonția | | | | | |
| Equivalence Validation of Analog Behavioral Models | Hardik Parekh, Manish Kumar Karna, Mohit Jain, Atul Pandey, and Sandeep Mittal | | | | | |
| Equivalence Validation of Analog Behavioral Models | Manish Kumar Karna, Hardik Parekh, Mohit Jain, Atul Pandey, and Sandeep Mittal | | | | | |
| Equivalence Validation of Analog Behavioral Models | Hardik Parekh, Manish Kumar Karna, Mohit Jain, Atul Pandey, and Sandeep Mittal | | | | | |
| Eradicating X-bugs and Achieving Higher Design Quality Using Static X-propagation Sign-off | Sanjay Thatte, Andrew Guyler, Nikhil Rahagude, and Savitha Raghunath | | | | | |
| Error Injection in a Subsystem Level Constrained Random UVM Testbench | Jeremy Ridgeway and Hoe Nguyen | | | | | |
| Error Injection in a Subsystem Level Constrained Random UVM Testbench | J. Ridgeway and H. Nguyen | | | | | |
| Error Injection: When Good Input Goes Bad | Kurt Schwartz and Tim Corcoran | | | | | |
| Error Injection: When Good Input Goes Bad | Kurt Schwartz and Tim Corcoran | | | | | |
| ESL Design and Modeling with SystemCAMS for Mixed-Signal IoTand Automotive Applications | Karsten Einwich, Martin Barnasconi, Christoph Grimm, and Torsten Mähne | | | | | |
| Essential Adjuncts of Verification Infrastructure | Kunal Panchal, Harshit Mehta | | | | | |
| Estimating Power Dissipation of End-User Application on RTL | Magdy El-Moursy | | | | | |
| Evaluating the Feasibility of a RISC V Core for Real Time Applications Using a Virtual Prototype | J. Santana , G. Pachiana, T. Markwirth, C. Sohrmann, B. Fischer, M. Matschnig | | | | | |
| Evaluating the Feasibility of a RISCV Core for Real-Time Applications Using a Virtual Prototype | Juan Santana, Gabriel Pachiana, Thomas Markwirth, Christoph Sohrmann, Bernhard Fischer, and Martin Matschnig | | | | | |
| Every Cloud – Post-Silicon Bug Spurs Formal Verification Adoption | Blaine Hsieh, Stewart Li, and Mark Eslinger | | | | | |
| Every Cloud – Post-Silicon Bug Spurs Formal Verification Adoption | Blaine Hsieh, Stewart Li, and Mark Eslinger | | | | | |
| Evolution of CDC recipe: Learning through real case studies and methodology improvements | Amit Kulkarni, Suhas DS, Deepmala Sachan | | | | | |
| Evolution of Triage: Real-time Improvements in Debug Productivity | Gordon Allan | | | | | |
| Evolutionary and Revolutionary Innovation for Effective Verification Management & Closure | Darron May, Mark Carey, Dan Yu | | | | | |
| Exhaustive Equivalence Checking on AMD’s Next-generation Microprocessor Core | Baosheng Wang, Brian McMinn, Borhan Roohipour, Ashok Venkatachar, Arun Chandra, Richard Bartolotti, and Lerzan Celikkanat | | | | | |
| Exhaustive Latch Flow – Through Verification with Formal Methods | Baosheng Wang, Sean Ater, Baris Piyade, Brian McMinn, and Borhan Roohipour | | | | | |
| Exhaustive Latch Flow-through Verification with Formal Methods | Baosheng Wang, Sean Ater, Baris Piyade, Brian McMinn, and Borhan Roohipour | | | | | |
| Exhaustive Reset Verification Enablement: Client PCIE Design Reset Verification Case Study | Rohit Kumar Sinha, Praveen Dornala | | | | | |
| Exhaustive validation of a cache memory controller using Formal Verification to meet performance and timing requirements | Himani Jawa, Nishant Raman, Sini Balakrishnan, Manas Karanjekar | | | | | |
| Exhaustive validation of a cache memory controller using Formal Verification to meet performance and timing requirements | Himani Jawa, Nishant Raman, Sini Balakrishnan, Manas Karanjekar | | | | | |
| Expedite any Simulation with DMTCP and Save Decades of Computation | Balaji R, Sathish Kumar Sugumaran, Rohan Garg, Jiajun Cao | | | | | |
| Expediting the Code Coverage Closure Using Static Formal Techniques – A Proven Approach at Block and SoC Levels | | | | | | |
| Expediting Verification of Critical SoC Components Using Formal Methods | Nuni Srikanth, Lakshman Easwaran, Maddipatla Shankar Naidu | | | | | |
| Experience of using Formal Verification for a Complex Memory Subsystem Design | Sujeet Kumar,Vandana Goel,Hrushikesh Vaidya, and Ronak Sarikhada | | | | | |
| Experience of Using Formal Verification for a Complex Memory Subsystem Design | Sujeet Kumar, Vandana Goel, Hrushikesh Vaidya and Ronak Sarikhada | 2020 | Paper | | y2020 | paper |
| Experience with OVM-Based Mixed-Signal Verification of the Impedance Calibration Block for a DDR Interface | Harry Wang, Wessam El-Naji, and Kenneth Bakalar | | | | | |
| Experience with OVM-Based Mixed-Signal Verification of the Impedance Calibration Block for a DDR Interface | Harry Wang, Wessam El-Naji, and Kenneth Bakalar | | | | | |
| Experiences in Migrating a Chip-Level Verification Environment from UVM EA to UVM 1.1 | Ashish Kumar, Dave Stang, Dudyala Sasidhar, S, Manikandan, and Thirumalai Srishan | | | | | |
| Experiences in Migrating a Chip-Level Verification Environment from UVM-EA to UVM-1.x | Ashish Kumar, S Manikandan, Sasidhar Dudyala, Srishan Thirumalai, and Dave Stang | | | | | |
| Experiencing Checkers for a Cache Controller Design | Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari, and Lisa Piper | | | | | |
| Exploring Machine Learning to assign debug priorities to improve the design quality | Vyasa Sai, Vaibhav Gupta, Fylur Rahman | | | | | |
| Exploring Machine Learning to assign debug priorities to improve the design quality | Vyasa Sai, Vaibhav Gupta and Fylur Rahman Sathakathulla | | | | | |
| Exquisite modeling of verification IP: Challenges and Recommendations | Anuradha Tambad, Subashini Rajan, Shivani Upasani, Prashanth Srinivasa, Imran Ali, and Adiel Khan | | | | | |
| Exquisite Modeling of VIP | Adiel Khan, Anuradha Tambad, Imran Ali, Prashanth Srinivasa, Shivani Upasani, and Subashini Rajan | | | | | |
| Extendable Messaging Techniques for Debugging and Analyzing UVM Testbench Structure and Transaction Flow | Jun Zhao, Bindesh Patel, and Rex Chen | | | | | |
| Extendable Messaging Techniques for Debugging and Analyzing UVM Testbench Structure and Transaction Flow | Jun Zhao, Bindesh Patel, and Rex Chen | | | | | |
| Extending a Traditional VIP to Solve PHY Verification Challenges | Amit Tanwar, Manoj Manu | | | | | |
| Extending functionality of UVM components by using Visitor design pattern | Darko M. Tomušilović | | | | | |
| Extending functionality of UVM components by using Visitor design pattern | Darko M. Tomušilović | | | | | |
| Extending Proven Digital Verification Techniques for Mixed-Signal SoCswith VCS AMS | Helene Thibieroz, Adiel Khan, Pierluigi Daglio, and Gernot Koch | | | | | |
| Extending the UVM register model generation and integration flow to support user-defined scenarios and register mask values | Shuang Han, Kees van Kaam, and Martin Barnasconi | | | | | |
| Extending the UVM register model generation and integration flow to support user-defined scenarios and register mask values | Shuang Han, Kees van Kaam, and Martin Barnasconi | | | | | |
| Extending UVM Register Abstraction Layer for Verification of Register Access via Serial Bus Interface | Darko M. Tomušilović | | | | | |
| Extending UVM Register Abstraction Layer for Verification of Register Access via Serial Bus Interface | Darko Tomušilović | | | | | |
| Extension of the Power-Aware IP Reuse Approach to ESL | Antonio Genov, Loic Leconte, Fran ç ois Verdier | | | | | |
| Fabric Verification | Galen Blake and Steve Chappell | | | | | |
| Facilitating Transactions in System Verilog and VHDL | Rich Edelman | | | | | |
| Facilitating Transactions in VHDL and SystemVerilog | Rich Edelman | | | | | |
| Failure Triage: The Neglected Debugging Problem | Sean Safarpour, Evean Qin, Yu-Shen Yang, and Brian Keng | | | | | |
| Failure Triage: The Neglected Debugging Problem | Sean Safarpour, Evean Qin, Yu-Sheng Yang, and Brian Keng | | | | | |
| Fast and Furious Quick Innovation from Idea to Real Prototype | Simone Fontanesi, Gaetano Formato, Thomas Arndt, and Andrea Monterastelli | | | | | |
| Fast and FuriousQuick Innovation from Idea to Real Prototy | Simone Fontanesi, Gaetano Formato, Thomas Arndt, and Andrea Monterastelli | | | | | |
| Fast Congestion Planning and Floorplan QoR Assessment | Harn Hua Ng, Kirvy Teo | | | | | |
| Fast Convergence Modular Advanced Smart-Hybrid Testbench (FCMAST) to automate and expedite SoC gate level simulations closure | Harshal Kothari, Eldin Ben Jacob, Chandrachud Murali, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | |
| Fast Convergence Modular Advanced Smart-Hybrid Testbench (FCMAST) to automate and expedite SoC gate level simulations closure | Harshal Kothari, Eldin Ben Jacob, Chandrachud Murali, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | |
| Fast forward Software Development using Advanced Hybrid Technologies | Xiaowei Pan | | | | | |
| Fast Track Formal Verification Signoff | Mandar Munishwar, Xiaolin Chen, Arunava Saha, and Sandeep Jana | | | | | |
| Fast Track Formal Verification Signoff | Mandar Munishwar, Xiaolin Chen, Arunava Saha, and Sandeep Jana | | | | | |
| Fast Track RISC-V System Validation Using Hardware Assisted Verification Platforms | Prasad Kadookar, Mohan Singh | | | | | |
| Fast, Parallel RISC-V Simulation for Rapid Software Verification | Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers | | | | | |
| Faster Elaborations with Cloud Storage | Shobhit Shukla, Amit Kumar | | | | | |
| Fault Campaign Framework for FuSa Verification of ISO 26262 Compliant Automotive Products | Prashantkumar Ravindr, Mangesh Pande, and Vinay Rawat | | | | | |
| Fault Campaign Framework for FuSa Verification of ISO 26262 Compliant Automotive Products | Prashantkumar Ravindra, Mangesh Pande, and Vinay Rawat | | | | | |
| Fault Effect Propagation using Verilog A for Analog Test Coverage | Aishwarya Prabhakaran, Ahmed Sokar, and Jaafar Mejri | | | | | |
| Fault Effect Propagation using Verilog-A for Analog Test Coverage | Aishwarya Prabhakaran, Ahmed Sokar and Jaafar Mejri | | | | | |
| Fault Injection Analysis for Automotive Safety and Security | Sesha Sai Kumar C V, Ayman Mouallem, Jamil Mazzawi | | | | | |
| Fault Injection Analysis for Automotive Safety and Security | Sesha Sai Kumar C.V., Jamil Mazzawi, Ayman Mouallem | | | | | |
| Fault Injection Made Easy Unified Formal Verification of Normal and Safety Functions | Sergio Marchese, Jörg Grosse, Ashish Darbari | | | | | |
| Fault Injection Strategy to Validate ASIL-D Requirements of BMS Components | Praneeth Uddagiri, Veera Satya Sai Gavirni, Prashantkumar Ravindra | | | | | |
| Fault Injection Strategy to Validate ASIL-D Requirements of BMS Components | Praneeth Uddagiri, Veera Satya Sai Gavirni, Prashantkumar Ravindra | | | | | |
| Fault Proof: Using Formal Techniques for Safety Verification and Fault Analysis | Adrian Traskov, Thorsten Ehrenberg, Sacha Loitz, Abdelouahab Ayari, Avidan Efody, and Joseph Hupcey III | | | | | |
| Fault Proof: Using Formal Techniques for Safety Verification and Fault Analysis | Adrian Traskov,Thorsten Ehrenberg, Sacha Loitz, Abdelouahab Ayari, Avidan Efody, and Joseph Hupcey III | | | | | |
| Fault-Effect Analysis on Multiple Abstraction Levels in Hardware Modeling | B-A. Tabacaru, M. Chaari, W. Ecker, T. Kruse, and C. Novello | | | | | |
| Fault-Effect Analysis on Multiple Abstraction Levels in Hardware Modeling | Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, and Cristiano Novello | | | | | |
| Filtering noise in RDC analysis by clockoff specification | Anupam Saxena, Inayat Ali, SulabhKumar Khare, and Atul Sharma | | | | | |
| Filtering noise in RDC analysis by clockoff specification | Anupam Saxena, Inayat Ali, Sulabh Kumar Khare and Atul Sharma | | | | | |
| Finding a Needle in a Haystack: A Novel Log Analysis Method with Test Clustering in Distributed System | Jin Choi | | | | | |
| Finding a Needle in a Haystack: A Novel Log Analysis Method with Test Clustering in Distributed Systems | Jin Choi, Sangwoo Noh, Sooncheol Hong, Hanna Jang, Seonghee Yim, and Seonil Brian Choi | | | | | |
| Finding Hidden Bugs In Deep Cycles: Advanced Debug Methodologies for Software-first System Validation | Youcef Qassid and Andy Jolley | | | | | |
| Finding the Last Bug in a CNN DMA Unit | Bruno Lavigueur, Dean Ke, Eric Rao, Fergus Casey, Achin Mittal, Pallavi Kumari, Michael Thompson, and Roger Sabbagh | | | | | |
| Finding the Last Bug in a CNN DMA Unit | Bruno Lavigueur, Dean Ke, Eric Rao, Fergus Casey, Achin Mittal, Pallavi Kumari, Michael Thompson, and Roger Sabbagh | | | | | |
| Firmware Firmly under Control: New Optimization and Verification Techniques for Application Specific Electronic System | Daniel Große, Manuel Strobel, Daniel Mueller-Gritschneder, Vladimir Herdt, and Tobias Ludwig | | | | | |
| First Reports from the UVM Trenches: User-friendly, Versatile and Malleable, or just the Emperor’s New Methodology? | Jonathan Bromley | | | | | |
| Five Ways to Make Your Specman Environment More Reusable and Configurable | Stefan Sljukic, Nikola Knezevic, Filip Dojcinovic | | | | | |
| Flattening the UVM Learning Curve Automated Solutions for DSP Filter Verification | Avinash Lakshminarayana, Eric Jackowski, Eric Cigan, and Mark Lin | | | | | |
| Flattening the UVM Learning Curve: Automated Solutions for DSP Filter Verification | Avinash Lakshminarayana, Eric Jackowski,Eric Cigan, Mark Lin | | | | | |
| Flexible Checker: A one-stop shop for all your checkers and a methodology for elastic scoreboarding | Saad Zahid, Chandra Veedhi, and Sumit Dhamanwala | | | | | |
| Flexible Indirect Registers with UVM | Uwe Simm | | | | | |
| Flexible Indirect Registers With UVM | Uwe Simm | | | | | |
| Flexible Indirect Registers With UVM | Uwe Simm | | | | | |
| Fnob: Command Line-Dynamic Random Generator | Haoxiang Hu, Tuo Wang | | | | | |
| Fnob: Command Line-Dynamic Random Generator | Haoxiang Hu and Tuo Wang | | | | | |
| Formal Architectural Specification and Verification of A Complex SOC | Shahid Ikram, Isam Akkawi, David Asher, and Jim Ellis | | | | | |
| FORMAL ARCHITECUTRAL SPECIFICATION AND VERIFICATION OF A COMPLEX SOC | Shahid Ikram, Isam Akkawi, David Asher, and Jim Ellis | | | | | |
| Formal Assisted Fault Campaign for ISO26262 Certification | Nitin Ahuja, Mayank Agarwal, Sandeep Jana | | | | | |
| Formal Bug Hunting with “River Fishing” Techniques | Mark Eslinger and Ping Yeung | | | | | |
| Formal Bug Hunting with “River Fishing” Techniques | Mark Eslinger and Ping Yeung | | | | | |
| Formal Fault Propagation Analysis that Scales to Modern Automotive SoCs | Sergio Marchese | | | | | |
| Formal Fault Propagation Analysis that Scales to Modern Automotive SoCs | Sergio Marchese and Jörg Grosse | | | | | |
| Formal For Adjacencies Expanding the Scope of Formal Verification | M Achutha KiranKumar V, Bindumadhava Ss., Vichal Verma, Savitha Manojna | | | | | |
| Formal for Adjacencies Expanding the Scope of Formal Verification | M Achutha KiranKumar V, Bindumadhava Ss., Vichal Verma, Savitha Manojna | | | | | |
| Formal Methods to Verify the Power Manager for an Embedded Multiprocessor Cluster | Kesava R. Talu | | | | | |
| Formal Proof for GPU Resource Management | Jia Zhu, Chuanqin Yan, and Nigel Wang | | | | | |
| Formal Proof for GPU Resource Management | Jia Zhu, Chuanqin Yan, and Nigel Wang | | | | | |
| Formal Property Verification of the Digital Section of an Ultra-Low Current Digitizer ASIC | Katharina Ceesay-Seitz, Sarath Kundumattathil Mohanan, Hamza Boukabache, Daniel Perrin | | | | | |
| Formal Sign-off Methodology for IP Blocks | Anna Chang, Chia-An Hsu | | | | | |
| Formal Verification + CIA Triad: Winning Formula for Hardware Security | Vedprakash Mishra, Anshul Jain | | | | | |
| Formal Verification + CIA Triad: Winning Formula for Hardware Security | Vedprakash Mishra, Anshul Jain | | | | | |
| Formal Verification Accelerating Coherent Bridge IP Development and Fast Forward DV | Pulicharla Ravindrareddy, Chayan Pathak, Venkatesh Chepuri, Nitin Neralkar, Sourabh Bhattacharjee, Piyush Upadhyay, Madhusudhan Koothapaakkam | | | | | |
| Formal Verification Bootcamp | Mike Bartley | | | | | |
| Formal Verification by The Book: Error Detection and Correction Codes | K. Devarajegowda, V. Hiltl, T. Rabenalt, D. Stoffel, W. Kunz, and W. Ecker | | | | | |
| Formal Verification Experiences: Silicon Bug Hunt with “Deep Sea Fishing” | Mark Handover, Abdelouahab Ayari and Ping Yeung | | | | | |
| Formal Verification Experiences: Silicon Bug Hunt with “Deep Sea Fishing” | Ping Yeung, Mark Handover, and Abdelouahab Ayari | | | | | |
| Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt | Ping Yeung, Mark Eslinger, Jin Hou | | | | | |
| Formal Verification in the Real World | Jonathan Bromley and Jason Sprott | | | | | |
| Formal Verification of a Highly Configurable DDR Controller IP | Sumit Neb, Chirag Agarwal, Deepak K. Gupta, and Roger Sabbagh | | | | | |
| Formal Verification of Connections at SoC-level | Penny Yang, Prasun Das, Yuya Kao, and Mingchu Kuo | | | | | |
| Formal Verification of Connections at SoC-level | Penny Yang, Prasun Das, Yuya Kao, and Mingchu Kuo | | | | | |
| FORMAL VERIFICATION OF FLOATING-POINT HARDWARE WITH ASSERTION-BASED VIP | Ravi Ram, Adam Elkins, Adnan Pratama, Sasa Stamenkovic, Sven Beyer, and Sergio Marchese | | | | | |
| Formal Verification of Floating-Point Hardware with Assertion-Based VIP | Ravi Ram, Adam Elkins, Adnan Pratama, Sasa Stamenkovic, Sven Beyer, and Sergio Marchese | | | | | |
| Formal verification of low-power RISC-V processors | Ashish Darbari | | | | | |
| Formal Verification of Macro-op Cache for Arm Cortex-A77, and its Successor CPU | Vaibhav Agrawal | | | | | |
| Formal verification of Macro-op cache for Arm Cortex-A77, and its successor CPU | Vaibhav Agrawal | | | | | |
| Formal Verification of Silicon for Software Defined Networking | Saurabh Shrivastava, Keqin Han, Anh Tran, Chirag Agarwal, Ankit Saxena, Achin Mittal, Anshul Jain, and Roger Sabbagh | | | | | |
| Formal Verification on Deep Learning Instructions of GPU | Jian (Jeffrey) Wang and Jia Zhu | | | | | |
| Formal Verification Tutorial Breaking Through the Knowledge Barrier | Sean Safarpour, Iain Singleton, Shaun Feng, Syed Suhaib, and Mandar Munishwar | | | | | |
| Formal Verificationin the Real World | Jonathan Bromley and Jason Sprott | | | | | |
| Formalize the Cache: Formal Verification Techniques to Verify Different Cache Configurations | Sudhanshu Srivastava, Rupali Tewari, Aman Vyas, Sachin Kumawat | | | | | |
| FPGA Debug Using Configuration Readback | Mike Dini | | | | | |
| FPGA Implementation Validation and Debug | Rohit Goel, Rakesh Jain, Aman Rana, Ankit Goel | | | | | |
| FPGA-based Clock Domain Crossing Validation for Safety-Critical Designs | Alexander Gnusin | | | | | |
| FPGA-based Clock Domain Crossing Validation for Safety-Critical Designs | Alexander Gnusin | | | | | |
| Framework for Creating Performance Model of AI Algorithms for Early Architecture Exploration | Amit Dudeja, Amit Tara, Amit Garg, Tushar Jain | | | | | |
| Framework for Creating Performance Model of AI Algorithms for Early Architecture Exploration | Amit Dudeja, Amit Tara, Amit Garg, Tushar Jain | | | | | |
| Framework For Exploring Interconnect Level Cache Coherency | Parvinder Pal Singh | | | | | |
| Framework for Holistic Assessment of Potential Performance Gains with Different Simulation Acceleration Modes | Parag Goel, Adiel Khan, Amit Sharma | | | | | |
| Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF | Progyna Khondkar, Ping Yeung, Gabriel Chidolue, Joe Hupcey, Rick Koster, and Madhur Bhargava | | | | | |
| Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF | Progyna Khondkar, Ping Yeung, Gabriel Chidolue, Joe Hupcey, Rick Koster, and Madhur Bhargava | | | | | |
| From Device Trees to Virtual Prototypes | Sakshi Arora, Vikrant Kamboj, Preeti Sharma | | | | | |
| From Spec to Verification Closure: a case study of applying UVM-MS for first pass success to a complex Mixed-Signal SoC design | Neyaz Khan and Yaron Kashai | | | | | |
| From Spec to Verification Closure: A case study of applying UVM-MS for first pass success to a complex MS-SoC design | Neyaz Khan and Yaron Kashai | | | | | |
| From the Magician’s Hat: Developing a Multi-Methodology PCIe Gen2 VIP | Amit Sharma, Abhisek Verma, Varun S., and Anoop Kumar | | | | | |
| fsim_logic – A VHDL type for testing of FLYTRAP | Joanne E. DeGroat, Ph.D. | | | | | |
| fsim_logic – A VHDL type for testing of FLYTRAP | Joanne E. DeGroat, Ph.D. | | | | | |
| FSM Minesweeper – Scalable Formal Verification Methodology for Detecting Hangs in Interacting FSMs | Anshul Jain, Achutha KiranKumar V M, Harbaksh Gupta, Shashwat Singh | | | | | |
| FSM Minesweeper – Scalable FV Methodology for Detecting Hangs in Interacting FSMs | Anshul Jain, Achutha KiranKumar V M, Harbaksh Gupta, Shashwat Singh | | | | | |
| Full Flow Clock Domain Crossing – From Source To Si | Mark Litterick | | | | | |
| Full Flow Clock Domain Crossing – From Source to Si | M. Litterick | | | | | |
| Fully Automated Functional Coverage Closure | Manohar Kodi, Sagar Sudam Patil, and Ranjith Nair | | | | | |
| Fully Automated Functional Coverage Closure | Manohar Kodi, Sagar Sudam Patil, and Ranjith Nair | | | | | |
| Fully Hierarchical CDC Analysis Using Comprehensive CDC Meta Database | Youngchan Lee, Youngsik Kim, Soenil Brian Choi, and Vikas Sachdeva | | | | | |
| Fully Hierarchical CDC Analysis Using Comprehensive CDC Meta-Database | Youngchan Lee, Youngsik Kim, and Seonil Brian Choi | | | | | |
| Fun with UVM Sequences – Coding and Debugging | Rich Edelman | | | | | |
| Fun with UVM Sequences Coding and Debugging | Rich Edelman | | | | | |
| Functional Coverage – without SystemVerilog! | Alan Fitch and Doug Smith | | | | | |
| Functional Coverage Collection for Analog Circuits – Enabling Seamless Collaboration between Design and Verification | Z. Ye, H. Lin and A. M. Khan | | | | | |
| Functional Coverage Collection for Analog Circuits –Enabling Seamless Collaboration between Design and Verification | Zhipeng Ye, Honghuang Lin and Asad Khan | | | | | |
| Functional Coverage Generator | Munjal Mistry | | | | | |
| Functional Coverage of Register Access via Serial Bus Interface using UVM | D. M. Tomušilović | | | | | |
| FUNCTIONAL COVERAGE OF REGISTER ACCESS VIA SERIAL BUS INTERFACE USING UVM | Darko M. Tomušilovic | | | | | |
| Functional coverage-driven verification with SystemC on multiple level of abstraction | Christoph Kuznik and Wolfgang M¨uller | | | | | |
| Functional Instruction Set Simulator (ISS) of a Neural Network Accelerator IP with native “brain float16” format | Debajyoti Mukherjee, Arpita Sahu, Arathy B S, Saranga P Pogula | | | | | |
| Functional safety architecture that suppresses increases in circuit size and power consumption in ISO26262 compliant LSI development slides | Toshiyuki Hamatani | | | | | |
| Functional Safety Verification For ISO 26262 | Kevin Rich, Shekhar Mahatme, and Meirav Nitzan | | | | | |
| Functional Safety Verification for ISO 26262 – Compliant Automotive Designs | JM Forey and Werner Kerscher | | | | | |
| Functional Safety Verification Methodology for ASIL-B Automotive Designs | Onkar Bhuskute | | | | | |
| Functional Safety WG Update | Alessandra Nardi | | | | | |
| Functional Verification of CSI2 Rx-PHY using AMS Co-simulations | Ratheesh Mekkadan | | | | | |
| Functional Verification of CSI-2 Rx-PHY using AMS Co-simulations | Ratheesh Mekkadan | | | | | |
| Functional Verification of CSI-2 Rx-PHY using AMS Co-simulations | Ratheesh Mekkadan | | | | | |
| Functional-Coverage Sampling in UVM RAL Use of 2 Obscure Methods | Muneeb Ulla Shariff, Ravi Reddy | | | | | |
| Functional-Coverage Sampling in UVM RAL: Use of 2 Obscure Methods | Muneeb Ulla Shariff, Ravi Reddy | | | | | |
| FV: A Robust Solution for Tackling Design Complexities – A Case Study on In-Band ECC | Yash Sachin Pawar, Aarti Gupta, Disha Puri | | | | | |
| FV: A Robust Solution for Tackling Design Complexities – A Case Study on In-Band ECC | Yash Sachin Pawar, Aarti Gupta, Disha Puri | | | | | |
| Gatelevel Simulations: Continuing Value in Functional Simulation | Ashok Chandran, Roy Vincent | | | | | |
| Gatelevel Simulations: Continuing Value in Functional Simulations | Ashok Chandran, Roy Vincent | | | | | |
| Gathering Memory Hierarchy Statistics in QEMU | Clément Deschamps, Mark Burton, Eric Jenn and Frédéric Pétrot | | | | | |
| Gathering Memory Hierarchy Statistics in QEMU | Clément Deschamps, Mark Burton, Eric Jenn, and Frédéric Pétrot | | | | | |
| Generating Bus Traffic Patterns | Jacob Sander Andersen, Lars Viklund and Kenneth Branth | | | | | |
| Generation of (at least) UVM Register Models from IP Xact Using Model Driven SW Techniques | Jacob Sander Andersen | | | | | |
| Generation of Constraint Random Transactions for Verification of Mixed-Signal Blocks | Alexander W. Rath, Sebastian Simon, Volkan Esen, and Wolfgang Ecker | | | | | |
| Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS* | Ronan Lucas, Marie-Minerve Louërat, Yao Li, Zhi Wang, Jean-Paul Chaput, François Pêcheux, Ramy Iskander, Martin Barnasconi, and Thilo Vörtler | | | | | |
| Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS* | Ronan Lucas and Philippe Cuenot | | | | | |
| Generic Core-Monitor for Hardware/Software Co-Debugging targeting Emulation Platform | Shreya Morgansgate, Johannes Grinschgl, Djones Lettnin | | | | | |
| Generic High-Level Synthesis Flow from MATLAB/Simulink Model | Petri Solanti, Shusaku Yamamoto | | | | | |
| Generic High-Level Synthesis Flow from MATLAB/Simulink Model | Petri Solanti, Shusaku Yamamoto | | | | | |
| Generic Programming in SystemVerilog | Mark Glasser | | | | | |
| Generic SCSI-Based Host Controller Verification Framework Using SystemVerilog | Mohamed Rayan, Mohamed Samy, Haytham Ashour, Ashraf Salem | | | | | |
| Generic Solution for NoC design exploration | Tushar Garg | | | | | |
| Generic Solution for NoC design exploration | Tushar Garg and Ranjan Mahajan | | | | | |
| Generic Solution for NoCdesign exploration | Tushar Garg and Ranjan Mahajan | | | | | |
| Generic Solution for NoCdesign exploration | Tushar Garg and Ranjan Mahajan | | | | | |
| Generic Testbench/Portable Stimulus/Promotability | Revati Bothe and Jesvin Johnson | | | | | |
| Generic Verification Infrastructure around Serial Flash Controllers | Harsimran Singh, Snehlata Gutgutia, Chanpreet Singh | | | | | |
| Get Ready for UVM-SystemC | Martin Barnasconi, Anupam Bakshi | | | | | |
| Getting Beyond ISA Compliance: Advanced Core/SoC Verification for RISC-V and other Beasts | Adnan Hamid | | | | | |
| Getting Rid of False Errors when Verifying LSI Designs Including Non-Determinism | Matthieu Parizy and Hiroaki Iwashita | | | | | |
| Git for Hardware Designers | Jeffery Scott and Sanjeev Singh | | | | | |
| GIT for Hardware Designers | Jeffery Scott and Sanjeev Singh | | | | | |
| Global Broadcast with UVM Custom Phasing | Jeremy Ridgeway, Dolly Mehta | | | | | |
| Global Broadcast with UVM Custom Phasing | Jeremy Ridgeway and Dolly Mehta | | | | | |
| Go Figure – UVM Configure The Good, The Bad, The Debug | Rich Edelman and Dirk Hansen | | | | | |
| Go Figure – UVM Configure The Good, The Bad, The Debug | Rich Edelman and Dirk Hansen | | | | | |
| Goal Driven Stimulus Solution Get Yourself Out of the Redundancy Trap | Rohit Bansal | | | | | |
| Goal Driven Stimulus Solution Get Yourself Out of the Redundancy Trap | Rohit Bansal | | | | | |
| Golden UPF: Preserving Power Intent From RTL to Implementation | Himanshu Bhatt and Harsh Chilwal | | | | | |
| Goldilocks and System Performance Modeling | Rich Edelman and Shashi Bhutada | | | | | |
| Goldilocks and System Performance Modelling A SystemVerilog Adaptive Rate Control (ARC) Stimulus Generation Methodology | Rich Edelman and Shashi Bhutada | | | | | |
| GoldMine: Automatic Assertion Generation and Coverage Closure in Design Validation | David Sheridan, Lingyi Liu, and Shobha Vasudevan | | | | | |
| Graph-IC Verification | Dennis Ramaekers and Grégory Faux | | | | | |
| Graph-IC Verification | Gregory Faux and Dennis Ramaekers | | | | | |
| GraphCov: RTL Graph Based Test Biasing for Exploring Uncharted Coverage Landscape | Debarshi Chatterjee, Spandan Kachhadia, Chen Luo, Kumar Kushal, Siddhanth Dhodhi | | | | | |
| GraphCov: RTL Graph Based Test Biasing for Exploring Uncharted Coverage Landscape | Debarshi Chatterjee, Spandan Kachhadia, Chen Luo, Kumar Kushal, Siddhanth Dhodhi | | | | | |
| Graphical Topology Info Structure for Constrained Random Verification in SoC/Subsystem Tests | Evean Qin, Richard Bell, and David Chen | | | | | |
| Graphical Topology Info Structure for Constrained Random Verification in SoC/Subsystem Tests | Evean Qin, Richard Bell, and David Chen | | | | | |
| Guaranteed Vertical Reuse – C Execution In A UVM Environment | Rachida El Idrissi and Alain Gonier | | | | | |
| Guaranteed Vertical Reuse – C Execution In a UVM Environment | Rachida El Idrissi and Alain Gonier | | | | | |
| Guiding Functional Verification Regression Analysis Using Machine Learning and Big Data Methods | Eman El Mandouh, Laila Maher, Moutaz Ahmed and Amr G. Wassal | | | | | |
| Handling Asynchronous Reset(s) Testing by building reset-awareness into UVM testbench components | Wei Wei Cheong, Katherine Garden, Ana Sanz Carretero | | | | | |
| Hardware Acceleration for UVM Based CLTs | Mohamed Saheel, Rohith M. S., and Andrew Tan | | | | | |
| Hardware construction with SystemC | Roman Popov and Roman Popov | | | | | |
| Hardware Emulation: ICE vs Virtual | Lauro Rizzatti | | | | | |
| Hardware Implementation of Smallscale Parameterized Neural Network Inference Engine | Vishnu P Bharadwaj, Shruti Narake, Saurabh D Patil | | | | | |
| Hardware Security – Industry Trends, Attacks and Solutions | Shashank Kulkarni | | | | | |
| Hardware Software Co-verification in Hybrid QEMU/HDL Environment | Radoslaw Nawrot and Krzysztof Szczur | | | | | |
| Hardware Trojan Design and Detection with Formal Verification to Deep Neural Network | Si-Han Chen, Yu-Ting Huang, Yi-Chun Kao, Yean-Ru Chen, Shang-Wei Lin, Chia-I Chen | | | | | |
| Hardware verification through software scheduling for USB using xHCI | Wasiq Zia, Navneet Jha, and Vipin Chauhan | | | | | |
| Hardware verification through software scheduling for USB using xHCI | Wasiq Zia, Navneet Jha, and Vipin Chauhan | | | | | |
| Hardware verification through software scheduling for USB using xHCIThe | Wasiq Zia, Navneet Jha, and Vipin Chauhan | | | | | |
| Hardware verification through software scheduling for USB using xHCIThe | Wasiq Zia, Navneet Jha, and Vipin Chauhan | | | | | |
| Hardware/Software Co-Simulation of SPI enabled ASICs and Software Drivers for Fault Injection and Regression Tests | Elias Kyrlies-Chrysoulidis, Andreas Plange, Thomas Gürtler, Matthias Auerswald, and Josef Schmid | | | | | |
| Hardware/Software Co-Simulation of SPI enabled ASICs and Software Drivers for Fault Injection and Regression Tests | Elias Kyrlies-Chrysoulidis, Andreas Plange, Thomas Guertler, Matthias Auerswald, and Josef Schmid | | | | | |
| Hardware/Software Co-Verification Using Generic Software Adapter | Vijaya Bhaskar, Krishna Chaitanya, Kirtika Sharma | | | | | |
| Hardware/Software Co-Verification Using Specman and SystemC with TLM Ports | Horace Chan | | | | | |
| Hardware/Software co-verification using Specman and SystemC with TLM ports | Horace Chan and Brian Vandegriend | | | | | |
| Hardware/Software Interface Formats A Discussion | Richard Weber, Jamsheed Agahi, Josh Rensch, Eric Sherk | | | | | |
| Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex PMIC designed for SSD Applications | Vijay Kumar, Shrikant Pattar, Yaswanth Chebrolu, Vinayak Hegde | | | | | |
| Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex PMIC designed for SSD Applications | Vijay Kumar, Shrikant Pattar, Yaswanth Chebrolu, Vinayak Hegde | | | | | |
| Harnessing the Power of UVM for AMS Verification with XMODEL | Jaeha Kim, Charles Dančak | | | | | |
| Has The Performance of a Sub-System Been Beaten to Death | Subhash Joshi, Vaddineni Manohar, Sangaiyah Pandithurai | | | | | |
| Heterogeneous Virtual Prototyping for IoTApplications | Paul Ehrilich, Karsten Einwich, Mark Burton, and Luc Michel | | | | | |
| Heterogenous Virtual Prototyping for IoT Applications | Mark Burton, Luc Michel, Paul Ehrlich, and Karsten Einwich | | | | | |
| Hierarchical UPF Design – The ‘Easy’ Way | Brandon Skaggs, Chris Turman, Joe Whitehouse | | | | | |
| Hierarchical UPF Design – The ‘Easy’ Way | Brandon Skaggs, Chris Turman, Joe Whitehouse | | | | | |
| Hierarchical UPF: Uniform UPF across FE & BE | Dipankar Narendra Arya, Balaji Vishwanath Krishnamurthy, Aditi Nigam, Tahir Ali | | | | | |
| Hierarchical UPF: Uniform UPF across FE & BE | Dipankar Narendra Arya, Balaji Vishwanath Krishnamurthy, Aditi Nigam, and Ali Tahir | | | | | |
| High Frequency Response Tracking System micro-architecture | Gopalakrishnan Sridhar, Vadlamuri Venkata Sateesh | | | | | |
| High Frequency Response Tracking System Micro-architecture | Gopalakrishnan Sridhar, Vadlamuri Venkata Sateesh | | | | | |
| High-Level Synthesis Walks the Talk: Synthesizing a Complete Graphics Processing Application | Thomas Bollaert | | | | | |
| High-Performance Mixed-Signal ESL Design of a Magneto Resistive Sensor Application | Martin Barnasconi and Sumit Adhikari | | | | | |
| High-Performance Mixed-Signal ESL Design of a Magneto Resistive Sensor Application | Martin Barnasconi and Sumit Adhikari | | | | | |
| High-Speed Interface IP Validation based on Virtual Emulation Platform | Jaehun Lee, Daeseo Cha, and Sungwook Moon | | | | | |
| High-Speed Interface IP Validation based on Virtual Emulation Platform | Jaehun Lee, DaeSeo Cha, and Sungwook Moon | | | | | |
| Highly Configurable UVM Environment for Parameterized IP Verification | HongLiang Liu and Karl Whiting | | | | | |
| Highly Configurable UVM Environment for Parameterized IP Verification | HongLiang Liu and Karl Whiting | | | | | |
| Highly Flexible and Robust System Level HW-SW Power Management Verification based on RISC-V | Subramanian Ravichandran, Sekhar Dangudubiyyam | | | | | |
| HISIG- An Efficient Gate Level Simulation Flow for a Hard IP Inside a Soft IP | Ishwar Ganiger, Vishal Dalal, Johannes Grinschgl | | | | | |
| HISIG- An Efficient Gate Level Simulation Flow for a Hard IP Inside a Soft IP | Ishwar Ganiger, Vishal Dalal, Johannes Grinschgl | | | | | |
| Holistic Approach to IO Timing Verification Using Portable Stimulus and Assertions | Amitesh Khandelwal and Praveen Kumar | | | | | |
| Holistic Approach to IO Timing Verification Using Portable Stimulus and Assertions | Amitesh Khandelwal and Praveen Kumar | | | | | |
| Holistic Automated Code Generation: No Headache with Last-Minute Changes | Klaus Strohmayer and Norbert Pramstaller | | | | | |
| Holistic Automated Code Generation: No Headache with Last-Minute Changes | Klaus Strohmayer and Norbert Pramstaller | | | | | |
| Holistic Verification of Bus Health Monitor in Automotive SoC using BHMVC and ParaHunter | Gaurav Kumar Yadav, Abhisek Hota, Prashantkumar Sonavane | | | | | |
| Holistic Verification of Bus Health Monitor in Automotive SoC using BHMVC and ParaHunter | Gaurav Kumar Yadav, Abhisek Hota, Prashantkumar Shukranath Sonavane, Garima Srivastava | | | | | |
| Holistic Verification of Bus Health Monitor in Automotive SoC using BHMVC and ParaHunter | Gaurav Kumar Yadav, Abhisek Hota, Prashantkumar Shukranath Sonavane, Garima Srivastava | | | | | |
| Hopscotch: A Scalable Flow-Graph Based Approach to Formally Specify and Verify Memory-Tagged Store Execution in Arm CPUs | Abhinav Sethi, Madhu Iyer, Sai Komaravelli, and Vikram Khosa | | | | | |
| Hopscotch: A Scalable Flow-Graph Based Approach to Verify CPU Store Execution | Abhinav Sethi, Madhu Iyer, Sai Komaravelli, and Vikram Khosa | | | | | |
| How creativity kills reuse – A modern take on UVM/SV TB architecture | Andrei Vintila, Sergiu Duda | | | | | |
| How creativity kills reuse – A modern take on UVM/SV TB architectures | Andrei Vintila, Sergiu Duda | | | | | |
| How Do You Verify Your Verification Components? | Josh Rensch and Neil Johnson | | | | | |
| How Far Can You Take UVM Code Generation and Why Would You Want To? | John Aynsley | | | | | |
| How Far Can You Take UVM Code Generation and Why Would You Want To? | John Aynsley | | | | | |
| How Far Can You Take UVM Code Generation and Why Would You Want To? | John Aynsley | | | | | |
| How Far Can You Take UVM Code Generation and Why Would You Want To? | John Aynsley | | | | | |
| How HLS and SystemC is Delivering on its Promise of Design and Verification Productivity | Stuart Swan, Mike Meredith, Matthew Bone, and Rangharajan Venkatesan | | | | | |
| How I Learned to Stop Worrying and Love Benchmarking Functional Verification! | Mike Bartley | | | | | |
| How I Learned to Stop Worrying and Love Benchmarking Functional Verification! | Mike Bartley and Mike Benjamin | | | | | |
| How rich descriptions enable early detection of hookup issues | Peter Birch, Thomas Brown | | | | | |
| How the Right Mindset Increases Quality in RISC-V Verification | Philippe Luc, Salaheddin Hetalani, Nicolae Tusinschi | | | | | |
| How the Right Mindset Increases Quality in RISC-V Verification | Philippe Luc, Salaheddin Hetalani | | | | | |
| How to achieve verification closure of configurable code by combining static analysis and dynamic testing | Antonello Celano, Alexandre Langenieux | | | | | |
| How to achieve verification closure of configurable code by combining static analysis and dynamic testing | Antonello Celano, Alexandre Langenieux | | | | | |
| How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage | Mark Eslinger, Joseph V Hupcey III, and Nicolae Tusinschi | | | | | |
| How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage | Mark Eslinger, Joseph V Hupcey III, and Nicolae Tusinschi | | | | | |
| How to Create a Complex Testbench in a Couple of Hours | Tom Fitzpatrick and Graeme Jessiman | | | | | |
| How to Create Reusable Portable Testing and Stimulus Standard (PSS) Verification IP | Sharon Rosenberg | | | | | |
| How to Kill 4 Birds with 1 Stone: Using Formal Verification to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software Specifications | Saurabh Shrivastava, Kavita Dangi, Darrow Chu, and Mukesh Sharma | | | | | |
| How to Kill 4 Birds with 1 Stone: Using Formal Verification to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software Specifications | Saurabh Shrivastava, Kavita Dangi, Darrow Chu, and Mukesh Sharma | | | | | |
| How to make debug more efficient in day-to-day life using Verisium Debug | Kiran Kumar Indrakanti, Sai Asrith Tabdil | | | | | |
| How to Overcome Editor Envy: Why Can’t My Editor Do That? | Dillan Mills, Chuck McClish | | | | | |
| How to overcome the hurdle of customizing RISC-V with formal | Pascal Gouédo, Seiya Nakagawa, Nicolae Tusinschi, Salaheddin Hetalani | | | | | |
| How to Reuse Sequences with the UVM-ML Open Architecture library | Hannes Fröhlich and Kishore Sur | | | | | |
| How to Stay Out of the News with ISO26262-Compliant Verification | Charles Battikha and Doug Smith | | | | | |
| How to Succeed Against Increasing Pressure: Automated Techniques for Unburdening Verification Engineers | James Pascoe and Steve Hobbs | | | | | |
| How to Succeed Against Increasing Pressure: Automated Techniques for Unburdening Verification Engineers | James Pascoe, Pierre Kuhn, and Steve Hobbs | | | | | |
| How to test the whole firmware/software when the RTL can’t fit the emulator | Horace Chan and Byron Watt | | | | | |
| How to test the whole firmware/software when the RTL can’t fit the emulator | Horace Chan and Byron Watt | | | | | |
| How to Use Formal Analysis to Prevent Deadlocks | Abdelouahab Ayari, Mark Eslinger and Joe Hupcey III | | | | | |
| How to Verify Complex FPGA Designs for Free | Sebastian Dreßler, Nikos Anastasiadis, and Thomas Richter | | | | | |
| How to Verify Complex FPGA Designs for Free | Sebastian Dreßler, Nikos Anastasiadis, and Thomas Richter | | | | | |
| How To Verify Encoder And Decoder Designs Using Formal Verification | Jin Hou | | | | | |
| How To Verify Encoder And Decoder Designs Using Formal Verification | Jin Hou | | | | | |
| How UPF 3.1 Reduces the Complexities of Reusing PA Macros | Madhusudhana Reddy Lebaka, Abraham Guizer, and Progyna Khondkar | | | | | |
| How UPF 3.1 Reduces the Complexities of Reusing Power Aware Macros | Madhusudhana Reddy Lebaka, Abraham Guizer, and Progyna Khondkar | | | | | |
| HSI Issues – Fake News or Not? How Hardware/Software Interface Impacts Tape-Outs | Gary Stringham, Rich Weber, and Jamsheed Agahi | | | | | |
| Hybrid Approach to Testbench and Software Driven Verification on Emulation | Debdutta Bhattacharya and Ayub Khan | | | | | |
| Hybrid Approach to Testbench and Software Driven Verification on Emulation | Debdutta Bhattacharya and Ayub Khan | | | | | |
| Hybrid Emulation Use Cases | Sylvain Bayon de Noyer | | | | | |
| Hybrid Emulation: Accelerating Software Driven Verification and Debug | Issac P Zacharia and Jitendra Aggarwal | | | | | |
| Hybrid Emulation: Accelerating Software Driven Verification and Debug | Issac P Zacharia and Jitendra Aggarwal | | | | | |
| Hybrid Emulation: Accelerating Software Driven Verification and Debug | Issac P Zacharia and Jitendra Aggarwal | | | | | |
| Hybrid Emulation: Accelerating Software Driven Verification and Debug | Issac P Zacharia and Jitendra Aggarwal | | | | | |
| Hybrid Flow: A smart methodolgy to migrate from traditional Low Power Methodology | Rohit Kumar Sinha and N. Prashanth | | | | | |
| Hybrid Flow: A smart methodology to migrate from traditional Low Power Methodology | Rohit Kumar Sinha and Prashanth N | | | | | |
| I created the Verification Gap | Ram Narayan and Tom Symons | | | | | |
| I created the Verification Gap | Ram Narayan and Tom Symons | | | | | |
| I’m Still In Love With My X! (but, do I want my X to be an optimist, a pessimist, or eliminated?) | Stuart Sutherland | | | | | |
| I’m Still In Love With My X! (but, do I want my X to be an optimist, a pessimist, or eliminated?) | Stuart Sutherland | | | | | |
| IDeALS for all – Intelligent Detection and Accurate Localization of Stalls | Pallavi Jesrani | | | | | |
| IDeALS For All – Intelligent Detection and Accurate Localization of Stalls | Pallavi Jesrani | | | | | |
| Identifying and Overcoming Multi-Die System Verification Challenges | Varun Agrawal | | | | | |
| Identifying unique power scenarios with data mining techniques at full SoC level with real workloads | Amir Attarha | | | | | |
| Identifying unique power scenarios with data mining techniques at full SoC level with real workloads | Amir Attarha, Pankaj Chauhan, Diwakar Agrawal, Satish-Kumar Agrawal, Gaurav Saharawat | | | | | |
| IDEs SHOULD BE AVAILABLE TO HARDWARE ENGINEERS TOO! | Syed Daniyal Khurram and Horace Chan | | | | | |
| IDEs Should be Available to Hardware Engineers Too! | Syed Daniyal Khurram and Horace Chan | | | | | |
| IEEE 1800-2009 SystemVerilog: Assertion-based Checker Libraries | Eduard Cerny and Dmitry Korchemny | | | | | |
| IEEE 1800.2 UVM – Changes Useful UVM Tricks & Techniques | Clifford E. Cummings | | | | | |
| IEEE 1801 Assisted Custom IP Development and Low Power Checks Using Cadence Virtuoso Power Manager | Dr. Matthias Steffen, Amit Chopra and Amit Chopra | | | | | |
| IEEE 1801 Assisted Custom IP Development and Low Power Checks Using Cadence Virtuoso Power Manager | Matthias Steffen, Amit Chopra, and Sonal Singh | | | | | |
| IEEE-Compatible UVM Reference Implementation and Verification Components | Justin Refice, Mark Strickland, Mark Peryer, Uwe Simm, and Srivatsa Vasudevan | | | | | |
| IEEE2804 SHIM: Software-Hardware Interface for Multi-Many-Core | Masato Edahiro | | | | | |
| Implementation of a closed loop CDC verification methodology | Andrew Cunningham, Ireneusz Sobanski | | | | | |
| Implementation of a closed loop CDC verification methodology | Andrew Cunningham | | | | | |
| Improve Emulator Test Quality By Applying Synthesizable Functional Coverage | Hoyeon Hwang, Taesung Kim, Sanghyun Park, Yong-Kwan Cho, Dohyung Kim, Wonil Cho, Sanggyu Park | | | | | |
| Improve emulator test quality by applying synthesizable functional coverage | Hoyeon Hwang, Taeseong Kim, Sanghyun Park, Yong-Kwan Cho, Dohyung Kim, Wonil Cho, Sanggyu Park | | | | | |
| Improve the quality of SystemC IPs through coverage-driven random verification | Trung Pham, Huy Phan, Masayuki Masuda | | | | | |
| Improvement of UVM IP Validation using Portable Stimulus (PSS) | Robert R Martin, Alan M Curtis, Gopinath Narasimhan, Qingwei Zhou | | | | | |
| Improvement of UVM Scenario Generation, Control and Reproducibility using Portable Stimulus (PSS) for IP Validation | Robert R. Martin, Alan M. Curtis, Gopinath L. Narasimhan, Qingwei Zhou | | | | | |
| Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation | Eldon Nelson M.S. P.E. | | | | | |
| Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation | Eldon Nelson M.S. P.E. | | | | | |
| Improving Debug Productivity using latest AI & ML Techniques | Amod Khandekar, Sundararajan Ananthakrishnan, Amit Verma | | | | | |
| Improving Simulation Performance at SoC/Subsystem Level Using LITE Environment Approach | Avni Patel, Heena Mankad | | | | | |
| Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification | Deepak Narayan Gadde, Sebastian Simon, Djones Lettnin, Thomas Ziller | | | | | |
| Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification | Deepak Narayan Gadde, Sebastian Simon, Djones Lettnin, Thomas Ziller | | | | | |
| Improving Software Testing Speed by 100X with SystemC Virtualization in IoT Devices | David Barahona, Motaz Thiab, Isael Díaz, Joakim Urdahl, and Milica Orlandic | | | | | |
| Improving the Confidence Level in Functional Safety Simulation Tools for ISO 26262 | Ahmet Cagri Bagbaba, Felipe Augusto Da Silva, and Christian Sauer | | | | | |
| Improving the UVM Register Model: Adding Product Feature based API for Easier Test Programming | Krishnan Balakrishnan, Courtney Fricano, and Kaushal Modi | | | | | |
| Improving the UVM Register Model: Adding Product Feature based API for Easier Test Programming | Krishnan Balakrishnan, Courtney Fricano, and Kaushal Modi | | | | | |
| Improving Verification Predictability and Efficiency Using Big Data | Darron K. May | | | | | |
| Improving Verification Predictability and Efficiency Using Big Data | Darron May | | | | | |
| In pursuit of Faster Register Abstract Layer (RAL) Model | Anmol Rana, Bhagwan Jha, and Harjeet Singh Sanga | | | | | |
| Incomplete Low-Power Verification Flow & the oncoming Internet of Things (IoT) Tsunami! | Neyaz Khan and Kamran Haqqani | | | | | |
| Increase Productivity with Reflection API in Design Verification | Shivayogi V. Kerudi, Vijay Mukund Srivastav, Vani S, Brad Quinton | | | | | |
| Increased Regression Efficiency with Jenkins Continuous Integration | Thomas Ellis | | | | | |
| Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee | Thomas Ellis | | | | | |
| Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee | Thom Ellis | | | | | |
| Increasing Efficiency and Reuse in Modeling SystemC/TLM IPs Targeting Virtual Prototypes for Software Development | David Spieker, Thomas Schuster, Rafael Zuralski, and Christian Sauer | | | | | |
| Increasing Regression Efficiency with Portable Stimulus | Niyaz. K. Zubair and Subba Kota Rao Sajja | | | | | |
| Indago™ Debug Platform Overview | | | | | | |
| Innovative methodologies for analyzing CDC and RDC violations in complex SoC using Automations, formal verification, and Hierarchical CDC model | Maitri Mishra, Dharmendra Kumar | | | | | |
| Innovative Techniques to Solve Complex RDC Challenges | Rohit Kumar Sinha | | | | | |
| Innovative Technological Narratives Leveraging the Idea of Authenticity in a Human Being | Anna M. Ravitzki, Uri Feigin, and Hagai Arbel | | | | | |
| Innovative Uses of SystemVerilog Bind Statements within Formal Verification | Xiushan Feng and Christopher Starr | | | | | |
| Innovative Uses of SystemVerilog Bind Statements within Formal Verification | Xiushan Feng and Christopher Starr | | | | | |
| Institutionalize a certified ISO26262 safety process | M. Rohleder, C. Röttgermann, amd M. Müller | | | | | |
| Institutionalizing a certified ISO26262 safety process: Experiences and lessons learned | Michael Rohleder, Clemens Röttgermann, and Marcus Müller | | | | | |
| Integrating a Virtual Platform Framework for Smart Devices | V. Guarnieri, F. Stefanni, F. Fummi, M. Grosso, D. Lena, A. Ciccazzo, G. Gangemi, and S. Rinaudo | | | | | |
| Integrating Different Types of Models into a Complete Virtual System | Jakob Engblom, Andreas Hedström, Xiuliang Wang, and Håkan Zeffer | | | | | |
| Integrating Different Types of Models into a Complete Virtual System: The Simics SystemC* Library | Jakob Engblom, Andreas Hedström, Xiuliang Wang, and Håkan Zeffer | | | | | |
| Integrating L1 & L2 Cache for multi-Core UVM-based extended Low Power Library Package | Avnita Pal, Priyanka Gharat, Sastry Puranapanda | | | | | |
| Integrating L1&L2 Cache for multi-Core UVM based extended Low Power Library Package | Avnita Pal, Priyanka Gharat, Sastry Puranapanda | | | | | |
| Integrating Parallel SystemC Simulationinto Simics® Virtual Platform | Daniel Mendoza, Ajit Dingankar, ZhongqiCheng and Rainer Doemer | | | | | |
| Integrating Parallel SystemC Simulationinto Simics® Virtual Platform | Daniel Mendoza, Ajit Dingankar, Zhongqi Cheng and Rainer Doemer | | | | | |
| Integration of HDL Logic inside SystemVerilog UVM based Verification IP | Aleksandra Panajotu | | | | | |
| Integration of HDL Logic inside SystemVerilog UVM based Verification IP | Aleksandra Panajotu | | | | | |
| Integration of modern verification methodologies in a TCL test framework | Matteo De Luigi and Alessandro Ogheri | | | | | |
| Intelligent Coverage Driven, Modern Verification for VHDL Based Designs in Native VHDL with OSVVM | Vijay Mukund Srivastav, Anupam Maurya, Prabhat Kumar, Juhi | | | | | |
| Interface Centric UVM Acceleration for Rapid SOC Verification | Jiwoong Kim, Yoona Lhim, Hyungjin Park, Hyunsun Ahn, and Seonil Brian Choi | | | | | |
| Interfacing Python with a Systemverilog Test Bench | Lakshay Grover and Kaushal Modi | | | | | |
| INTERPRETING UPF FOR A MIXED-SIGNAL DESIGN UNDER TEST | Kenneth Bakalar and Eric Jeandeau | | | | | |
| Interpreting UPF for aMixed‐Signal Design Under Test | | | | | | |
| Introducing IEEE 1800.2 the Next Step for UVM | Srivatsa Vasudevan | | | | | |
| Introducing UVM-SystemC For a Resilient And Structured ESL Validation | Akhila M | | | | | |
| Introducing your team to an IDE | S. Dawson and M. Ballance | | | | | |
| Introduction to Accellera TLM 2.0 | Aravinda Thimmapuram | | | | | |
| Introduction to Next Generation Verification Language – Vlang | Puneet Goel and Sumit Adhikari | | | | | |
| Introduction to Next Generation Verification Language – Vlang | Puneet Goel and Sumit Adhikari | | | | | |
| Introduction to the 5 Levels of RISC-V Processor Verification | Simon Davidmann and Lee Moore | | | | | |
| Introspection Into Systemverilog Without Turning It Inside Out | Dave Rich | | | | | |
| INTROSPECTION INTO SYSTEMVERILOG WITHOUT TURNING IT INSIDE OUT. | Dave Rich | | | | | |
| IP Generators – A Better Reuse Methodology | Amanjyot Kaur | | | | | |
| IP Generators -A Better Reuse Methodology | Amanjyot Kaur | | | | | |
| IP Security Assurance Workshop: Introduction | Mike Borza, Ambar Sarkar, Adam Sherer, and Brent Sherman (in spirit) | | | | | |
| IP-Coding Style Variants in a Multi-layer Generator Framework | Zhao Han, Keerthikumara Devarajegowda, Andreas Neumeier, and Wolfgang Ecker | | | | | |
| IP-Coding Style Variants in a Multi-layer Generator Framework | Zhao Han, Keerthikumara Devarajegowda, Andreas Neumeier and Wolfgang Ecker | | | | | |
| IP-XACT based SoC Interconnect Verification Automation | YoungRae Cho, YoungSik Kim, and Seonil Brian Choi | | | | | |
| IP-XACT based SoC Interconnect Verification Automation | YoungRae Cho, YoungSik Kim, and Seonil Brian Choi | | | | | |
| IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 45 minutes! | Nikita Gulliya, Asif Ahmad, Devender Khari | | | | | |
| IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 90 minutes! | Nikita Gulliya, Neena Chandawale, and Anupam Bakshi | | | | | |
| Ironic But Effective: How Formal Analysis Can Perfect Your Simulation Constraints | Penny Yang, Jin Hou, Yuya Kao, Nan-Sheng Huang, Ping Yeung, and Joe Hupcey | | | | | |
| Ironic But Effective: How Formal Analysis Can Perfect Your Simulation Constraints | Penny Yang, Jin Hou, Yuya Kao, Nan-Sheng Huang, Ping Yeung, and Joe Hupcey | | | | | |
| Is It a Software Bug? Is It a Hardware Bug? | Horace Chan, Mame Maria Mbaye, and Sim Ang | | | | | |
| Is It a Software Bug? It Is a Hardware Bug? | Horace Chan, Maria Mbaye, and Sim Ang | | | | | |
| Is Power State Table (PST) Golden? | Ankush Bagotra, Neha Bajaj, and Harsha Vardhan | | | | | |
| Is Power State Table Golden? | Harsha Vardhan, Ankush Bagotra, and Neha Bajaj | | | | | |
| Is Specman Still Relevant? Using UVM-ML to Take Advantage of Multiple Verification Languages | Timothy Pertuit, Doug Gibson, and David Lacey | | | | | |
| Is Specman Still Relevant? Using UVM-ML to Take Advantage of Multiple Verification Languages | Timothy Pertuit, David Lacey, and Doug Gibson | | | | | |
| Is the simulator behavior wrong for my SystemVerilog code? | Weihua Han | | | | | |
| Is The Simulator Behavior Wrong With My SystemVerilog Code | Weihua Han | | | | | |
| Is Your Hardware Dependable? | DARPA, AMD, Arm Research, and Synopsys | | | | | |
| Is your Power Aware design really x-aware? | Durgesh Prasad and Jitesh Bansal | | | | | |
| Is your Power Aware design really x-aware? | Durgesh Prasad and Jitesh Bansal | | | | | |
| Is Your System’s Security preserved? Verification of Security IP integration | Predrag Nikolic | | | | | |
| Is Your System’s Security preserved? Verification of Security IP integration | Predrag Nikolic | | | | | |
| Is Your Testing N wise or Unwise? Pairwise and N wise Patterns in SystemVerilog for Efficient Test Configuration and Stimulus | Jonathan Bromley and Kevin Johnston | | | | | |
| Is Your Testing N-wise or Unwise? Pairwise and N-wise Patterns in SystemVerilog for Efficient Test Configuration and Stimulus | Jonathan Bromley and Kevin Johnston | | | | | |
| ISO 26262 Dependent Failure Analysis Using PSS | Moonki Jang | | | | | |
| ISO 26262 Dependent Failure Analysis using PSS | Moonki Jang, Jiwoong Kim, and Dongjoo Kim | | | | | |
| ISO 26262 Fault Analysis in Safety Mechanisms Considering the impact of residual and latent faults in hardware safety mechanisms | Jörg Grosse, Mark Hampton, Sergio Marchese, Jörg Koch, Neil Rattray and Alin Zagardan | | | | | |
| ISO 26262: Better be safe with modelling and simulation on system-level | Joachim Hößler, Sven Johr, Thang Nguyen, Stephan Schulz, and Gert-Jan Tromp | | | | | |
| ISO 26262: Better be safe with modelling and simulation on system-level | Joachim Hößler, Sven Johr, Thang Nguyen, Stephan Schulz, and Gert-Jan Tromp | | | | | |
| It Should Just Work! Tips and Tricks for Creating Flexible, Vendor Agnostic Analog Behavioral Models | Chuck McClish | | | | | |
| It’s Not Too Late to Adopt: The Full Power of UVM | Kathleen Wittmann | | | | | |
| It’s Been 24 Hours –Should I Kill My Formal Run? | Mark Eslinger, Jin Hou, Joe Hupcey III, and Jeremy Levitt | | | | | |
| It’s Not Too Late to Adopt: The Full Power of UVM | Kathleen Wittmann | | | | | |
| JESD204B Deterministic Latency Verification with UVM Constrained Random Approaches | Girish Nadiger and Ashok Chandran | | | | | |
| JESD204B Deterministic Latency Verification with UVM Constrained Random Approaches | Girish Nadiger and Ashok Chandran | | | | | |
| Jump start your RISCV project with OpenHW | Mike Thompson, Jingliang (Leo) Wang, Steve Richmond, Lee Moore, David McConnell, Greg Tumbush | | | | | |
| Jump-Start Portable Stimulus Test Creation with SystemVerilog Reuse | Matthew Ballance | | | | | |
| Jump-Start Portable Stimulus Test Creation with SystemVerilog Reuse | Matthew Ballance | | | | | |
| Jump-Start Software-Driven Hardware Verification with a Verification Framework | Matthew Ballance | | | | | |
| Jump-Start Software-Driven Hardware Verification with a Verification Framework | Matthew Ballance | | | | | |
| Just do it! Who cares if a Structural Analysis tool is using Formal Verification | Scott Aron Bloom | | | | | |
| Keeping Score, Part 1 of 2 – Architectural Considerations for Scoreboard Design | Gordon Allan | | | | | |
| Keeping Up with Chip — the Proposed SystemVerilog 2012 Standard Makes Verifying Ever-increasing Design Complexity More Efficient | Stuart Sutherland and Tom Fitzpatrick | | | | | |
| Keeping Up with Chip — the Proposed SystemVerilog 2012 Standard Makes Verifying Ever-increasing Design Complexity More Efficient | Stuart Sutherland | | | | | |
| Keeping Your Sequences Relevant | Nicholas Zicha and Eric Combes | | | | | |
| Key Gochas in implementing CDC for various Bus Protocols | Nikita Gulliya, Mukesh Kumar Singh, and Abhishek Bora | | | | | |
| Key Gochas in implementing CDC for various Bus Protocols | Nikita Gulliya, Mukesh Kumar Singh, and Abhishek Bora | | | | | |
| Keynote: Challenges in Soc Verification for 5G and Beyond | Axel Jahnke | | | | | |
| Keynote: Developing the Chip-to-Cloud Architecture for the Most Desirable Cars | Magnus Östberg | | | | | |
| Language Agnostic Communication for SystemC TLM Compliant Virtual Prototypes | Smurti Khire, Kunal Sharma, Vishal Chovatiya | | | | | |
| Lay it On Me: Creating Layered Constraints | Bryan Morris | | | | | |
| Lean Verification Techniques: Executable SystemVerilog UVM Defect Table For Simulations | Steve Burchfiel, Kevin Schott, Kamel Belhous and Paul Ulrich | | | | | |
| Lean Verification Techniques: Executable SystemVerilog UVM Defect Table For Simulations | Kamel Belhous and Steve Bu | | | | | |
| Leaping Left: Seamless IP to SoC Hand off | Swetha Thiagarajan, Rashika Madan, Hiran Morar, and Sangeivi Sivagnanasundaram | | | | | |
| Leaping Left: Seamless IP to SoC Hand-off | Swetha Thiagarajan, Rashika Madan, Hiran Morar, and Sangeivi Sivagnanasundaram | | | | | |
| Learning From Advanced Hardware Verification for Hardware Dependent Software | Simond Davidmann and Duncan Graham | | | | | |
| Left shift catching of critical low power bugs with Formal Verification | Manish Kumar, Madan Kumar, Madhusudhana Lebaka, Srobona Mitra | | | | | |
| Left shift catching of critical low power bugs with Formal Verification | Manish Kumar, Madan Kumar, Srobona Mitra, Madhusudhana Lebaka | | | | | |
| Left shift catching of critical low power bugs with Formal Verification | Manish Kumar, Madan Kumar, Madhusudhana Lebaka, Srobona Mitra | | | | | |
| Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges | Kotha Kavya and Sinha Rohit Kumar | | | | | |
| Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges | Rohit Kumar Sinha and Kavya Kotha | | | | | |
| Left Shift of Perf Validation Using Hardware-Based Acceleration | Abhiram.L.S, Anoop.H.C, Vijayakrishnan Rousseau, Vimpesh Kankariya | | | | | |
| Lessons from the field – IP/SoC integration techniques that work | David Murray and Sean Boylan | | | | | |
| Lessons from the field IP/SoC integration techniques that work | David Murray | | | | | |
| Let’s be Formal While Talking About Verification Quality: A Novel Approach to Qualify Assertion Based VIPs | Sachin Scaria, Surinder Sood, and Erik Seligman | | | | | |
| Let’s DisCOVER Power States | Pankaj Kumar Dwivedi, Amit Srivastava, and Veeresh Vikram Singh | | | | | |
| Lets be Formal While Talking About Verification Quality: A Novel Approach Of Qualifying Assertion Based IPs | Surinder Sood, Sachin Scaria, and Erik Seligman | | | | | |
| Lets disCOVER Power States | Pankaj Kumar Dwivedi, Amit Srivastava, and Veeresh Vikram Singh | | | | | |
| Leveraging ESL Approach to Formally Verify Algorithmic Implementations | M, Achutha KiranKumar V, Bindumadhava S S, Aarti Gupta, Disha Puri | | | | | |
| Leveraging Formal to Verify SoC Register Map | Abdul Elaydi and Jose Barandiaran | | | | | |
| Leveraging Formal to Verify SoC Register Map | Abdul Elaydi and Jose Barandiaran | | | | | |
| Leveraging hardware emulation to accelerate SoCverification in multi-physics automotive simulation environment via the Functional Mock-up Interface | Pierre-Guillaume Le Guay, Henrique Vicente De Souza, Caaliph Andriamisaina, Emmanuel Molina Gonzalez, and Tanguy Sassolas | | | | | |
| Leveraging hardware emulation to accelerate SoCverification in multi-physics automotive simulation environment via the Functional Mock-up Interface | Pierre-Guillaume Le Guay, Henrique Vicente De Souza, Caaliph Andriamisaina, Emmanuel Molina Gonzalez and Tanguy Sassolas | | | | | |
| Leveraging IEEE 1800.2-2017 UVM for Improved RAL Modelling | Vikas Sharma, Manoj Manu, Ankit Garg | | | | | |
| Leveraging IEEE 1800.2-2017 UVM for Improved RAL Modelling | Vikas Sharma, Manoj Manu, Ankit Garg | | | | | |
| Leveraging IP-XACT standardized IP interfaces for rapid IP integration | David Murray and Simon Rance | | | | | |
| Leveraging IP-XACT Standardized IP Interfaces for Rapid IP Integration | David Murray | | | | | |
| Leveraging more from GLS: Using metric driven GLS stimuli to boost timing verification | Sowmya Ega, Richardson Jeyapaul, and Kunal Jani | | | | | |
| Leveraging more from GLS: Using metric driven GLS stimuli to boost Timing Verification | Sowmya Ega, Richardson Jeyapaul, and Kunal Jani | | | | | |
| Leveraging RAL and alternate automation (cocotb) techniques to improve Register Verification in UVM | Sougata Bhattacharjee | | | | | |
| Leveraging the UVM RAL for Memory Sub-System Verification | Tudor Timisescu and Uwe Simm | | | | | |
| Leveraging the UVM Register Abstraction Layer for Memory Sub-System Verification | Tudor Timisescu and Uwe Simm | | | | | |
| Leveraging UVM-based Low Power Package Library to SOC Designs | Shikhadevi Katheriya, Avnita Pal, Puranapanda Sastry | | | | | |
| Leveraging UVM-based Low Power Package Library to SOC Designs | Shikhadevi Katheriya, Avnita Pal, Puranapanda Sastry | | | | | |
| Leveraging Virtual Platform ESL and TLM SystemVerification in RTL using UVM | Ashok Mehta, Albert Chiang, and Wei-Hua Han | | | | | |
| Leveraging virtual prototypes from concept to silicon | Rob Kaye | | | | | |
| Lies, Damned Lies, and Coverage | Mark Litterick | | | | | |
| Lies, Damned Lies, and Coverage | Mark Litterick | | | | | |
| Logic Equivalence Check without Low Power – you are at risk!! | Aishwarya Nair, Krishna Patel | | | | | |
| Low Power Apps (Shaping the Future of Low Power Verification) | Awashesh Kumar, Madhur Bhargava, Vinay Kumar Singh, and Pankaj Gairola | | | | | |
| Low Power Apps: Shaping the Future of Low Power Verification | Awashesh Kumar, Madhur Bhargava, Vinay Singh, and Pankaj Gairola | | | | | |
| Low Power Coverage: The Missing Piece in Dynamic Simulation | Progyna Khondkar, Gabriel Chidolue, and Ping Yeung | | | | | |
| Low Power Coverage: The Missing Piece in Dynamic Simulation | Progyna Khondkar | | | | | |
| Low Power Emulation for Power Intensive Designs | Harpreet Kaur, Mohit Jain, Piyush Kumar Gupta, Jitendra Aggarwal | | | | | |
| Low Power Extension In UVM Power Management | Priyanka Gharat, Shikhadevi Katheriya, Avnita Pal | | | | | |
| Low Power Extension in UVM Power Management | Priyanka Gharat, Avnita Pal, Shikhadevi Katheriya | | | | | |
| Low Power SoC Verification: IP Reuse and Hierarchical Composition using UPF | Amit Srivastava, Rudra Mukherjee, Erich Marschner, and Chuck Seeley | | | | | |
| Low Power SoC Verification: IP Reuse and Hierarchical Composition using UPF | Amit Srivastava, Rudra Mukherjee, Erich Marschner, and Chuck Seeley | | | | | |
| Low Power Static Verification- Beyond Linting and Corruption Semantics | Kaustav Guha , Ankush Bagotra, and Neha Bajaj | | | | | |
| Low Power Techniques in Emulation | Pragati Mishra & Jitendra Aggarwal | | | | | |
| Low Power Validation on Emulation Using Portable Stimulus Standard | Joydeep Maitra, Deepinder Singh Mohoora, Vikash Kumar Singh | | | | | |
| Low Power Verification Challenges and Coverage Recipe to Sign-Off PA Verification | Deepmala Sachan, Raghavendra Prakash, Venugopal Jennarapu, Syed S Thameem | | | | | |
| Low power Verification challenges and coverage recipe to sign-off Power aware Verification | Deepmala Sachan, Thameem Syed S, Raghavendra Prakash, Venugopal Jennarapu | | | | | |
| Low Power Verification With LDO | Shang-Wei Tu, Amol Herlekar, and Yu-Juei Chen | | | | | |
| Low Power Verification with LDO | Shang-Wei Tu and Amol Herlekar | | | | | |
| Low Power Verification with UPF: Principle and Practice | Jianfeng Liu, Mi-Sook Hong, Bong Hyun Lee JungYun Choi, HyoSig Won, Kyu-Myung Choi, Harsha Vardhan, and Aditya Kher | | | | | |
| Low-Power Verification at Gate Level for Zen Microprocessor Core | Baosheng Wang, Keerthi Mullangi, Raluca Stan, and Diana Irimia | | | | | |
| Low-Power Verification Automation – A Practical Approach | Shaji Kunjumohamed and Hendy Kosasih | | | | | |
| LOW-POWER VERIFICATION AUTOMATION: A PRACTICAL APPROACH | Shaji K. Kunjumohamed and Hendy Kosasih | | | | | |
| Low-Power Verification Methodology using UPF Query functions and Bind checkers | Madhur Bhargava and Durgesh Prasad | | | | | |
| Low-Power Verification Methodology using UPF Query functions and Bind checkers | Madhur Bhargava and Durgesh Prasad | | | | | |
| Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design Verification | Honghuang Lin, Zhipeng Ye, and Asad Khan | | | | | |
| Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design Verification | H. Lin, Z. Ye, and A. M. Khan | | | | | |
| Machine Learning based Structure Recognition in Analog Schematics for Constraints Generation | Rituj Patel, Husni Habal, Konda Reddy Venkata | | | | | |
| Machine Learning Based Verification Planning Methodology Using Design and Verification Data | Hanna Jang, Seonghee Yim, Sunchang Choi, and Seonil Brian Choi | | | | | |
| Machine Learning Based Verification Planning Methodology Using Design and Verification Data | Hanna Jang, Seonghee Yim | | | | | |
| Machine Learning Driven Verification A Step Function in Productivity and Throughput | Daniel Hansson, John Rose, and Matt Graham | | | | | |
| Machine Learning for Coverage Analysis in Design Verification | V Jayasree | | | | | |
| Machine Learning Introduction and Exemplary Application in Embedded Wireless Platforms | Jonathan Ah Sue | | | | | |
| Machine Learning-based Smart Assessment of User Floorplan Quality without running Place & Route | Harn Hua Ng, Kirvy Teo | | | | | |
| Machine Learning-Guided Stimulus Generation for Functional Verification | Saumil Gogri, Jiang Hu, Aakash Tyagi, Mike Quinn, Swati Ramachandran, Fazia Batool, and Amrutha Jagadeesh | | | | | |
| Machine Learning-Guided Stimulus Generation for Functional Verification | S. Gogri, J. Hu, A. Tyagi, M. Quinn S. Ramachandran, F. Batool, and A. Jagadeesh | 2020 | Presentation | | y2020 | presentation |
| Make your Testbenches Run Like Clockwork! | Markus Brosch, Salman Tanvir, and Martin Ruhwandl | | | | | |
| Make Your Testbenches Run Like Clockwork! | Markus Brosch, Salman Tanvir and Martin Ruhwandl | | | | | |
| Making Autonomous Cars Safe | Joern Stohmann and Frederico Ferlini | | | | | |
| Making Autonomous Cars Safer – One chip at a time | Apurva Kalia and Ann Keffer | 2018 | Presentation | | y2018 | presentation |
| Making Formal Property Verification Mainstream: An Intel Graphics Experience | M Achutha KiranKumar V, Erik Seligman, Aarti Gupta, Ss Bindumadhava, and Abhijith Bharadwaj | | | | | |
| Making Formal Property Verification Mainstream: An Intel® Graphics Experience | M Achutha Kiran, Kumar V., Erik Seligman, Aarti Gupta, Bindumadhava S. S., and Abhijith A. Bharadwaj | | | | | |
| Making Formal Property Verification Mainstream: An Intel® Graphics Experience | M Achutha KiranKumar V, Bindumadhava S S, Abhijith A Bharadwaj | | | | | |
| Making ISO26262 Functional Safety Verification a Natural Extension of Functional Verification | Andrew Betts and Ann Keffer | | | | | |
| Making Legacy Portable with the Portable Stimulus Specification | Matthew Ballance | | | | | |
| Making Legacy Portable with the Portable Stimulus Specification | Matthew Ballance | | | | | |
| Making RAL Jump, an Introspection | Jeremy Ridgeway, Karishma Dhruv, and Manmohan Singh | | | | | |
| Making RAL Jump, an Introspection | Jeremy Ridgeway, Karishma Dhruv, and Manmohan Singh | | | | | |
| Making Security Verification “SECURE” | Subin Thykkoottathil and Nagesh Ranganath | | | | | |
| Making Security Verification “SECURE” | NAGESH RANGANATH and SUBIN THYKKOOTTATHIL | | | | | |
| Making the Most of the UVM Register Layer and Sequences | David Long | | | | | |
| Making Virtual Prototypes Work | Kartik Jivani, Jigar Patel | | | | | |
| Making Your DPI-C Interface a Fast River of Data | Rich Edelman | | | | | |
| MANAGING AND AUTOMATING HW/SW TESTS FROM IP TO SOC | Matthew Ballance | | | | | |
| Managing and Automating Hw/Sw Tests from IP to SoC | Matthew Ballance | | | | | |
| Managing Highly Configurable Design and Verification | Jeremy Ridgeway | | | | | |
| Managing Highly Configurable Design and Verification | J. Ridgeway | | | | | |
| Marrying Simulation and Formal Made Easier! | Lun Li, Durga Rangarajan, Christopher Starr, and James Greene | | | | | |
| Mastering Unexpected Situations Safely | Sacha Loitz | | | | | |
| Matrix Math package for VHDL | David W. Bishop | | | | | |
| Matrix Math package for VHDL | David W. Bishop | | | | | |
| Maximize PSS Reuse with Unified Test Realization Layer Across Verification Environments | Simranjit Singh, Ashwani Aggarwal, Suman Kumar Reddy Mekala, Arun K.R., Woojoo Space Kim , Seonil Brian Choi, Gnaneshwara Tatuskar | | | | | |
| Maximize Vertical Reuse, Building Module to System Verification Environments with UVM e | Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss | | | | | |
| Maximize Vertical Reuse, Building Module to System Verification Environments with UVMe | Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss | | | | | |
| Maximizing Formal ROI through Accelerated IP Verification Sign-off | Hao Chen, Kamakshi Sarat Vallabhapurapu, Scott Peverelle, Rosanna Yee, Hee Chul Kim, Johann Te, and Jacob Hotz | | | | | |
| Maximizing Formal ROI through Accelerated IP Verification Sign-off | Scott Peverelle, Hao Chen, Kamakshi Sarat Vallabhapurapu, Rosanna Yee, Hee Chul Kim, Johann Te, and Jacob Hotz | | | | | |
| May the powers be with you! – Unleashing powerful new features in UPF IEEE 1801 | Srinivasan Venkataramanan and Ajeetha Kumari | | | | | |
| MDLL & Slave Delay Line Performance Analysis Using Novel Delay Modeling | Abhijith Kashyap, Avinash S and Kalpesh Shah | | | | | |
| MDLL & Slave Delay Line Performance Analysis Using Novel Delay Modeling | Abhijith Kashyap, Avinash Shambu, Kalpesh Shah | | | | | |
| Mechanical mounting variation effects on magnetic speed sensor applications | Simone Fontanesi, Se Hwan Kim, Gernot Binder and Andrea Monterastelli | | | | | |
| Mechanical mounting variation effects on magnetic speed sensor applications Combining finite element methods and SystemC simulations to study the effects of mechanical tilts and offset on magnetic speed sensor applications | Simone Fontanesi, Se Hwan Kim, Gernot Binder and Andrea Monterastelli | | | | | |
| Mechanism to Generate FIFO VC Dependency Graph and Its Application to System Level Deadlock Verification | Debarshi Chatterjee, Chad Parsons, Siddhanth Dhodhi | | | | | |
| Media Performance Validation in Emulation and Post Silicon Using Portable Stimulus Standard | Suresh Vasu, Nithin Venkatesh, Joydeep Maitra | | | | | |
| Melioration of Enhanced Low Power Memory Retention and Low Power Feature Validation Using API’s | Nithin Venkatesh, Akula Hareesh | | | | | |
| Melting Verification Pot: Integrating RVM/VMM and UVM, a Practical Guide and Lessons Learned. | Mark A. Azadpour | | | | | |
| Melting Verification Pot: Integrating RVM/VMM and UVM, a Practical Guide and Lessons Learned. | Mark Azadpour | | | | | |
| Memory Debugging of Virtual Platforms | George F. Frazier, Neeti Bhatnagar, Qizhang Chao, and Kathy Lang | | | | | |
| Memory Debugging of Virtual Prototypes with TLM 2.0 | George F. Frazier, Qizhang Chao, Neeti Bhatnagar, and Kathy Lang | | | | | |
| Memory Subsystem Verification – Can it be taken for granted? | Shivani Upasani | | | | | |
| Memory Subsystem Verification: Can it be taken for granted? | Shivani Upasani and Prashanth Srinivasa | | | | | |
| MeSSMArch – A Memory System Simulator for Hardware Multithreading Architectures | Sushil Menon | | | | | |
| MeSSMArch – A Memory System Simulator for Hardware Multithreading Architectures | Sushil Menon | | | | | |
| Meta Design Framework | Sanjeev Singh and Jonathan Sadowsky | | | | | |
| Meta Design Framework: Building Designs Programmatically | Sanjeev Singh and Jonathan Sadowsky | | | | | |
| Metadata Based Testbench Generation | Daeseo Cha, Soonoh Kwon, and Ahhyung Shin | | | | | |
| Metadata Based Testbench Generation Automation | Daeseo Cha, Soonoh Kwon, Ahhyung Shin, Youngnam Youn, Youngsik Kim, and Seonil Brian Choi | | | | | |
| Method for early performance verification of hardware-accelerated embedded processor systems in RTL simulation | Luca Sasselli, Mehmet Tukel, David Guthrie | | | | | |
| Method for Generating Unique Coverage Classes to Enable Meaningful Covergroup Merges Across Testbenches | Eldon Nelson, MS, PE | | | | | |
| Method for Generating Unique Coverage Classes to Enable Meaningful Covergroup Merges Across Testbenches | Eldon Nelson, M.S., P.E. | | | | | |
| Methodology for Abstract Power Intent Specification and Generation | Pramod Warrier, Bhavesh Jeewani, Juergen Karmann, Michael Velten | | | | | |
| Methodology for Automated Generation and Validation of Analog Behavioral Models for Mixed-Signal Verification | Nan Ni, Chunya Xu, and Sebastian Simon | | | | | |
| Methodology for automating coverage-driven interrupt testing of instruction sets | David McConnell, Greg Tumbush | | | | | |
| Methodology for checking UVM VIPs | Milan Vlahovic and Ilija Dimitrijevic | | | | | |
| Methodology for checking UVM VIPs | Milan Vlahovic and Ilija Dimitrijevic | | | | | |
| Methodology for Hardware Software Co-verification of Video Systems on Pre and Post Silicon | Vinesh Peringat | | | | | |
| Methodology for Hardware Software Co-verification of Video Systems on Pre and Post Silicon | Vinesh Peringat, Balajee Premraj, Venkatesh Merugu | | | | | |
| Methodology for Separation of Design Concerns Using Conservative RTL Flipflop Inference | Maya H. Safieddine, Fadi A. Zaraket, and Rouwaida Kanj | | | | | |
| Methodology for Separation of Design Concerns Using Conservative RTL Flipflop Inference | Maya H. Safieddine, Fadi A. Zaraket, and Rouwaida Kanj | | | | | |
| Methodology for system-level comparison of ARM vs RISC-V cores for latency and power consumption | Tom Jose, Deepak Shankar | | | | | |
| Methodology for Verification Regression Throughput Optimization using Machine Learning | Arun.K.R, Preetham Lakshmikanthan, and Ashwani Aggarwal | | | | | |
| Methodology for Verification Regression Throughput Optimization using Machine Learning | Arun K.R. Preetham Lakshmikanthan, Ashwani Aggarwal, and Sundararajan Ananthakrishnan | | | | | |
| Methodology of Communication Protocols Development: from Requirements to Implementation | Irina Lavrovskaya and Valentin Olenev | | | | | |
| Metric Driven Mixed-Signal Verification Methodology and Practices for Complex Mixed-signal ASSPs | Frank Yang, Andy Sha, Morton Zhao, and Yanping Sha | | | | | |
| Metric Driven Mixed-Signal Verification Methodology and Practices for Complex Mixed-signal ASSPs | Frank Yang, Andy Sha, Morton Zhao, and Yanping Sha | | | | | |
| Metric Driven Verification of Mixed-Signal Designs | Neyaz Khan, Yaron Kashai, and Hao Fang | | | | | |
| Metrics Driven Sign-off for SoC Specific Logic (SSL) Using Formal Techniques | Abhinav Gaur, Gaurav Jain, Ruchi Singh | | | | | |
| Metrics in SoC Verification | Andreas Meyer and Harry Foster | | | | | |
| Micro-processor verification using a C++11 sequence-based stimulus engine. | Stephan Bourduas and Chris Mikulis | | | | | |
| Micro-processor verification using a C++11 sequence-based stimulus engine. | Stephan Bourduas and Chris Mikulis | | | | | |
| MicroTESK: Automated Architecture Validation Suite Generator for Microprocessors | Mikhail Chupilko, Alexander Kamkin, Alexander Protsenko, Sergey Smolov, and Andrei Tatarnikov | | | | | |
| Migrating from OVM to UVM The Definitive Guide | Adiel Khan | | | | | |
| Migrating from UVM to UVM-AMS | Tom Fitzpatrick, Abhijit Madhu Kumar | | | | | |
| Migrating to UVM : Conquering Legacy | Santosh Sarma, Amit Sharma, and Adiel Khan | | | | | |
| Mind the Gap(s): Creating & Closing Gaps Between Design and Verification | Chris Giles and Kurt Takara | | | | | |
| Mining Coverage Data for Test Set Coverage Efficiency | Monica Farkash, Bryan Hickerson, Mike Behm, and Balavinayagam Samynathan | | | | | |
| Mining Coverage Data for Test Set Coverage Efficiency | Bryan Hickerson, Mike Behm, Balavinayagam Samynathan, and Monica Farkash | | | | | |
| MIPI M-PHY Analog Modeling in Verilog-AMS (Wreal) and Verification Using SV/UVM-MS Methodology | Mallikarjuna Reddy Y, Venkatramana Rao K, Somanatha Shetty A | | | | | |
| Mixed Electronic System Level Power/Performance Estimation | Antonio Genov, Loic Leconte and François Verdier | | | | | |
| Mixed ESL Power/Performance Estimation using SystemC/TLM2.0 Modeling and PwClkARCHLibrary | Antonio Genov, Loic Leconte, and François Verdier | | | | | |
| Mixed Signal Assertion-Based Verification | Prabal Bhattacharya, Don O’Riordan, and Walter Hartong | | | | | |
| Mixed Signal Design Verification: Leveraging the Best of AMS and DMS | Rock Z. Shi, Padmashree Bhinge, Preston Birdsong, Geeta Chaitanya, and Kunal Jani | | | | | |
| Mixed Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP Simulation | S. Do, J. Park, D. Kim, and J. Jang | | | | | |
| Mixed Signal Verification of a Voltage Regulator using a State Space Approach and the SV-DC extensions | Rajat Mitra | | | | | |
| Mixed Signal Verification of Dynamic Adaptive Power Management in Low Power SoC | Neyaz Khan | | | | | |
| Mixed Signal Verification of UPF based designs A Practical Example | Andrew Milne and Damian Roberts | | | | | |
| Mixed Signal Verification of UPF based designs A Practical Example | Andrew Milne and Damian Roberts | | | | | |
| Mixed-abstraction Modeling Approach with Fault Injection for Hardware-Firmware Co-design and Functional Co-verification of an Automotive Airbag System on Chip Product | Dipl.-Ing. Dr.-techn. Thang Nguyen, Dipl.-Ing. and Dieter Haerle | | | | | |
| Mixed-abstraction Modeling Approach with Fault Injection for Hardware-Firmware Co-design and Functional Co-verification of an Automotive Airbag System on Chip Product | Thang Nguyen, Dipl.-Ing.-Dr. and Dieter Haerle, Dipl.-Ing. | | | | | |
| Mixed-Signal Design Verification: Leveraging the Best of AMS and DMS | Rock Z. Shi, Padmashree Bhinge, Preston Birdsong, Geeta Chaitanya, and Kunal Jani | | | | | |
| Mixed-Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP Simulation | S. Do, J. Park, D. Kim, and J. Jang | | | | | |
| Mixed-Signal Systems-on-Chip Design Verification With Automatic Real-Number Abstraction | Nancy Qiu, Frank Yang, and Himadri De | | | | | |
| Mixed-Signal Verification Methodology to Verify Type-C USB | Varun R, Vinayak Hegde, and Somasunder Kattepura Sreenath | | | | | |
| Mixed-Signal Verification Methodology to Verify USB Type-C | Varun R, Vinayak Hegde ans Somasunder Kattepura Sreenath | | | | | |
| ML-Based Verification and Regression Automation | Abhishek Chauhan, Asif Ahmad | | | | | |
| Model based Automation of Verification Development for automotive SOCs | Aljoscha Kirchner, Jan Hendrik Oetjens, and Oliver Bringmann, | | | | | |
| Model Extraction for Designs Based on Switches for Formal Verification | Amar Patel, Naman Jain | | | | | |
| Model Extraction for Designs Based on Switches for Formal Verification | Amar Patel, Naman Jain | | | | | |
| Model Validation for Mixed-Signal Verification | Carsten Wegener | | | | | |
| Model Validation for Mixed-Signal Verification The Importance of Being Earnest about Modeling | Carsten Wegener | | | | | |
| Model-Based Automation of Verification Development for Automotive SOCs | Aljoscha Kirchner, Jan-Hendrik Oetjens and Oliver Bringmann | | | | | |
| Model-Based Design The Top-Level System Design Method | Alan P. Su | | | | | |
| Modeling a Hierarchical Register Scheme with UVM | Joshua Hardy | | | | | |
| Modeling a Hierarchical Register Scheme with UVM | Joshua Hardy | | | | | |
| Modeling Analog Devices Using SV-RNM | Mariam Maurice | | | | | |
| Modeling Analog Devices using SV-RNM | Mariam Maurice | | | | | |
| Modeling Analog Systems Using Full Digital Simulations (A State Space Approach) | Rajat K Mitra | | | | | |
| Modeling Memory Coherency During Concurrent/Simultaneous Accesses | Subramoni Parameswaran | | | | | |
| Modeling Memory Coherency for Concurrent/Parallel Accesses | Subramoni Parameswaran | | | | | |
| Modeling Memory Coherency for concurrent/parallel accesses | Subramoni Parameswaran | | | | | |
| Modeling of Generic Transfer Functions in SystemVerilog | Elvis Shera | | | | | |
| Modeling of Generic Transfer Functions in SystemVerilog. Demystifying the Analytic Model | Elvis Shera | | | | | |
| Modelling Finite-State Machines in the Verification Environment using Software Design Patterns | Darko M. Tomušilović | | | | | |
| Modelling Finite-State Machines in the Verification Environment using Software Design Patterns | Darko M. Tomušilović and Mihajlo Z. Minović | | | | | |
| Modelling of UVC Monitor Class as a Finite State Machine for a Packet-Based Interface | Djordje Velickovic, Milos Mitic | | | | | |
| Modelling of UVC Monitor Class as a Finite State Machine for a Packet-Based Interface | Djordje Velickovic, Milos Mitic | | | | | |
| Modern methodologies in a TCL test environment | Matteo De Luigi and Alessandro Ogheri | | | | | |
| Molding Functional Coverage for Highly Configurable IP | J. Ridgeway, K. Chaturvedula, and K. Dhruv | | | | | |
| Molding Functional Coverage for Highly Configurable IP | Jeremy Ridgeway, Kavitha Chaturvedula, and Karishma Dhruv | | | | | |
| Monitors, Monitors Everywhere – Who Is Monitoring the Monitors | Rich Edelman and Raghu Ardeishar | | | | | |
| Monitors, Monitors Everywhere … | Rich Edelman and Raghu Ardeishar | | | | | |
| Moving beyond Assertions: An Innovative approach to Low-Power Checking using UPF Tcl Apps | Madhur Bhargava | | | | | |
| Moving SystemC to a New C++ Standard | Ralph Görgen and Philipp A. Hartmann | | | | | |
| MS-SoC Best Practices – Advanced Modeling & Verification Techniques for first-pass success | Neyaz Khan, Greg Glennon, and Dan Romaine | | | | | |
| Multi-Domain Verification: When Clock, Power and Reset Domains Collide | Ping Yeung, Erich Marschner, and Kaowen Liu | | | | | |
| Multi-Domain Verification: When Clock, Power and Reset Domains Collide | Ping Yeung, Erich Marschner, and Kaowen Liu | | | | | |
| Multi-Language Verification: Solutions for Real World Problems | Bryan Sniderman and Vitaly Yankelevich | | | | | |
| Multi-Language Verification: Solutions for Real World Problems | Bryan Sniderman and Vitaly Yankelevich | | | | | |
| Multi-Variant Coverage: Effective Planning and Modelling | Vikas Sharma and Manoj Manu | | | | | |
| Multi-Variant Coverage: Effective Planning and Modelling | Vikas Sharma and Manoj Manu | | | | | |
| Multimedia IP DMA verification platform | Suhyung Kim, Sangkyu Park, Myungwoo Seo, Sangjin Lee, and Jiyeon Park | | | | | |
| Multimedia IP DMA verification platform | Suhyung Kim, Sangkyu Park, Myungwoo Seo, Sangjin Lee, and Jiyeon Park | | | | | |
| Multiplier-Adder-Converter Linear Piecewise Approximation for Low Power Graphics Applications | Dina M. Ellaithy, Magdy A. El-Moursy, Amal Zaki, and Abdelhalim Zekry | | | | | |
| Multithreading a UVM Testbench for Faster Simulation | Benjamin Applequist, Vijayakrishnan Rousseau, Andrew Tan, and Jayasrinivas Sesham | | | | | |
| Mutable Verification Environments Through Visitor and Dynamic Register Map Configuration | Matteo Barbati, Alberto Allara | | | | | |
| Mutable Verification Environments through Visitor and Dynamic Register Map Configuration | Matteo Barbati and Alberto Allara | | | | | |
| My Testbench Used to Break! Now it Bends (Adapting to Changing Design Configurations) | Jeff Vance, Jeff Montesano, Kevin Vasconcellos, and Kevin Johnston | | | | | |
| My Testbench Used to Break! Now it Bends: Adapting to Changing Design Configurations | Jeff Vance, Jeff Montesano, Kevin Vasconcellos, and Kevin Johnston | | | | | |
| Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage Modeling | Jason Sprott, Paul Marriott, and Matt Graham | | | | | |
| Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage Modeling | Jason Sprott, Paul Marriott, and Matt Graham | | | | | |
| Netlist Enabled Emulation Platform for Accelerated Gate Level Verification | Samhith Pottem, Vasudeva Reddy, Rahul S S, Sarang Kalbande, Garima Srivastava, Hyundon Kim | | | | | |
| Netlist Enabled Emulation Platform for Accelerated Gate Level Verification | Samhith Pottem, Vasudeva Reddy, Rahul S S, Sarang Kalbande, Garima Srivastava, Hyundon Kim | | | | | |
| Netlist Paths | Jamie Hanlon, Samuel Kong | | | | | |
| Network Packet Header Generation Using Graph Based Techniques Combined with Software Testing Strategies | Sridevi Navulur, Satheesh Parasumanna, Rama Chaganti | | | | | |
| Never Too Late With Formal: Stepwise Guide for Applying Formal Verification in Post-Silicon Phase to Avoid Re-Spins | Anshul Jain, Aarti Gupta, Achutha KiranKumar V M, Bindumadhava Ss, Shivakumar S Kolar, and Siva Gadey NV | | | | | |
| Never Too Late with Formal: Stepwise Guide for Applying FV in Post Si Phase to Avoid Re-Spins | Anshul Jain, Aarti Gupta, Achutha KiranKumar V M, Bindumadhava Ss, Shivakumar S Kolar, Siva Gadey NV | | | | | |
| New and active ways to bind to your design | Kaiming Ho | | | | | |
| New and Active Ways to Bind to Your Designs | Kaiming Ho | | | | | |
| New Challenges in Verification of Mixed-Signal IP and SoC Design | Luke Lang and Christina Chu | | | | | |
| New Constrained Random and Metric-Driven Verification Methodology using Python | Marek Cieplucha and Witold A. Pleskacz | | | | | |
| New Constrained Random and Metric-Driven Verification Methodology using Python | Marek Ciepłucha and Witold Pleskacz | | | | | |
| New Trends in RTL Verification: Bug Localization, Scan- Chain-Based Methodology, GA-Based Test Generation | Khaled Salah | | | | | |
| New Trends in RTL Verification: Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation | Khaled Salah | | | | | |
| Next Frontier in Formal Verification | Ping Yeung, Rajesh Rathi, Vaibhav Kumar, Puneet Anand, Ravindra Aneja | | | | | |
| Next Gen System Design and Verification for Transportation | Bryan Ramirez, Petri Solanti and Richard Pugh | | | | | |
| Next Gen System Design and Verification for Transportation | David Aerne, Jacob Wiltgen, and Richard Pugh | | | | | |
| Next Generation ISO 26262-basedDesign Reliability Flows | Jörg Große and Sanjay Pillay | | | | | |
| Next Generation Verification for the Era of AI/ML and 5G | Frank Schirrmeister, Pete Hardee, Larry Melling, Amit Dua, and Moshik Rubin | | | | | |
| Next-generation Power Aware CDC Verification – What have we learned? | Kurt Takara, Chris Kwok, Naman Jain, and Ashish Hari | | | | | |
| Next-generation Power Aware CDC Verification What have we learned? | Kurt Takara, Chris Kwok, Naman Jain, and Ashish Hari | | | | | |
| No Country For Old Men – A Modern Take on Metrics Driven Verification | Svetlomir Hristozkov, James Pallister, Richard Porter | | | | | |
| No gain without RISC- A novel approach for accelerating and streamlining RISC-V Processor functional verification with register change dump methodology | Damandeep Saini, Chethan AS, Anil Deshpande, Raviteja Gopagiri, Somasundar, Niharika Sachdeva | | | | | |
| No gain without RISC- A novel approach for accelerating and streamlining RISC-V Processor functional verification with register change dump methodology | Damandeep Saini, Chethan AS, Anil Deshpande, Raviteja Gopagiri, Somasundar, Niharika Sachdeva | | | | | |
| No RTL Yet? No Problem UVM Testing a SystemVerilog Fabric Model | Rich Edelman | | | | | |
| No RTL Yet? No Problem UVM Testing a SystemVerilog Fabric Model | Rich Edelman | | | | | |
| NO.001: Applicable to eSim Development for Automatic Construction of UVM Verification Platform For Large-Scale Data Communication Chips | Ankui Ge, Lei Wang, and Feng Wang | | | | | |
| NO.002: Accurate Charge-pump Regulator Modeling using SV EEnet | Sherry Li, Tulong Yang, and Ayesha Huq | | | | | |
| NO.003: RISC-V Processor Core Verification Based on Open Source Tools | Yanbing Xu | | | | | |
| NO.005: Improvement of chip verification automation technology | Ma Yao, Shao Haibo, Yue Yaping, and Cao Zhu | | | | | |
| NO.006: A Systematic IP Verification Solution of Complex Memory Management for Storage SOC | Jinsong Liu and Shuhui Wang | | | | | |
| NO.008: LiteX: a novel open source framework for SoC | Feng Li | | | | | |
| NO.009: Transaction Equivalence Formal Check (DPV) in Video Algorithm/FPU/AI Area | Minqi Bao | | | | | |
| NO.010: Silicon Bug Hunt with“Deep Sea Fishing”Formal Verification | Ping Yeung and Jin Hou | | | | | |
| NO.011: Completely Release the Power of VerificationIP–A Step-by-Step Guidance for In-HouseIPDevelopment | Bin Liu, Xiaoming Ma, Kailong Wang, and Qiaochu Zhu | | | | | |
| NO.012: How Fast Can You Run SLEC For Verifying Design Optimizations and Bug Fixes | Jin Hou Wenli Liang, and Lina Guo | | | | | |
| NO.013: Sequential Equivalence Checking Beyond Clock Gating Verification | Xiushan Feng, Xiaolin Chen, and Sarah Li | | | | | |
| NO.014: An Intelligent SOC Verification Platform | Deyong Yang and Fabo Deng | | | | | |
| NO.015: A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores | Nicolae Tusinschi, Wei Wei Chen, and Tom Anderson | | | | | |
| NO.015: A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores | Nicolae Tusinschi, Wei Wei Chen, and Tom Anderson | | | | | |
| NOT JUST FOR HARDWARE DEBUG: PROTOTYPE DEBUGGERS FOR SYSTEM VALIDATION AND OPTIMIZATION | Michael Sachtjen and Joe Gaubatz | | | | | |
| Not Just for Hardware Debug: Prototype Debuggers for System Validation and Optimization | Michael Sachtjen and Joe Gaubatz | | | | | |
| Novel Adaptive CPU Scoreboard Methodology for a Multi-language environment | Pooja Madhusoodhanan, Saya Goud Langadi, Labeeb K | | | | | |
| Novel Adaptive CPU Scoreboard Methodology for a Multi-language environment | Pooja Madhusoodhanan, Saya Goud Langadi, Labeeb K | | | | | |
| Novel approach for SoC pipeline latency and connectivity verification using Formal | Deepak Mohan, Senthilnath Subbarayan, Sandeep Kumar | | | | | |
| Novel approach for SoC pipeline latency and connectivity verification using Formal | Deepak Mohan, Senthilnath Subbarayan, Sandeep Kumar | | | | | |
| Novel Approach to ASIC Prototyping | Mohamed Saheel, Suresh Balasubramanian, and Vijayakrishnan Rousseau | | | | | |
| Novel Approaches for C vs. RTL Formal Verification of Vertex Attribute Address Generator Unit | Nianchen Wu, Christopher Starr, and Xiushan Feng | | | | | |
| Novel GUI Based UVM Test Bench Template Builder | Vignesh Manoharan | 2022 | Poster | | y2022 | poster |
| Novel GUI Based UVM Test Bench Template Builder | Vignesh Manoharan | | | | | |
| Novel Methodology for TLM Model Unit Verification | Navaneet Kumar, Archna Verma, Ashish Mathur | | | | | |
| Novel Mixed Signal Verification Methodology using complex UDNs | Rakesh Dama, Ravi Reddy, and Andy Vitek | | | | | |
| Novel Mixed Signal Verification Methodology Using Complex UDNs | Rakesh Dama, Ravi Reddy, and Andy Vitek | | | | | |
| Novel Model First Approach to Shift-Left Soft-Logic RTL Development on Intel Agilex FPGA for Data Centre IPU Design | Pravat K Nayak, Vikrant Kapila, Pushpa Naik, Niketkumar Sharma | | | | | |
| Novel Paradigm in Formally Verifying Complex Algorithms | M Achutha KiranKumar V, Disha Puri, Mohit Choradia, Paras Gupta | | | | | |
| Novel Test Case Design Techniques for Logical Specifications of Safety Critical Systems Software in Aerial Vehicle | Lakshmi KVNS and Sanjeev Kumar | | | | | |
| Novel Verification Techniques for ARM A15 Multi-core Subsystem Using IEEE 1647 | Vaibhav Mahimkar, Akshit Dayal, Tomas Huynh, Van Huynh, and Erwin Hermanto | | | | | |
| Novel Verification Techniques for ARM A15 Multi-core Subsystem Using IEEE 1647 | Vaibhav Mahimkar, Akshit Dayal, Tomas Huynh, Van Huynh, and Erwin Hermanto. | | | | | |
| Novelty-Driven Verification: Using Machine Learning to Identify Novel Stimuli and Close Coverage | Tim Blackmore, Rhys Hodson, Sebastian Schaal | | | | | |
| NRFs Indentification & Signoff with GLS Validation | Rohit Kumar Sinha, Rakesh Misra, Nagesh Kulkarni | | | | | |
| NVMe Development and Debug for a 16 x Multicore System | Soummya Mallick, Raj Mathur, Arindam Guha, and Frank Schirrmeister | | | | | |
| NVVM: A Netlist-based Verilog Verification Methodology for Mixed-Signal Design | Jiping Qiu, Kurt Schwartz | | | | | |
| NVVM: A Netlist-based Verilog Verification Methodology for Mixed-Signal Design | Jiping Qiu, Kurt Schwartz | | | | | |
| Obscure Face of UVM RAL: To Tackle Verification of Error Scenarios | Subhash Pai, Lavanya Polineni | | | | | |
| Obscure face of UVM RAL: To Tackle Verification of Error Scenarios | Subhash Pai, Lavanya Polineni | | | | | |
| Of Camels and Committees | Tom Fitzpatrick and Dave Rich | | | | | |
| Of Camels and Committees: Standardization Should Enable Innovation, Not Strangle It | Tom Fitzpatrick and Dave Rich | | | | | |
| Off To The Races With Your Accelerated SystemVerilog Testbench (A Methodology for Hardware-Assisted Acceleration of SystemVerilog Testbenches) | Hans van der Schoot, Anoop Saha, Ankit Garg, and Krishnamurthy Suresh | | | | | |
| OIL check of PCIe with Formal Verification | Vedprakash Mishra, Carlston Lim, Zhi Feng Lee, Jian Zhong Wang, Anshul Jain and Achutha KiranKumar V M | | | | | |
| On Verification Coverage Metrics in Formal Verification and Speeding Verification Closure with UCIS Coverage Interoperability Standard | Rajeev Ranjan, PhD, Ross Weber, and Ziyad Hanna, PhD | | | | | |
| One Compile to Rule Them All: An Elegant Solution for OVM/UVM Testbench Topologies | Galen Blake and Steve Chappell | | | | | |
| One Compile to Rule them All: An elegant solution for OVM/UVM Testbench Topologies | Galen Blake and Steve Chappell | | | | | |
| One Stop Solution for DFT Register Modelling in UVM | Rui Huang | | | | | |
| One Stop Solution of DFT Register Modelling in UVM | Rui Huang | | | | | |
| One Testbench to Rule them all! | Salman Tanvir, Markus Brosch, Amer Siddiqi | | | | | |
| Open Source Solution for RISC-V Verification | Mikhail Chupilko, Alexander Kamkin and Alexander Protsenko | | | | | |
| Open Source Solution for RISC-V Verification | Mikhail Chupilko, Alexander Kamkin, and Alexander Protsenko | | | | | |
| Open Source Virtual Platforms for SW Prototyping on FPGA Based HW | Chen Qian, Praveen Wadikar, Mark Burton | | | | | |
| Open-source Framework for Co-emulation using PYNQ | Ioana-Cătălina Cristea, Dragoș Dospinescu | | | | | |
| Optimal Usage of the Computer Farm for Regression Testing | Daniel Hansson and Patrik Granath | | | | | |
| Optimal Usage of the Computer Farm for Regression Testing | Daniel Hansson and Patrik Granath | | | | | |
| Optimizing Area and Power Using Formal Method | Alan Carlin, Chris Komar Cadence, and Anuj Singhania | | | | | |
| Optimizing Design Verification using Machine Learning | William Hughes, Sandeep Srinivasan, Rohit Suvarna, Maithilee Kulkarni | | | | | |
| Optimizing Random Test Constraints Using Machine Learning Algorithms | Stan Sokorac | | | | | |
| Optimizing Random Test Constraints Using Machine Learning Algorithms | Stan Sokorac | | | | | |
| Optimizing Turnaround Times In A CI Flow Using a Scheduler Implementation | Robert Strong | | | | | |
| Optimizing Turnaround Times in a Continuous Integration Flow Using a Scheduler Based Implementation | Robert Strong | | | | | |
| OS aware IP Development Methodology | Hyunjae Woo, Woojoo Kim, Youngsik Kim, and Seonil Brian Choi | | | | | |
| OS-aware IP Development Methodology | Hyunjae Woo, Woojoo Kim, Youngsik Kim, and Seonil Brian Choi | | | | | |
| OS-aware Performance and Power Analysis Methodology | Hyunjae Woo, HojinJo, Woojoo Kim, and Seonil Brian Choi | | | | | |
| OSVVM and Error Reporting | Jim Lewis | 2015 | Paper | | y2015 | paper |
| OSVVM and Error Reporting | Jim Lewis | | | | | |
| OSVVM: Advanced Verification for VHDL | Jim Lewis | | | | | |
| OSVVM: Advanced Verification for VHDL | Jim Lewis | | | | | |
| Our Experience of Glitches at Clock Trees, CDC Paths and Reset Trees | Jebin Mohandas | | | | | |
| Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath Scoreboards | Bochra Elmaray and Joerg Mueller | | | | | |
| Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath Scoreboards | Bochra El-Meray and Jörg Müller | | | | | |
| Overcoming Challenges in Functional Verification of Automotive Traffic Schedulers | Harshit Jaiswal, Hemlata Bist, Rohit Mishra, Ori Tal | | | | | |
| Overcoming Challenges in SoC RTL Verification of USB Subsystem | Tijana Mišić and Marko Mišić, | | | | | |
| Overcoming System Verilog Assertions limitations through temporal decoupling and automation | Mattia De Pascalis, Xia Wu, Matteo Vottero, Jacob Sander Andersen | | | | | |
| Overcoming SystemVerilog Assertions limitations through temporal decoupling and automation | Mattia De Pascalis, Xia Wu, Matteo Vottero, Jacob Sander Andersen | | | | | |
| OVM & UVM Techniques for On-the-fly Reset | Muralidhara Ramalingaiah and Boobalan Anantharaman | | | | | |
| OVM & UVM Techniques for On-the-fly Reset | Muralidhara Ramalingaiah and Boobalan Anantharaman | | | | | |
| OVM & UVM Techniques for Terminating Tests | Clifford E. Cummings and Tom Fitzpatrick | | | | | |
| OVM TO UVM DEFINITIVE GUIDE PART 1 | Adiel Khan, Justin Refice, and Warren Stapleton | | | | | |
| PA-APIs: Looking beyond power intent specification formats | Amit Srivastava and Awashesh Kumar | | | | | |
| PA-APIs: Looking beyond power intent specification formats | Amit Srivastava and Awashesh Kumar | | | | | |
| Paged and Alternate View Registers in UVM | Kirti Srivastava, Harshit Kumar Baghel | | | | | |
| Panel: 5G Chip Design Challenges and their Impact on Verification | Accellera Systems Initiative | | | | | |
| Panel: Are Processor/SoC Discontinuities Turning Verification on its Head? | Accellera Systems Initiative | | | | | |
| Panning for Gold in RTL Using Transactions | Rich Edelman, Raghu Ardeishar, Akshay Sarup, and Suman Kasam | | | | | |
| Paper Session 1: Applicable to the Development Of Large-Scale Data Communication Chip Performance Analysis Tools | Dinglai He, Guanfeng Wang, Feng Wang, and Lirong Zhang | | | | | |
| Paper Session 2: UVM is Now IEEE1800.2-2020 Standard: A 2020 Adoption Primer | Roman Wang | 2021 | Paper | | y2021 | paper |
| Paper Session 3: Co-simulation platform of SystemC and System-Verilog for algorithm verification | Li Jinghui, Shao Haibo and Gou Jiazhen | | | | | |
| Paper Session 4: Unified Automation Verification Management Approach | Liu Wenbo, Tian Libo, and Shao Haibo | | | | | |
| Paper Session 5: Cache Coherency Verification for Multi-Core Processors Based on the PSS | Yang Yang | | | | | |
| Paper Session 6: High Reliability Reset Domain Checking Solution for the Modern Soc Design | Wanggen Shi, Yuxin You and Kurt Takara | | | | | |
| Paper Session 7: Best Practice Coding Assertion IP (AIP) to Get More Predictable Results | SJ Wu and Leon Yin | | | | | |
| Paper Session 8: Advanced Techniques for Enabling Gate-level CDC Verification Closure | Gunjan Jain, Kurt Takara, and Yuxin You | | | | | |
| Paradigm Shift in Power Aware Simulation Using Formal Techniques | Sachin Bansal, Girish Marudwar, Sandeep Jana, Kamalesh Ghosh, Yogananda Mesa | | | | | |
| Paradigm Shift in Power Aware Simulation Using Formal Techniques | Sachin Bansal, Girish Marudwar, Sandeep Jana, Kamalesh Ghosh, Yogananda Mesa | | | | | |
| Parallel Computing for Functional Verification and Compute Farms: The Holy Matrimony | Amit Sharma, Shekhar Basavanna, and Srinivasan Venkataramanan | | | | | |
| Parameter Passing From SystemVerilog to SystemC | Bishnupriya Bhattacharya, Samik Das, Zhiting Duan, Chandra Sekhar Katuri, and Pradipta Laha | | | | | |
| Parameter Passing from SystemVerilog to SystemC for Highly Configurable Mixed-Language Designs | Bishnupriya Bhattacharya, Samik Das, Zhiting Duan, Chandra Sekhar Katuri, and Pradipta Laha | | | | | |
| Parameterize Like a Pro: Handling Parameterized RTL in your UVM Testbench | Jeff Montesano | | | | | |
| Parameterized and Re-usable Jitter Model for Serial and Parallel Interfaces | Malathi Chikkanna and Amlan Chakrabarti | | | | | |
| Parameterized and Re-usable Jitter Model for Serial and Parallel Interfaces | Amlan Chakrabarti and Malathi Chikkanna | | | | | |
| Parameterized and Re-usable Jitter Model for Serial and Parallel Interfaces | Amlan Chakrabarti, Malathi Chikkanna | | | | | |
| Parameters and OVM — Can’t They Just Get Along? | Bryan Ramirez and Michael Horn | | | | | |
| Parameters, UVM, Coverage & Emulation – Take Two and Call Me in the Morning | Michael Horn, Bryan Ramirez, and Hans van der Schoot | | | | | |
| Part 9 An Efficient Methodology for Development of Cryptographic Engines | Sandesh Kanchodu, Tarun Rajendra Mittal, Sachin Kashyap, Subramanian Parameswaran | | | | | |
| Path-based UPF Strategies: Optimally Manage Power on your Designs | Progyna Khondkar | | | | | |
| Path-Based UPF Strategies: Optimally Manage Power on Your Designs | Progyna Khondkar | | | | | |
| Paving a Path to Hardware-Based Acceleration in a Single UVM Environment (Because there can be only one UVM environment!) | Axel Scherer and Mark Azadpour | | | | | |
| Pay Me Now or Pay Me Later Exploring the Implementation and Analysis Cost Trade-Offs of Coverage Model Design | Paul Graykowski and Andrew Piziali | | | | | |
| PCIe Gen5 Validation – The Real World | Yuan Chen | | | | | |
| Pedal Faster! Or Make Your Verification Environment More Efficient. You Choose. | Rich Edelman, Raghu Ardeishar, and Rohit Jain | | | | | |
| Pedal Faster! Or Make Your Verification Environment More Efficient. You Choose. | Rich Edelman, Raghu Ardeishar, and Rohit Jain | | | | | |
| Performance Analysis and Acceleration of High Bandwidth Memory System | Rohit Devidas Chavan, Jyoti Verma, Sekhar Dangudubiyyam | | | | | |
| Performance Analysis and Acceleration of High Bandwidth Memory System | Rohit Devidas Chavan, Jyoti Verma, Sekhar Dangudubiyyam | | | | | |
| Performance modeling and timing verification for DRAM memory subsystems | Thomas Schuster, Peter Prüller, and Christian Sauer | | | | | |
| Performance modeling and timing verification for DRAM memory subsystems | Thomas Schuster, Peter Prüller, and Christian Sauer | | | | | |
| Performance Modelling for the Control Backbone | Raghav Tenneti, Padam Krishnani, Praveen Wadikar | | | | | |
| Performance Validation Strategy for collaborative SoC developments where two worlds meets in GDS only | Chirag Kedia and Rahul Gupta | | | | | |
| Performance Validation Strategy for collaborative SoC developments where two worlds meets in GDS only | Chirag Kedia, Mukesh Ameria, and Rahul Gupta | | | | | |
| Performance Verification of a 6 Gbps HSlink Receiver Including Equalization and Clock Recovery Using Mixed Signal Simulations | Aashish Ram Bhide, Abhishek Chowdhary, Alok Kaushik, and Vivek Uppal | | | | | |
| Perspec System Verifier Overview | | | | | | |
| PHY IP Verification – Are Conventional Digital DV Techniques Sufficient? | Somasunder Kattepura Sreenath | | | | | |
| Plan & Metric Driven Mixed-Signal Verification for Medical Devices | Gregg Sarkinen | | | | | |
| Please! Can Someone Make UVM Easier to Use? | Raghu Ardeishar, Rich Edelman | | | | | |
| Please! Can Someone Make UVM Easy to Use? | Rich Edelman, Raghu Ardeishar | | | | | |
| Plugging the Holes: SystemC and VHDL Functional Coverage Methodology | Pankaj Singh and Gaurav Kumar Verma | | | | | |
| Portable Stimuli over UVM using portable stimuli in HW verification flow | Efrat Shneydor, Slava Salnikov, Liran Kosovizer and Dr’ Shlomo Greenberg | | | | | |
| Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication bridge | Andrei Vintila and Ionut Tolea | | | | | |
| Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication bridge | Andrei Vintila and Ionut Tolea | | | | | |
| Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication endpoint | Andrei Vintila and Ionut Tolea | | | | | |
| Portable Stimulus Models for C/SystemC, UVM and Emulation | Mike Andrews and Boris Hristov | | | | | |
| Portable Stimulus Models for C/SystemC, UVM and Emulation | Mike Andrews and Boris Hristov | | | | | |
| Portable Stimulus Standard Update PSS in the Real World | Accellera Portable Stimulus Working Group | | | | | |
| Portable Stimulus Standard Update: PSS in the Real World | Accellera Portable Stimulus Working Group | | | | | |
| Portable Stimulus Standard: The Promises and Pitfalls of Early Adoption | Mike Bartley | | | | | |
| Portable Stimulus Standard’s Hardware Software Interface (HSI) to validate 4G 5G Forward Error Correction Encoder/Decoder IP in Emulation Silicon | Joydeep Maitra, Suresh Vasu, Nithin Venkatesh, Suhas Reddy, Luis Campos, Vinit Shenoy | | | | | |
| Portable Stimulus vs Formal vs UVM: A Comparative Analysis of Verification Methodologies Throughout the Life of an IP Block | Gaurav Bhatnagar | | | | | |
| Portable Stimulus vs Formal vs UVM: A Comparative Analysis of Verification Methodologies Throughout the Life of an IP Block | Gaurav Bhatnagar and David Brownell | | | | | |
| Portable Stimulus: What’s Coming in 1.1 and What it Means For You | Portable Stimulus Working Group | | | | | |
| Portable Test and Stimulus Standard | Hiroshi Hosokawa | | | | | |
| Portable Test and Stimulus: The Next Level of Verification Productivity is Here | Accellera Portable Stimulus Working Group | | | | | |
| Portable Test and Stimulus: The Next Level of Verification Productivity is Here | Tom Fitzpatrick and Sharon Rosenberg | | | | | |
| Post Silicon Performance Validation Using PSS | Dayoung Kim, Jaehun Lee, Daeseo Cha, Phu L. Huynh, and Jake Kim | | | | | |
| Post-Silicon Performance Validation Using PSS | Dayoung Kim, Jaehun Lee, and Daeseo Cha | | | | | |
| Power Aware CDC Analysis at Top Level Using SOC Abstract Flow | Venkatesh Ranga and Pramod Rajan K S | | | | | |
| Power Aware CDC Analysis at Top Level Using SOC Abstract Flow | Venkatesh Ranga and Pramod Rajan K S | | | | | |
| Power Aware CDC Verification at RTL for Faster SoC Verification Closure | Anindya Chakraborty, Naman Jain, Saumitra Goel | | | | | |
| Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts | Mark Handover, Jonathan Lovett, and Kurt Takara | | | | | |
| Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts | Mark Handover, Jonathan Lovett, and Kurt Takara | | | | | |
| Power Aware Models: Overcoming barriers in Power Aware Simulation | Mohit Jain, Amit Singh, J.S.S.S. Bharath, Amit Srivastava, and Bharti Jain | | | | | |
| Power Aware Models: Overcoming barriers in Power Aware Simulation | Mohit Jain, Amit Singh, J.S.S.S. Bharath, Amit Srivastava, and Bharti Jain | | | | | |
| Power Aware Verification Strategy for SoCs | Boobalan Anantharaman and Arunkumar Narayanamurthy | | | | | |
| Power Aware Verification Strategy for SoCs | Boobalan Anantharaman and Arunkumar Narayanamurthy | | | | | |
| Power estimation – what to expect what not to expect | Prakash Parikh | | | | | |
| Power Estimation Techniques – what to expect, what not to expect | Prakash Parikh | | | | | |
| Power Management Verification for SoC ICs | David Akselrod, Alex Miretsky, Sergey Golubkov, Pearl Liu, Afshin Parvaresh, Shu Wang, and Feng Yan | | | | | |
| Power Management Verification for SOC ICs | David Akselrod, Alex Miretsky, Sergey Golubkov, Pearl Liu, Afshin Parvaresh, Shu Wang, and Feng Yan | | | | | |
| Power models & Terminal Boundary: Get your IP Ready for Low Power | Progyna K., William W., Phil G., Brandon S. | | | | | |
| Power Models and Terminal Boundary: Get your IP Ready for Low Power | Progyna Khondkar, William Winkeler, Phil Giangarra and Brandon Skaggs | | | | | |
| Power State to PST Conversion: Simplifying static analysis and debugging of power aware designs | Madhur Bhargava and Pankaj Gairola | | | | | |
| Power State to PST Conversion: Simplifying static analysis and debugging of power aware designs | Madhur Bhargava and Pankaj Gairola | | | | | |
| Power-Aware CDC Verification at RTL for Faster SoC Verification Closure | Anindya Chakraborty, Naman Jain, Saumitra Goel | | | | | |
| Power-Aware Verification in Mixed-Signal Simulation | Atul Pandey, Mattias Welponer, and Gregor Kowalczyk | | | | | |
| Power-Aware Verification in Mixed-Signal Simulation | Atul Pandey, Mattias Welponer, and Gregor Kowalczyk | | | | | |
| Practical Applications of the Portable Testing and Stimulus Standard (PSS) | Sharon Rosenberg | | | | | |
| Practical Approach Using a Formal App to Detect X-Optimism-Related RTL Bugs | Shuqing Zhao, Shan Yan, and Yafang Feng | | | | | |
| Practical Approach Using a Formal App to Detect X-Optimism-Related RTL Bugs | Shuqing Zhao, Shan Yan, and Yafang Feng | | | | | |
| Practical Considerations for Real Valued Modeling of High Performance Analog Systems | Dushyant Juneja, Siddharth Prabhu, and Syam Veluri | | | | | |
| Practical Considerations for Real Valued Modeling of High Performance Analog Systems | Dushyant Juneja, Siddharth Prabhu, and Syam Veluri | | | | | |
| Practical Considerations for Real Valued Modeling of High Performance Analog Systems | Dushyant Juneja, Siddharth Prabhu, and Syam Veluri | | | | | |
| Practical Considerations for Real Valued Modeling of High Performance Analog Systems | Dushyant Juneja, Siddharth Prabhu, and Syam Veluri | | | | | |
| Practical Experience in Automatic Functional Coverage Convergence and Reusable Collection Infrastructure in UVM | Roman Wang, Suresh Babu Pusphaparaj, Mike Bartley | | | | | |
| Practical experience in automatic functional coverage convergence and reusable collection infrastructure in UVM verification | Roman Wang, Suresh Babu Pusphaparaj | | | | | |
| Practical experience in automatic functional coverage convergence and reusable collection infrastructure in UVM verification | Roman Wang and Suresh Babu Pusphaparaj | | | | | |
| Practical Issues in Implementing Fast and Accurate SystemC-Constructed Virtual Platform Simulation | Yu-Fu Yeh and Chung-Yang (Ric) Huang | | | | | |
| Practical Issues in Implementing Fast and Accurate SystemC-Constructed Virtual Platform Simulation | Yu-Fu Yeh and Chung-Yang (Ric) Huang | | | | | |
| Practical Scheme to Enhance Verification Turn-Around-Time by Using Reusable Harness Interface (RHI) | Jongpil Jung, Hyunju Lee, Jaejin Ha, and Yonghee Im | | | | | |
| Practical Scheme to Enhance Verification Turn-Around-Time by Using Reusable Harness Interface (RHI) | Jong pil Jung, Hyunju Lee, Jaejin Ha, and Yonghee Im | | | | | |
| PRACTICAL SCHEMES TO ENHANCE VERTICAL, HORIZONTAL AND PLATFORM REUSABILITY OF VERIFICATION COMPONENTS IN AMBA BASED SOC DESIGN | Ieryung Park, Nara Cho, and Yonghee Im | | | | | |
| Practical Schemes to Enhance Vertical, Horizontal and Platform Reusability of Verification Components in AMBA Based SoC Design | Ieryung Park, Nara Cho and Yonghee Im | | | | | |
| Pragmatic Formal Verification of Sequential Error Detection and Correction Codes (ECCs) used in Safety-Critical Design | Aman Kumar | | | | | |
| Pragmatic Formal Verification of Sequential Error Detection and Correction Codes (ECCs) used in Safety-Critical Design | Aman Kumar | | | | | |
| Pragmatic Verification Reuse in a Vertical World | Mark Litterick | | | | | |
| Pragmatic Verification Reuse in a Vertical World | Mark Litterick | | | | | |
| Pre-Silicon Debug Automation Using Transaction Tagging and Data-Mining | Kamalesh V, Senthilkumar N, Kaustubh G, Deepak S | | | | | |
| Pre-Silicon Debug Automation using Transaction Tagging and Data-Mining | Kamalesh Vikramsimhan, SenthilKumar Narayanaswamy, Deepak Sadasivam, Kaustubh Godbole | | | | | |
| Pre-Silicon Host-based Unit Testing of Driver Software using SystemC Models | Aravinda Thimmapuram, Somarka Chakravarti, Tamal Saha, Rathina Thalaiappan | | | | | |
| Pre-Silicon Power Management Verification of Complex SOCs: Experiences with Intel Moorefield | Rajeev Muralidhar, Nivedha Krishnakumar, Bryan Morgan, Robert Karas, Billy Dennie, and Neil Rosenberg | | | | | |
| Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads using Hybrid System Level Emulation SoC Platform | Neeraj Gupta, Reddaiah Yedoti, Dixit Sethi, and Sarvesh Kumar Pandey | | | | | |
| Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads Using Hybrid System Level Emulation SoC Platform | Neeraj Gupta, Reddaiah Yedoti, Dixit Sethi, and Sarvesh Kumar Pandey | | | | | |
| Predicting Bad Commits | Christian Graber, Daniel Hansson, and Adam Tornhill | | | | | |
| Preventing Chip-Killing Glitches on CDC Paths with Automated Formal Analysis | Jackie Hsiung, Ashish Hari, and Sulabh Kumar Khare | | | | | |
| Preventing Chip-Killing Glitches on CDC Paths with Automated Formal Analysis | Jackie Hsiung, Sulabh Kumar Khare, and Ashish Hari | | | | | |
| Preventing Glitch Nightmares on CDC Paths: The Three Witches | Jian-Hua Yan, Ping Yeung, Stewart Li, Sulabh-Kumar Khare | | | | | |
| Primary, Anonymous, or What? The Destiny of Ports from Design Top that Ultimately are Driven from Off-Chip… | Brandon Skaggs, Progyna Khondkar | | | | | |
| Probing UPF Dynamic Objects: Methodologies to Build Your Custom Low-Power Verification | Progyna Khondkar | | | | | |
| Probing UPF Dynamic Objects: Methodologies to Build Your Custom Low-Power Verification Platform | Progyna Khondkar | | | | | |
| Problematic Bi-Directional Port Connections: How Well is Your Simulator Filling the UPF LRM Void? | Brandon Skaggs | | | | | |
| Problematic Bi-Directional Port Connections: How Well Is Your Simulator Filling the UPF LRM Void? | Brandon Skaggs | | | | | |
| Processing deliberate verification errors during regression | Alastair Lefley, Roger Witlox, Clemens Süßmuth, Thomas Ziller, and Kawe Fotouhi | | | | | |
| Processing deliberate verification errors during regression | Alastair Lefley, Roger Witlox, Clemens Süßmuth, Thomas Ziller and Kawe Fotouhi | | | | | |
| Product Life Cycle of an Interconnect Bus: A Portable Stimulus Methodology for Performance Modeling, Design Verification, and Post-Silicon Validation | Gaurav Bhatnagar and Courtney Fricano | | | | | |
| Product Life Cycle of Interconnect Bus:A Portable Stimulus Methodology for Performance Modeling, Design Verification, and Post-Silicon Validation | Gaurav Bhatnagar and Courtney Fricano | | | | | |
| Profiling Virtual Prototypes: Simulation Performance Analysis & Optimization | Sandeep Jain | | | | | |
| Profiling Virtual Prototypes: Simulation Performance Analysis & Optimization | Sandeep Jain | | | | | |
| Programmable Analysis of RISC-V Processor Simulations using WAL | Lucas Klemmer, Eyck Jentzsch, Daniel Große | | | | | |
| Programming Model Inheritance and Sequence Reuse | Aji Varghese | | | | | |
| Proper probing: Flexibility on the TLM level | Gergő V kony | | | | | |
| Proper Probing: Flexibility on the TLM Level | Gergö Vékony | | | | | |
| Property-Driven Development of a RISC-V CPU | Tobias Ludwig, Michael Schwarz, Joakim Urdahl, Lucas Deutschmann, Salaheddin Hetalani, Dominik Stoffel, and Wolfgang Kunz | | | | | |
| Property-Driven Development of a RISC-V CPU | Tobias Ludwig | | | | | |
| PropGen: An Automated Flow to Generate SVA Properties for Formal and Simulation methods | Amith Shambhu, Vishal Dalal, Basavaraj Naik | | | | | |
| PropGen: An Automated Flow to Generate SVA Properties for Formal and Simulation methods | Amith Shambhu, Vishal Dalal, Basavaraj Naik | | | | | |
| Protocol verification of an IEEE 802.3bw PHY Application of mixed signal extensions to an UVM verification environment | Joen Westendorp and Marcel Oosterhuis | | | | | |
| Prototyping Next-Gen Tegra SoC | Sivarama Prasad Valluri, Ramanan Sanjeevi Krishnan | | | | | |
| Proven Strategies for Better Verification Planning: DVCon 2022 Workshop | Paul Marriott, Jeff Vance, and Jeff McNeal | | | | | |
| Pseudo-LRU Not Efficient in Real World? Use Formal Verification to Bridge the Gap | Paras Gupta, Sachin Kumawat, and Kevin Bhensdadiya | | | | | |
| Pseudo-LRU Not Efficient in Real World? Use Formal Verification to Bridge the Gap | Paras Gupta, Sachin Kumawat, and Kevin Bhensdadiya | | | | | |
| PSL/SVA Assertions in SPICE | Donald O’Riordan and Prabal Bhattacharya | | | | | |
| PSS action sequence modeling using Machine Learning | Moonki Jang | | | | | |
| PSS Action Sequence Modeling Using Machine Learning | Moonki Jang | | | | | |
| PSS Action Sequence Modeling Using Machine Learning | Moonki Jang, Myeongwhan Hyun, Hyunkyu Ahn, Jiwoong Kim, Yunwhan Kim, and Dongjoo Kim | | | | | |
| PSS: The Promises and Pitfalls of Early Adoption | Mike Bartley | | | | | |
| Pushbutton Complete IP Generation | Freddy Nunez | | | | | |
| Python empowered GLS Bringup Vehicle | Debarati Banerjee, Nikhil Singla, Shantha B, Pandithurai Sangaiyah | | | | | |
| Python empowered GLS Bringup Vehicle | Debarati Banerjee, Nikhil Singla, Shantha B, Pandithurai Sangaiyah | | | | | |
| Pythonized SystemC A non-intrusive scripting approach | Eyck Jentzsch and Rocco Jonack | | | | | |
| QED & Symbolic QED Pre-silicon Verification, Post-silicon Validation, Industrial Results | Subhasish Mitra, Eshan Singh and K. Devarajegowda | | | | | |
| Qualification of a Verification IP under Requirement Based Verification standards An approach to the verification of the verification | Francois Cerisier, Adrien Carmagnat, Alessandro Basili, and Gilles Curchod | | | | | |
| Qualification of Formal Properties for Productive Automotive Microcontroller Verification | Holger Busch | | | | | |
| Quantification of Formal Properties for Productive Automotive Microcontroller Verification | Holger Busch | | | | | |
| Quiescent Formal Checks (QFC) for Detecting Deep Design Bugs – Sooner and Faster | Somesh Mishra, Mayank, Kumar, Ketan Mishra, Anshul Jain, Bharath Varma Gottumukkala | | | | | |
| Quiescent Formal Checks (QFC) for Detecting Deep Design Bugs – Sooner and Faster | Somesh Mishra, Mayank, Kumar, Ketan Mishra, Anshul Jain, Bharath Varma Gottumukkala | | | | | |
| Raising the Bar: Achieving Formal Verification Sign-Off for Complex Algorithmic Designs, with a Dot Product Accumulate Case Study | Disha Puri, Madhurima Eranki, Shravya Jampana | | | | | |
| Raising the Bar: Achieving Formal Verification Sign-Off for Complex Algorithmic Designs, with a Dot Product Accumulate Case Study | Disha Puri, Madhurima Eranki, Shravya Jampana | | | | | |
| Raising the level of Formal Signoff with End to End Checking Methodology | Ping Yeung, Arun Khurana, Dhruv Gupta, Ashutosh Prasad, Achin Mittal | | | | | |
| Raising the Level of Formal Signoff with End-to-End Checking Methodology | Ping Yeung, Arun Khurana, Dhruv Gupta, Ashutosh Prasad, and Achin Mittal | | | | | |
| Raising the level of Formal Signoff with End-to-End Checking Methodology | Ping Yeung, Arun Khurana, Dhruv Gupta, Ashutosh Prasad, Achin Mittal | | | | | |
| Raising the level of Formal Signoff with End-to-End Checking Methodology | Ping Yeung, Arun Khurana, Dhruv Gupta, Ashutosh Prasad, Achin Mittal | | | | | |
| Random Directed Low Power Coverage Methodology: A Smart Approach to Power Aware Verification Closure | Awashesh Kumar and Madhur Bhargava | | | | | |
| Random Directed Low Power Coverage Methodology:(A Smart Approach to Power Aware Verification Closure) | Awashesh Kumar and Madhur Bhargava | | | | | |
| Random Stimuli Models for UVM Registers | Jacob Sander Andersen, Lars Viklund and Laura Montero | | | | | |
| Random Testcase Generation and Verification of Debug Unit for a RISC-V Processor Core | Sneha Mishra, Lu Hao, Ajay Sharma, Afshan Anjum, Lucia Franco, Sourav Roy, Jeff Scott | | | | | |
| Random Testcase Generation and Verification of Debug Unit for a RISC-V Processor Core | Sneha Mishra, Lu Hao, Ajay Sharma, Afshan Anjum, Lucia Franco, Sourav Roy, Jeff Scott | | | | | |
| Randomizing UVM Config DB Parameters | Jeremy Ridgeway | | | | | |
| Randomizing UVM Config DB Parameters | Jeremy Ridgeway | | | | | |
| Rapid Virtual Prototype Model development using UML and IP-XACT SystemC Code Generation | Deepak S Kurapati and Aravinda Thimmapuram | | | | | |
| Real Number Modeling | Tom Cole, Wes Queen, Mark Kautzman, and Dan Romaine | | | | | |
| Real Number Modeling Enables Fast, Accurate Functional Verification | Wes Queen, Tom Cole, and Dan Romaine | | | | | |
| Real Number Modeling for RF Circuits | Jakub Dudek, Joshua Nekl and Keith O’Donoghue | | | | | |
| Real Number Modeling of RF Circuits | Jakub Dudek, Joshua Nekl, and Keith O’Donoghue | | | | | |
| Reboot your Reset Methodology: Resetting Anytime with the UVM Reset Package | Courtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm | | | | | |
| Reboot your Reset Methodology: Resetting Anytime with the UVM Reset Package | Courtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm | | | | | |
| Recipe for bug hunting: Tips & Tricks for Low power silicon sign-off | Monika Rawat, Dipankar Narendra Arya, Anuroop R, Deepmala Sachan | | | | | |
| Recipes for Better Simulation Acceleration Performance | Vijayakrishnan Rousseau, Gaurang Nagrecha | | | | | |
| Reconfigurable Radio Design and Verification | Vladimir Ivanov, Markus Mueck, Seungwon Choi | | | | | |
| Reducing simulation life cycle time of Fault Simulations using Artificial Intelligence and Machine Learning techniques on Big dataset | Darshan Sarode, Pratham Khande, Priyanka Gharat | | | | | |
| Reducing the simulation life cycle time of Fault Simulations using Artificial Intelligence and Machine Learning techniques on Big Data dataset | Darshan Sarode, Pratham Khande, Priyanka Gharat | | | | | |
| Reducing the simulation life cycle time using Artificial Intelligence and Machine learning techniques on Big Data dataset | Darshan Sarod, Pratham Khande, Gopi Srinivas Deepala, Priyanka Gharat, Avnita Pal | | | | | |
| Refining Successive Refinement: Improving a Methodology for Incremental Specification of Power Intent | Desinghu PS, Adnan Khan, Erich Marschner, and Gabriel Chidolue | | | | | |
| Refining Successive Refinement: Improving a Methodology for Incremental Specification of Power Intent | Erich Marschner and Gabriel Chidolue | | | | | |
| RegAnalyzer – A tool for programming analysis and debug for verification and validation | Suresh Vasu | | | | | |
| RegAnalyzer -A tool for programming analysis and debug for verification and validation | Suresh Vasu | | | | | |
| Register Modeling – Exploring Fields, Registers and Address Maps | Rich Edelman | | | | | |
| Register Modeling – Exploring Fields, Registers and Address Maps | Rich Edelman | | | | | |
| Register Testing – Exploring Tests, Register Model Libraries, Sequences and Backdoor Access | Rich Edelman | | | | | |
| Register Testing – Exploring Tests, Register Model Libraries, Sequences and Backdoor Access | Rich Edelman | | | | | |
| Register This! Experiences Applying UVM Registers | Sharon Rosenberg | | | | | |
| Register This! Experiences Applying UVM Registers | Kathleen Meade | | | | | |
| Register Verification: Do We Have Reliable Specification? | NamDo Kim, Junhyuk Park, Byeong Min, and Wesley Park | | | | | |
| Register Verification: Do We Have Reliable Specification? | NamDo Kim, Junhyuk Park, Byeong Min, and Wesley Park | | | | | |
| Registering the standard: Migrating to the UVM_REG code base | Sachin Patel, Amit Sharma, and Adiel Khan | | | | | |
| Regressions in the 21st Century – Tools for Global Surveillance | David Crutchfield, Tushar Grupta, Frank Roberts, and Venkataramanan Srinivasan | | | | | |
| Regressions in the 21st Century – Tools for Global Surveillance | David Crutchfield, Tushar Grupta, Frank Roberts, and Venkataramanan Srinivasan | | | | | |
| Regvue Modern Hardware/Software Interface (HSI) Documentation | Rob Donnelly, Josh Geden | | | | | |
| Regvue Modern Hardware/Software Interface Documentation | Rob Donnelly, Josh Geden | | | | | |
| Relieving the Parameterized Coverage Headache | Christine Lovett | | | | | |
| Relieving the Parameterized Coverage Headache | Christine Lovett, Bryan Ramirez, Stacey Secatch, and Michael Horn | | | | | |
| Requirement Driven Safety Verification | Ranga Kadambi, Vladimir Litovtchenko, Jens Rosenbusch, and Antonio Vilela | | | | | |
| Requirement Driven Safety Verification | Ranga Kadambi, Vladimir Litovtchenko, Jens Rosenbusch, and Antonio Vilela | | | | | |
| Requirements Driven Design Verification Flow Tutorial | Ateş Berna and Ahmet Jorghanxhi | | | | | |
| Requirements driven Verification methodology (for standards compliance) | Serrie-Justine Chapman, Darren Galpin, and Mike Bart | | | | | |
| Requirements driven Verification methodology (for standards compliance) | Serrie-justine Chapman, Mike Bartley, and Darren Galpin | | | | | |
| Requirements-driven Verification Methodology for Standards Compliance | Serrie-justine Chapman and Mike Bartley | | | | | |
| Reset and Initialization, the Good, the Bad and the Ugly | Ping Yeung and Kaowen Liu | | | | | |
| Reset and Initialization, the Good, the Bad and the Ugly | Ping Yeung and Kaowen Liu | | | | | |
| Reset and Initialization: the Good, the Bad and the Ugly | Ping Yeung and Kaowen Liu | | | | | |
| Reset Domain Crossing for designs with set-reset flops | Abdul Moyeen, Inayat Ali | | | | | |
| Reset Verification using formal tool | Arju Khatun, Shiva Nagendar Pokala | | | | | |
| Reset Your Reset Domain Crossing (RDC) Verification with Machine Learning | Mark Handover | | | | | |
| Reset Your Reset Domain Crossing (RDC) Verification with Machine Learning | Mark Handover | | | | | |
| Reset Your Reset Domain Crossing (RDC) Verification with Machine Learning | Mark Handover | | | | | |
| Resetting Anytime with the Cadence UVM Reset Package | Courtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm | | | | | |
| Resetting Anytime with the Cadence UVM Reset Package | Courtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm | | | | | |
| Resetting RDC Expectations | Eamonn Quigley, Jonathan Niven, Mark Handover | | | | | |
| Responding to TAT Improvement Challenge Through Testbench Configurability and Re-use | Akhila M, Kartik Jain, Renuka Devi, Mukesh Bhartiya | | | | | |
| Responding to TAT Improvement Challenge through Testbench Configurability and Re-use | Kartik Jain, Renuka Devi Nagarajan, M Akhila, Mukesh Bhartiya | | | | | |
| Results Checking Strategies with Portable Stimulus | Tom Fitzpatrick and Matthew Ballance | | | | | |
| Results Checking Strategies with Portable Stimulus | Tom Fitzpatrick and Matthew Balance | | | | | |
| Results Checking Strategies with Portable Stimulus | Tom Fitzpatrick and Matthew Ballance | | | | | |
| Retention based low power DV challenges in DDR Systems | Subhash Joshi, Sangaiyah Pandithurai, and Halavarthi Math Revana Siddesh | | | | | |
| Retrascope: Open-Source Model Checkerfor HDL Descriptions | Alexander Kamkin, Mikhail Lebedev and Sergey Smolov | | | | | |
| Retrascope: Open-Source Model Checkerfor HDL Descriptions | Alexander Kamkin, Mikhail Lebedev, and Sergey Smolov | | | | | |
| Retry with Confidence: Use Formal Property Verification to Verify Link Layer Retry (LLR) Mechanism of Compute Express Link (CXL) | Anshul Jain, Aman Vyas, Binal Sodavadia, Sava Krstic, Achutha KiranKumar V M | | | | | |
| Reusable DPI flow across Verification, Validation & SW | Prasad Haldule, Pushkar Naik | | | | | |
| Reusable Processor Verification Methodology Based on UVM | Mustafa Khairallah and Maged Ghoneima | | | | | |
| Reusable Processor Verification Methodology Based on UVM | Mustafa Khairallah and Maged Ghoneima | | | | | |
| Reusable System-Level Power-Aware IP Modeling Approach | Antonio Genov, Francois Verdier, and Loic Leconte | | | | | |
| REUSABLE UPF: Transitioning from RTL to Gate Level Verification | Durgesh Prasad, Jitesh Bansal, and Madhur Bhargava | | | | | |
| REUSABLE UPF: Transitioning from RTL to Gate Level Verification | Durgesh Prasad, Jitesh Bansal, and Madhur Bhargava | | | | | |
| Reusable UVM_REG Backdoor Automation | Balasubramanian G., Allan Peeters, Bob Blais | | | | | |
| Reusable UVM_REG Backdoor Automation | Balasubramanian G., Allan Peeters, Bob Blais | | | | | |
| Reusable Verification Environment for a RISC-V Vector Accelerator | R. Ignacio Genovese, Josue Quiroga, Ivan Diaz, Henrique Yano, Asif Ali, Nehir Sonmez, Oscar Palomar, Victor Jimenez, Mario Rodriguez, Marc Dominguez | | | | | |
| Reusable Verification Environment for a RISC-V Vector Accelerator | Josue Quiroga, Roberto Ignacio Genovese, Ivan Diaz, Henrique Yano, Asif Ali, Nehir Sonmez, Oscar Palomar, Victor Jimenez, Mario Rodriguez, Marc Dominguez | | | | | |
| Reuse C test and UVM sequence utilizing TLM2, register model and interrupt handler | Liu HongLiang and Gao Teng-Fei | | | | | |
| Reuse C test and UVM sequence utilizing TLM2, register model and interrupt handler | HongLiang Liu and Teng-Fei Gao | | | | | |
| Reuse doesn’t come for free – learnings from a UVM deployment | Sumeet Gulati, Srinivasan Venkataramanan, Azhar Ahammad, Ketki Gosavi, and Saumya Anvekar | | | | | |
| Reuse doesn’t come for free – learnings from a UVM deployment | Sumeet Gulati, Srinivasan Venkataramanan, Ketki Gosavi, Saumya Anvekar, and Azhar Ahammad | | | | | |
| Reuse of System-Level Verification Components within Chip-Level UVM Environments | Diego Alagna, Marzia Annovazzi, Alessandro Cannone, Marcello Raimondi, Simone Saracino, Mukesh Chugh, Marc Erickson, Cristian Macario, Giuseppe Ridinò | | | | | |
| Reusing Sequences in a Multi-Language environment using UVM-ML OA | Hannes Fröhlich, Kishore Sur | | | | | |
| Reusing Testbench Components in a Hybrid Simulation-Formal Environment | Ritero Chi and Xiaolin Chen | | | | | |
| Reusing UVM Test Benches in a Cycle Simulator | Kristina Hager, Carter Alvord, Andrew Lynch, and Umer Yousafzai | | | | | |
| Reusing UVM Testbenches in a Cycle Simulator | Kristina Hager, Andrew Lynch, Umer Yousafzai, and Carter Alvord | | | | | |
| Revitalizing Automotive Safety Hard and Soft Error Approaches | Nael Qudsi and Ayman Mouallem | | | | | |
| Revolutionary Debug Techniques to Improve Verification Productivity | Nadav Chazan | | | | | |
| Revolutionizing Proof Convergence for Algorithmic Designs: Combining Multiple Formal Verification Tools | Suraj Kamble, Rajib Lochan Jana, Disha Puri | | | | | |
| Revolutionizing Proof Convergence for Algorithmic Designs: Combining Multiple Formal Verification Tools | Suraj Kamble, Rajib Lochan Jana, Disha Puri | | | | | |
| Richard Weber, Jamsheed Agahi, Josh Rensch, Eric Sherk | Pratik Parvati | | | | | |
| RISC-V Compliance & Verification Techniques Processor Cores and Custom Extensions | Simon Davidmann, Lee Moore, Richard Ho, Doug Letcher and Kevin McDermott | | | | | |
| RISC-V Integrity: A Guide for Developers and Integrators | Nicolae Tusinschi | | | | | |
| RISC-V Processor Verification: Case Study | Adi Maymon, Shay Harari, Lee Moore, Larry Lapides | | | | | |
| RISC-V Security Verification using Perspec/Portable Stimulus | Junxia Wang, Siyan. Li, Leven. Li, A T S Prasad, Kiran Kumar Palla, Yung Cheng Chen | | | | | |
| Robust Low Power Verification Strategy for a Complex 3DIC System with Split Power Management Architecture | Atiq Jamadar, Ayush Agrawal, Subramanian R, Sekhar Dangudubiyyam | | | | | |
| Robust Low Power Verification Strategy for a Complex 3DIC System with Split Power Management Architecture | Atiq Jamadar, Ayush Agrawal, Subramanian R, Sekhar Dangudubiyyam | | | | | |
| Robust Physical Layer IP Verification for DDR4-3DS Memory by Channel Modelling | Aditya S Kumar, Gowdra Bomanna Chethan, Shivani Maurya, Kumar Rajeev Ranjan, Anil Deshpande, Somasunder Kattepura Sreenath | | | | | |
| Rockin’ the Polymorphism for an Elegant UVM Testbench Architecture | Mike Baird and Frank Verhoorn | | | | | |
| Rockin’ the polymorphism for an Elegant UVM testbench Architecture for a Scalable, Highly Configurable, Extensible DUT | Michael Baird and Frank Verhoorn | | | | | |
| Rolling the dice with random instructions is the safe bet on RISC-V verification | Simon Davidmann and Lee Moore, Richard Ho and Tao Liu, and Doug Letcher and Aimee Sutton | | | | | |
| RTL Quality for TLM Models | Preeti Sharma | | | | | |
| RTL2RTL Formal Equivalence: Boosting the Design Confidence | M. Achutha KiranKumar V, Aarti Gupta, and Ss. Bindumadhava | | | | | |
| RTL2RTL Formal Equivalence: Boosting the Design Confidence | M. Achutha KiranKumar V, Aarti Gupta, and Ss. Bindumadhava | | | | | |
| Run-time Configuration of a Verification Environment – A Novel Use of the OVM/UVM Analysis Pattern | Paul Marriott and Mark Ronan | | | | | |
| Run-Time Configuration of a Verification Environment: A Novel Use of the OVM/UVM Analysis Pattern | Paul Marriott | | | | | |
| Run-Time Phasing in UVM: Ready for the Big Time or Dead in the Water? | John Aynsley | | | | | |
| Run-Time Phasing in UVM: Ready for the Big Time or Dead in the Water? | John Aynsley | | | | | |
| Runtime Fault-Injection Tool for Executable SystemC Models | Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, and Thomas Kruse | | | | | |
| Safety and Security Aware Pre-silicon Concurrent Software Development and Verification | Frank Schirrmeister, Joe Fabbre, and Max Hinson | | | | | |
| Safety and Security Aware Pre-silicon Concurrent Software Development and Verification | Frank Schirrmeister, Joe Fabbre, and Max Hinson | | | | | |
| Safety and Security Aware Pre-Silicon Hardware / Software Co-Development | Nikola Velinov and Frank Schirrmeister | | | | | |
| Safety-Verification Flow Sporting Gate-Level Accuracy and Near Virtual-Prototype Speed | B.-A. Tabacaru, M. Chaari, W. Ecker, T. Kruse, and C. Novello | | | | | |
| Safety-Verification Flow Sporting Gate-Level Accuracy and Near Virtual-Prototype Speed | Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, and Cristiano Novello | | | | | |
| Same bits, different meaning – when direct execution based simulation becomes complicated | Evgeny Yulyugin | | | | | |
| SAR ADC Layout Generation Using Digital Place-and-Route Tools | Yao-Hung Tsai and Shen-Iuan Liu | | | | | |
| Saving and Restoring Simulation Methodology using UVM Factory Overriding to Reduce Simulation Turnaround Time | Ahhyung Shin, Yungi Um, Youngsik Kim, and Seonil Brian Choi | | | | | |
| Saving and Restoring Simulation Methodology using UVM Factory Overriding to Reduce Simulation Turnaround Time | Ahhyung Shin, Yungi Um, Youngsik Kim, and Seonil Brian Choi | | | | | |
| SAWD: Systemverilog Assertions Waveform-based Development Tool | Ahmed Alsawi | | | | | |
| SAWD: Systemverilog Assertions Waveform-based Development tool | Ahmed Alsawi | | | | | |
| Scalable Mixed Features Stimulus Generation for Cluster Network Using Sequence Decorator | Chi-Ming Li | | | | | |
| Scalable Multi-Domain Multi-Variant Reset Management in Complex Verification IPs | Kaustubh Kumar, Munnangi Sirisha, Lokesh Kumar | | | | | |
| Scalable Multi-Domain, Multi-Variant Reset Management in Verification IPs | Kaustubh Kumar, Munnangi Sirisha, and Lokesh Kumar | | | | | |
| Scalable Reset Domain Crossing Verification Using Hierarchical Data Model | Soumya Palit, Anwesha Choudhury, and Kurt Takara | | | | | |
| Scalable Test bench Architecture and Methodology for Faster Codec and Computer Vision Scenario Verification | Azhar Ahammad, Shreekara Murthy | | | | | |
| Scalable Test bench Architecture and Methodology for Faster Codec and Computer Vision Scenario Verification | Azhar Ahammad, Shreekara Murthy | | | | | |
| SCALABLE, RE-USABLE UVM DMS AMS BASED VERIFICATION METHODOLOGY FOR MIXED-SIGNAL SOCS | Nilesh Sonara, Noorulla Mohammad, Poonam Singh, David Stoops, Joseph Fernando, and Kartik Sudarshana | | | | | |
| Scalable, Re-usable UVM DMS AMS based Verification Methodology for Mixed-Signal SOCs | Nilesh Sonara, Noorulla Mohammad, Poonam Singh, David Stoops, Joseph Fernando, and Kartik Sudarshana | | | | | |
| Second Generation Completeness Analysis of Formal Assertions on Compatibility of RISC-V Cores | Wayne Yun | | | | | |
| Securing design confidence for Low power and Functional features of Image Sensor SOC – Reuse of UVM simulation testbench on HW acceleration platform | Vivek Kumar, Manish Mallan, Karthik Majeti | | | | | |
| Security Verification using Perspec/Portable Stimulus | Junxia Wang, Leven Li, Siyan Li, A T S Prasad, Kiran Kumar Palla, Yung Cheng Chen | | | | | |
| Security Verification Using Portable Stimulus Driven Test Suite Synthesis | Adnan Hamid and David Kelf | | | | | |
| See the Forest for the Trees – How to Effectively Model and Randomize a Directed Rooted Tree Structure | Harry Duque and Lars Viklund | | | | | |
| See the Forest for the Trees – How to Effectively Model and Randomize a DRT Structure | Harry Duque, Lars Viklund | | | | | |
| Semi-formal Reformulation of Requirements for Formal Property Verification | Katharina Ceesay-Seitz, Hamza Boukabache and Daniel Perrin | | | | | |
| Sequence, Sequence on the Wall – Who’s the Fairest of Them All? | Rich Edelman and Raghu Ardeishar | | | | | |
| SERDES Rx CDR Verification Using Jitter, Spread-Spectrum Clocking (SSC) Stimulus | Somasunder Sreenath, Raghuram Kolipaka, Chirag Shah, Parag Lonkar | | | | | |
| SERDES Rx CDR Verification Using Jitter, Spread-Spectrum Clocking (SSC) Stimulus | Somasunder Sreenath, Raghuram Kolipaka, Chirag Shah, and Parag Lonkar | | | | | |
| Seven Separate Sequence Styles Speed Stimulus Scenarios | Mark Peryer | | | | | |
| Seven Separate Sequence Styles Speed Stimulus Scenarios | Mark Peryer | | | | | |
| SGEN2: Evolution of a Sequence-Based Stimulus Engine for Micro-Processor Verification | Stephan Bourduas and Christopher Mikulis | | | | | |
| SGEN2: Evolution of a sequence-based stimulus engine for micro-processor verification. | Stephan Bourduas and Chris Mikulis | | | | | |
| Shaping Formal Traces without Constraints: A Case Study in Closing Code Coverage on a Crypto Engine Using Formal Verification | David N. Goldberg, Adriana Maggiore, and David J. Simpson | | | | | |
| Shaping Formal Traces without Constraints: A Case Study in Closing Code Coverage on a Crypto Engine using Formal Verification | David N. Goldberg, Adriana Maggiore, and David J. Simpson | | | | | |
| Sharing Generic Class Libraries in SystemVerilog Makes Coding Fun Again | Keisuke Shimizu | | | | | |
| Sharing Generic Class Libraries in SystemVerilog Makes Coding Fun Again | Keisuke Shimizu | | | | | |
| Shifting functional verification to high value HLV | Junichi Tatsuda | | | | | |
| Shifting functional verification to high value HLV | Junichi Tatsuda | | | | | |
| Shifting Left CXL Interop using Simulation Techniques | John Shinto K S, Suhas Pai | | | | | |
| Sign-off with Bounded Formal Verification Proofs | NamDo Kim, Junhyuk Park, HarGovind Singh, and Vigyan Singhal | | | | | |
| Sign-off with Bounded Formal Verification Proofs | NAMDO KIM, JUNHYUK PARK, HARGOVIND SINGH, and VIGYAN SINGHAL | | | | | |
| SIM-V Fast, Parallel RISC-V Simulation for Rapid Software Verification | Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers | | | | | |
| Simple & Rapid Design Verification using SystemVerilog Testbench on Intel’s Next-Generation Microprocessor | Thomas Alsop, Wayne Clift, Luke Hood, and Jeff Gray | | | | | |
| SimpleLink™ MCU Platform: IP-XACT to UVM Register Model – Standardizing IP and SoC Register Verification | Jasminka Pasagic and Frank Donner | | | | | |
| SimpleLink™ MCU Platform: IP-XACT to UVM Register Model – Standardizing IP and SoC Register Verification “UVM is a perfect start” | Jasminka Pasagic and Frank Donner | | | | | |
| Simpler Register Model | Sanjeev Singh | | | | | |
| Simpler Register Model Package for UVM Testbenches. | Sanjeev Singh | | | | | |
| Simplifying Hierarchical Low Power Designs Using Power Models in Intel Design | Rohit Kumar Sinha | | | | | |
| Simplifying Hierarchical Low Power Designs Using Power Models in Intel Design | Rohit Kumar Sinha | | | | | |
| Simplifying UVM in SystemC | Thilo Vörtler, Thomas Klotz, Karsten Einwich, and Felix Assma | | | | | |
| Simplifying UVM in SystemC | Thilo Vörtler, Thomas Klotz, Karsten Einwich, and Felix Assma | | | | | |
| SimPy for Chips | Hachem Tassine, Daniel Wilkinson, Graham Cunnigham, Iason Myttas | | | | | |
| Simulation Acceleration with ZeBu to Speed IP and Platform Verification | Hillel Miller and Wei-Hua Han | | | | | |
| Simulation Analog Fault Injection Flow for Mixed-Signal Designs | Pablo Cholbi Alenda, Dylan OConnor Desmond, Raman K | | | | | |
| Simulation Analog Fault Injection Flow for Mixed-Signal Designs | Pablo Cholbi Alenda, Dylan OConnor Desmond, Raman K | | | | | |
| Simulation and Debug of Mixed Signal Virtual Platforms for Hardware-Software co-development | Vincent Motel, Alexandre Roybier, and Serge Imbert | | | | | |
| Simulation and Debug of Mixed Signal Virtual Platforms for Hardware-Software co-development | Vincent Motel, Alexandre Roybier, and Serge Imbert | | | | | |
| Simulation Based Pre-Silicon Characterization | Saurabh Pandey, Venkatseema Das, Arif Mohammed, Nishant Gurunath | | | | | |
| Simulation Based Pre-Silicon Characterization | Saurabh Pandey, Venkatseema Das, Arif Mohammed, Nishant Gurunath | | | | | |
| Simulation Guided Formal Verification with “River Fishing” Techniques | Bathri Narayanan Subramanian, Ping Yeung | | | | | |
| Simulation Runtime Optimization of Constrained Random Verification using Machine Learning Algorithms | Sarath Mohan Ambalakkat and Eldon Nelson | | | | | |
| Simulation Runtime Optimization of Constrained Random Verification using Machine Learning Algorithms | Sarath Mohan Ambalakkat M.S. and Eldon Nelson M.S. P.E. | | | | | |
| Single Source Register Sequencing Toolkit and Methodology for FW and Verification Co-Development | Josh Loo, Anthony Cabrera, Kiel Boyle, and Scott R. Nelson | | | | | |
| Single Source System to Register-Transfer Level Design Methodology Using High-Level Synthesis | Petri Solanti and Thomas Arndt | | | | | |
| Single Source System to Register-Transfer Level Design Methodology Using High-Level Synthesis | Petri Solanti and Thomas Arndt | | | | | |
| Slaying the UVM Reuse Dragon | Mike Baird and Bob Oden | | | | | |
| Slaying the UVM Reuse Dragon Issues and Strategies for Achieving UVM Reuse | Mike Baird and Bob Oden | | | | | |
| Slicing Through the UVM’s Red TapeA Frustrated User’s Survival Guide | Jonathan Bromley © Accellera | | | | | |
| Slicing Through the UVM’s Red Tape: A Frustrated User’s Survival Guide | Jonathan Bromley | | | | | |
| Small Scale Parameterized Inference Engine | Vishnu Bharadwaj, Shruti Narake, and Saurabh Patil | | | | | |
| Smart Centralized Regression (SCR) | Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath, Siddhant Kumar Yadav, Ajay Pennam, Aman Jain | | | | | |
| Smart Formal for Scalable Verification | Ashish Darbari | | | | | |
| Smart Formal for Scalable Verification | Ashish Darbari | | | | | |
| Smart Recipe for Quick Bug Hunting: Boosting functional sign-off with Low-Power Assertions | Jeevan G R, Deepmala Sachan, Thameem Syed, Raghavendra Prakash | | | | | |
| Smarter Verification Management | David Zhang | | | | | |
| Sneak Preview of UVM-SystemC: The Missing Piece in ESL Verification | Martin Barnasconi, Karsten Einwich | | | | | |
| So There’s My Bug! Debugging Universal Verification Methodology (UVM) Environments | Mike Floyd | | | | | |
| So you think you have good stimulus: System-level distributed metrics analysis and results | Andreas Meyer | | | | | |
| So you think you have good stimulus: System-level distributed metrics analysis and results | Andreas Meyer | | | | | |
| SOBEL FILTER: Software Implementation to RTL using High Level Synthesis | Bhavna Aggarwal, Umesh Sisodia, and Snigdha Tyagi | | | | | |
| SOBEL FILTER: Software Implementation to RTL using High Level Synthesis | Bhavna Aggarwal, Umesh Sisodia and Snigdha Tyagi | | | | | |
| SoC Firmware Debugging Tracer in Emulation Platform | Kubendra Kumbar, Sandeep Vallabhaneni, Ken Joseph Kannampuzha, Hojun Shim, and Byung Chul Yoo | | | | | |
| SoC Firmware Debugging Tracer in Emulation Platform | Kubendra Kumbar, Sandeep Vallabhaneni, Ken Joseph Kannampuzha, Hojun Shim, and Byung Chul Yoo | | | | | |
| SoC Verification Enablement Using HM Model | Vineet Tanwar, Chirag Kedia, Rahul Gupta | | | | | |
| SoC Verification of Analog IP Integration through Automated, Formal-Based, Rule-driven Spec Generation | Murugesh Palaniswamy, Ravi Kalyanaraman, Gargi Sharma, and Bharat Baliga-Savel | | | | | |
| SoC Verification of Analog IP Integration through Automated, Formal-Based, Rule-driven Spec Generation | Murugesh Palaniswamy, Ravi Kalyanaraman, Gargi Sharma, and Bharat Baliga-Savel | | | | | |
| SoC verification of Security x Safety aspects for memory programmed into secure and non-secure regions in Automotive devices | Ruchi Bora, Ramit Rastogi | | | | | |
| SoC Verification Speed – More is Better | Fernanda Braga, John Rose, William Winkeler, Sharon Rosenberg, and Frank Schirrmeister | | | | | |
| SoC Verification using OVM : Leveraging OVM Constructs to Perform Processor Centric Verification | Cedric Macadangdang and Paul Yue | | | | | |
| Soft Constraints in SV: Semantics and Challenges | Mark Strickland | | | | | |
| Soft Constraints in SystemVerilog Semantics and Challenges | Mark Strickland, Joseph Hanli Zhang, Jason Chen, Dhiraj Goswami, and Alex Wakefield | | | | | |
| Software Driven Hardware Verification: A UVM/DPI Approach | Milan Purohit, Santanu Bhattacharyya, Puneet Goel, Amit Sharma | | | | | |
| Software Driven Test of FPGA PrototypeMethods & Use cases | Krzysztof Szczur and Radosław Nawrot | | | | | |
| Solving Next Generation IP Configurability | David Murray and Simon Rance | | | | | |
| Solving Next Generation IP Configurability | David Murray and Simon Rance | | | | | |
| Solving Problems with hierarchical CDC analysis of large designs with encrypted blocks | Abdul Moyeen, Arpita Agarwal, Aman Shaikh, Abhay Deshpande | | | | | |
| Soumak – How rich descriptions enable early detection of hookup issues | Peter Birch, Thomas Brown | | | | | |
| Source Control…$100 Regression Script…$500 Good Automated Release Steps…$Priceless | Jeffrey Wren | | | | | |
| Specification by Example for Hardware Design and Verification | Jussi Mäkelä | | | | | |
| Specification by Example for Hardware Design and Verification | Jussi Mäkelä | | | | | |
| Specification Driven Analog and Mixed-Signal Verification | Henry Chang and Ken Kundert | | | | | |
| Specification Driven Analog and Mixed-Signal Verification | Henry Chang and Ken Kundert | | | | | |
| Standard Regression Testing Does not Work | Daniel Hansson | | | | | |
| Standard Regression Testing Does Not Work | Daniel Hansson | | | | | |
| State-Space “Switching” Model of DC-DC Converters in SystemVerilog | Elvis Shera | | | | | |
| State-Space “Switching” Model of DC-DC Converters in SystemVerilog. | Elvis Shera | | | | | |
| Static Analysis of SystemC/SystemC-AMS System and Architectural Level Models | Karsten Einwich and Thilo Vörtler | | | | | |
| Static Analysis of SystemC/SystemC-AMS System and Architectural Level Models | Karsten Einwich and Thilo Vörtler | | | | | |
| Static Checking for Correctness of Functional Coverage Models | Wael Mahmoud | | | | | |
| Static Checking for Correctness of Functional Coverage Models | Wael Mahmoud | | | | | |
| Static Power Intent Verification of Power State Switching Expressions | Srobona Mitra, Bhaskar Pal, Kaushik De, Soumen Ghosh, Rajarshi Mukherjee | | | | | |
| Static power-management verification of Cypress’s PSoC® Programmable System-on-Chip for embedded systems | Johnie Au and Prapanna Tiwari | | | | | |
| Static Sign-Off Best Practices Learnings and Experiences from Industry Use Cases | Vikas Sachdeva | | | | | |
| Static Sign-Off Best Practices Learnings and Experiences from Industry Use Cases | Vikas Sachdeva | | | | | |
| Static Sign-Off Best Practices Learnings and Experiences from Industry Use Cases | Vikas Sachdeva | | | | | |
| Static Signoff Best Practices – Learnings and experiences from industry use cases | Vikas Sachdeva | | | | | |
| Statically Dynamic or Dynamically Static? Exploring the power of classes and enumerations in SystemVerilog Assertions for reusability and scalability | Sachin Scaria, Sreenu Yerabolu, and Don Mills | | | | | |
| Statically Dynamic or Dynamically Static? Exploring the power of classes and enumerations in SystemVerilog Assertions for reusability and scalability | Sachin Scaria and Sreenu Yerabolu | | | | | |
| Statistical Analysis of Clock Domain Crossing | Rajat Singla, Tanneru Sai Pavan, Naveen Dugar, Varun Sharma | | | | | |
| Statistical Analysis of Clock Domain Crossing | Rajat Singla, Tanneru Sai Pavan, Naveen Dugar, Varun Sharma | | | | | |
| Step-up your Register Access Verification | Nisha Kadhirvelu, Sundar Krishnakumar, and Wesley Park | | | | | |
| Step-up your Register Access Verification | Nisha Kadhirvelu, Sundar Krishnakumar, and Rimpy Chugh | | | | | |
| Stepping into UPF 2.1 world: Easy solution to complex Power Aware Verification | Amit Srivastava and Madhur Bhargava | | | | | |
| Stepping into UPF 2.1 world: Easy solution to complex Power Aware Verification | Amit Srivastava and Madhur Bhargava | | | | | |
| Stepwise Refinement and Reuse: The Key to ESL | Ashok B. Mehta, Mark Glasser, Shabtay Matalon, and Dan Gardner | | | | | |
| Stimulating Scenarios in the OVM and VMM | JL Gray and Scott Roland | | | | | |
| Stimulus Generation for Functional Verification of Memory Systems | Vaibhav Anant Ashtikar | | | | | |
| Stimulus Generation for Functional Verification of Memory Systems in Advanced Microprocessors | BhanuPratap Singh Chouhan, Vaibhav Anant Ashtikar, Basavaraj Talawar, Vani M., Krishnakumar Ranganathan | | | | | |
| Strategies and Methods of using PSS2.0 high level modeling techniques to augment UVM verification | Swami Venkatesan | | | | | |
| Strategies on CDC False Alarm Rapid Location | Jianhua Yan, Meiling Qi, Yunyang Song | | | | | |
| Strategies to Maximize Reusability of UVM Test Scenarios in SoC Verification | Hyeonman Park, Namyoung Kim, Kyoungmin Lee, Hongkyu Kim, Jaein Hong, Kiseok Bae | | | | | |
| Strategies to Maximize Reusability of UVM Test Scenarios in SoC Verification | Namyoung Kim, Hyeonman Park, Kyoungmin Lee, Hongkyu Kim, Jaein Hong, Kiseok Bae | | | | | |
| Strategy and Environment for SOC Mixed-Signal Validation: A Case Study | Erik A McShane and Intel | | | | | |
| Sub-design Interface Aware Top Only Static Low Power Verification | Heichang Lee, Nikhil Amin, Jianfeng Liu, Minyoung Mo, and Dongkwan Han | | | | | |
| Successes and Challenges of Validation Content Reuse | Mike Chin, Jonathan Edwards, Josh Pfrimmer, and Hooi Jing Tan | | | | | |
| Successive Refinement – An Approach to Decouple Front End and Back End Power Intent | Sinha Rohit Kumar and Kotha Kavya | | | | | |
| Successive Refinement – An Approach to Decouple Front Front-End and Back Back-End Power Intent | Kotha Kavya and Sinha Rohit Kumar | | | | | |
| Successive Refinement – An approach to decouple Front-End and Back-end Power Intent | Rohit Kumar Sinha | | | | | |
| Successive Refinement of UPF Power Switches | Prabhakar Satya Ayyagari, William G Crocco | | | | | |
| Successive Refinement: A Methodology for Incremental Specification of Power Intent | Adnan Khan, Eamonn Quigley, John Biggs, and Erich Marschner | | | | | |
| Successive Refinement: A Methodology for Incremental Specification of Power Intent | Adnan Khan, John Biggs, Eamonn Quigley, and Erich Marschner | | | | | |
| Successive Refinement: A Methodology for Incremental Specification of Power Intent | Adnan Khan, Eamonn Quigley, John Biggs, and Erich Marschner | | | | | |
| Supercharge Your Verification Using Rapid Expression Coverage as the Basis of a MC/DC-Compliant Coverage Methodology | Gaurav Kumar Verma and Doug Warmke | | | | | |
| Supercharge Your Verification Using Rapid Expression Coverage as the Basis of a MC/DC-Compliant Coverage Methodology | Gaurav Kumar Verma and Doug Warmke | | | | | |
| Supplementing Simulation of a Microcontroller Flash Memory Subsystem with Formal Veri cation | Othmane Bahlous and Abdelouahab Ayari | | | | | |
| Supplementing Simulation of a Microcontroller Flash Memory Subsystem with Formal Verification | Othmane Bahlous and Abdel Ayari | | | | | |
| Supply network connectivity: An imperative part in low power gate-level verification | Vinay Kumar Singh and Gabriel Chidolue | | | | | |
| Supply network connectivity: An imperative part in low power gate-level verification | Gabriel Chidolue, Vinay Singh, and Divyeshkumar Dhanjibhaiv Vora | | | | | |
| Supporting root cause analysis of inaccurate bug prediction based on machine learning – Lessons learned when interweaving training data and source code | Oscar Werneman, Markus Borg, Daniel Hansson | | | | | |
| Survey of Machine Learning (ML) Applications in Functional Verification (FV) | Dan Yu, Harry Foster, Tom Fitzpatrick | | | | | |
| SVA Encapsulation in UVM: enabling phase and configuration aware assertions | Mark Litterick | | | | | |
| SVA Encapsulation in UVM: enabling phase and configuration aware assertions | Mark Litterick | | | | | |
| SwiftCov: Automated Coverage Closure Tool | Nisha Mallya, Kunal Panchal, Pushkar Naik | | | | | |
| Switch the Gears of the UVM Register Package to cruise through the street named “Register Verification”. | Parag Goel, Amit Sharma, Varun S, Abhisek Verma, and Gaurav Gupta | | | | | |
| Switch the Gears of the UVM Register Package to cruise through the street named “Register Verification”. | Amit Sharma, Varun S, Abhisek Verma, and Gaurav Gupta | | | | | |
| Synchronicity: Bringing Order to SystemVerilog/UVM Synchronizing Chaos | Bryan Morris and P. Eng | | | | | |
| Synchronicity: Bringing Order to the SystemVerilog/UVM Synchronizing Chaos | Bryan Morris | | | | | |
| Synthesis of Decoder Tables using Formal Verification Tools | Keerthikumara Devarajegowda, Johannes Schreiner, and Wolfgang Ecker | | | | | |
| Synthesis of Decoder Tables using Formal Verification Tools | Keerthikumara Devarajegowda, Johannes Schreiner, and Wolfgang Ecker | | | | | |
| Synthesis of Decoder Tables Using Formal Verification Tools | Keerthikumara Devarajegowda, Johannes Schreiner, and Wolfgang Ecker | | | | | |
| Synthesizable Random Testbench for Multimedia IP Verification | Sanggyu Park | | | | | |
| SysML based Architecture Definition and Platform Generation Flow | Ralph Görgen and Erwin de Kock | | | | | |
| SYSTEM LEVEL FAULT INJECTION SIMULATION USING SIMULINK | Wai Yuen Tang, Marcelo Mizuki, Mitch Norcross, and Fengying Qiao | | | | | |
| System Level Fault Injection Simulation Using Simulink | Wai Yuen Tang, Marcelo Mizuki, Mitch Norcross, and Fengying Qiao | | | | | |
| System level random verification: How it should be done | Madhusudan Rathi and Ashok Chandran | | | | | |
| System Model – A Testbench Library Component Aided for Emulating User Interaction | Hussain Wadia | | | | | |
| System Responsiveness Verification of large Multi Processor System Configurations using Micro Benchmarks and a Multi Level Analysis | Dr. Ralf Winkelmann, Edward Chencinski, Hanno Eichelberger, Michael Fee, Carsten Otte, and Christoph Raisch | | | | | |
| System Responsiveness Verification of large Multi-Processor System Configurations using Micro-Benchmarks and a Multi-Level Analysis | Dr. Ralf Winkelmann, Edward Chencinski, Hanno Eichelberger, Michael Fee, Carsten Otte, Christoph Raisch | | | | | |
| System to catch Implementation gotchas in the RTL Restructuring process | Anmol Rattan, Satinder Malhi, and Balwinder Soni | | | | | |
| System to catch Implementation gotchas in the RTL Restructuring process | Anmol Rattan, Satinder Singh Malhi, Balwinder Singh Soni, Anuj Kumar, Navneet Chaurasia, and Sami Akhtar | | | | | |
| System Verification with MatchLib | Russell Klein | | | | | |
| System Verilog Assertion Linting: Closing Potentially Critical Verification Holes | Erik Seligman, Laurence Bisht, and Dmitry Korchemny | | | | | |
| System Verilog Assertions Verification | Ionuț Ciocîrlan and Andra Radu | | | | | |
| System-Level Power Estimation of SSDs under Real Workloads using Emulation | Sangmin Kim, Kwanghyo Ahn, Changhoon Han, Hyunsik Kim, Jaewoo Im | | | | | |
| System-Level Power Estimation of SSDs under Real Workloads using Emulation | Sangmin Kim, Kwanghyo Ahn, Changhoon Han, Hyunsik Kim, Jaewoo Im | | | | | |
| System-Level Random Verification: How it should be done | Madhusudan Rathi and Ashok Chandran | | | | | |
| System-Level Register Verification and Debug | Utkarsh Bhiogade, Kautilya Joshi, Puneet Goel | | | | | |
| System-Level Security Verification Starts with the Hardware Root of Trust | Dr. Jason Oberg | | | | | |
| Systematic Application of UCIS to Improve the Automation on Verification Closure | Christoph Kuznik, Marcio F. S. Oliveira, Gilles Bertrand Defo, and Wolfgang Mueller | | | | | |
| Systematic Application of UCIS to Improve the Automation on Verification Closure | Christoph Kuznik, Marcio F. S. Oliveira, Gilles Bertrand Defo, and Wolfgang Mueller | | | | | |
| Systematic Constraint Relaxation (SCR): Hunting for Over Constrained Stimulus | Debarshi Chatterjee, Spandan Kachhadia, Ismet Bayraktaroglu, Siddhanth Dhodhi | | | | | |
| Systematic Constraint Relaxation (SCR): Hunting for Over-Constrained Stimulus | Debarshi Chatterjee, Spandan Kachhadiya, Ismet Bayraktaroglu, and Siddhanth Dhodhi | | | | | |
| Systematic Speedup Techniques for Functional CDC Verification Closure | Sulabh Kumar Khare and Ashish Hari | | | | | |
| Systematic Speedup Techniques for Functional CDC Verification Closure | Sulabh Kumar Khare and Ashish Hari | | | | | |
| Systematically Achieving CDC Verification Closure based on Coverage Models and Coverage Metrics | Ashish Hari and Yogesh Badaya | | | | | |
| Systematically Achieving CDC Verification Closure based on Coverage Models and Coverage Metrics | Ashish Hari and Yogesh Badaya | | | | | |
| SystemC extension for power specification, simulation and verification | Mikhail Moiseev, Ilya Klotchkov, and Kirill Gagarski | | | | | |
| SystemC extension for power specification,simulation and verification | Mikhail Moiseev, Ilya Klotchkov, Maxim Petrov, and Kirill Gagarski | | | | | |
| SystemC FMU for Verification of Advanced Driver Assistance Systems | Keroles Khalil and Magdy A. El-Moursy | | | | | |
| SystemC gaps encountered in Virtual Platform development | Eyck Jentzsch | | | | | |
| SystemC Virtual Prototype: Ride the Earliest Train for Time-To-Market | Shweta Saxena and Mahantesh Danagouda | | | | | |
| SystemC Virtual Prototype: Ride the earliest train for Time-To-Market! | Shweta Saxena and Mahantesh Danagouda | | | | | |
| SystemC-to-Verilog Compiler: a productivity-focused tool for hardware design in cycle-accurate SystemC | Mikhail Moiseev, Roman Popov, and Ilya Klotchkov | | | | | |
| SystemC-to-Verilog Compiler: a productivity-focused tool for hardware design in cycle-accurate SystemC | Mikhail Moiseev, Roman Popov and Ilya Klotchkov | | | | | |
| SystemC: Focusing on High Level Synthesis and Functional Coverage for SystemC | Dragos Dospinescu, Frederic Doucet, Mike Meredith, Bob Condon, Dragos Dospinescu and Mike Meredith | | | | | |
| SystemRDL to PSS BASIC TO PRO | Anupam Bakshi and Amanjyot Kaur | | | | | |
| SystemUVM™ Driving Portable Stimulus Ease-Of-Use | Nambi Ju | | | | | |
| SystemVerilog Assertion Linting: Closing Potentially Critical Verification Holes | Laurence S. Bisht, Dmitry Korchemny, and Erik Seligman | | | | | |
| SystemVerilog Assertions for Clock-Domain-Crossing Data Paths | Don Mills | | | | | |
| SystemVerilog Assertions for Clock-Domain-Crossing Data Paths | Don Mills | | | | | |
| SystemVerilog Checkers: Key Building Blocks for Verification IP | Laurence Bisht, Dmitry Korchemny, and Erik Seligman | | | | | |
| SystemVerilog Configurations and Tool Flow Using SCons (an Improved Make) | Don Mills and Dillan Mills | | | | | |
| SystemVerilog Constraint Layering via Reusable Randomization Policy Classes | John Dickol | | | | | |
| SystemVerilog Constraint Layering via Reusable Randomization Policy Classes | John Dickol | | | | | |
| SystemVerilog Constraints: Appreciating What You Forgot In School to Get Better Results | Dave Rich | | | | | |
| SystemVerilog for Design | Saminathan Chockalingam, Deepa Anantharaman | | | | | |
| SystemVerilog Format of Portable Stimulus | Wayne Yun, David Chen, Theta Yang, and Evean Qin | | | | | |
| SystemVerilog FrameWorksTM Scoreboard: An Open Source Implementation Using UVM | Ambar Sarkar | | | | | |
| SystemVerilog Interface Classes – More Useful Than You Thought | Stan Sokorac | | | | | |
| SystemVerilog Interface Classes More Useful Than You Thought | Stan Sokorac | | | | | |
| SystemVerilog Interface Cookbook | Paul Egan and Kathleen Otten | | | | | |
| SystemVerilog Interface Cookbook | Paul Egan and Kathleen Otten | | | | | |
| SystemVerilog Meets C++: Re-use of Existing C/C++ Models Just Got Easier | John Aynsley | | | | | |
| SystemVerilog Real Models for an InMemory Compute Design | Daniel Cross | | | | | |
| SystemVerilog-2009 Enhancements: Priority/Unique/Unique | Clifford E. Cummings | | | | | |
| SystemVerilog, Batteries Included: A Programmer’s Utility Library for SystemVerilog | Jonathan Bromley and André Winkelmann | | | | | |
| SystemVerilog, Batteries Included: A Programmer’s Utility Library for SystemVerilog | Jonathan Bromley and André Winkelmann | | | | | |
| Table-based Functional Coverage Management for SOC Protocols | Shahid Ikram, Jack Perveiler, Isam Akkawi, Jim Ellis, and David Asher | | | | | |
| Table-based Functional Coverage Management for SOC Protocols | Shahid Ikram, Jack Perveiler, Isam Akkawi, Jim Ellis, and David Asher | | | | | |
| Tabled Data Into Query Able Data, ‘Key’ Concepts Demonstrated Using DDR5 | Rahil Jha, Joseph Bauer | | | | | |
| Tabled Data Into Query Able Data, ‘Key’ Concepts Demonstrated Using DDR5 | Rahil Jha, Joseph Bauer | | | | | |
| Tackling Random Blind Spots with Strategy-Driven Generation | Matthew Ballance | | | | | |
| Tackling Random Blind Spots with Strategy-Driven Stimulus Generation | Matthew Ballance | | | | | |
| Tackling Register Aliasing Verification Challenges in Complex ASIC Design | Shan Yan, Jie Wu, and Jing Li | | | | | |
| Tackling Register Aliasing Verification Challenges in Complex ASIC Design | Shan Yan, Jie Wu, and Jing Li | | | | | |
| Tackling the challenge of simulating multi-rail macros in a power aware flow | Himanshu Bhatt, Amol Herlekar, Vikas Grover, and Subhadip Nath | | | | | |
| Tackling the challenge of simulating multi-rail macros in a power-aware flow | Himanshu Bhatt, Amol Herlekar, Vikas Grover, and Subhadip Nath | | | | | |
| Tackling the Complexity Problem in Control and Datapath Designs with Formal Verification | Ravindra Aneja, Ashish Darbari, Nitin Mhaske, and Per Bjesse | | | | | |
| Tackling the verification complexities of a processor subsystem through Portable stimulus | Vivek Gopalkrishna, Ponnambalam Lakshmanan, Nitish Swamy | | | | | |
| Tackling the verification complexities of a processor subsystem through Portable stimulus | Vivek Gopalkrishna, Ponnambalam Lakshmanan, Nitish Swamy | | | | | |
| Take AIM! Introducing the Analog Information Model | Chuck McClish | | | | | |
| Take AIM! Introducing the Analog Information Model | Chuck McClish | | | | | |
| Taking Design Automation to the next level with User Experience Design | Jamie Lai, Bodo Hoppe | | | | | |
| Taking Real-Value Modeling to the next level: Power-aware verification of mixed-signal designs | Subin Thykkoottathil, Jakub Dudek, Nagesh Ranganath, Nimay Shah, and Santosh Singh | | | | | |
| Taking RNM Model to the Next Level: Power-Aware Verification of Mixed-Signal Designs | Subin Thykkoottathil, Nagesh Ranganath, Santosh Singh, Jakub Dudek, and Nimay Shah | | | | | |
| Taming a Complex UVM Environment | Manjunath Shetty, and Ramamurthy Gorti | | | | | |
| Taming a Complex UVM Environment | Manjunath Shetty and Ramamurthy Gorti | | | | | |
| Taming the beast: A smart generation of Design Attributes (Parameters) for Verification Closure Using Specman | Meirav Nitzan, Yael Kinderman, and Efrat Gavish | | | | | |
| Techniques to identify reset metastability issues due to soft resets | Reetika, Sulabh Kumar Khare | | | | | |
| Techniques to identify reset metastability issues due to soft resets | Reetika, Sulabh Kumar Khare | | | | | |
| Temporal assertions in SystemC | Mikhail Moiseev, Leonid Azarenkov, and Ilya Klotchkov | | | | | |
| Temporal Assertions in SystemC | Mikhail Moiseev, Leonid Azarenkov and Ilya Klotchkov | | | | | |
| Temporal Decoupling – Are “Fast” and “Correct” Mutually Exclusive? | Jakob Engblom | | | | | |
| Temporal Decoupling – Are “Fast” and “Correct” Mutually Exclusive? | Jakob Engblom | | | | | |
| Test driving Portable Stimulus at AMD | Prabhat Gupta and Matan Vax | | | | | |
| Test Parameter Tuning with Blackbox Optimization: A Simple Yet Effective Way to Improve Coverage | Qijing Huang*, Hamid Shojaei, Fred Zyda, Azade Nazi, Shobha Vasudevan, Sat Chatterjee, Richard Ho | | | | | |
| Test Parameter Tuning with Blackbox Optimization: A Simple Yet Effective Way to Improve Coverage | Qijing Huang, Hamid Shojaei, Fred Zyda, Azade Nazi, Shobha Vasudevan, Sat Chatterjee, Richard Ho | | | | | |
| Test-driving PSS for System Low-Power Validation | Prabhat Gupta and Matan Vax | | | | | |
| Testbench Configuration Mantra | Stephen D’Onofrio | | | | | |
| Testbench Flexiblity as a Foundation for Success | Ana Sanz Carretero, Katherine Garden, Wei Wei Cheong | | | | | |
| Testing the Testbench | Stan Sokorac | | | | | |
| Testing the Testbench | Stan Sokorac | | | | | |
| Testpoint Synthesis Using Symbolic Simulation | Kai-Hui Chang, Yen-Ting Liu and Chris Browy | | | | | |
| Testpoint Synthesis Using Symbolic Simulation | Kai-Hui Chang, Yen-Ting Liu and Chris Browy | | | | | |
| The Application of Formal Technology on Fixed Point Arithmetic SystemC Designs | Sven Beyer, Dominik Straßer, and Dave Kelf | | | | | |
| The Application of Formal Technology on Fixed-Point Arithmetic SystemC Designs | Sven Beyer, Dominik Straßer, and David Kelf | | | | | |
| The Art of Portable and Reusable UVM Shared System Memory Model Verification Methodology across Multiple Verification Platforms | Roman Wang, Thomas Bodmer, and Beryl Chen | | | | | |
| The Art of Portable and Reusable UVM Shared System Memory Model Verification Methodology Across Multiple Verification Platforms | Roman Wang, Thomas Bodmer, and Beryl Chen | | | | | |
| The Art of Writing Predictors Efficiently Using UVM | Dolly Mehta, Jeremy Ridgeway | | | | | |
| The Best Verification Strategy You’ve Never Heard Of | David Aerne, Amir Attarha, Harry Foster, and Kurt Takara | | | | | |
| The Big Brain Theory – Visualizing SoC Design & Verification Data | Gordon Allan | | | | | |
| The Big Brain Theory: Visualizing SoC Design & Verification Data | Gordon Allan | | | | | |
| The Case for Low-Power Simulation-to-Implementation Equivalence Checking | Himanshu Bhatt, John Decker, and Hiral Desai | | | | | |
| The Case for Low-Power Simulation-to-Implementation Equivalence Checking | Himanshu Bhatt, John Decker, and Hiral Desai | | | | | |
| The CHIPS ACT and Its Impact On The Design & Verification Markets | BOB SMITH | | | | | |
| The Cost of SoC Bugs | Ken Albin | | | | | |
| The Cost of SoC Bugs | Ken Albin | | | | | |
| The Cost of Standard Verification Methodology Implementations | Abigail Williams, Svetlomir Hristozkov, Adam Hizzey | | | | | |
| The Cost Of Standard Verification Methodology Implementations | Adam Hizzey, Abigail Williams, Svetlomir Hristozkov | | | | | |
| The Evolution of RISC-V Processor Verification | Aimee Sutton, Lee Moore, Mike Thompson | | | | | |
| The Evolution of RISC-V Processor Verification: Open Standards and Verification IP | Lee Moore, Aimee Sutton, Mike Thompson | | | | | |
| The Evolution of Triage – Real-time Improvements in Debug Productivity | Gordon Allan | | | | | |
| The Exascale Debug Challenge: Time to advance your emulation debug game | Ribhu Mittal and Melvyn Goveas | | | | | |
| The Finer Points of UVM: Tasting Tips for the Connoisseur | John Aynsley | | | | | |
| The Finer Points of UVM: Tasting Tips for the Connoisseur | John Aynsley | | | | | |
| The Formal Way – Fast and Accurate Hashing Algorithm Verification | Sini Balakrishnan, Sireesha Tulluri, Bindumadhava SS, Disha Puri | | | | | |
| The future of formal model checking is NOW! | Ram Narayan | | | | | |
| The Future of Formal Model Checking is NOW! | Ram Narayan | | | | | |
| The Growing Need for End-to-end Protocol Verification for IP to Multi-die Systems | Varun Agrawal, Shakir Ali | | | | | |
| The How To’s of Advanced Mixed-Signal Verification | John Brennan, Thomas Ziller, Kawe Fotouhi, and Ahmed Osman | | | | | |
| The How To’s of Metric Driven Verification to Maximize Productivity | Matt Graham and John Brennan | | | | | |
| The Importance of Complete Signoff Methodology for Formal Verification | Mahesh Parmar, Iain Singleton, Geogy Jacob | | | | | |
| The Importance of Complete Signoff Methodology for Formal Verification | Iain Singleton, Mahesh Parmer, and Geogy Jacob | | | | | |
| The Industry eFPGA soft IP fully customizable, for hardware reconfiguration in the field | Mrs Imen Baili | | | | | |
| The Life of a SystemVerilog Variable | Dave Rich | | | | | |
| The Missing Link: The Testbench to DUT Connection | David Rich | | | | | |
| The missing SystemC and TLM asynchronous features enabling inter-simulation synchronization. | Guillaume Delbergue, Mark Burton, Bertrand Le Gal and Christophe Jego | | | | | |
| The Need for Speed: Understanding design factors that make multi-core parallel simulations efficient | Shobana Sudhakar and Rohit K Jain | | | | | |
| The Need for Speed: Understanding design factors that make multi-core parallel simulations efficient | Shobana Sudhakar and Rohit K Jain | | | | | |
| The New Power Perspective – Realistic Workloads – Real Results | Xiaoming Li | | | | | |
| The Next Generation Of EDA | Luke Yang | | | | | |
| The Open Source DRAM Simulator DRAMSys4.0 | Matthias Jung | | | | | |
| The Open-Source DRAM Simulator DRAMSys4.0 | Matthias Jung | | | | | |
| The OVM-VMM Interoperability Library: Bridging the Gap | Tom Fitzpatrick and Adam Erickson | | | | | |
| The Problems with Lack of Multiple Inheritance in SystemVerilog and a Solution | David Rich | | | | | |
| The Process and Proof for Formal Sign-Off –A Live Case Study | Ipshita Tripathi, Ankit Saxena, Anant Verma, and Prashant Aggarwal | | | | | |
| The Process and Proof for Formal Sign-off A Live Case Study | Ipshita Tripathi, Ankit Saxena, Anant Verma, and Prashant Aggarwal | | | | | |
| The Top Most Common SystemVerilog Constrained Random Gotchas | Ahmed Yehia | | | | | |
| The Top Most Common SystemVerilog Constrained Random Gotchas | Ahmed Yehia | | | | | |
| The Universal Translator | David Cornfield | | | | | |
| The Universal Translator – A Fundamental UVM Component for Networking Protocols | David Cornfield | | | | | |
| The Universal Translator – A Fundamental UVM Component for Networking Protocols | David Cornfield | | | | | |
| The Untapped Power of UVM Resources and Why Engineers Should Use the uvm_resource_db API | Clifford E. Cummings, Heath Chambers, Mark Glasser | | | | | |
| The Untapped Power of UVM Resources and Why Engineers Should Use the uvm_resource_db API | Clifford E. Cummings, Heath Chambers, Mark Glasser | | | | | |
| The UPF 2.1 Library Commands: Truly Unifying the Power Specification Formats | Amit Srivastava, Awashesh Kumar, and Vinay Singh | | | | | |
| The UPF 2.1 library commands: Truly unifying the power specification formats | Amit Srivastava, Awashesh Kumar, and Vinay Singh | | | | | |
| THE VERIFICATION COCKPIT – A ONE-STOP SHOP FOR YOUR VERIFICATION DATA | Alia Shah, Eugene Rotter, Avi Ziv, Raviv Gal, and Divya Joshi | | | | | |
| There’s something wrong between Sally Sequencer and Dirk Driver – why UVM sequencers and drivers need some relationship counselling | Mark Peryer | | | | | |
| There’s something wrong between Sally Sequencer and Dirk Driver (Why UVM sequencers and drivers need some relationship counseling) | Mark Peryer | | | | | |
| Thinking Ahead – Advanced Verification and Debug Techniques for the Imminent IoT Wave | Vamsi Krishna Doppalapudi | | | | | |
| Thinking Beyond the Box Adopt the Reusable UVM Thread Management and Customized UVM Reset Package to Attack Thread Aware Verification Challenges | Roman Wang, Uwe Simm, Malathi Chikkanna | | | | | |
| Thinking In TransactionsVisualizing and Validating | Rich Edelman, Mustufa Kanchwala | | | | | |
| Timing Coverage: An Approach to Analyzing Performance Holes | Surbhi Kalia, Shubhadeep Karmakar, Vikas Makhija, and Apoorva Mathur | | | | | |
| Timing-Aware High Level Power Estimation of Industrial Interconnect Module | Amal Ben Ameur, Antonio Genov, François Verdier and Loic Leconte | | | | | |
| Timing-Aware high level power estimation of industrial interconnect module | Amal Ben Ameur, Antonio Genov, François Verdier, and Loic Leconte | | | | | |
| Tips for Developing Performance Efficient Verification Environments | Prashanth Srinivasa, Sarath Chandrababu Valapala, and Varun S | | | | | |
| Title: Using Test-IP Based Verification Techniques in a UVM Environment | Vidya Bellippady, Sundar Haran, and Jay O’Donnell | | | | | |
| TLM based Virtual Platforms at Ericsson Challenges and Experiences | Ola Dahl, Michael Lebert, and Eric Frejd | | | | | |
| TLM Beyond Memory Mapped Busses | Bart Vanthournout and Mark Burton | | | | | |
| TLM modeling and simulation for NAND Flash and Solid State Drive systems | Tim Kogel and Victor Reyes | | | | | |
| TLM-2.0 in SystemVerilog | Mark Glasser and Janick Bergeron, | | | | | |
| TLM-based Virtual Platforms at Ericsson: Challenges and Experiences | Ola Dahl, Michael Lebert, and Eric Frejd | | | | | |
| To Infinity And Beyond – Streaming Data Sequences in UVM | Mark Litterick, Jeff Vance, Jeff Montesano | | | | | |
| Tough Verification Challenges: Data Visualization to the Rescue | Shaji Kunjumohamed | | | | | |
| Towards 5G Internet of Things | Sabine Roessel | | | | | |
| Towards a UVM-based Solution for Mixed-signal Verification | Alexander W. Rath, Sebastian Simon, Volkan Esen, and Wolfgang Ecker | | | | | |
| Towards a UVM-based Solution for Mixed-signal Verification | Alexander W. Rath, Sebastian Simon, Volkan Esen, and Wolfgang Ecker | | | | | |
| Towards Early Validation of Firmware Using UVM Simulation Framework | Amaresh Chellapilla, Pandithurai Sangaiyah | | | | | |
| Towards Early Validation of Firmware Using UVM Simulation Framework | Amaresh Chellapilla, Pandithurai Sangaiyah | | | | | |
| Towards Provable Protocol Conformance of Serial Automotive Communication IP | Jens E. Becker, Oliver Sander, Alexander Klimm, J¨urgen Becker, Katharina Weinberger, and Slava Bulach | | | | | |
| Traditional top level static low power rule check | | | | | | |
| Traffic Profiling and Performance Instrumentation For On-Chip Interconnects | Mark Peryer and Bruce Mathewson | | | | | |
| Traffic Profiling and Performance Instrumentation For On-Chip Interconnects | Mark Peryer | | | | | |
| Transaction Recording Anywhere Anytime | Rich Edelman | | | | | |
| Transaction-Based Acceleration—Strong Ammunition In Any Verification Arsenal | Chandrasekhar Poorna, Varun Gupta, and Raj Mathur | | | | | |
| Transaction-Level Friending: An Open-Source, Standards-Based Library for Connecting TLM Models in SystemC and SystemVerilog | Adam Erickson | | | | | |
| Transaction-Level State Charts in UML and SystemC with Zero-Time Evaluation | Rainer Findenig , Thomas Leitner, Michael Velten, and Wolfgang Ecker | | | | | |
| Transaction‐Based Testing with OSVVM and the OSVVM Model Library | Jim Lewis and Patrick Lehmann | | | | | |
| Transactional Memory Subsystem Verification for an ARMv8 Server Class CPU | Ramdas M., Parveez Ahamed, Brijesh Reddy, Jayanto Minocha | | | | | |
| Transactional Memory Subsystem Verification for an ARMv8 Server Class CPU | Ramdas Mozhikunnath, Parveez Ahamed, Brijesh Reddy, Jayanto Minocha | | | | | |
| Translating and Adapting to the “real” world: SerDes Mixed Signal Verification using UVM | Akhila Madhu Kumar and Karl Herterich | | | | | |
| Translating and Adapting to the “real” world: SerDesMixed Signal Verification using UVM | Akhila Madhu Kumar and Karl Herterich | | | | | |
| Transparent SystemC Model Factory for Scripting Languages | Rolf Meyer, Bastian Farkas, Syed Abbas Ali Shah, and Mladen Berekovic | | | | | |
| Transparent SystemC Model Factory for Scripting Languages | Rolf Meyer, Bastian Farkas, Syed Abbas Ali Shah, and Mladen Berekovic | | | | | |
| Transparently Checkpointing Software Test Benches to Improve Productivity of SoC Verification in an Emulation Environment | Ankit Garg, K. Suresh, Gene Cooperman, Rohan Garg, and Jeff Evans | | | | | |
| Transparently Checkpointing Software Test Benches to Improve Productivity of SOC Verification in an Emulation Environment | Ankit Garg, K. Suresh, Jeff Evans, Gene Cooperman, and Rohan Garg | | | | | |
| Traversing the Interconnect: Automating Configurable Verification Environment Development | Prashanth Srinivasa and Mathew Roy | | | | | |
| Tree Data Framework for Code Generation: Application of Generating UVM Testbench for Complex Designs | Chenhui Huang, Yu Sun, Divyang Agrawal | | | | | |
| Tree Data Framework for Code Generation: Application of Generating UVM Testbench for Complex Designs | Chenhui Huang, Yu Sun, Divyang Agrawal | | | | | |
| Trends in Functional Verification: A 2016 Industry Study | Harry D. Foster | | | | | |
| Trends in Functional Verification: A 2016 Industry Study | Harry D. Foster | | | | | |
| Trials and Tribulations of Migrating a Native UVM Testbench from Simulation to Emulation | Vikas Billa, Sundar Haran | | | | | |
| Tried and Tested Speedups for SW-driven SoC Simulation | Gordon Allan | | | | | |
| Tried/Tested speedups for SW-driven SoC Simulation | Gordon Allan | | | | | |
| Tutorial 7 Tutorial on RISC-V Design and Verification | Kevin McDermott, Zdenek Prikryl, and Peter Shields | | | | | |
| Tutorial creating effective formal testbench | Hiroshi Nonoshita | | | | | |
| Tutorial IP-XACT IEEE 1685 from 101 to latest info | Koji Nakamura | | | | | |
| Tutorial RTL Verification using Python | Akio Mitsuhashi | | | | | |
| Tutorial SoC Verification Strategy | Seiichi Futami | | | | | |
| Tweak-Free Reuse Using OVM | Sharon Rosenberg | | | | | |
| TwIRTee design exploration with Capella and IP-XACT | Philippe Cuenot, Bassem Ouni, and Pierre Gaufillet | | | | | |
| TwIRTee: design exploration with Capella and IP-XACT | Bassem Ouni, Philippe Cuenot, and Pierre Gaufillet | | | | | |
| Two Stage Framework for Corner Case Stimuli Generation Using Transformer and Reinforcement Learning | Chung An Wang, Chiao Hua Tseng, Chia Cheng Tsai, Tung Yu Lee, Yen Her Chen, Chien Hsin Yeh, Chia Shun Yeh, Chin Tang Lai MediaTek, Hsinchu, Taiwan | | | | | |
| Two-Stage Framework for Corner Case Stimuli Generation Using Transformer and Reinforcement Learning | Chung-An Wang, Chiao-Hua Tseng, Chia-Cheng Tsai, Tung-Yu Lee, Yen-Her Chen, Chien-Hsin Yeh, Chia-Shun Yeh, and Chin-Tang Lai | | | | | |
| Types of Robustness Test According to DO-254 Guideline for Avionic Systems | Gözde Asena KILINÇ, Yavuz AKSU, Fatih BAYSAL | | | | | |
| Types of Robustness Test According to DO-254 Guideline for Avionic Systems | Gözde Asena KILINÇ, Yavuz AKSU, Fatih BAYSAL | | | | | |
| Types of Robustness Test According to DO-254 Guideline for Avionic Systems | Gözde Asena KILINÇ, Yavuz AKSU, Fatih BAYSAL | | | | | |
| UCIe based Design Verification | Anunay Bajaj, Sundararajan Ananthakrishnan | | | | | |
| UCIS APPLICATIONS: IMPROVING VERIFICATION PRODUCTIVITY, SIMULATION THROUGHPUT, AND COVERAGE CLOSURE PROCESS | Ahmed Yehia | | | | | |
| UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process | Ahmed Yehia | | | | | |
| Ultimate Shift Left: Unleash the Power of UVM Virtual LAB Methodology upon SoC Verification | Roman Wang | | | | | |
| Ultimate Shift Left: Unleash the Power of UVM Virtual LAB Methodology upon SoC Verification | Roman Wang | | | | | |
| Unconstrained UVM SystemVerilog Performance | Wes Queen and Justin Sprague | | | | | |
| Unconstrained UVM SystemVerilog Performance | Wes Queen | | | | | |
| Uncover: Functional Coverage Made Easy | Akash S, Rahul Jain, Gaurav Agarwal | | | | | |
| Uncover: Functional Coverage Made Easy | Akash S, Rahul Jain, Gaurav Agarwal, Nvidia Graphics | | | | | |
| Understanding the effectiveness of your system-level SoC stimulus suite | Robert Fredieu, Alan Hunter, and Andreas Meyer | | | | | |
| Understanding the effectiveness of your system-level SoC stimulus suite | Alan Hunter , Robert Fredieu, and Andreas Meyer | | | | | |
| Understanding the Low Power Abstract | Gary Delp, Erich Marschner, and Kenneth Bakalar | | | | | |
| Understanding the RISC-V Verification Ecosystem | imon Davidmann, Aimee Sutton, Lee Moore | | | | | |
| Unified Firmware Debug throughout SoC Development Lifecycle | Dimitri Ciaglia, Thomas Winkler, Jurica Kundrata | | | | | |
| Unified firmware debug throughout SoC development lifecycle | D. Ciaglia, T. Winkler, J. Kundrata | | | | | |
| Unified Functional and Performance FrameworkA Case Study of Cache: Using SystemC TLM Non Blocking Interfaces | Chaitra K V | | | | | |
| Unified Functional Safety Verification Platform for ISO 26262 Compliant Automotive | Joerg Richter | | | | | |
| Unified Model/Hardware-in-the-Loop Methodology for Mixed-Signal System Design and Hardware Prototyping | Martin Barnasconi, Wil Kitzen, Thieu Lammers, Paul Ehrlich, Karsten Einwich | | | | | |
| Unified Test Writing Framework for Pre and Post Silicon Verification | Rahulkumar Patel, Pablo Cholbi, Sivasubrahmanya Evani, Raman K | | | | | |
| Unified Test Writing Framework for Pre and Post Silicon Verification | Rahulkumar Patel, Pablo Cholbi, Sivasubrahmanya Evani, Raman K | | | | | |
| Unified Test Writing Framework for Pre and Post Silicon Verification | Rahulkumar Patel, Pablo Cholbi, Sivasubrahmanya Evani and Raman K | | | | | |
| Unifying Hardware-Assisted Verification and Validation Using UVM and Emulation | Hemant Sharma, Hans van der Schoot, and Achutam Murarka | | | | | |
| Unifying Hardware-Assisted Verification and Validation Using UVM and Emulation | Hemant Sharma, Hans van der Schoot, and Achutam Murarka | | | | | |
| Unifying Mixed-Signal and Low-Power Verification | Adam Sherer, Andre Baguenier, Kawe Fotouhi, Abhijit Madhu Kumar, Qingyu Lin, Raj Mitra, and William Winkeler | | | | | |
| Unique Verification Case Studies of Low Power Mixed Signal Chips | Venkatesh Ranga, Madhusudhan Subramanya, Anand Shirwal, Pramod Rajan K S, and Jeff Goswick | | | | | |
| Unique Verification Case Studies of Low Power Mixed Signal Chips | Jeff Goswick, Venkatesh Ranga, Madhusudhan Subramanya, Anand Shirwal, and Pramod Rajan K S | | | | | |
| Universal Scripting Interface for SystemC | Rolf Meyer, Jan Wagner, Rainer Buchty, and Mladen Berekovic | | | | | |
| Universal Scripting Interface for SystemC | Rolf Meyer | | | | | |
| Unleashing Portable Stimulus Productivity with a PSS Reuse Strategy | M. Ballance | | | | | |
| Unleashing Portable Stimulus Productivity with a Reuse Strategy | Matthew Balance | | | | | |
| Unleashing the Full Power of UPF Power States | Erich Marschner and John Biggs | | | | | |
| Unleashing the Full Power of UPF Power States | Erich Marschner and John Biggs | | | | | |
| Unleashing the Power of UPF 3.0: An Innovative Approach for Faster and Robust Low-power Coverage | Awashesh Kumar, Madhur Bhargava | | | | | |
| Unraveling the Complexities of Functional Coverage: An advanced guide to simplify your use model | Thomas Ellis and Rohit Jain | | | | | |
| Unraveling the Complexities of Functional Coverage: An advanced guide to simplify your use model | Thom Ellis and Rohit Jain | | | | | |
| Unveil the Mystery of Code Coverage in Low Power Designs (Achieving Power Aware Verification Closure) | Madhur Bhargava, Durgesh Prasad, and Pavan Rangudu | | | | | |
| Unveil the Mystery of Code Coverage in Low-Power Designs: Achieving Power Aware Verification Closure | Madhur Bhargava, Durgesh Prasad, and Pavan Rangudu | | | | | |
| UPF 1.0, UPF 2.0, UPF 2.1, UPF 3.0, and now UPF 3.1: The big Q “Which is the Right Standard for My Design”? | Madhur Bhargava | 2020 | Presentation | | y2020 | presentation |
| UPF Code Coverage and Corresponding Power Domain Hierarchical Tree for Debugging | Shang-Wei Tu, Tom Lin, Archie Feng, and Chen Ya Ping | | | | | |
| UPF GENERIC REFERENCES: UNLEASHING THE FULL POTENTIAL | Durgesh Prasad and Jitesh Bansal | | | | | |
| UPF Generic References: Unleashing the Full Potential | Jitesh Bansal and Durgesh Prasad | | | | | |
| UPF Power Models: Empowering the power intent specification | Amit Srivastava and Harsh Chilwal | | | | | |
| UPF: How to avoid traps in a Hierarchical Implementation Low Power flow? | Frederic Saint-Preux, | | | | | |
| UPF: How to avoid traps in a Hierarchical Implementation Low Power flow? | Frederic Saint-Preux | | | | | |
| Use of Aliasing in SystemVerilog Verification Environment | Evean Qin | | | | | |
| Use of Aliasing in SystemVerilog Verification Environment | Evean Qin | | | | | |
| Use of CDC-jitter-modeling in clock-domaincrossing- circuits in RTL design phase | Jan Hayek, Jochen Neidhardt, and Robert Richter | | | | | |
| Use of CDC-Jitter-Modeling inClock-Domain-Crossing-Circuits in RTL Design Phase | Jan Hayek, JochenNeidhardt, and Robert Richter | | | | | |
| Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262 | Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Said Hamdioui, and Christian Sauer | | | | | |
| Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262 | Felipe A. da Silva, Ahmet C. Bagbaba, Said Hamdioui and Christian Sauer | | | | | |
| Use of Message Bus Interface to Verify Lane Margining in PCIe | Ankita Vashisht, Narasimha Babu G V L | | | | | |
| Use of Portable Stimulus to Verify Task Dispatching and Scheduling Functions in an LTE Switch | Adnan Hamid | | | | | |
| Use Stimulus Domain for Systematic Exploration of Time Dimension and Automatic Testcase Construct | Ning Chen and Martin Ruhwandl | | | | | |
| User Experiences with the Portable Stimulus Standard | Tom Fitzpatrick, Prabhat Gupta, Mike Chin | | | | | |
| User Experiences with the Portable Stimulus Standard | Tom Fitzpatrick, Prabhat Gupta, Mike Chin | | | | | |
| Using a Generic Plug and Play Performance Monitor for SoC Verification | Ambar Sarkar, Kaushal Modi, Janak Patel, Bhavin Patel, Ajay Tiwari | | | | | |
| Using a Generic Plug and Play Performance Monitor for SoC Verification | Ajay Tiwari, Bhavin Patel, Janak Patel, Kaushal Modi | | | | | |
| Using a modern build system to speed up complex hardware design | Varun Koyyalagunta | | | | | |
| Using a modern software build system to speed up complex hardware design | Varun Koyyalagunta | | | | | |
| Using Advanced OOP Concepts To Integrate Templatized Algorithms for Standard Protocols With UVM | Anunay Bajaj and Gaurav Chugh | | | | | |
| Using Advanced OOP Concepts To Integrate Templatized Algorithms for Standard Protocols With UVM | Anunay Bajaj and Gaurav Chugh | | | | | |
| Using an Enhanced Verification Methodology for Back-to-Back RTL/TLM Simulation | Frank Poppen, Ralph Görgen, Kai Schulz, Andreas Mauderer, Jan-Hendrik Oetjens, Robert Bosch, Joachim Gerlach, and Hochschule, Albstadt-Sigmaringen | | | | | |
| Using an Enhanced Verification Methodology for Back-to-Back RTL/TLM Simulation | Frank Poppen, Ralph Görgen, Kai Schulz, Andreas Mauderer, Jan-Hendrik Oetjens, Robert Bosch, Joachim Gerlach, and Hochschule Albstadt-Sigmaringen | | | | | |
| Using Assertions in an Active W ay to Design and Verify Interface between Analog and Digital B locks | HyunDon Kim, Jiang Long, Wesley Park, ChiHo Cha, JaeBeom Kim, Byeong Min, and KyuMyung Choi | | | | | |
| Using Automation to Close the Loop Between Functional Requirements and Their Verification | Brian Craw, David Crutchfield, Martin Oberkoenig, Markus Heigl, and Martin O’Keeffe | | | | | |
| Using Automation to Close the Loop Between Functional Requirements and Their Verification | Brian Craw, David Crutchfield, Martin Oberkoenig, Markus Heigl, and Martin O’Keeffe | | | | | |
| Using Cadence and MathWorksTools Together for Mixed-Signal Design and Verification | Graham Reith and Andrew Beckett | | | | | |
| Using Constraints for SystemC AMS Design and Verification | Thilo Vörtler, Karsten Einwich, Muhammad Hassan, and Daniel Große | | | | | |
| Using Constraints for SystemC AMS Design and Verification | Thilo Vörtler, Karsten Einwich, Muhammad Hassan, and Daniel Große | | | | | |
| Using Dependency Injection Design Pattern in Power Aware Tests | Mehmet Tukel, Luca Sasselli, David Guthrie | | | | | |
| Using Formal Applications to Create Pristine IPs | Lee Burns, David Crutchfield, Bob Metzler, and Hithesh Velkooru | | | | | |
| Using Formal Applications to Create Pristine IPs | Lee Burns, David Crutchfield, and Hithesh Velkooru | | | | | |
| Using Formal Techniques to Verify SoC Reset Schemes | Kaowen Liu, Penny Yang, Mark Eslinger, Jeremy Levitt, and Matt Berman | | | | | |
| Using Formal Techniques to Verify System on Chip Reset Schemes | Kaowen Liu, Penny Yang, Jeremy Levitt, Matt Berman, and Mark Eslinger | | | | | |
| Using Formal to Exaustively Determine Unsafe Clock Ratios Between Asynchronous Blocks | Eric Hendrickson, Bill Au, Richard Llaca, and Joe Hupcey III | | | | | |
| Using Formal to Exhaustively Determine Unsafe Clock Ratios Between Asynchronous Blocks | Eric Hendrickson, Bill Au, Richard Llaca, and Joe Hupcey III | | | | | |
| Using Formal to Prevent Deadlocks | Abdelouahab Ayari, Mark Eslinger and Joe Hupcey III | | | | | |
| Using Formal Verification to Exhaustively Verify SoC Assemblies | Mark Handover and Kenny Ranerup | | | | | |
| Using Formal Verification to Exhaustively Verify SoC Assemblies | Kenny Ranerup and Mark Handover | | | | | |
| Using High-level Synthesis and Emulation to Rapidly Develop AI Algorithms in Hardware | John Stickley and Petri Solanti | | | | | |
| Using HLS to improve Design-for-Verification of multi-pipeline designs with resource sharing | Sarmad Dahir, Nils Luetke-Steinhorst, Christian Sauer | | | | | |
| Using IP-XACT IEEE1685-2014 | Prashant Karandikar | | | | | |
| Using Machine Learning in Register Automation and Verification | Nikita Gulliya, Abhishek Bora, Nitin Chaudhary, and Amanjyot Kaur | | | | | |
| Using Machine Learning in Register Automation and Verification | Nikita Gulliya, Abhishek Bora, Nitin Chaudhary, and Amanjyot Kaur | | | | | |
| Using Modal Analysis to Increase Clock Domain Crossing (CDC) Analysis Efficiency and Accuracy | Kurt Takara, Gargi Sharma, Ajay Thadhlani, and Bhrugurajsinh Chudasama | | | | | |
| Using Modal Analysis to Increase Clock Domain Crossing (CDC) Analysis Efficiency and Accuracy | Kurt Takara, Gargi Sharma, Ajay Thadhlani, and Bhrugurajsinh Chudasama | | | | | |
| Using Model Checking to Prove Constraints of Combinational Equivalence Checking | Xiushan Feng, Joseph Gutierrez, Mel Pratt, Mark Eslinger, and Noam Farkash | | | | | |
| Using Mutation Coverage for Advanced Bug Hunting | Vladislav Palfy and Nicolae Tusinschi | | | | | |
| Using Mutation Coverage for Advanced Bug Hunting and Verification Signoff | Nicolae Tusinschi | | | | | |
| Using Open-Source EDA Tools in an Industrial Design Flow | Daniela Sánchez Lopera, Sven Wenzek, Wolfgang Ecker | | | | | |
| Using Open-Source EDA Tools in an Industrial Design Flow | Daniela Sánchez Lopera, Prajwal Kashyap, Nicolas Gerlin, Sven Wenzek, Wolfgang Ecker | | | | | |
| Using Portable Stimulus to Verify an ARMv8 Sub-System SoC Integration | Mike Baird and Aileen Honess | | | | | |
| Using Portable Stimulus to Verify an LTE Base-Station Switch | Adnan Hamid | | | | | |
| Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC | Adnan Hamid and Raja Pantangi | | | | | |
| Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC | Adnan Hamid, David Koogler, and Thomas L. Anderson | | | | | |
| Using PSS-2.0 Hardware-Software Interface to validate 4G/5G Forward Error Correction Encoder/Decoder IP in Emulation & Silicon | Vinit Shenoy, Suresh Vasu, Nithin Venkatesh, Suhas Reddy, Joydeep Maitra | | | | | |
| Using Save/Restore is Easy, Right? A User’s Perspective on Deploying Save/Restore in a Mature Verification Methodology | Ed Powell, Ron Thurgood, and Aneesh Samudrala | | | | | |
| Using Save/Restore is easy, Right?A User’s Perspective on Deploying Save/Restore | Ron Thurgood, Ed Powell, and Aneesh Samudrala | | | | | |
| Using Simulation Acceleration to Achieve 100X Performance Improvement with UVM Based Testbenches | Narla Venkateswara Rao, K Ranjith Kumar, Vikas Verma, Gautam Kumar | | | | | |
| Using Simulation Acceleration to Achieve 100X Performance Improvement with UVM Based Testbenches | Narla Venkateswara Rao, Ranjith Kumar K, Vikas Verma, Gautam Kumar | | | | | |
| Using Software Design Patterns in Testbench Development for a Multi-layer Protocol | Pavan Yeluri, Ranjith Nair | | | | | |
| Using Static RTL Analysis to Accelerate Satellite FPGA Verification | Adam Taylor and Dave Wallace | | | | | |
| Using SystemVerilog “Interfaces” as Object-Oriented RTL Modules | Geoff Barnes | | | | | |
| Using SystemVerilog Interfaces and Structs for RTL Design | Tom Symons and Nihar Shah | | | | | |
| Using SystemVerilog Interfaces and Structs for RTL Design | Tom Symons and Nihar Shah | | | | | |
| Using SystemVerilog Packages in Real Verification Proj | Kaiming Ho | | | | | |
| Using Test-IP Based Verification Techniques in a UVM Environment | Vidya Bellippady, Sundar Haran, and Jay O’Donnell | | | | | |
| Using UPF Information Model APIs to write re-usable Low Power Testbenches and customized coverage models for Low Power | Shreedhar Ramachandra and Himanshu Bhatt | | | | | |
| Using UVM Virtual Sequencers & Virtual Sequences | Clifford E. Cummings and Janick Bergeron | | | | | |
| Using UVM-e Testbenches Utilizing Metric-Driven Verification and Advanced Debug Capabilities | Himanshu Rawal, Vijay Kumar Birange, Daniel Bayer | | | | | |
| Using UVM-ML library to enable reuse of TLM2.0 models in UVM test benches | Sarmad Dahir, Hans-Martin Bluethgen, Rafael Zuralski, Nils Luetke-Steinhorst, and Christian Sauer | | | | | |
| Using UVM-ML library to enable reuse of TLM2.0 models in UVM test benches | Samah Dahir | | | | | |
| Using UVM: The Condensed Guide For Designers, Debuggers, Test-Writers And Other Skeptics | Gordon Allan | | | | | |
| Using UVM: The Condensed Guide For Designers, Debuggers, Test-Writers And Other Skeptics | Gordon Allan | | | | | |
| Utilization of Emulation for accelerating the Functional Verification Closure | Varun Kumar C, Sekhar Dangudubiyyam, Madhukar Ramegowda | | | | | |
| Utilization of RNM to confirm specification consistency between digital analog | Takashi Honda | | | | | |
| Utilizing Technology Implementation Data in blended hardware/software power optimization. | Theodore Wilson and Frank Schirrmeister | | | | | |
| UVM – Stop Hitting Your Brother Coding Guidelines | Rich Edelman and Chris Spear | | | | | |
| UVM – Stop Hitting Your Brother Coding Guidelines | Chris Spear and Rich Edelman | | | | | |
| UVM & Emulation Architecting SystemVerilog UVM Testbenches for Simulation-Emulation Portability to Boost Block-to-System Verification Productivity – Tutorial | Hans van der Schoot and Ellie Burns-Brookens | | | | | |
| UVM & Emulation Creating SystemVerilog & UVM Testbenches for Simulation & Emulation Platform Portability to Boost Block-to-System Verification Productivity | Hans van der Schoot | | | | | |
| UVM Acceleration Using Hardware Emulator at Pre-silicon Stage | Sunil Roe, YunGi Um, Hyunwoo Koh, Hyunsun Ahn, Youngsik Kim, and Seonil Brian Choi | | | | | |
| UVM Acceleration using Hardware Emulator at Pre-silicon Stage | Sunil Roe, YunGi Um, Hyunwoo Koh, Hyunsun Ahn, Youngsik Kim, and Seonil Brian Choi | | | | | |
| UVM and C – Perfect Together | Rich Edelman | | | | | |
| UVM and C – Perfect Together | Rich Edelman | | | | | |
| UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-up | Hans van der Schoot and Ahmed Yehia | | | | | |
| UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-up | Hans van der Schoot and Ahmed Yehia | | | | | |
| UVM and SystemC Transactions – An Update | David Long and John Aynsley | | | | | |
| UVM and SystemC Transactions – An Update | David Long | | | | | |
| UVM and UPF: an application of UPF Information Model | Amit Srivastava, Harsh Chilwal, and Srivatsa Vasudevan | | | | | |
| UVM and UPF: an application of UPF Information Model | Amit Srivastava, Harsh Chilwal, and Srivatsa Vasudevan | | | | | |
| UVM Audit Tutorial Assessing UVM Testbenches to Expose Coding Errors & Improve Quality | Mark Litterick | | | | | |
| UVM Based Approach To Model Validation For SV-RNM Behavioral Models | Donald Lewis and Courtney Fricano | | | | | |
| UVM Based Approach To Model Validation For SV-RNM Behavioral Models | Donald Lewis and Courtney Fricano | | | | | |
| UVM based configurable FSM model for System level verification of DDR5 DIMM High end Server Chipset | Vinoth Kumar Subramani and Gagandeep Singh | | | | | |
| UVM based configurable FSM model for System level verification of DDR5 DIMM High end Server Chipset | Vinoth Kumar Subramani and Gagandeep Singh | | | | | |
| UVM Based Generic Interrupt Handler (UGIH) | Nikhil Singla, Debarati Banerjee | | | | | |
| UVM based Hardware/Software Co- Verification of a HW Coprocessor using Host Execution Techniques | François Cerisier, Christian Rivier, Andrea Battistella, and Arnaud Grasset | | | | | |
| UVM based Hardware/Software Co-Verification of a HW Coprocessor using Host Execution Techniques | François Cerisier, Christian Rivier, Andrea Battistella and Arnaud Grasset | | | | | |
| UVM Based Mixed-Signal Verification of a Display PMIC Designed for OLED Display Applications | Vijay Kumar & Adnan Malik | | | | | |
| UVM Based Mixed-Signal Verification of a Display PMIC Designed for OLED Display Applications | Vijay Kumar & Adnan Malik | | | | | |
| UVM Do’s and Don’ts for Effective Verification | Kathleen Meade and Sharon Rosenberg | | | | | |
| UVM for HLS: An Expedient Approach to the Functional Verification of HLS Designs | Dave Burgoon and Robert Havlik | | | | | |
| UVM for HLS: An Expedient Approach to the Functional Verification of HLS Designs | Dave Burgoon and Robert Havlik | | | | | |
| UVM for RTL Designers | Srinivasan Venkataramanan, Krishna Thottempudi, Praneshsairam A, Mani S | | | | | |
| UVM goesUniversal -IntroducingUVM in SystemC | Stephan Schulz, Thilo Vörtler, and Martin Barnasconi | | | | | |
| UVM hardware assisted acceleration with FPGA co-emulation | Alex Grove | | | | | |
| UVM IEEE Shiny Object | Rich Edelman and Moses Satyasekaran | | | | | |
| UVM IEEE Shiny Object | Rich Edelman | | | | | |
| UVM Interactive Debug Library: Shortening the Debug Turnaround Time | Horace Chan | | | | | |
| UVM Interactive Debug Library: Shortening the Debug Turnaround Time | Horace Chan | | | | | |
| UVM Layering for Protocol Modeling Using State Pattern | Tony George, Girish Gupta, Shim Hojun, and Byung C. Yoo | | | | | |
| UVM Made Language Agnostic – Introducing UVM For SystemC Application of UVM-SystemC | Akhila M | | | | | |
| UVM Made Language Agnostic: Introducing UVM For SystemC | Akhila M | | | | | |
| UVM mixed signal extensionsSharing Best Practice and Standardization Ideas | Joen Westendorp, Sebastian Simon, and Joachim Geishauser | | | | | |
| UVM Random Stability | Avidan Efody | | | | | |
| UVM Rapid Adoption: A Practical Subset of UVM | Stuart Sutherland and Tom Fitzpatrick | | | | | |
| UVM Rapid Adoption: A Practical Subset of UVM | Stuart Sutherland and Tom Fitzpatrick | | | | | |
| UVM Rapid Adoption: A Practical Subset of UVM | Stuart Sutherland and Tom Fitzpatrick | | | | | |
| UVM Reactive Stimulus Techniques | Cliff Cummings, Heath Chambers, and Stephen Donofrio | | | | | |
| UVM Ready: Transitioning Mixed-Signal Verification Environments to Universal Verification Methodology | Arthur Freitas, Régis Santonja | | | | | |
| UVM Ready: Transitioning Mixed-Signal Verification Environments to Universal Verification Methodology | Arthur Freitas, Régis Santonja | | | | | |
| UVM Register Map Dynamic Configuration | Matteo Barbati and Alberto Allara | | | | | |
| UVM Register Map Dynamic Configuration | Matteo Barbati and Alberto Allara | | | | | |
| UVM Register Modelling at the Integration- Level Testbench | Wayne Yun | | | | | |
| UVM Sans UVM An approach to automating UVM testbench writing | Rich Edelman and Shashi Bhutada | | | | | |
| UVM Sans UVM: An approach to automating UVM testbench writing | Rich Edelman and Shashi Bhutada | | | | | |
| UVM SchmooVM – I Want My C Tests! | Rich Edelman and Raghu Ardeishar | | | | | |
| UVM SchmooVM! – I Want My C Tests! | Rich Edelman and Raghu Ardeishar | | | | | |
| UVM Scoreboards and Checkers Memory, TLB and Cache | Rich Edelman, C. H. Liu | | | | | |
| UVM Sequence Layering for Register Sequences | Muneeb Ulla Shariff, Sangeetha Sekar, Ravi Reddy | | | | | |
| UVM Sequence Layering for Register Sequences | Muneeb Ulla Shariff, Sangeetha Sekar, Ravi Reddy | | | | | |
| UVM SystemC Functional coverage & constrained randomization | Stephan Gerth, Dragos Dospinescu, Muhammad Hassan, Thilo Vörtler and Manuel Soto | | | | | |
| UVM Testbench Considerations for Acceleration | Kathleen A Meade | | | | | |
| UVM Testbench Considerations for Acceleration | Kathleen A Meade | | | | | |
| UVM testbench design for ISA functional verification of a microprocessor | Gabriel Wang, Hongtao Ma, and Maoduo Sun | | | | | |
| UVM testbench design for ISA functional verification of a microprocessor | Gabriel Wang, Hongtao Ma, and Maoduo Sun | | | | | |
| UVM Transaction Recording Enhancements | Rex Chen, Bindesh Patel, and Jun Zhao | | | | | |
| UVM Usage for Selective Dynamic Re-configuration of Complex Designs | Kunal Panchal, Pushkar Naik | | | | | |
| UVM Usage for Selective Dynamic Re-configuration of Complex Designs | Kunal Panchal, Pushkar Naik | | | | | |
| UVM Verification Environment Based on Software Design Patterns | D. M. Tomušilović and H. J. Arbel | | | | | |
| UVM Verification Environment Based on Software Design Patterns | Darko M. Tomušilović and Hagai Arbel | | | | | |
| UVM Working Group Releases 1800.2-2020-2.0 Library | Srivatsa Vasudevan, Jamsheed Agahi, Mark Strickland | | | | | |
| uvm_mem – challenges of using UVM infrastructure in a hierarchical verification | Joachim Geishauser, Aditya Chopra, Stephan Ruettiger, Luca Rossi, Sanjay Kakasaniya, L.N. Zhang | | | | | |
| uvm_mem – challenges of using UVM infrastructure in a hierarchical verification | Joachim Geishauser, Aditya Chopra, Stephan Ruettiger, Luca Rossi, Sanjay Kakasaniya, L.N. Zhang | | | | | |
| UVM-based extended Low Power Library package with Low Power Multi-Core Architectures | Avnita Pal, Priyanka Gharat | | | | | |
| UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer | Marcela Zachariasova, Lubos Moravec, John Stickley, Hans van der Schoot, and Shakeel Jeeawoody | | | | | |
| UVM-based verification of a RISC-V Processor Core Using a Golden predictor model and a Configuration Layer | Marcela Zachariasova, Lubos Moravec, John Stickley, Hans van der Schoot, and Shakeel Jeeawoody | | | | | |
| UVM-FM: Reusable Extension Layer for UVM to Simplify Functional Modeling | Ahmed Kamal | | | | | |
| UVM-FM: Reusable Extension Layer for UVMto Simplify Functional Modeling | Ahmed Kamal | | | | | |
| UVM-Light A Subset of UVM for Rapid Adoption | Stuart Sutherland and Tom Fitzpatrick | | | | | |
| UVM-Multi-Language Hands-On | Thorsten Dworzak and Angel Hidalga | | | | | |
| UVM-Multi-Language Hands-On Integrating a System-C model into a SV-UVM testbench | Thorsten Dworzak and Angel Hidalga | | | | | |
| UVM-RAL: Registers on Demand Elimination of the Unnecessary | Sailaja Akkem | | | | | |
| UVM-SV Feedback Loop – The Foundation of Self-Improving Testbenches | Andrei Vintila, Sergiu Duda | | | | | |
| UVM-SV Feedback Loop – The foundation of Self-Improving Testbenches | Andrei Vintila, Sergiu Duda | | | | | |
| UVM-SystemC Applications in the real world | Stephan Schulz, Thilo Vörtler, and Martin Barnasconi | | | | | |
| UVM-SystemC based hardware in the loop simulations for accelerated Co-Verification | Paul Ehrlich, Thang Nguyen, and Thilo Vörtler | | | | | |
| UVM-SystemC based hardware in the loop simulations for accelerated Co-Verification | Paul Ehrlich, Thang Nguyen, and Thilo Vörtler | | | | | |
| UVM-SystemC: Migrating complex verification environments | Stephan Gerth and Akhila Madhukumar | | | | | |
| UVM, VMM and Native SV: Enabling Full Random Verification at System Level | Ashok Chandran | | | | | |
| UVM, VMM and Native SV: Enabling Full Random Verification at System Level | Ashok Chandran | | | | | |
| UVM: Conquering Legacy | Santosh Sarma, Amit Sharma, and Adiel Khan | | | | | |
| UVM’s MAM to the Rescue | Michael Baird | | | | | |
| UVM’s MAM to the Rescue | Michael Baird | | | | | |
| UVM/SystemVerilog based infrastructure and testbench automation using scripts | Prakash Parikh | | | | | |
| UVM/SystemVerilog based infrastructure and testbench automation using scripts | Prakash Parikh | | | | | |
| UX Design & EDA – Enable Collaboration on Functional Coverage using Opens Source Software | Bodo Hoppe, Jamie Lai | | | | | |
| Validation of Timing Constraints on RTL Reducing Risk and Effort on Gate-Level | Peter Limmer, Dirk Moeller, Marcus Mueller and Clemens Roettgermann | | | | | |
| Validation of Timing Constraints on RTL Reducing Risk and Effort on Gate-Level | Peter Limmer, Dirk Moeller, Marcus Mueller, and Clemens Roettgermann | | | | | |
| Veloce HYCON: Software-enabled SoC verification and validation on day 1 | Jeffrey Chen | | | | | |
| Verification 2.0 – Multi Engine, Multi-Run – AI-Driven Verification | Matt Graham | | | | | |
| Verification 2.0 – Multi Engine, Multi-Run AI-Driven Verification | Matt Graham | | | | | |
| Verification 2.0 – Multi-Engine, Multi-Run AI Driven Verification | Matt Graham | | | | | |
| Verification Challenges & Solutions of 10BaseT1s Automotive Ethernet PHY | Harshdeep Verma, Vedansh Seth | | | | | |
| Verification Challenges For Deep Color Mode In HDMI | Snigdha Arora and Apoorva Mathur | | | | | |
| Verification Challenges for Deep Color Mode in HDMI | Snigdha Arora and Apoorva Mathur | | | | | |
| Verification Environment Automation from RTL | Zhidong Chen, Yunyang Song, Wenting Hou, Junna Qiao, Junxia Wang, Ling Bai, and Kei-Wang Yiu | | | | | |
| Verification Environment Automation from RTL | Zhidong Chen, Yunyang Song, Wenting Hou, Junna Qiao, Junxia Wang, Ling Bai, and Kei-Wang Yiu | | | | | |
| Verification IP for Complex Analog and Mixed-Signal Behavior | Thilo Vörtler and Karsten Einwich | | | | | |
| Verification IP for Complex Analog and Mixed-Signal Behavior | Thilo Vörtler and Karsten Einwich | | | | | |
| Verification Learns a New Language: – An IEEE 1800.2 Implementation | Ray Salemi, Tom Fitzpatrick | | | | | |
| Verification Macros: Maintain the integrity of verifiable IP UPF through integration | Amit Srivastava, Shreedhar Ramachandra | | | | | |
| Verification Macros: Maintain the integrity of verifiable IP UPF through integration | Amit Srivastava, Shreedhar Ramachandra | | | | | |
| Verification Methodology for Functional Safety Critical Work Loads | G Prashanth Reddy and Debajyoti Mukherjee | | | | | |
| Verification Methodology for Functional Safety Critical Work Loads | G Prashanth Reddy and Debajyoti Mukherjee | | | | | |
| Verification Mind Games | Jeffrey Montesano and Mark Litterick | | | | | |
| Verification Mind Games | Jeffrey Montesano and Mark Litterick | | | | | |
| Verification of a Multi-language Components A case Study: Specman E Env with SV UVM VIP | Eran Lahav | | | | | |
| Verification of a Multi-language Components A Case Study: Specman E Environment with SystemVerilog UVM | Eran Lahav | | | | | |
| Verification of Accelerators in System Context | Russell A. Klein | | | | | |
| Verification of an Image Processing Mixed-Signal ASIC | Kevin Buescher, Milos Becvar, Greg Tumbush, and David Jenkins | | | | | |
| Verification of Clock Domain Crossing Jitter and Metastability Tolerance using Emulation | Ashish Hari, Suresh Krishnamurthy, Amit Jain, and Yogesh Badaya | | | | | |
| Verification of High-Speed Links through IBIS-AMI Models | Ganesh Rathinavel | | | | | |
| Verification of High-Speed Links through IBIS-AMI Models | Ganesh Rathinavel | | | | | |
| Verification of Inferencing Algorithm Accelerators | Russell Klein, Petri Solanti | | | | | |
| Verification of Inferencing Algorithm Accelerators | Russell Klein, Petri Solanti | | | | | |
| Verification of Inferencing Algorithm Accelerators | Russell Klein, Petri Solanti | | | | | |
| Verification of Virtual Platform Models – What do we Mean with Good Enough? | Jakob Engblom, Ola Dahl | | | | | |
| Verification of Virtual Platform Models – What do we Mean with Good Enough? | Ola Dahl, Jakob Engblom | | | | | |
| Verification Patterns – Taking Reuse to the Next Level | Harry Foster, Michael Horn, Bob Oden, Pradeep Salla, and Hans van der Schoot | | | | | |
| Verification Patterns in the Multicore SoC Domain | Gordon Allan | | | | | |
| Verification Reuse for a Non-Transaction Based Design across Multiple Platforms | Luis Li, Pablo Salazar, and Andrés Cordero | | | | | |
| Verification Reuse Strategy for RTL Quality SoC Functional Virtual Prototypes | Rajesh Kumar Jain, Gaurav Sharma, Marcel Achim, Ashish Mathur, Prateek Sikka | | | | | |
| Verification Strategies and Modelling for the Uninvited Guest in the System: Clock Jitter | Deepak Nagaria, Vikas Makhija, Apoorva Mathur | | | | | |
| Verification strategy for pipeline type of design | Djuro Grubor | | | | | |
| Verification Strategy for Pipeline Type of Design | Djuro Grubor | | | | | |
| Verification Techniques for CPU Simulation Model | Sandeep Jain, Gaurav Sharma | | | | | |
| Verification with multi-core parallel simulations: Have you found your sweet spot yet? | Rohit K Jain and Shobana Sudhakar | | | | | |
| Verification with multi-core parallel simulations: Have you found your sweet spot yet? | Rohit K Jain and Shobana Sudhakar | | | | | |
| Verifying clock-domain crossing at RTL IP level using coverage-driven methodology | Jean-François Vizier, Dennis Ramaekers, and Zheng Hai Zhou | | | | | |
| Verifying Functional, Safety and Security Requirements (for Standards Compliance) | Mike Bartley | | | | | |
| Verifying functionality is simply not enough | Rajesh Bawankule | | | | | |
| Verifying functionality is simply not enough | Rajesh Bawankule | | | | | |
| Verifying Layered Protocols – Leveraging Advanced UVM Capabilities | Parag Goel and Amit Sharma | | | | | |
| Verifying Layered Protocols – Leveraging Advanced UVM Capabilities | Parag Goel | | | | | |
| Verifying Multiple DUV Representations with a Single UVM-e Testbench | Matt Graham | | | | | |
| Verifying Multiple DUV Representations with a Single UVM-e Testbench | Matt Graham | | | | | |
| Verifying RO registers: Challenges and the solution | Ivana Dobrilovic | | | | | |
| Verifying RO registers: Challenges and the solution | Ivana Dobrilovic | | | | | |
| Verifying the I/O peripherals of OpenTitan SOC using the Portable Stimulus Standard | Mahesh R, Bidisha Das, Raj S Mitra, Loganath Ramachandran Ph.D., Viraphol Chaiyakul Ph.D. | | | | | |
| Verifying the I/O peripherals of OpenTitan SOC using the Portable Stimulus Standard | Mahesh R, Bidisha Das, Raj S Mitra, Loganath Ramachandran Ph.D., Viraphol Chaiyakul Ph.D. | | | | | |
| Versatile UVM Scoreboarding | Jacob Andersen, Peter Jensen, and Kevin Steffensen | | | | | |
| Versatile UVM Scoreboarding | Jacob Andersen, Peter Jensen, and Kevin Steffensen | | | | | |
| Versatile UVM Scoreboarding | Jacob Andersen, Peter Jensen, and Kevin Steffensen | | | | | |
| Versatile UVM Scoreboarding | Jacob Andersen, Peter Jensen, and Kevin Steffensen | | | | | |
| Vertical Reuse of functional verification from subsystem to SoC level (with seamless SoC emulation) | Pranav Kumar, Digvijaya Pratap SINGH, and Ankur Jain | | | | | |
| VHDL 2018 New and Noteworthy | Hendrik Eeckhaut and Lieven Lemiengre | | | | | |
| VHDL 2018: New and Noteworthy | L. Lemiengre and H. Eeckhaut | | | | | |
| VIP Shielding | Jeremy Ridgeway and Karishma Dhruv | | | | | |
| VIP Shielding | Jeremy Ridgeway and Karishma Dhruv | | | | | |
| VirtIO based GPU model | Pratik Parvati | | | | | |
| Virtual Platform for a Multi-Chip WLAN System Using a Generic IO Connectivity Scheme | Rajesh Jain, Sandeep Jain | | | | | |
| Virtual Platform for Software Enablement and Hardware Verification | Rajesh Jain, Sandeep Jain, Sumail Singh Brar, Sourav Roy | | | | | |
| Virtual Platforms for Automotive: Use Cases, Benefits and Challenges | Angela Kramer and Martin Vaupel | | | | | |
| Virtual Platforms for complex IP within system context | Rocco Jonack | | | | | |
| Virtual Platforms to Shift-Left Software Development and System Verification | Ross Dickson and Pankaj Kakkar | | | | | |
| Virtual Prototypes and PlatformsA Primer | Eyck Jentzsch, Rocco Jonack, and Josef Eckmüller | | | | | |
| Virtual Prototyping in SpaceFibre System-on-Chip Design | Ilya Korobkov | | | | | |
| Virtual Prototyping in SpaceFibre System-on-Chip Design System-level design | Elena Suvorova | | | | | |
| Virtual Prototyping of Power Converter Systems based on AURIX™ using SystemC AMS | Radovan Vuletic, Dineshkumar Selvaraj, Thomas Arndt | | | | | |
| Virtual Prototyping using SystemC and TLM-2.0 | John Aynsley | | | | | |
| Virtual Sequencers & Virtual Sequences | Clifford E. Cummings and Janick Bergeron | | | | | |
| Virtual Test: Simulating ATE Vectors in a SystemVerilog Testbench for Faster Time to Market | John Mackintosh, Matthew Borto, Cecil Stone, David Brownell, and Courtney Fricano | | | | | |
| Virtual Test: Simulating ATE Vectors in a SystemVerilog Testbench for Faster Time to Market | John Mackintosh, Matthew Borto, Cecil Stone, David Brownell, and Courtney Fricano | | | | | |
| VirtualATE: SystemC support for Automatic Test Equipment | Nitin Garg, Shabarish Sundar, Amaranath Reddy, Sacha Loitz | | | | | |
| Vlang A System Level Verification Perspective | Puneet Goel | | | | | |
| Vlang A System Level Verification Perspective | Puneet Goel | | | | | |
| VP Performance Optimization – How to analyze and optimize the speed of SystemC TLM models? | Rocco Jonack and Juan Lara Ambel | | | | | |
| VP Performance Optimization – How to analyze and optimize the speed of SystemC TLM models? | Rocco Jonack and Juan Lara Ambel | | | | | |
| VP Quality Improvement Methodology | Meghana Moorthy, Melwyn Scudder, Kartik Shah | | | | | |
| Walking the Graph: A Holistic Approach to Graph-based Verification for Logic with Sparse State Space | Sandeep Korrapati, Holger Horbach, Klaus Keuerleber, Alexander Jung | | | | | |
| Want a Boost in your Regression Throughput? Simulate common setup phase only once. | Rohit K Jain and Shobana Sudhakar | | | | | |
| Want a Boost in your Regression Throughput? Simulate common setup phase only once. | Rohit K Jain and Shobana Sudhakar | | | | | |
| Watch Out! Generating Coordinated Random Traffic in UVM | Nigasan Ragunathan, Christine Thomson | | | | | |
| Wave Digital Filter Modeling for Complex Automotive Sensor Load Case Verification | Andrei-Daniel Basa, Thang Nguyen, and Dirk Hammerschmidt | | | | | |
| Wave Digital Filter Modeling for Complex Automotive Sensor Load Case Verification | A. Basa, T. Nguyen, and D. Hammerschmidt | | | | | |
| Weathering the Verification Storm: Methodology Enhancements used on a Next Generation Weather Satellite C&DH Program | Michael Donnelly and Michael Horn | | | | | |
| Weathering the Verification Storm: Methodology Enhancements used on a Next Generation Weather Satellite CDH Program | Michael Horn | | | | | |
| Web Template Mechanisms in SOC Verification | Alberto Allara, Via Tolomeo, Rinaldo Franco, and Via Remo | | | | | |
| Web Template Mechanisms in SOC Verification | Rinaldo Franco and Alberto Allara | | | | | |
| What Does The Sequence Say? Powering Productivity with Polymorphism | Rich Edelman | | | | | |
| What Does The Sequence Say? Powering Productivity with Polymorphism | Rich Edelman | | | | | |
| What Ever Happened to AOP? | James Strober, P.Eng, and Corey Goss | | | | | |
| What Ever Happened to AOP? | James Strober, P.Eng, and Corey Goss | | | | | |
| What I Wish My Regression Run Manager’s Vendor Knew! | David Crutchfield, Brian Craw, Jason Lambirth | | | | | |
| What I Wish My Regression Run Manager’s Vendor Knew! | Brian Craw, David Crutchfield, Jason Lambirth | | | | | |
| What is needed on top of TLM-2 for bigger Systems? | Jerome Cornet and Martin Schnieringer | | | | | |
| What is new in IP-XACT IEEE Std. 1685-2022? | Erwin de Kock, Jean-Michel Fernandez, Devender Khari | | | | | |
| What is new in IP-XACT Std. IEEE 1685-2022? | Erwin de Kock, Jean-Michel Fernandez, Devender Khari | | | | | |
| What is new in IP-XACT Std. IEEE 1685-2022? | Richard Weber, Edwin Dankert | | | | | |
| What is next for SystemC Synthesizable Subset? | Peter Frey | | | | | |
| What Time Is It: Implementing a SystemVerilog Object-Oriented Wrapper for Interacting with the C Library time | Eldon Nelson M.S. P.E. | | | | | |
| What Time Is It: Implementing a SystemVerilog Object-Oriented Wrapper for Interacting with the C Library time | Eldon Nelson M.S. P.E. | | | | | |
| What Your Software Team Would Like the RTL Team to Know. | Josh Rensch | | | | | |
| What-If analysis of Safety Mechanism’s impacts on ETHMAC design under Functional Safety flow | Udaykrishna J, Sujatha Hiremath, Kapil Kumar, Sachin Pathak, Gaurav Goel | | | | | |
| What’s Next for SystemVerilog in the Upcoming IEEE 1800 standard | Dave Rich | | | | | |
| What’s Next for SystemVerilog in the Upcoming IEEE 1800 standard | Dave Rich | | | | | |
| When Last Minute FV Strikes Gold: A Case Study on Finding Starvations & Deadlocks in a Project Nearing Tape-in | Abhishek Potdar, Sachin Kumawat, Sudhanshu Srivastava, Anshul Jain | | | | | |
| When Last Minute FV Strikes Gold: A Case Study on Finding Starvations & Deadlocks in a Project Nearing Tape-in | Abhishek Potdar, Sachin Kumawat, Sudhanshu Srivastava, Anshul Jain | | | | | |
| Where OOP Falls Short of Hardware Verification Needs | Matan Vax | | | | | |
| Who takes the driver seat for ISO 26262 and DO 254 verification? | Avidan Efody | | | | | |
| Who takes the driver seat for ISO 26262 and DO 254 verification? | Avidan Efody | | | | | |
| Who’s Watching the Watchmen? The Time has Come to Objectively Measure the Quality of Your Verification | David Brownell | | | | | |
| Who’s Watching the Watchmen? The Time has Come to Objectively Measure the Quality of Your Verification Environment | David Brownell | | | | | |
| Whose Fault Is It Formally? Formal Techniques for Optimizing ISO 26262 Fault Analysis. | Ping Yeung, Doug Smith, and Abdelouahab Ayari | | | | | |
| Whose Fault Is It Formally? Formal Techniques for Optimizing ISO 26262 Fault Analysis. | Ping Yeung, Doug Smith, and Abdelouahab Ayari | | | | | |
| Whose fault is it? Advanced techniques for optimizing ISO 26262 fault analysis | Avidan Efody | | | | | |
| Whose fault is it? Advanced techniques for optimizing ISO 26262 fault analysis | Avidan Efody | | | | | |
| Why Not “Connect” Using UVM Connect: Mixed Language Communication Got Easier with UVMC | Vishal Baskar | | | | | |
| Why Not “Connect” Using UVM Connect: Mixed Language Communication Got Easier with UVMC | Vishal Baskar | | | | | |
| Wiretap your SoC | Avidan Efody | | | | | |
| Wiretap your SoC: Why scattering Verification IPs throughout your design is a smart thing to do | Avidan Efody | | | | | |
| With Great Power Comes Great Responsibility A method to verify PMICs with UVM-MS | Dor Spigel and Moshik Hershcovitch | | | | | |
| With great power comes great responsibility: A method to verify PMICs using UVM-MS | Dor Spigel and Moshik Hershcovitch | | | | | |
| Wrapping Verilog Bus Functional Model (BFM) and RTL as Drivers in Customized UVM VIP Using Abstract Classes | Roman Wang and Thomas Bodmer | | | | | |
| Wrapping Verilog Bus Functional Model (BFM) and RTL as Drivers in Customized UVM VIP Using Abstract Classes | Roman Wang and Thomas Bodmer | | | | | |
| Wrong clamps can kill your chip!!….find them early | Akhil Arora, Rajiv Kumar, Sonik Sachdeva | | | | | |
| Wrong clamps can kill your chip!!….find them early | Akhil Arora, Rajiv Kumar, Sonik Sachdeva | | | | | |
| Wrong FPGA Low Power measures that people with ASIC design experience tend to fall into and the correct method paper | Junichi Chonan | | | | | |
| Wrong FPGA Low Power measures that people with ASIC design experience tend to fall into and the correct method paper | Junichi Chonan | | | | | |
| X-Propagation Woes: Masking Bugs at RTL and Unnecessary Debug at the Netlist | Lisa Piper and Vishnu Vimjam | | | | | |
| X-propagation Woes: Masking Bugs at RTL and Unnecessary Debug at the Netlist | Lisa Piper | | | | | |
| XploR, a Platform to Accelerate Silicon Transformation | | | | | | |
| YAMM Yet Another Memory Manager | Andrei Vintila, Ionut Tolea, and Teodor Vasilache | | | | | |
| YAMMYet Another Memory Manager | Andrei Vintila and Ionut Tolea | | | | | |
| Yet Another Memory Manager (YAMM) | Ionut Tolea and Andrei Vintila | | | | | |
| Yet Another Memory Manager (YAMM) | Ionut Tolea, Andrei Vintila, and Cosmin-Teodor Vasilache | | | | | |
| Yikes! Why is My SystemVerilog Still So Slooooow? | Cliff Cummings, John Rose, and Adam Sherer | | | | | |
| Yikes! Why is My SystemVerilog Testbench So Slooooow? | Frank Kampf | | | | | |
| Yikes! Why is my SystemVerilog Testbench So Slooooow? | Justin Sprague | | | | | |
| You Are In a Maze of Twisty Little Sequences, All Alike – or Layering Sequences for Stimulus Abstraction | Rich Edelman, Adam Rose, Andreas Meyer, Raghu Ardeishar, and Jason Polychronopoulos | | | | | |
