DVCon: Document Library

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TitleAuthor(s)YearTypeLinkhf:tax:event_yearhf:tax:document_type
“Bounded Proof” sign-off with formal coverageAbhishek Anand, Chinyu Chen, Bathri Narayanan Subramanian, Joe Hupcey2021Papery2021paper
“C” you on the faster side: Accelerating SV DPI based co-simulationParag Goel, Amit Sharma, and Hari Vinodh Balisetty2014Papery2014paper
“C” you on the faster side: Accelerating SV DPI based co-simulationHari Vinod Balisetty, Parag Goel, and Amit Sharma2014Presentationy2014presentation
“In-Emulator” UVM++ Randomized Testbenches for High Performance Functional VerificationAdnan Hamid and David Kelf2022Presentationy2022presentation
“Shift left” Hierarchical Low-Power Static Verification Using SAMBharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal2020Papery2020paper
“Shift left” Hierarchical Low-Power Static Verification Using SAMBharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal2020Postery2020poster
“What-If” analysis of Safety Mechanism’s impacts on ETHMAC design under Functional Safety flowUdaykrishna J, Sujatha Hiremath, Kapil Kumar, Sachin Pathak, Gaurav Goel2022Presentationy2022presentation
1,2,3,…8 simple steps towards a single digital signal processing testbench supporting heterogeneous interfaces and datatypesNico Lugil2016Papery2016paper
1,2,3,…8 simple steps towards a single digital signal processing testbench supporting heterogeneous interfaces and datatypesNico Lugil2016Presentationy2016presentation
400G IPU Case Study: Demonstrating Shift-left of Soft Logic RTL Development on Real World Design using Intel Agilex FPGA SystemC ModelPravat K Nayak, Vikrant Kapila, Pushpa Naik & Niketkumar Sharma2023Papery2023paper
5.1 Smart Verification leveraging PSS; 5.2 When Automotive FuSa Met ICDavid Hwang and Sera Gao2021Presentationy2021presentation
5G – Chances and Challenges from Test & Measurement PerspectiveMeik Kottkamp2017Presentationy2017presentation
5G / NR Explained From 3GPP 5G Standard Fundamentals To 5G Enabled VerticalsMichael Faerber and Kilian Roth2019Presentationy2019presentation
5G for people and things Spectrum Opportunities and Challenges of 5G 2017Presentationy2017presentation
A 30 Minute Project Makeover Using Continuous IntegrationJL Gray and Gordon McGregor2012Presentationy2012presentation
A 30 Minute Project Makeover Using Continuous IntegrationJL Gray2012Papery2012paper
A 360 Degree View of UVM EventsVikas Billa, Nagesh Kokonda2017Presentationy2017presentation
A 360 Degree View of UVM Events – A Case StudyDeepak Kumar E V, Sathish Dadi, and Vikas Billa2016Papery2016paper
A 360 Degree View of UVM Events (A Case Study)Deepak Kumar E V, Sathish Dadi, and Vikas Billa2016Presentationy2016presentation
A Client-Server Method for Register Design and DocumentationScott D Orangio and Julien Gagnon2016Papery2016paper
A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISC V CoreJunaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, Aashir Ahsan2022Presentationy2022presentation
A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISCV CoreJunaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, and Aashir Ahsan2022Papery2022paper
A comparison of methodologies to simulate mixed-signal ICSimone Fontanesi, Karsten Einwich, Paul Ehrlich, Gaetano Formato, Andrea Possemato2021Papery2021paper
A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance AnalysisBishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel2016Postery2016poster
A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance Analysis.Bishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel2016Papery2016paper
A Compositional Simulation Framework for Testing Adversarial Robustness of Deep Neural NetworksYoussef Maher Nader, Mostafa Lotfy Hatab, Mazen Mostafa Ghaleb, Safia Medhat Bakr, Tasneem A. Awaad, Ahmed AlGanzouri, Mohamed Abdelsalam, and M. Watheq El-Kharashi2023Papery2023paper
A Compositional Simulation Framework for Testing Adversarial Robustness of Deep Neural NetworksYoussef Maher Nader; Mostafa Lotfy Hatab; Mazen Mostafa Ghaleb; Safia Medhat Bakr; Tasneem A. Awaad; Ahmed AlGanzouri; Mohamed Abdelsalam; M. Watheq El-Kharashi2023Papery2023paper
A Comprehensive Verification Platform for RISC-V based ProcessorsEmre Karabulut, Berk Kisinbay, Abdullah Yildiz and Rifat Demircioglu2020Papery2020paper
A Comprehensive Verification Platform for RISC-V based ProcessorsEmre Karabulut, Berk Kisinbay, Abdullah Yildiz, and Rifat Demircioglu 2020Presentationy2020presentation
A concept for expanding a UVM testbench to the analog-centric toplevelFelix Assmann, Axel Strobel and Hans Zander2015Papery2015paper
A concept for expanding a UVM testbenchto the analog-centric toplevelFelix Assmann, Axel Strobel and Hans Zander2015Postery2015poster
A Coverage-Driven Formal Methodology for Verification Sign-offAng Li, Hao Chen, Jason K Yu, Ee Loon Teoh, and Iswerya Prem Anand2019Papery2019paper
A Coverage-Driven Formal Methodology for Verification Sign-offAng Li, Hao Chen, Jason K Yu, Ee Loon Teoh and, Iswerya Prem Anand2019Presentationy2019presentation
A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMSMuhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, Daniel Große2022Papery2022paper
A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMSMuhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, Daniel Große2022Presentationy2022presentation
A Dyadic Transformation Based Methodology To Achieve Coverage Driven Verification GoalSwapnajit Mitra2017Presentationy2017presentation
A Dyadic Transformation Based Methodology to Achieve Coverage Driven Verification GoalSwapnajit Mitra2017Papery2017paper
A Dynamic Approach Towards Register Coverage Generation and Collection to Reduce Compilation Overhead of Traditional UVM Register LayersSubham Banerjee2020Presentationy2020presentation
A Faster and Efficient Timing Constraint Verification Methodology for GFX SOCsVineeth B, Deepmala Sachan2023Presentationy2023presentation
A Faster and Efficient Timing Constraint Verification Methodology for GFX SOCsVineeth B, Deepmala Sachan2023Papery2023paper
A Formal Verification App Towards Efficient Chip-Wide Clock Gating VerificationProsenjit Chatterjee, Scott Fields, and Syed Suhaib2014Presentationy2014presentation
A Formal Verification App Towards Efficient, Chip-Wide Clock Gating VerificationProsenjit Chatterjee, Scott Fields, and Syed Suhaib2014Papery2014paper
A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog-AMSMike Bartley and Jeganath Gandhi R2014Papery2014paper
A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog-AMSMike Bartley, Jeganath Gandhi R2014Papery2014paper
A Framework for the Execution of Python Tests in SystemC and Specman TestbenchesChristoph Tietz, Sebastian Stieber , Najdet Charaf, Diana Göhringer2022Papery2022paper
A Framework for the Execution of Python Tests in SystemC and Specman TestbenchesChristoph Tietz, Sebastian Stieber, Najdet Charaf, Diana Göhringer2022Presentationy2022presentation
A Framework for Verification of Program Control Unit of VLIW processorsSanthosh Billava, Sharangdhar M Honwadkar2014Presentationy2014presentation
A Framework for Verification of Program Control Unit of VLIW ProcessorsSanthosh Billava, Sharangdhar M Honwadkar2014Papery2014paper
A Generic Approach to Handling Sideband SignalsMarkus Brosch and Salman Tanvir2019Presentationy2019presentation
A Generic Configurable Error Injection Agent for On-Chip MemoriesNiharika Sachdeva, Arjun Suresh Kumar, Damandeep Saini, Anil Deshpande, Ravi Teja Gopagiri, Somasunder KS, Jaechul Park2022Papery2022paper
A Generic Configurable Error Injection Agent for All On-Chip MemoriesNiharika Sachdeva, Arjun Suresh Kumar, Raviteja Gopagiri, Anil Deshpande, Somasunder Kattepura Sreenath, Damandeep Saini2022Presentationy2022presentation
A Generic Configurable Error Injection Agent for All On-Chip MemoriesAnil Deshpande, Jaechul Park, Niharika Sachdeva, Arjun Suresh Kumar, Raviteja Gopagiri, Somasund Kattepura Sreenath, Damandeep Saini2022Presentationy2022presentation
A Generic Configurable Error Injection Agent for On-Chip MemoriesNiharika Sachdeva, Arjun Suresh Kumar, Raviteja Gopagiri, Anil Deshpande, Somasunder Kattepura Sreenath2022Papery2022paper
A Generic Verification Methodology for Chip to Chip Interrupt Handling in a Multi-Chip SoC (3DIC)Vignesh Adiththan, Padma Vutukuru, Lalithraj Mailappa, Sekhar Dangudubiyyam2023Presentationy2023presentation
A Generic Verification Methodology for Chip to Chip Interrupt Handling in a Multi-Chip SoC (3DIC)Vignesh Adiththan, Padma Vutukuru, Lalithraj Mailappa, Sekhar Dangudubiyyam2023Papery2023paper
A Guide To Using Continuous Integration Within The Verification EnvironmentJason Sprott2014Presentationy2014presentation
A Guide To Using Continuous Integration Within The Verification EnvironmentJason Sprott, André Winkelmann, and Gordon McGregor2014Papery2014paper
A Guide To Using Continuous Integration Within The Verification EnvironmentAndré Winkelmann, Jason Sprott, and Gordon McGregor2014Postery2014poster
A Hardware and Software integrated power optimization approach with power aware simulations at SOCEldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2023Papery2023paper
A Hardware and Software Integrated Power Optimization Approach with Power Aware Simulations at SOCEldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2023Postery2023poster
A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power IntentVijay Kumar Sankaran, Lakshmanan Balasubramanian, Bharath Kumar Poluri, Venkatraman Ramakrishnan, Badrinarayan Zanwar, and Qingyu Lin2016Papery2016paper
A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power IntentQingyu Lin2016Postery2016poster
A Holistic Overview on Preventive & Corrective Action To Handle GlitchesRohit Kumar Sinha, Parimal Das2022Postery2022poster
A Holistic View of Mixed-Language IP IntegrationPankaj Singh and Gaurav Kumar Verma2010Papery2010paper
A Hybrid Approach For Interrupts VerificationGiovanni Auditore, Francesco Rua’, Qibo Peng2023Presentationy2023presentation
A Hybrid Approach To Interrupt VerificationGiovanni Auditore, Francesco Rua’, Qibo Peng2023Papery2023paper
A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGAAntonis Papagrigoriou, Miltos D. Grammatikakis and Voula Piperaki2018Presentationy2018presentation
A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGA*Antonis Papagrigoriou, Antonis Papagrigoriou and Voula Piperaki2018Papery2018paper
A Hybrid Verification Solution to RISC V Vector ExtensionChenghuan Li, Yanhua Feng, Liam Li2022Presentationy2022presentation
A Hybrid Verification Solution to RISC-V Vector ExtensionChenghuan Li, Yanhua Feng, and Liam Li2022Papery2022paper
A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance CorrelationThomas Soong, Christopher Browne, and Chenhui Huang2022Postery2022poster
A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance CorrelationThomas Soong, Chenhui Huang, and Christopher Browne2022Papery2022paper
A Meta-Model-Based Approach for Semantic Fault Modeling on Multiple Abstraction LevelsMichael Schwarz and Moomen Chaari, Bogdan-Andrei Tabacaru2015Papery2015paper
A Meta-Model-Based Approach for Semantic Fault Modeling on Multiple Abstraction LevelsM. Schwarz M. Chaari, B.-A. Tabacaru, and W. Ecker2015Presentationy2015presentation
A Meta-Modeling-Based Approach for Automatic Generation of Fault-Injection ProcessesBogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, and Thomas Kruse2014Papery2014paper
A Meta-Modeling-Based Approach for Automatic Generation of Fault-Injection ProcessesB.-A. Tabacaru, M. Chaari, W. Ecker, and T. Kruse2014Presentationy2014presentation
A Method to Accelerate SoC Implementation Cycle by Automatically Generating CDC ConstraintsAshish Hari, Sulabh Kumar Khare2015Presentationy2015presentation
A Methodology for Evaluating SI Artefacts in DDR4-3DS PHY using Channel ModellingAditya S Kumar, Gowdra Bomanna Chethan, Shivani Maurya, Anil Deshpande, Somasunder Kattepura Sreenath2021Papery2021paper
A Methodology for Interrupt Analysis in Virtual PlatformsPuneet Dhar2015Presentationy2015presentation
A Methodology for Power and Energy Efficient Systems DesignMohammed Fahad2023Presentationy2023presentation
A Methodology for Using Traffic Generators with Real-Time ConstraintsAvinash Mehta2015Presentationy2015presentation
A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation AccelerationHorace Chan, Brian Vandegriend, and Efrat Shneydor2015Presentationy2015presentation
A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation AccelerationHorace Chan, Brian Vandegriend, and Efrat Shneydor2015Papery2015paper
A Methodology to Reuse Unit Level Validation InfrastructureAshutosh Parkhi2017Presentationy2017presentation
A Methodology to Verify Functionality, Security, and Trust for RISC-V CoresW. W. Chen, N. Tusinschi and T. L. Anderson2020Papery2020paper
A Methodology to Verify Functionality, Security, and Trust for RISC-V CoresW. W. Chen, N. Tusinschi, and T. L. Anderson2020Presentationy2020presentation
A Metric-driven Methodology For Firmware Verification In Simulation/Emulation EnvironmentsGoran Savić2016Papery2016paper
A Mixed Signal System Design Methodology in SystemC AMS for Automotive Audio Power AmplifiersSkule Pramm, Joen Westendorp, and Quino Sandifort2019Papery2019paper
A Model-Based Reusable Framework to Parallelize Hardware and Software DevelopmentJouni Sillanpää, Håkan Pettersson & Tom Richter2023Papery2023paper
A Mutually-Exclusive Deployment of Formal and Simulation Techniques Using Proof-Core AnalysisKeerthikumara Devarajegowda, Jeroen Vliegen, Goran Petrovity, and Kawe Fotouhi2017Presentationy2017presentation
A Mutually-Exclusive Deployment of Formal and Simulation Techniques Using Proof-Core AnalysisKeerthikumara Devarajegowda, Jeroen Vliegen, Goran Petrovity, and Kawe Fotouhi2017Papery2017paper
A New Approach for Generating View GeneratorsJohannes Schreiner, Felix Willgerodt, and Wolfgang Ecker2017Papery2017paper
A New Approach for Generating View GeneratorsJohannes Schreiner, Felix Willgerodt, and Wolfgang Ecker2017Postery2017poster
A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain CrossingsOmri Dassa and Yossi (Joseph) Mirsky2022Papery2022paper
A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain CrossingsOmri Dassa, Yossi Mirsky2022Presentationy2022presentation
A New Approach to Low-Power Verification: Low Power AppsMadhur Bhargava and Awashesh Kumar2018Papery2018paper
A New Class Of RegistersM. Peryer and D. Aerne2016Papery2016paper
A New Class Of RegistersMark Peryer and David Aerne2016Postery2016poster
A New Epoch is Beginning: Are You Getting Ready for Stepping Into UVM-1.2?Roman Wang,Uwe Simm2014Papery2014paper
A New Epoch is Beginning: Are You Getting Ready for Stepping Into UVM-1.2?Roman Wang, Uwe Simm2014Postery2014poster
A NOVEL AND EFFICIENT METHODOLOGY TO EXPEDITE COMPLEX SOC DV CLOSURE BY LEVERAGING MODULARLY ARCHITECTURED SCALABLE ENVIRONMENTVinay Swargam, Guttapalem Yatisha, Ayush Agrawal, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Papery2022paper
A Novel Approach to Accelerate Latency of Assertion SimulationJack Yen, Felix Tung2023Papery2023paper
A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM DomainsSubham Banerjee and Keshava Krishna Raja2017Papery2017paper
A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM Domains 2017Postery2017poster
A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoCHarshal Kothari, Manishadevi Satyanarayana Cheernam, Vignesh Adiththan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath2022Papery2022paper
A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoCHarshal Kothari, Manishadevi Satyanarayana Cheernam, Vignesh Adiththan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath2022Postery2022poster
A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoCHarshal Kothari, Manishadevi Satyanarayana Cheernam, Vignesh Adiththan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath2022Presentationy2022presentation
A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform DevelopmentHarshal Kothari, Vinay Swargam, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Papery2022paper
A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform DevelopmentHarshal Kothari, Vinay Swargam, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Postery2022poster
A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform DevelopmentHarshal Kothari, Vinay Swargam, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Presentationy2022presentation
A Novel Approach to Functional Test Development and Execution using High-Speed IOMarcus Schulze Westenhorst, Jörg Simon, Markus Bücker, Klaus Dieter Hilliges, Michael Braun2021Papery2021paper
A NOVEL APPROACH TO HARDWARE CONTROLLED POWER AWARE VERIFICATION WITH OPTIMISED POWER CONSUMPTION TECHNIQUES AT SOCEldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Presentationy2022presentation
A NOVEL APPROACH TO HARDWARE CONTROLLED POWER AWARE VERIFICATION WITH OPTIMISED POWER CONSUMPTION TECHNIQUES AT SOCEldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Papery2022paper
A Novel Approach to Hardware Controlled Power Aware Verification with Optimized Power Consumption Techniques at SOCEldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Papery2022paper
A Novel Approach To In-System SRAM Repair Verification in Embedded SoC to Bridge Gap between Test and Functional ModeHarshal Kothari, Eldin Ben Jacob, Ajay Vamshi Krishna, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath2021Papery2021paper
A Novel Approach to Reduce Power Consumption By Bridging The Gap between Standalone Functional Scenario and Real Time Scenario at SOCEldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Postery2022poster
A Novel Approach to Reuse Firmware for Verification of Controller based Sub-Systems using PSSVishnu Ramadas, Simranjit Singh, Ashwani Aggarwal, Woojoo Space Kim , Seonil Brian Choi2021Papery2021paper
A novel approach to standardize reusable Modular Plug and Play Skeleton Structure (MPPSS) to expedite verification closureHimanshu Dixit, Chandrachud Murali, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Papery2022paper
A novel approach to standardize reusable Modular Plug and Play Skeleton Structure (MPPSS) to expedite verification closureChandrachud Murali, Himanshu Dixit, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Postery2022poster
A Novel Approach to Standardize Verification Configurations using YAMLNikhil Tambekar2023Papery2023paper
A Novel Approach to Standardize Verification Configurations using YAMLNikhil Tambekar2023Presentationy2023presentation
A Novel Approach to Verify CNN Based Image Processing UnitSumit K. Kulshreshtha, Raghavendra J N2021Papery2021paper
A Novel Framework to Accelerate System Validation on EmulationManoj Sharma Khandelwal, Rinkesh Yadav, Sarang Kalbande & Garima Srivastav2023Papery2023paper
A Novel Performance Evaluation Methodology using Virtual Prototyping and EmulationWoojooSpace Kim2019Presentationy2019presentation
A Novel Performance Evaluation Methodology using Virtual Prototyping and EmulationWoojoo Space Kim2018Presentationy2018presentation
A Novel Processor Verification Methodology based on UVMAbhineet Bhojak, Tejbal Prasad, and Stephan Herrmann2015Papery2015paper
A Novel Variation-Aware Mixed-Signal Verification Methodology to achieve High-Sigma Variation coverage at nanometer designsTibi Galambos, Sumit Vishwakarma2021Papery2021paper
A perfect blend of verification techniques, platforms, and AI-empowered debugging in Ethernet Subsystem VerificationOlivera Stojanovic & Tijana Misic2023Papery2023paper
A Practical Approach to Measuring and Improving the Functional Verification of Embedded SoftwareStéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès2012Papery2012paper
A Practical Approach to Measuring and Improving the Functional Verification of Embedded SoftwareStéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès2012Presentationy2012presentation
A Practical Look @ SystemVerilog Coverage – Tips, Tricks, and GotchasDoug Smith and John Aynsley2011Papery2011paper
A Pragmatic Approach Leveraging Portable Stimulus from Subsystem to SoC level and SoC EmulationKarandeep Singh, Aditya Chopra, Joachim Geishauser, Nitin Verma2019Presentationy2019presentation
A Pragmatic Approach Leveraging Portable Stimulus from Subsystem to SoC level and SoC EmulationKarandeep Singh, Aditya Chopra, Joachim Geishauser, Nitin Verma2019Papery2019paper
A Pragmatic Approach to Metastability-Aware SimulationJoseph Bulone, Roger Sabbagh2014Papery2014paper
A Pragmatic Approach to Metastability-Aware SimulationJoseph Bulone, Roger Sabbagh2014Presentationy2014presentation
A real world application of IP-XACT for IP packaging Bridging the usability gapPhilip Todd2014Papery2014paper
A real world application of IP-XACT for IP packaging Bridging the usability gapPhilip Todd2014Presentationy2014presentation
A Real-World Clock Generator Class for UVMRhitam Datta, Ankit Somani2017Presentationy2017presentation
A Recipe for swift Tape-out of Derivative SoCs: A Comprehensive Validation Approach using Formal-based Sequential Equivalence and Connectivity CheckingPriyanshu Jain, Saket Gaddagi, Sandeep Kumar and Ipshita Tripathi2022Presentationy2022presentation
A Reconfigurable And Fully Automated SRAM Environment Generation Flow for Robust Verification And To Accelerate DV ClosureVinay Swargam, Lakshmana Kumar Arumugasamy, Sriram Kazhiyur Sounderrajan2023Postery2023poster
A Reconfigurable Interface Architecture to Protect System IPArshad Riazuddin, Shoab A. Khan2022Papery2022paper
A Reconfigurable Interface Architecture to Protect System IPArshad Riazuddin, Shoab A. Khan2022Presentationy2022presentation
A Reusability Combat in UVM Callbacks vs FactoryDeepak Kumar EV, Vikas Billa, Satish Dadi, Ranganath Kempanahally2015Postery2015poster
A Reusable, Scalable Formal App for Verifying Any Configuration of 3D IC ConnectivityDaniel Han, Walter Sze, Benjamin Ting, and Darrow Chu2013Papery2013paper
A scalable framework to validate interconnect-based firewalls to enhance SoC security coverageAshutosh Mishra, Suresh Vasu2022Presentationy2022presentation
A scalable framework to validate interconnect-based firewalls to enhance SoC security coverageAshutosh Mishra, Suresh Vasu2022Papery2022paper
A scalable VIP component to increase robustness of co-verification within an ASICMario de Matteis, Matteo Barbati2023Presentationy2023presentation
A scalableVIP component to increase robustness of co-verification within an ASICMario de Matteis & Matteo Barbati2023Papery2023paper
A Semi-Formal Verification Methodology for Efficient Configuration Coverage of Highly Configurable Digital DesignsAman Kumar, Sebastian Simon2021Papery2021paper
A Shift-left Methodology for an Early Power Closure Using EDCs and Power AnalysisMohammed Fahad2022Presentationy2022presentation
A shift-left Methodology for an early power closure using PowerProMohammed Fahad2022Papery2022paper
A Simplified Approach Using UVM Sequence Items for Layering Protocol VerificationChristine Thomson and Haiqian Yu2017Presentationy2017presentation
A Simplified Approach Using UVM Sequence Items for Layering Protocol VerificationHaiqian Yu and Christine Thomson2017Papery2017paper
A Simulation Expert’s Guide to Formally Proving SW Status and InterruptsNeil Johnson2023Presentationy2023presentation
A Simulation Expert’s Guide to Formally Verifying Software Status and InterruptsNeil Johnson2023Papery2023paper
A single generated UVM Register Model to handle multiple DUT configurationsSalvatore Marco Rosselli and Giuseppe Falconeri2020Presentationy2020presentation
A SMART GENERATION OF DESIGN ATTRIBUTES FOR VERIFICATION CLOSURE USING SPECMANMeirav Nitzan, Yael Kinderman, and Efrat Gavish2013Postery2013poster
A Smart Synchronizer – Pragmatic way to cross asynchronous clock domainsPriyank Parakh and Steven J Kommrusch2011Papery2011paper
A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing LogicPriya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed2018Papery2018paper
A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing LogicPriya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed2018Postery2018poster
A Step Towards Zero Silicon Bugs Using Assertion Based Assumption ValidationRohit Kumar Sinha and Babu Christie2020Papery2020paper
A Step towards Zero Silicon Bugs: SVA Protocol Based Assumption ValidationRohit Kumar Sinha and Babu Christie2020Poster, Presentationy2020poster presentation
A streamlined approach to validate FP matrix multiplication with formalGerardo Nahum, Nicolae Tusinschi, Seiya Nakagawa2023Presentationy2023presentation
A Structured Approach to verify Ties, Unconnected Signals and ParametersSaurabh Singh, Peter Limmer, and Thomas Luedeke2016Presentationy2016presentation
A Structured Approach to verify Ties, Unconnected Signals and ParametersSaurabh Singh, Peter Limmer, and Thomas Luedeke2016Papery2016paper
A Study on Virtual Prototyping based Design Verification MethodologyWoojoo Kim, Kunhyuk Kang, Seonil Brian Choi2023Postery2023poster
A Study on Virtual Prototyping based Design Verification MethodologyWoojoo Kim, Kunhyuk Kang, and Seonil Brian Choi.2023Papery2023paper
A Survey of Machine Learning Applications in Functional VerificationDan Yu, Harry Foster, Tom Fitzpatrick2023Papery2023paper
A Systematic Approach to Power State Table (PST) DebuggingBhaskar Pal2013Presentationy2013presentation
A Systematic Approach to Power State Table (PST) DebuggingBhaskar Pal, Suman Nandan, Kaushik De, and Rajarshi Mukherjee2013Papery2013paper
A Systematic Formal Reuse Methodology: From Blocks to SoC SystemsHao Chen, Yi Sun, Ang Li, and Dorry Cao2020Presentationy2020presentation
A Systematic Methodology for Verifying Clock Domain Crossing ReconvergencePriya Viswanathan2017Presentationy2017presentation
A Systematic Take on Addressing Dynamic CDC Verification ChallengesSukriti Bisht, Sulabh Kumar Khare, and Ashish Hari2019Papery2019paper
A Systematic Take on Addressing Dynamic CDC Verification ChallengesSukriti Bisht, Sulabh Kumar Khare, and Ashish Hari2019Presentationy2019presentation
A SystemC Library for Advanced TLM VerificationMarcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen2012Papery2012paper
A SystemC Library for Advanced Verification – Towards an Enhanced OVM/UVM for SystemCMarcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen2012Presentationy2012presentation
A SystemC-based UVM verification infrastructureMike Bartley and Harshavardhan Narla2015Papery2015paper
A SystemC-based UVM verification infrastructureMike Bartley and Harshavardhan Narla2015Postery2015poster
A SystemVerilog Framework for Easy Method Advice in Object-oriented Test BenchesEric Ohana2013Papery2013paper
A SystemVerilog Framework for Easy Method Advice in Object-oriented Test BenchesEric Ohana2013Postery2013poster
A SystemVerilog Framework for Efficient Randomization of Images with Complex Inter-Pixel DependenciesAxel Voss, Gabriel Jönsson, and Lars Viklund2020Presentationy2020presentation
A Tale of Two Languages – SystemVerilog and SystemCDavid C Black2013Papery2013paper
A Tale of Two Languages: SystemVerilog & SystemCDavid C Black2013Presentationy2013presentation
A Tool for Investigating Cyber-Physical Systems via SystemC AMS Virtual Prototypes Derived from SysML ModelsDaniela Genius; Ludovic Apvrille2023Papery2023paper
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A UVM Based Methodology for Processor VerificationAbhineet Bhojak, Tejbal Prasad2015Presentationy2015presentation
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A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline ReceiversJaeha Kim2023Presentationy2023presentation
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Absolute GLS Verification An Early Simulation of Design Timing ConstraintsAteet Mishra, Deepak Mahajan, Shiva Belwal2015Presentationy2015presentation
Abstract Layer for Firmware Access: A Unique Approach for SOC Functional VerificationGupta Girish Kumar, Rugmini Navia Vishnu, Choudhary Praval, Syed Mobeenuddin2021Papery2021paper
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Accelerated Coverage Closure by Utilizing Local Structure in the RTL CodeRhys Buggy, Gokce Sarar, Guillaume Shippee, Han Nuou, Vishal Karna, Tushit Jain2021Papery2021paper
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Accelerated SOC verification Using UVM Methodology for a Mix-signal Low Power DesignGiuseppe Scata, Ashwini Padoor, Vladimir Milosevic2014Papery2014paper
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Accelerated, High Quality SoC Memory Map Verification using Formal TechniquesCletan Sequeira, Rajesh Kedia, Lokesh Babu Pundreeka, and Bijitendra Mittra2014Papery2014paper
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Accelerating CDC Verification Closure on Gate-Level DesignsAnwesha Choudhury and Ashish Hari2017Presentationy2017presentation
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Accelerating Functional Verification Through Stabilization of Testbench Using AI/MLSrikanth Vadanaparthi, Pooja Ganesh, Dharmesh Mahay, Malay Ganai2023Papery2023paper
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Accelerating Functional Verification Coverage Data Manipulation Using Map ReduceEman El Mandouh, A. Gamal, A. Khaled, T. Ibrahim, Amr G. Wassal, Elsayed Hemayed2017Papery2017paper
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Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing ProductsYoga Priya Vadivelu, Arpan Shah, Deepinder Singh Mohoora, Ullas, and Praveen Buddireddy2022Papery2022paper
Accelerating RTL Simulation TechniquesLior Grinzaig2015Papery2015paper
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Accelerating Semiconductor Time to ISO 26262 ComplianceKirankumar Karanam2022Presentationy2022presentation
Accelerating SoC Sensor Network Verification Sign-off through Dynamic and Formal SynergyVinod Usha, Shreeram Hegde, Prasad Reddy2023Postery2023poster
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Accelerating SoC Verification Signoff using Save & Restart/Dynamic Test Reload Enhanced Regression flowVanshlata B, Divya M, Garima S, Seonil Brian Choi2021Papery2021paper
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Accelerating the IP Design Cycle with Formal Techniques Beyond Everyday FPVBhushan Parikh, Shaman Narayana, Buck Lem, David Cassetti2021Papery2021paper
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Acceleration Startup Design & VerificationTim Sun, Barry Yin, and Haifeng Jiang2021Presentationy2021presentation
Accellera FS WG UpdateAlessandra Nardi, Ghani Kanawati2022Presentationy2022presentation
Accellera Functional Safety Working Group Update and Next StepsAlessandra Nardi, Ghani Kanawati2023Presentationy2023presentation
Accellera PSS being adopted in real projects TutorialAccellera Systems Initiative2022Presentationy2022presentation
Accellera Systems Initiative SystemC Standards UpdateBishnupriya Bhattacharya2015Presentationy2015presentation
Accellera Systems InitiativeSystemC Standards UpdateMartin Barnasconi, Philipp A. Hartmann, Trevor Wieman2014Presentationy2014presentation
Accellera Systems InitiativeSystemC Standards UpdateMartin Barnasconi, Philipp A. Hartmann, and Stephan Schulz 2015Presentationy2015presentation
Accellera UpdateLu Dai2023Presentationy2023presentation
Accellera UVM-AMS Standard UpdateTom Fitzpatrick and Tim Pylant2022Presentationy2022presentation
Accellera, Standards, and Semiconductor Supply ChainLu Dai2023Presentationy2023presentation
Ace’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power ConsumptionMehul Kumar, Tushar Mattu, and Amir Nilipour2016Papery2016paper
ACE’ing the Verification of a Coherent System Using UVMRomondy Luo, Ray Varghese, Parag Goel, Amit Sharma, Satyapriya Acharya, and Peer Mohammed2012Papery2012paper
ACE’ing the Verification of a Coherent System Using UVMParag Goel; Amit Sharma, Ray Varghese, Romondy Luo, Satyapriya Acharya, Peer Mohammed2012Presentationy2012presentation
ACE’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power ConsumptionMehul Kumar, Shawn Honess, Amir Nilipour, and Tushar Mattu2016Postery2016poster
Achieve Complete SoC Memory Map Verification Through Efficient Combination of Formal and Simulation TechniquesClemens Roettgermann, Peter Limmer, and Michael Rohleder2015Papery2015paper
Achieve Complete SoC Memory Map Verification through Efficient Combination of Formal and Simulation TechniquesClemens Roettgermann, Peter Limmer, and Michael Rohleder2015Presentationy2015presentation
Achieve Faster Debug Closure by Applying Big Data & Advanced RCA TechnologiesSundararajan Ananthakrishnan, Sundararajan PH2022Presentationy2022presentation
Achieving Faster Code Coverage Closure using High-Level SynthesisSurendhar Thudukuchi Chandrapandiyan, Preetham Lakshmikanthan, Ashwani Aggarwal, Youngchan Lee, Youngsik Kim, Seonil Brian Choi2021Papery2021paper
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Achieving First-Time Success with a UPF-based Low Power Verification FlowKjeld Svendsen, Chuck Seeley, and Erich Marschner2011Papery2011paper
Achieving Portable Stimulus with Graph-Based Verification – TutorialJosef Derner, Holger Horbach, Frederic Krampac, Staffan Berg2014Presentationy2014presentation
Achieving Real Time Performance for Algorithms Using SOC TLM ModelSaurin Patel, Pushkar Sareen, Sharath Naidu, Baljinder S Sood2015Presentationy2015presentation
Achieving system dependability: the role of automation and scalabilityAlessandra Nardi2022Papery2022paper
Achieving system dependability: the role of automation and scalabilityTeo Cupaiuolo, Paul Baron, Ghani Kanawati2022Presentationy2022presentation
Activity Trend Guided Efficient Approach to Peak Power Estimation Using EmulationGaurav Saharawat, Saurabh Jain, and Madhur Bhatia2016Presentationy2016presentation
Activity Trend Guided Efficient Approach to Peak Power Estimation Using EmulationGaurav Saharawat, Saurabh Jain, and Madhur Bhatia2016Papery2016paper
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Adapting the UVM Register Layer for Burst AccessM. P. Villalpando2016Papery2016paper
Adaptive Test Generation for Fast Functional Coverage ClosureAzade Naziz, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhosseiniz, and Richard Ho2022Papery2022paper
Adaptive Test Generation for Fast Functional Coverage ClosureAzade Nazi, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhoseini, Richard Ho2022Presentationy2022presentation
Adaptive UVM AMOD Testbench for Configurable DSI IPKrishnapal Singh, Pavan Yeluri, Ranjith Nair2019Papery2019paper
Adding Agility to Hardware Design-Verification using UVM & AssertionsFrancois Cerisier, Ajeetha Kumari, Gurubasappa, Srujana Reddy2017Presentationy2017presentation
Addressing Asynchronous FIFO Verification ChallengeAnchal Gupta, Ashish Hari, Sulabh Kumar Khare2018Presentationy2018presentation
Addressing Asynchronous FIFO Verification ChallengeAnchal Gupta, Ashish Hari and Sulabh Kumar Khare2019Presentationy2019presentation
Addressing Challenges in Verification of DSP based Audio IPs using a Novel Hybrid-TestBench ArchitectureSuvadeep Bose, Kanak Singh Rajput, Parag S Lonkar, Somasunder K Sreenath2021Papery2021paper
Addressing HW/SW Interface Quality through StandardsDavid Murray and Sean Boyan2012Papery2012paper
Addressing Renewed Gate Level Simulation Needs for 10nm-28nm and BelowGagandeep Singh2016Papery2016paper
Addressing Shared IP Instances in a Multi-CPU System Using Fabric Switch A Comprehensive SolutionPriyanka Gharat, Avnita Pal, Sastry Puranapanda2023Papery2023paper
Addressing Shared IP Instances in a MultiCPU System Using Fabric SwitchPriyanka Gharat, Avnita Pal, Sastry Puranapanda2023Presentationy2023presentation
Addressing the Challenges of ABV in Complex SOCsRithin A N, Arif M, Rupinjeet Singh, Jeevan2015Postery2015poster
Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail MacrosBrandon Skaggs2020Postery2020poster
Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail MacrosBrandon S. Skaggs2020Papery2020paper
Addressing the Challenges of Reset Verification in SoC DesignsChris Kwok, Priya Viswanathan, and Ping Yeung2015Papery2015paper
Addressing the Challenges of Reset Verification in SoC DesignsChris Kwok, Priya Viswanathan, and Ping Yeung2015Presentationy2015presentation
Addressing the Complex Challenges in Low-Power Design and VerificationMadhur Bhargava, Durgesh Prasad, Jitesh Bansal, and Gabriel Chidolue2016Presentationy2016presentation
Addressing the Complex Challenges in Low-Power Design and VerificationMadhur Bhargava, Durgesh Prasad, and Jitesh Bansal2016Papery2016paper
Addressing the verification challenge of SERDES-based FPGAs: The performance/accuracy/efficiency trade-offChris Schalick2011Papery2011paper
Adopting Accellera’s Portable Stimulus Standard: Early Development and Validation using Virtual PrototypingSimranjit Singh, Ashwani Aggarwal, Harshita Prabha, Vishnu Ramadas, Seonil Brian Choi, Woojoo Space Kim2021Papery2021paper
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Adopting UVM for safety Verification requirementsSrinivasan Venkatarmanan, Hemakiran Kolli, Gurubasappa Kinagi, and Satinder Paul Singh2017Presentationy2017presentation
Adopting UVM for safety Verification requirementsSrinivasan Venkatarmanan, Hema Kiran, and Satinder Paul Singh2017Papery2017paper
Advance Approach for Formal Verification of Configurable Pulse Width Modulation ControllerSumit K. Kulshreshtha, Raghavendra J N2021Papery2021paper
Advance your Design and Verification Flow Using IP XACTEdwin Dankert, Maximilian Albrecht and Vincent Thibaut2019Presentationy2019presentation
Advanced Digital-Centric Mixed-Signal MethodologyMichael Kontz, David Lacey, and Peter Maroni2015Papery2015paper
Advanced Digital-Centric Mixed-Signal MethodologyMichael Kontz, David Lacey, and Peter Maroni2015Presentationy2015presentation
Advanced Functional Verification for Automotive System on a ChipJaein Hong, Jieun Jeong , Namyoung Kim, Hongkyu Kim, Sungcheol Park,2022Presentationy2022presentation
Advanced Functional Verification for Automotive System on a ChipJaein Hong, Jieun Jeong, Namyoung Kim, Hongkyu Kim, and Sungcheol Park2022Papery2022paper
Advanced Functional Verification Methodology Using UVM For Complex DSP Algorithms In Mixed Signal RF SoCsSrinivas Aluri and Jaimin Mehta2014Presentationy2014presentation
Advanced Functional Verification Methodology Using UVM for complex DSP Algorithms in Mixed Signal RF SoCsSrinivas Aluri and Jaimin Mehta2014Papery2014paper
Advanced RISC-V Verification Technique Learnings for SoC ValidationDavid Kelf, Nambi Ju2023Presentationy2023presentation
Advanced RISC-V Verification Technique Learnings for SoC ValidationDavid Kelf, Nambi Ju2023Presentationy2023presentation
Advanced SOC Randomization Tool for Complex SOC Level VerificationMarvin Mei, Chris Weller, Michael Sedmak, and Zhiqiang Ren2020Papery2020paper
Advanced specification driven methodology for quick and accurate RDC signoffSai Jagadeesh Ambati, Sulabh Kumar Khare, Atul Sharma2023Postery2023poster
Advanced Techniques for ARM L2 Cache Verification in an Accelerated Hardware and Software environmentRob Pelt and Jay O’Donnell2012Papery2012paper
Advanced Techniques for AXI Fabric Verification in a Software/Hardware OVM EnvironmentGalen Blake and Steve Chappell2012Papery2012paper
Advanced Techniques to Accomplish Power Aware CDC VerificationRohit K Sinha, Ashish Hari and Sulabh Kumar Khare2018Papery2018paper
Advanced Testbench Configuration with ResourcesMark Glasser2011Papery2011paper
Advanced Usage Models for Continuous Integration in Verification EnvironmentsJohn Dickol2015Papery2015paper
Advanced Usage Models for Continuous Integration in Verification EnvironmentsJohn Dickol2015Presentationy2015presentation
Advanced UVM Coding TechniquesDavid Long2016Presentationy2016presentation
Advanced UVM Command Line ProcessorSiddharth Krishna Kumar2022Presentationy2022presentation
Advanced UVM Command Line Processor for Central Maintenance and Randomization of Control KnobsSiddharth Krishna Kumar2022Papery2022paper
Advanced UVM in the real world ‐ TutorialMark Litterick, Jason Sprott, Jonathan Bromley, and Vanessa Cooper2014Presentationy2014presentation
Advanced UVM Register ModelingMark Litterick and Marcus Harnisch2014Papery2014paper
Advanced UVM Register ModelingMark Litterick2014Presentationy2014presentation
Advanced UVM Tutorial Taking Reuse to the Next LevelMark Litterick, Jason Sprott, and Jonathan Bromley2015Presentationy2015presentation
Advanced UVM, Multi-Interface, Reactive Stimulus TechniquesClifford E. Cummings, Stephen DOnofrio, Jeff Wilcox, Heath Chambers2021Papery2021paper
Advanced, High Throughput Debug From Design to SiliconGordon Allan & Michael Horn2015Presentationy2015presentation
Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IPEldhose P.M, Sagar Jayakrishnan, Suraj Vijay Shetty, Kuntal Pandya, Parag S. Lonkar2022Presentationy2022presentation
Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IPEldhose P.M, Sagar Jayakrishnan, Suraj Vijay Shetty, Kuntal Pandya, Parag S. Lonkar2022Papery2022paper
Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification CycleCharul Agrawal, Ashwin Vijayan, and Jakub Dudek2017Presentationy2017presentation
Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification CycleCharul Agrawal, Ashwin Vijayan, and Jakub Dudek2017Papery2017paper
Advancing system-level verification using UVM in SystemCMartin Barnasconi, François Pêcheux, and Thilo Vörtler2014Papery2014paper
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Advancing the SystemC EcosystemPhilipp A Hartmann, Jerome Cornet, Martin Scnierginger, and Frederic Doucet2017Presentationy2017presentation
Advancing traceability and consistency in Verification and ValidationWalter Tibboel and Martin Barnasconi2014Papery2014paper
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Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC.Nipun Bhatt2020Postery2020poster
Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC.Nipun Bhatt2020Papery2020paper
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Agile and dynamic functional coverage using SQL on the cloudFilip Dojcinovic and Mihailo Ivanovic2019Presentationy2019presentation
Agile Approaches to ASIC Verification (A3V) – A Novel Agile Flow in Functional VerificationAdithya Rangan, Vidyasagar Kantamneni, Vishal Dalal2022Papery2022paper
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Agnostic UVM-XX Testbench GenerationJacob Andersen, Stephan Gerth, and Filippo Dughetti2016Presentationy2016presentation
Agnostic UVM-XX Testbench Generation Replace XX (almost) as you see fit!Jacob Andersen, Stephan Gerth, and Filippo Dughetti2016Papery2016paper
AI Driven VerificationCurtis Tsai2023Papery2023paper
Algorithm Verification with Open Source and System VerilogAndra Socianu and Daniel Ciupitu2014Presentationy2014presentation
AMS Verification at SoC Level: A Practical Approach for Using VAMS vs SPICE ViewsNitin Pant, Gautham Harinarayan, Manmohan Rana2015Presentationy2015presentation
AMS Verification in a UVM EnvironmentSilvia Strähle2016Presentationy2016presentation
AMS Verification in a UVM EnvironmentSilvia Strähle2016Papery2016paper
An Accelerated System Level CPU Verification through Simulation-Emulation Co-ExistenceRuchi Misra, Samridh Deva, Sai Krishna Pallekonda, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi2022Papery2022paper
An Accelerated System Level CPU Verification through Simulation-Emulation Co-ExistenceRuchi Misra, Samridh Deva, P Sai Krishna, Alok Kumar, Garima Srivastava YoungSik Kim, Seonil Brian Choi2022Presentationy2022presentation
An Analysis of Stimulus Techniques for Efficient Functional Coverage ClosureCaglayan Yalein, Aileen McCabe2021Papery2021paper
An Analytical View of Test Results Using CityScapesMarkus Borg, Andreas Brytting, and Daniel Hansson2018Papery2018paper
An Analytical View of Test Results Using CityScapesMarkus Borg, Andreas Brytting, and Daniel Hansson2018Postery2018poster
An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 ExperienceMahesha Shankarathota, Vybhava S, and Indrajit Dutta2013Papery2013paper
An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 ExperienceMahesha Shankarathota, Vybhava S, and Indrajit Dutta2013Postery2013poster
An Assertion Based Approach to Implement VHDL Functional CoverageMichael Wazlowski, Susan Eickhoff, Michael Debole, and Tagbo Ekwueme-Okoli2014Presentationy2014presentation
An Assertion Based Approach to Implement VHDL Functional CoverageSusan Eickhoff, Michael DeBole, and Tagbo Ekwueme-Okoli2014Papery2014paper
An Automated Formal Verification Flow for Safety RegistersHolger Busch2015Papery2015paper
An Automated Formal Verification Flow for Safety RegistersHolger Busch2015Presentationy2015presentation
An Automated Pre-silicon IP Trustworthiness Assessment for Hardware AssuranceJohn Hallman, David Landoll, Sergio Marchese, Sven Beyer, Garrett Chan, Salam Zantout and Vikram Rao2020Papery2020paper
An Automated Pre-silicon IP Trustworthiness Assessment for Hardware AssuranceJ. Hallman, D. Landoll, S. Marchese, S. Beyer, G. Chan, S. Zantout, and V. Rao2020Poster, Presentationy2020poster presentation
An Automated Systematic CDC Verification Methodology based on SDC SetupAshish Hari, Sulabh Kumar Khare2014Presentationy2014presentation
An Automated Validation Framework for Power Management and Data Retention Logic Kits of Standard Cell LibraryAkshay Kamath, Bharath Kumar, Sunil Aggarwal, Subramanian Parameswaran, Parag Lonkar, Debi Prasanna, Somasunder Sreenath2021Papery2021paper
An Automatic Visual System Performance Stress Test for TLM DesignsGeorge F. Frazier, Neeti Bhatnagar, and Woody Larue2011Papery2011paper
An Easy VE/DUV Integration ApproachUwe Simm2015Presentationy2015presentation
An Easy VE/DUV Integration ApproachUwe Simm2015Papery2015paper
An Easy VE/DUV Integration ApproachUwe Simm2015Presentationy2015presentation
An Effective Design and Verification Methodology for Digital PLLBiju Viswanathan, Rajagopal P.C, Ramya Nair S. R, Joseph J Vettickatt, and Jobin Cyriac2014Papery2014paper
An Effective Design and Verification Methodology for Digital PLLBiju Viswanathan, Rajagopal P.C, Ramya Nair S. R, Joseph J Vettickatt, and Jobin Cyriac2014Postery2014poster
An efficient analog fault-injection flow harnessing the power of abstractionRenaud Gillon, Enrico Fraccaroliy, and Franco Fummi2019Postery2019poster
An Efficient and Modular Approach for Formally Verifying Cache ImplementationsM, Achutha KiranKumar V and Abhijith A Bharadwaj2018Papery2018paper
An Efficient and Modular Approach for Formally Verifying Cache implementationsM Achutha KiranKumar V, Abhijith A Bharadwaj, and Bindumadhava S S2018Presentationy2018presentation
An Efficient Method to Verify Dynamic IP Clock Frequency on SOC Level by Using Auto-generated Active Clock MonitorJaecheon Kim, Gyuhong Lee, Yeonho Jeong, Hyunsun Ahn, Daewoo Kim, Seonil Brian Choi2021Papery2021paper
An Efficient Methodology for Mutation-Coverage-Collection of Formal-Property-CheckingHolger Busch2022Papery2022paper
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An efficient requirements-driven and scenario-driven verification flowHeino van Orsouw 2017Presentationy2017presentation
An efficient requirements-driven and scenario-driven verification flowWalter Tibboel, Heino van Orsouw, and Shuang Han2017Papery2017paper
An Efficient Verification Framework for Audio/Video Interface ProtocolsNoha Shaarawy, Mustafa Khairallah, Khaled Khalifa, Hany Salah, Amr Salah and Maged Ghoneima2015Papery2015paper
An Efficient Verification Methodology to Achieve DV Sign-off with Emphasis on Quality and Quicker DV CyclePiyush Agnihotri, Nirmal Kumar, Arnab Ghosh, Parag S Lonkar 2023Presentationy2023presentation
An Efficient Verification Methodology to Achieve DV Sign-off with Emphasis on Quality and Quicker DV CyclePiyush Agnihotri, Nirmal Kumar, Arnab Ghosh, Parag S Lonkar2023Papery2023paper
An Elegant scoreboard eco-system deploying UVM Callbacks, Parameterization for Multimedia designs from Imaging perspectiveChakravarthi Devakinanda Vurukutla, Sahana Ranganathan, Devendra Satish Bilaye, Vivek Kumar & Karthik Majeti2023Papery2023paper
An Elegant scoreboard eco-system deploying UVM Callbacks, Parameterization for Multimedia designs from Imaging perspectiveChakravarthi Devakinanda, Sahana Ranganathan, Devendra Satish Bilaye, Vivek Kumar & Karthik Majeti2023Presentationy2023presentation
An end-to-end approach to Design and Verify Battery Management Systems: from Requirements to Virtual Field TestingIrina Costachescu, Marius-Lucian Andrei, Manuel Fedou, Conrado Ramirez Garcia, 2022Papery2022paper
An end-to-end approach to Design and Verify BMS: from Requirements to Virtual Field TestingConrado Ramirez, Irina Costachescu, Marius Andrei, Carlos Villegas2022Presentationy2022presentation
An Enhanced DV Approach for Effectively Verifying High Speed, Low Power MIPI-MPHY 5.0 DesignsEldhose PM, Kuntal Pandya, Sagar Jayakrishanan, Suraj Vijay Shetty, Parag S Lonkar2023Postery2023poster
An Enhanced DV Approach for Effectively Verifying High Speed, Low Power MIPI-MPHY5.0 DesignsEldhose P.M, Sagar Jayakrishnan, Suraj Vijay Shetty, Kuntal Pandya, Parag S. Lonkar2023Papery2023paper
An Enhanced Stimulus and Checking Mechanism on Cache VerificationChenghuan Li, Xiaohui Zhao, and Yunyang Song2019Postery2019poster
An Equivalent Modeling Approach for High-Density DRAM Array System-Level Design-Space Exploration in SystemVerilogSeyoung Kim, Jaeha Kim2021Papery2021paper
An Experience of Complex Design Validation: How to Make Semiformal Verification WorkSabih Agbaria, Dan Carmi, Orly Cohen, Dmitry Korchemny, Michael Lifshits, and Alexander Nadel2010Papery2010paper
An experience to finish code refinement earlier at behavioral levelDae-Han Youn, Sik Kim, Byeong Min, and Kyu-Myung Choi2011Papery2011paper
An Expert System Based Tool for Pre-design Chip Power EstimationBhanu Singh, Arunprasath Shankar, Francis Wolff, and Christos Papachristou2014Presentationy2014presentation
An Expert System Based Tool for Pre-design Chip Power EstimationBhanu Singh, Arunprasath Shankar, Francis Wolff, and Christos Papachristou2014Papery2014paper
An Improved Methodology for Debugging UPF Issues at SoC level Power Aware SimulationsRuchi Misra, S Shrinidhi Rao, Alok Kumar, Garima Srivastava & Sarang Kalbande2023Papery2023paper
An Industry Proven UVM Reuse Methodology for Coverage Driven Block Level Verification to SW Driven Chip Level Verification Across Simulation & EmulationPradeep Salla, Keshav Joshi2016Presentationy2016presentation
An Innovative Methodology for RTL and Verification IP Sharing Between Two ProjectsAlbert Xu and Joonyoung Kim2013Papery2013paper
An Innovative Methodology for RTL and Verification IP Sharing Between Two ProjectsAlbert Xu and Joonyoung Kim2013Postery2013poster
An Innovative Methodology for Verifying Mixed-Signal ComponentsFabian Delguste and Graeme Nunn2011Papery2011paper
An Integrated Framework for Power Aware VerificationHarsh Chilwal, Manish Jain, and Bhaskar Pal2012Papery2012paper
An Introduction to the Accellera Portable Stimulus StandardSrivatsa Vasudevan, Pradeep Salla, Sharon Rosenberg, Adnan Hamid, Karthick Gururaj, Srivatsa Vasudevan, Bishnupriya Bhattacharya2017Presentationy2017presentation
An Introduction to using Event-B for Cyber-Physical System Specification and DesignJohn Colley and Michael Butler2014Presentationy2014presentation
An Open and Fast Virtual Platform for TriCore™-based SoCs Using QEMUBastian Koppelmann, Bernd Messidat, Markus Becker, and Christoph Kuznik2014Papery2014paper
An Open and Fast Virtual Platform for TriCore™-based SoCs Using QEMUBastian Koppelmann2014Postery2014poster
An open and flexible SystemC to VHDL workflow for rapid prototypingBastian Farkas, Syed Abbas Ali Shah, Jan Wagner, Rolf Meyer, Rainer Buchty, and Mladen Berekovic2016Papery2016paper
An open and flexible SystemC to VHDL workflow for rapid prototypingBastian Farkas2016Presentationy2016presentation
An Overview of Ethernet 10Base-T1S in Automotive SoC and its VerificationBipul Halder, Jagtar Singh, Sahana S, Pushpal Nautiyal, Gaurav Chugh2023Presentationy2023presentation
An Overview of Security Annotation for Electronic Design Integration (SA-EDI) StandardSohrab Aftabjahani2022Presentationy2022presentation
Analog Modelling to Suit Emulation for Hardware-Software Co-VerificationSaranya Das2020Poster, Presentationy2020poster presentation
Analog Modelling to Suit Emulation for Hardware-Software Co-VerificationSaranya Das2020Papery2020paper
Analog Transaction Level Modeling for Verification of Mixed-Signal-BlocksAlexander W. Rath, Volkan Esen, and Wolfgang Ecker2012Papery2012paper
Analog Transaction Level Modeling for Verification of Mixed-Signal-BlocksAlexander W. Rath2012Presentationy2012presentation
Analysis of TLM-2.0 and it’s Applicability to Non Memory Mapped InterfacesGuillaume Delbergue, Mark Burton, and Bertrand Le Gal and Christophe Jego2016Papery2016paper
Analysis of TLM-2.0 and it’s Applicability to Non Memory Mapped InterfacesDelbergue Guillaume2016Presentationy2016presentation
Apples versus Apples HVL Comparison Finally Arrives Comparing OVM SystemVerilog to OVM eBrett Lammers and Riccardo Oddone2010Papery2010paper
Application Abstraction Layer: The Carpool Lane on the SoC Verification FreewayAbhisek Verma, Varun S, and Subramanian Kuppusamy2015Papery2015paper
Application Abstraction Layer: The Carpool Lane on the SoC Verification FreewayAbhisek Verma, Varun S, and Subramanian Kuppusamy2015Presentationy2015presentation
Application of SystemC/SystemC-AMS in 3G Virtual PrototypingTao Huang and Stefan Heinen2011Papery2011paper
Application Optimized HW/SW Design & Verification of a Machine Learning SoCLauro Rizzatti, Russell Klein, Stephen Bailey, and Andrew Meier2020Presentationy2020presentation
Applying Big Data to Next-Generation Coverage Analysis and ClosureTom Fitzpatrick, Darron May, Thom Ellis, Athira Panicker and Francisco Chen2021Presentationy2021presentation
Applying Design Patterns to accelerate development of reusable, configurable and portable UVCs. 2015Presentationy2015presentation
Applying Design Patterns to Maximize Verification Reuse at Block, Subsystem and System on Chip LevelPaul Kaunds, Revati Bothe and Jesvin Johnson2019Presentationy2019presentation
Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical PropertiesK. Selyunin, T. Nguyen, A.D. Basa, E. Bartocci, D. Nickovic, and R. Grosu2016Papery2016paper
Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical PropertiesKonstantin Selyunin, Thang Nguyen, Andrei-Daniel Basa, Ezio Bartocci, Dejan Nickovic, and Radu Grosu2016Presentationy2016presentation
Applying Test-Driven Development Methods to Design Verification SoftwareDoug Gibson and Mike Kontz2014Presentationy2014presentation
Applying Test-Driven Development Methods to Design Verification Software in UVM-eDoug Gibson and Mike Kontz2014Papery2014paper
Applying Transaction-level Debug and Analysis Techniques to DUT Simulated Activity Using Data- Mining TechniquesLeo Chai, Bindesh Patel, and Jun Zhao2014Papery2014paper
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ARC EM Core with Safety Package – ISO 26262 CertificationVikas Bhandari2015Postery2015poster
Architecting “Checker IP” for AMBA protocolsSrinivasan Venkataramanan and Ajeetha Kumari2017Papery2017paper
Architecting “Checker IP” for AMBA protocolsAjeetha Kumari and Srinivasan Venkataramanan2017Presentationy2017presentation
Architectural Evaluation Of a Programmable Accelerator For Baseband, Phy and Video Applications Using High Level SynthesisAndy Fox, Tigran Sargsyan, and Steven Anderson2014Postery2014poster
Architectural Evaluation of a Programmable Accelerator for Baseband, Phy and Video Applications using High Level SynthesisAndy Fox, Tigran Sargsyan, and Steven Anderson2014Papery2014paper
Architectural Formal Verification of System-Level DeadlocksMandar Munishwar and Vigyan Singhal2018Presentationy2018presentation
Architectural Formal Verification of System-Level DeadlocksMandar Munishwar1, Naveed Zaman, Anshul Jain, HarGovind Singh, and Vigyan Singhal2018Papery2018paper
Architecturally Scalable Testbench for Complex SoCSenthilnath Subbarayan, Arulanandan Jacob, Sandeep Kumar2019Papery2019paper
Architectures to tradeoff performance vs debug for software development on emulation platformsLoganath Ramachandran, Ragavendar Swamisai, Makato Ikeda2023Presentationy2023presentation
Architectures to Tradeoff Performance vs. Debug for Software Development on Emulation PlatformLoganath Ramachandran, Ragavendar Swamisai, Makato Ikeda2023Papery2023paper
Are OVM & UVM Macros Evil? A Cost-Benefit AnalysisAdam Erickson2011Papery2011paper
Are you really confident that you are getting the very best from your verification resources?Darron May and Fritz Ferstl2014Papery2014paper
Are you really confident that you are getting the very best from your verification resources?Darron May and Fritz Ferstl2014Postery2014poster
Are You Safe Yet? Safety Mechanism Insertion and ValidationPing Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen2020Papery2020paper
Are You Safe Yet? Safety Mechanism Insertion and ValidationPing Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen2020Postery2020poster
Are You Smarter Than Your Testbench? With a little work you can be.Rich Edelman and Raghu Ardeishar2015Papery2015paper
Are You Smarter Than Your Testbench? With a little work you could beRich Edelman and Raghu Ardeishar2015Postery2015poster
ASIC-Strength Verification in a Fast-Moving FPGA WorldBryan Murdock2013Papery2013paper
ASIC-Strength Verification in a Fast-Moving FPGA WorldBryan Murdock2013Postery2013poster
ASIL B/D Fault Campaign Strategy for Computer Vision core using Soft Test Library (STL)Shiva Pokala, Vasista A2023Presentationy2023presentation
Assertion Based Self-checking of Analog Circuits for Circuit Verification and Model Validation in SPICE and Co-simulation EnvironmentsLakshmanan Balasubramanian, Pooja Sundar, and Timothy W Fischer2011Papery2011paper
Assertion-based Verification for Analog and Mixed Signal DesignsSrinivas Aluri2017Papery2017paper
Assertion-based Verification for Analog andMixed Signal DesignsSrinivas Aluri2017Postery2017poster
Assisting Fault Injection Simulations for Functional Safety Sign-off using FormalPulicharla Ravindrareddy2019Presentationy2019presentation
Assisting Fault Injection Simulations for Functional Safety Sign-off using FormalPulicharla Ravindrareddy2019Papery2019paper
Asynchronous Behaviors Meet Their Match with SystemVerilog AssertionsDoug Smith2010Papery2010paper
Attack Your SoCPowerChallenges with Virtual PrototypingStefan Thiel and Gunnar Braun2014Presentationy2014presentation
Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor CoreWei Foong Thoo and David A. Burgoon2012Presentationy2012presentation
Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor CoreWei Foong Thoo and David A. Burgoon2012Papery2012paper
Automate and Accelerate RISC-V Verification by Compositional Formal MethodsYean-Ru Chen, Cheng-Ting Kao, Yi-Chun Kao, Tien-Yin Cheng, Chun-Sheng Ke and Chia-HaoHsu2018Presentationy2018presentation
Automate and Accelerate RISC-V Verification by Compositional Formal MethodsYean-Ru Chen, Cheng-Ting Kao, Yi-Chun Kao, Tien-Yin Cheng, Chun-Sheng Ke and Chia-Hao Hsu2019Presentationy2019presentation
Automate Interrupt Checking with UVM Macros and PythonAleksandra Dimanic, Nemanja Stevanovic, Yoav Furman, Itay Henigsberg2022Papery2022paper
Automate Interrupt Checking with UVM Macros and PythonAleksandra Dimanic, Nemanja Stevanovic, Yoav Furman, Itay Henigsberg2022Presentationy2022presentation
Automated approach to Register Design and Verification of complex SOCBallori Banerjee, Subashini Rajan, and Silpa Naidu2011Papery2011paper
Automated code generation for Early AURIX TM VPPratheek Mahesh and Dineshkumar Selvaraj2021Postery2021poster
Automated code generation for Early AURIX TM VPPratheek Mahesh and Dineshkumar Selvaraj2021Presentationy2021presentation
Automated Comparison of Analog Behavior in a UVM EnvironmentSebastian Simon2014Presentationy2014presentation
Automated Comparison of Analog Behavior in a UVM EnvironmentSebastian Simon, Alexander W. Rath, Volkan Esen, and Wolfgang Ecker2014Papery2014paper
Automated Configuration of System Level C-Based CPU Testbench in Modern SoCs : A Novel FrameworkRuchi Misra, Chetan Kulkarni, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi2022Papery2022paper
Automated Configuration of System Level C-Based CPU Testbench in Modern SoCs : A Novel FrameworkRuchi Misra, Chetan Kulkarni, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi2022Presentationy2022presentation
Automated Configuration of Verification Environments using Specman Macros DVcon Europe 2018 – Paper number 260-OH22Milos Mirosavljevic, Ron Sela, Dejan Janjic and Efrat Shneydor2018Papery2018paper
Automated Configuration of Verification Environments using SpecmanMacrosMilos Mirosavljevic, Ron Sela, Dejan Janjic and Efrat Shneydor2018Presentationy2018presentation
Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal VerificationSamantha Pandez, Christopher Geen2023Papery2023paper
Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal VerificationSamantha Pandez Christopher Geen2023Postery2023poster
Automated correct-by-construct methodology for RTL design and analog mixed-signal test bench generation: Enables early design closure of mixed-signal SoCLakshmanan Balasubramanian, Murugesh Prashanth Subramaniam, Atul Ramakant Lele, and Ranjit Kumar Dash2014Papery2014paper
Automated Creation of Reusable Generators for Analog IC Design with the Intelligent IP MethodUwe Eichler, Benjamin Prautsch, Torsten Reich2022Papery2022paper
Automated Creation of Reusable Generators for Analog IC Design with the Intelligent IP MethodUwe Eichler, Benjamin Prautsch, Torsten Reich2022Presentationy2022presentation
Automated Floating Trash Collecting BoatKaramalaputti Rahul, Gandham Magaraju2023Postery2023poster
Automated Generation of RAL-based UVM SequencesSatyajit Sinari, Timothy McLean, Benjamin Applequist, Vijayakrishnan Rousseau, and Geddy Lallathin2020Presentationy2020presentation
Automated Generation of RAL-based UVM SequencesVijayakrishnan Rousseau, Satyajit Sinari, Benjamin Applequist, Timothy McLean, and Geddy Lallathin2020Papery2020paper
Automated Modeling Testbench Methodology Tested with four Types of PLL ModelsJun Yan, Josh Baylor2023Presentationy2023presentation
Automated Modeling Testbench Methodology Tested with four Types of PLL ModelsAutomated Modeling Testbench Methodology Tested with four Types of PLL Models2023Papery2023paper
Automated Performance Verification to Maximize your ARMv8 pulling powerNick Heaton and Simon Rance2015Papery2015paper
Automated Performance Verification to Maximize your ARMv8 pulling powerNick Heaton and Simon Rance2015Presentationy2015presentation
Automated Physical Hierarchy Generation: Tools and MethodologyAli El-Zein, Alvan Ng, Benedikt Geukes, Maya H. Safieddine, and Wolfgang Roesner2018Papery2018paper
Automated Physical Hierarchy Generation: Tools and MethodologyAli El-Zein, Alvan Ng, Benedikt Geukes, Maya H. Safieddine, and Wolfgang Roesner2018Presentationy2018presentation
Automated RTL Update for Abutted DesignWonkyung Lee, Ayoung Kwon, Soyeong Kwon, Youngsik Kim, and Seonil Brian Choi2020Papery2020paper
Automated RTL Update for Abutted DesignWonkyung Lee, Ayoung Kwon, Soyeong Kwon, Youngsik Kim, and Seonil Brian Choi2020Postery2020poster
Automated Safety Verification for Automotive MicrocontrollersH. Busch2016Papery2016paper
Automated Safety Verification for Automotive MicrocontrollersHolger Busch2016Presentationy2016presentation
Automated Seed Selection Algorithm for an Arbitrary Test SuiteDavid Crutchfield, Brian Craw, Jim Sharpe, and Brandon Skaggs2018Presentationy2018presentation
Automated Seed Selection Algorithm for an Arbitrary Test SuiteDavid Crutchfield, Brian Craw, Jim Sharpe, and Brandon Skaggs2018Papery2018paper
Automated Specification Driven Verification by Generation of SystemVerilog AssertionsFerdinando Pace2016Papery2016paper
Automated Specification Driven Verification by Generation of SystemVerilog AssertionsFerdinando Pace2016Postery2016poster
Automated SystemC Model Instantiation with modern C++ Features and sc_vectorRalph Görgen and Philipp A. Hartmann2015Papery2015paper
Automated SystemC Model Instantiation with modern C++ Features and sc_vectorRalph Görgen, Philipp A. Hartmann, and Wolfgang Nebel2015Presentationy2015presentation
Automated Test Generation to Verify IP Modified for System Level Power ManagementChristophe Lamard2015Papery2015paper
Automated Test Generation to Verify IP Modified for System Level Power ManagementChristophe Lamard and Frederic Dupuis2015Presentationy2015presentation
Automated Thread Evaluation of Various RISC-V Alternatives using Random Instruction GenerationEndri Kaja, Nicolas Gerlin, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker2023Presentationy2023presentation
Automated Thread Evaluation of Various RISC-V Alternatives using Random Instruction GeneratorsEndri Kaja, Nicolas Gerlin, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker2023Papery2023paper
Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual PrototypeS N Ranjan and Puttaiah Jagadish2021Presentationy2021presentation
Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual PrototypeS N Ranjan and Puttaiah Jagadish2021Postery2021poster
Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual PrototypeS N Ranjan and Puttaiah Jagadish2021Presentationy2021presentation
Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual PrototypeS N Ranjan and Puttaiah Jagadish2021Postery2021poster
Automated traceability of requirements in the design and verification process of safety-critical mixed-signal systemsGabriel Pachiana, Maximilian Grunwald, Thomas Markwirth, Christoph Sohrmann2021Papery2021paper
Automated Traffic Simulation Framework for SoC Performance AnalysisDiviya Jain, Tarun Kathuria 2017Presentationy2017presentation
Automated vManager regression using JenkinsSneha Gokarakonda2022Postery2022poster
Automated, Systematic CDC Verification Methodology Based on SDC SetupAshish Hari, Sulabh Kumar Khare2014Papery2014paper
Automatic Debug Down to the LineDaniel Hansson and Patrik Granath2017Postery2017poster
Automatic Debug Down to the Line of CodeDaniel Hansson and Patrik Granath2017Papery2017paper
Automatic Diagram Creation for Design and TestbenchesPaul O’Keeffe, Jamie Beattie, and Gian Lorenzo2020Poster, Presentationy2020poster presentation
Automatic Diagram Creation for Design and TestbenchesPaul O’Keeffe, Jamie Beattie and Gian Lorenzo2020Papery2020paper
Automatic Exploration of Hardware/Software PartitioningSyed Abbas Ali Shah, Sven Alexander Horsinka, Basitan Farkas, Rolf Meyer, and Malden Berekovic2017Papery2017paper
Automatic Exploration of Hardware/Software PartitioningSyed Abbas Ali Shah, Sven Alexander Horsinka, Basitan Farkas, Rolf Meyer, and Malden Berekovic2017Presentationy2017presentation
Automatic Firmware Design for Application-specific Electronic Systems: Opportunities, Challenges and SolutionsDaniel Große, Joscha Benz, Vladimir Herdt, and Martin Dittrich2017Presentationy2017presentation
Automatic Firmware Verification for Automotive ApplicationsTorsten Andre and Daniel Valtiner2017Presentationy2017presentation
Automatic Firmware Verification for Automotive ApplicationsTorsten Andre and Daniel Valtiner2017Papery2017paper
Automatic Generation of Formal Properties for Logic Related to Clock GatingShuqing Zhao and Shan Yan2015Presentationy2015presentation
Automatic Generation of Formal Properties for Logic Related to Clock GatingShuqing Zhao and Shan Yan2015Papery2015paper
Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDLNikita Gulliya, Sudhir Bisht2023Presentationy2023presentation
Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDLSudhir Bisht, Nikita Gulliya2023Postery2023poster
Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDLSudhir Bisht2023Presentationy2023presentation
Automatic Generation of Infineon Microcontroller Product ConfigurationsPrateek Chandra, Leily Zafari, Boyko Traykov2019Presentationy2019presentation
Automatic Generation of Infineon Microcontroller Product ConfigurationsPrateek Chandra, Leily Zafari, Boyko Traykov2019Papery2019paper
Automatic Investigation of Power InefficienciesKuo Kai Hsieh, Li C. Wang, Wen Chen, Monica Farkash, and Jayanta Bhadra2017Presentationy2017presentation
Automatic Investigation of Power InefficiencyKuo-Kai Hsieh, Wen Chen, Monica Farkash, Jayanta Bhadra, and Li-C. Wang2017Papery2017paper
Automatic Netlist Modifications required by Functional SafetyHarald Lüpken, Dirk Hönicke, and Michael Rohleder2014Papery2014paper
Automatic Netlist Modifications required by Functional SafetyHarald Lüpken, Dirk Hönicke, and Michael Rohleder2014Postery2014poster
Automatic Partitioning for Multi-core HDL SimulationGaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra2015Papery2015paper
Automatic Partitioning for Multi-core HDL SimulationGaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra2015Postery2015poster
Automatic SOC Test Bench CreationDavid Crutchfield, Mark Glasser, and Stephen Roe2015Papery2015paper
Automatic SOC Test Bench CreationDavid Crutchfield, Mark Glasser, and Stephen Roe2015Presentationy2015presentation
Automatic Testbench Build to Reduce Cycle Time and Forster ReuseJoachim Geishauser and Alexander Schilling2017Papery2017paper
Automatic Testbench Build to Reduce Cycle Time and Foster ReuseJoachim Geishauser and Alexander Schilling2017Presentationy2017presentation
Automatic Translation of Natural Language to SystemVerilog AssertionsAbhishek Chauhan2022Presentationy2022presentation
Automatic Translation of Natural Language to SystemVerilog AssertionsAbhishek Chauhan2022Papery2022paper
Automatic verification for Assertion Based Verification: How can a SPIRIT IP-XACT extension help?Sofiene Mejri and Mirella Negro Marcigaglia2010Papery2010paper
Automatically Synthesizing Higher Level of Protocol Abstraction for Faster Debug and Deeper Insight Into Modern Digital DesignsAlasdair Ferro, Amar Patel, Chris Jones, Yogesh Badaya2019Papery2019paper
Automating information retrieval from EDA software reports using effective parsing algorithmsManish Bhati2022Postery2022poster
Automating sequence creation from a microarchitecture specificationSubramoni Parameswaran and Ravi Ram2016Postery2016poster
Automating sequence creation from a Microarchitecture specificationSubramoni Parameswaran and Ravi Ram2016Papery2016paper
Automating the formal verification sign-off flow of configurable digital IP’sGiovanni Auditore and Giuseppe Falconeri2019Presentationy2019presentation
Automating the formal verification sign-off flow of configurable digital IP’sGiovanni Auditore and Giuseppe Falconeri2019Papery2019paper
Automation for Early Detection of X-propagation in Power-Aware Simulation Verification using UPF IEEE 1801Tony Gladvin George, Ramesh Kumar, Kyuho Shim, Karan K, Wooseong Cheong, ByungChul Yoo2023Presentationy2023presentation
Automation for Early Detection of Xpropagation in Power-Aware Simulation Verification using UPF IEEE 1801Tony Gladvin George, Ramesh Kumar, Kyuho Shim, Karan K, Wooseong Cheong, ByungChul Yoo2023Papery2023paper
Automation Methodology for Bus Performance Verification using IP-XACTTaeyoung Jeon, Gunseo Koo, Youngsik Kim, Seonil Brian Cho2023Postery2023poster
Automation Methodology for Bus Performance Verification using IP-XACTTaeyoung Jeon, Gunseo Koo, Youngsik Kim, Seonil Brian Choi2023Papery2023paper
Automation of Power On Reset AssertionShang-Wei Tu, Penny Yang, Joydeep Gangopadhyay, and Amol Herlekar2015Papery2015paper
Automation of Reusable Protocol-Agnostic Performance Analysis in UVM EnvironmentsDaniel Carrington, Alan Pippin, and Timothy Pertuit2019Presentationy2019presentation
Automation of Reusable Protocol-Agnostic Performance Analysis in UVM EnvironmentsD. P. Carrington, A. J. Pippin, and T. Pertuit2019Papery2019paper
Automation of Waiver and Design Collateral generation for scalable IPsGopalakrishnan Sridhar, Vadlamuri Venkata Sateeshm, Midhun Krishna2019Papery2019paper
Automation of Waiver and Design Collateral Generation on Scalable IPsGopalakrishnan Sridhar, Midhun Krishna, Vadlamuri, Venkata Sateesh2019Presentationy2019presentation
Automotive RADAR Bitfields Verification to support Validation of Silicon bring-upAmol Dhok, Paulraj M K2023Presentationy2023presentation
Automotive RADAR Bitfields Verification to support Validation of Silicon bring-upAmol Dhok, Paulraj M K2023Papery2023paper
Autonomous Verification: Are We There Yet?Ajay Singh2023Presentationy2023presentation
Avoiding Configuration Madness The Easy WayRich Edelman2023Presentationy2023presentation
Avoiding Configuration Madness The Easy WayRich Edelman2023Papery2023paper
Avoiding Confounding Configurations an RDC Methodology for Configurable DesignsEamonn Quigley, Jonathan Niven, and Kurt Takara2022Postery2022poster
Avoiding Confounding Configurations An RDC Methodology for Configurable DesignsEamonn Quigley, Jonathan Niven, and Kurt Takara2022Papery2022paper
Back to Basics: Doing Formal “The Right Way”Joseph Hupcey III, Saumitra Goel 2017Presentationy2017presentation
BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering ProblemDebarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, Siddhanth Dhodhi, Spandan Kachhadiya2022Presentationy2022presentation
BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering ProblemDebarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, and Siddhanth Dhodhi2022Papery2022paper
Be a Sequence Pro to Avoid Bad Con SequencesMark Litterick2019Presentationy2019presentation
Be a Sequence Pro to Avoid Bad Con SequencesJeff Vance, Jeff Montesano, Mark Litterick, and Jason Sprott2019Presentationy2019presentation
Benefits of PSS coverage at SOC & its limitationsSundararajan Haran and Saleem Khan2019Presentationy2019presentation
Benefits of PSS Coverage at SOC and Its LimitationsSundararajan Haran, Saleem Khan2019Papery2019paper
Best Practices in Verification PlanningBenjamin Ehlers, Carmen Vargas, and Paul Carzola2013Papery2013paper
Best Practices in Verification PlanningBenjamin Ehlers and Paul Carzola2013Presentationy2013presentation
Better Living Through Better Class-Based SystemVerilog DebugRich Edelman, Raghu Ardeishar, and John Amouroux2012Papery2012paper
Better Living Through Better Class-Based SystemVerilog DebugRich Edelman, Raghu Ardeishar, and John Amouroux2012Presentationy2012presentation
Between the Dialog and the Algorithm or Innovative Technological Narratives Leveraging the Idea of Authenticity in a Human Being Visualizing log files enables intuitive comprehension of complex test scenariosAnna M. Ravitzki and Uri Feigin2017Papery2017paper
Beyond UVM: Creating Truly Reusable Protocol LayeringJanick Bergeron, Fabian Delguste, Steve Knoeck, Steve McMaster, Aron Pratt, and Amit Sharma2013Papery2013paper
Beyond UVM: Creating Truly Reusable Protocol LayeringJanick Bergeron2013Presentationy2013presentation
Bi-Directional UVM Agents and Complex Stimulus Generation for UDN and UPF PinsChuck McClish2021Papery2021paper
Big Data in Verification: Making Your Engineers SmarterDavid Lacey, Mike McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson2019Papery2019paper
Big Data in Verification: Making Your Engineers SmarterDavid Lacey, Michael McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson2019Presentationy2019presentation
Bit density based pre characterization of RAM cells for area critical SOC designDilip Kumar Ajay ([email protected])2020Presentationy2020presentation
Bit Density-Based Pre-Characterization of RAM Cells for Area Critical SOC DesignDilip Kumar Ajay2020Papery2020paper
Blending multiple metrics from multiple verification engines for improved productivityDarron May and Darren Galpin2012Papery2012paper
Boost Verification Results by Bridging the Hardware/Software Testbench GapMatthew Ballance2013Papery2013paper
Boost Verification Results by Bridging the Hw/Sw Testbench GapMatthew Ballance2013Presentationy2013presentation
Boost your productivity in FPGA & ASIC design and verificationBart Brosens2022Papery2022paper
Boost your productivity in FPGA & ASIC design and verificationBart Brosens2022Presentationy2022presentation
Boosting Debug Productivity Practical Applications of Debug Innovations in a UVM WorldJoerg Richter2017Presentationy2017presentation
Boosting Mixed-Signal Design Productivity with FPGA-Based Methods Throughout the Chip Design ProcessGabriel Rutsch, Simone Fontanesi, Steven G. Herbst, Steven Tan Hee Yeng, Andrea Possemato, Gaetano Formato, Mark Horowitz, and Wolfgang Ecker2020Papery2020paper
BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMSAhmed Yehia2013Papery2013paper
BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMSAhmed Yehia2013Postery2013poster
Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven GenerationHoang M. Le and Rolf Drechsler2015Papery2015paper
Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven GenerationHoang M. Le and Rolf Drechsler2015Presentationy2015presentation
Break the SoC with Random UVM Instruction DriverBogdan Todea, Pravin Wilfred, Madhukar Mahadevappa, Diana Dranga2019Papery2019paper
Break the SoC with UVM Dynamically Generated Program CodeBogdan Todea, Madhukar Mahadevappa & Pravin Wilfred2023Papery2023paper
Breaking Down Barriers: Seamless Protocol Conversion with UVM Component LayeringSantosh Mahale, Shantanu Lele2023Presentationy2023presentation
Breaking Down Barriers: Seamless Protocol Conversion with UVM Component LayeringSantosh Mahale, Shantanu Lele2023Papery2023paper
Bridge the Portable Test and Stimulus to UVM Simulation EnvironmentTheta Yang and Evean Qin2018Papery2018paper
Bridge the Portable Test and Stimulus to UVM Simulation EnvironmentTheta Yang and Evean Qin2018Presentationy2018presentation
Bridging the gap between system-level and chip-level performance optimizationSoniya Gupta, Vikrant Kapila & Holger Keding2023Papery2023paper
Bridging the gap between TLM-2.0 AT models and RTL – Experiments and OpportunitiesZhu Zhou, Atul Kwatra, Rajesh Gadiyar, and Paul Heraty2010Papery2010paper
Bring IP Verification Closer to SoC Scalable Methods to Bridge the Gap Between IP and SoC VerificationGaurav Gupta, Tejbal Prasad, Rohit Goyal, Sachin Jain, Vipin Verma2014Presentationy2014presentation
Bring IP Verification Closer to SoC Scalable Methods to Bridge the Gap Between IP and SoC VerificationGaurav Gupta, Tejbal Prasad, Rohit Goyal, Sachin Jain, Vipin Verma2014Papery2014paper
Bringing Constrained Random into SoC SW-driven VerificationAlberto Allara and Fabio Brognara2013Papery2013paper
Bringing Constrained Random into SoC SW-driven VerificationAlberto Allara and Fabio Brognara2013Presentationy2013presentation
BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPSPrabal K Bhattacharya, Swapnajit Chakraborti, Donald O’Riordan, Vaibhav Bhutani, and Scott Little2012Presentationy2012presentation
BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPSPrabal K Bhattacharya, Swapnajit Chakraborti, Scott Little, Donald O’Riordan, and Vaibhav Bhutani2012Papery2012paper
Bringing DataPath Formal to Designers’ FootstepsM, Achutha KiranKumar V, Disha Puri, Shriya Dharade2019Papery2019paper
Bringing Regression Systems into the 21st CenturyDavid Crutchfield and Thom Ellis2014Papery2014paper
Bringing Regression Systems into the 21st CenturyDavid Crutchfield2014Postery2014poster
Bringing Reset Domains and Power Domains together – Confronting issues due to UPF InstrumentationInayat Ali, Abdul Moyeen, Manish Bhati, Manjunatha Srinivas2021Papery2021paper
Bringing Reset Domains and Power Domains together – Non resettable registers amplifying issues in Power-Aware RDC Verification due to UPF InstrumentationManish Bhati, Inayat Ali2022Presentationy2022presentation
Bringing Reset Domains and Power Domains Together – Set/Reset Flops Augmenting Complexities in Power-Aware RDC Verification.Manish Bhati, Manjunatha Srinivas, Abdul Moyeen, Inayat Ali2021Papery2021paper
Bringing UVM to VHDLUVVM2022Presentationy2022presentation
Build Reliable and Efficient Reset Networks with a Comprehensive Reset Domain Crossing Verification SolutionWanggen Shi, Yuxin You, and Kurt Takara2020Presentationy2020presentation
Build Reliable and Efficient Reset Networks with a Comprehensive Reset Domain Crossing Verification SolutionWanggen Shi, Yuxin You, and Kurt Takara2020Papery2020paper
Building a coherent ESL design and verification eco-system with SystemC, TLM, UVM-SystemC, and CCIMartin Barnasconi2016Papery2016paper
Building a Comprehensive Hardware Security MethodologyAnders Nordstrom and Jagadish Nayak2022Presentationy2022presentation
Building a Virtual Driver for EmulatorChen Chih-Chiang2023Papery2023paper
Building And Modelling Reset Aware Testbench For IP Functional VerificationNaishal Shah2019Papery2019paper
Building Code Generators for Reuse – Demonstrated by a SystemC GeneratorSaad Siddiqui and Ulrich Nageldinger2017Papery2017paper
Building Code Generators for Reuse – Demonstrated by a SystemC GeneratorUlrich Nageldinger and Saad Siddiqui2017Presentationy2017presentation
Building Confidence in System level CPU Cache Coherency Verification for Complex SoC’s through a Configurable, Flexible and Portable TestbenchRuchi Misra, Shrinidhi Rao, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi2022Papery2022paper
Building Confidence in System Level CPU Cache Coherency Verification for Complex SoCs through a Configurable Flexible and Portable Test BenchS Shrinidhi Rao, Ruchi Misra, Alok Kumar, Garima Srivastava, YoungSik Kim, Seonil Brian Choi2022Presentationy2022presentation
Building Configurable UVM Testbench for Configurable Design IP (Configurable TB)Kilaru Vamsikrishna, Sushrut B Veerapur2022Presentationy2022presentation
Building Portable Stimulus Into your IP-XACT FlowPetri Karppa, Lauri Matilainen, and Matthew Ballance2018Presentationy2018presentation
Building Portable Stimulus Into Your IP-XACT FlowPetri Karppa, Lauri Matilainen, and Matthew Balance2018Papery2018paper
Building Smart SoCs Using Virtual Prototyping for the Design and SoC Integration of Deep Learning AcceleratorsHolger Keding2019Presentationy2019presentation
Building UVM Testbenches for High Quality Serial Design IPs Modelling real world scenariosKilaru Vamsikrishna, Sushrut B Veerapur2022Postery2022poster
C through UVM: Effectively using C based models with UVM based Verification IPChris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile2013Papery2013paper
C through UVM: Effectively using C based models with UVM based Verification IPAdiel Khan, Chris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile2013Presentationy2013presentation
Caching Tool Run Results in Large Scale RTL Development ProjectsAshfaq Khan2022Presentationy2022presentation
Caching Tool Run Results in Large-Scale RTL Development ProjectsAshfaq Khan2022Papery2022paper
Cadence vManager Platform and Virtuoso ADE Verifier Leading-edge technologies provide methodology for mixedsignal verification closureKawe Fotouhi and Walter Hartong2019Presentationy2019presentation
Calling All Checkers: Collaboratively Utilizing SVA in UVM Based SimulationHui C. K. Zhang2016Postery2016poster
Calling All Checkers: Collaboratively Utilizing SVA In UVM Based SimulationHui K. Zhang2016Papery2016paper
CAMEL – A Flexible Cache Model for Cache VerificationYue Liu, Fang Liu, Yunyang Song2022Presentationy2022presentation
CAMEL: A Flexible Cache Model for Cache VerificationYue Liu, Fang Liu, and Yunyang Song2022Papery2022paper
Can Formal Outsmart Synthesis: Improving Synthesis Quality of Results through Formal MethodsEldon Nelson2021Papery2021paper
Can My Synthesis Compiler Do That?Stuart Sutherland and Don Mills2014Papery2014paper
Can My Synthesis Compiler Do That?Stuart Sutherland and Don Mills2014Presentationy2014presentation
Can You Even Debug a 200M+ Gate Design?Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss2013Papery2013paper
Can You Even Debug a 200M+ Gate Design?Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss2013Postery2013poster
Case Study of Verification Planning to Coverage Closure @Block, Subsystem and System on Chip LevelPaul Kaunds, Revati Bothe, and Jesvin Johnson2018Presentationy2018presentation
Case Study: Low-Power Verification Success Depends on Positive PessimismJohn Decker2011Papery2011paper
Case Study: Power-aware IP and Mixed-Signal VeriLuke Lang2011Papery2011paper
Case Study: Successes and Challenges of Validation Content ReuseMike Chin, Jonathan Edwards, Josh Pfrimmer, and Hooi Jing Tan2022Papery2022paper
Case-study: Generating A Workload Model of the Chrome Browser from Android Execution Traces For Early Analysis of Power and Performance Trade-offsVikrant Kapila, Tim Kogel, Holger Keding, Amit Tara Amit Dudeja, Nishant Gautam2017Presentationy2017presentation
Catching the low hanging fruits on intel® Graphics DesignsM, Achutha KiranKumar V, Aarti Gupta, Bindumadhava S S, Savitha Manojna, and Abhijith A Bharadwaj2016Papery2016paper
Centralized Regression Optimisation Toolkit (CROT) for expediting Regression Closure With Simulator Performance OptimisationHarshal Kothari, Pavan M, Ajay Vamshi Krishna, Eldin Ben Jacob, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath2021Papery2021paper
Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation)Vikas Billa and Sundar Haran2018Papery2018paper
Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation)Vikas Billa and Sundar Haran2018Presentationy2018presentation
Challenges and Solutions for Creating Virtual Platforms of FPGA and SASIC DesignsKalen Brunham, Jakob Engblom2022Presentationy2022presentation
Challenges and Solutions for Creating Virtual Platforms of FPGA and SASIC DesignsKalen Brunham, Jakob Engblom2022Papery2022paper
Challenges in Mixed Signal VerificationAmlan Chakrabarti, Sachin-Sudhakar Kulkarni2015Presentationy2015presentation
Challenges in UVM + Python Random Verification Environment for Digital Signal Processing Datapath DesignShabbar Vejlani and Ashok Chandran2016Presentationy2016presentation
Challenges in UVM + Python random verification environment for Digital Signal Processing datapath design.Shabbar Vejlani and Ashok Chandran2016Papery2016paper
Challenges of Formal Verification on Deep Learning Hardware AcceleratorYellinidi Dasarathanaidu2019Presentationy2019presentation
Challenges of Formal Verification on Deep Learning Hardware AcceleratorYellinidi Dasarathanaidu2019Papery2019paper
Challenges of VHDL X-propagation SimulationsKarthik Baddam and Piyush Sukhija2015Papery2015paper
Challenges of VHDL X-propagation SimulationsKarthik Baddam and Piyush Sukhija2015Presentationy2015presentation
Challenges with Power Aware Simulation and Verification MethodologiesDivyeshkumar Vora2015Presentationy2015presentation
Challenges, Complexities and Advanced Verification Techniques in Stress Testing of Elastic Buffer in High Speed SERDES IPsKamesh Velmail, Suvadeep Bose, Ankit Garg, Parag S Lonkar, Somasunder K Sreenath2019Presentationy2019presentation
Challenges, Complexities and Advanced Verification Techniques in Stress Testing of Elastic Buffer in High Speed SERDES IPsKamesh Velmail, Suvadeep Bose, Parag Lonkar, Ankit Garg2019Papery2019paper
Channel Modelling in Complex Serial IPsJayesh Ranjan Majhi, Saravana Balakrishnan, Navnit Kumar Kashyap2022Postery2022poster
Channel Modelling in Complex Serial IPsJayesh Ranjan Majhi, Saravana Balakrishnan, Navnit Kumar Kashyap2022Papery2022paper
Characterizing RF Wireless Receivers Performance in UVM EnvironmentSalwa Elqassas, Salwa Elqassas and Mohammed T. Abdel-Hafe2018Papery2018paper
Check Low-Power Violations by Using Machine Learning Based ClassifierChi-Ming Lee, Chung-An Wang, Cheok-Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai2023Postery2023poster
Check Low-Power Violations by Using Machine Learning Based ClassifierChi-Ming Lee, Chung-An Wang, Cheok-Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai2023Papery2023paper
Checking security path with formal verification tool: new application developmentJulia Dushina, Saumil Shah, Joerg Mueller, and Vincent Reynolds2014Papery2014paper
Checking Security Path with Formal Verification Tool: New Application DevelopmentJulia Dushina and Joerg Mueller2014Postery2014poster
Chef’s Special – an Efficient Verification Recipe for Maximizing Productivity While Using a Third Party Verification IPVarun S and Bhavik Vyas2012Papery2012paper
Chiplevel Analog Regressions in ProductionYi Wang2021Papery2021paper
Choice is Yours: Either Struggle to Tame ‘X’ in the Wilderness of Multimillion Gates and Nets, OR Take it for a Walk in the RTL ParkNitin Jaiswal, Harsh Garg, Mayank Bindal2014Presentationy2014presentation
Cleaning Out Your Pipes – Pipeline Debug in UVM TestbenchesRich Edelman and Neil Bulman2018Papery2018paper
Cleaning Out Your Pipes – Pipeline Debug in UVM TestbenchesRich Edelman and Neil Bulman2018Postery2018poster
Clock Controller Unit Design Metrics: Area, Power, Software Flexibility and Congestion Impacts at System LevelMichele Chilla and Leonardo Gobbi2020Papery2020paper
CLOCK DOMAIN CROSSING CHALLENGES IN LATCH BASED DESIGNSMadan Das, PhD, Chris Kwok, and Kurt Takara2018Papery2018paper
Clock Domain Crossing Challenges in Latch Based DesignsMadan Das, Chris Kwok, and Kurt Takara2018Presentationy2018presentation
Clock Domain Crossing Verification in Transistor-level DesignHyungjung Seo, KwangSun Kim, YoungRok Choi, Jihwan Kim, and Jong-Bae Lee2019Postery2019poster
Clock Tree Design Considerations in The Presence of Asymmetric Transistor AgingFreddy Gabbay; Firas Ramadan; Majd Ganaiem2023Papery2023paper
Closed-Loop Model-First SoC Development With the Intel® Simics® SimulatorKalen Brunham, Anthony Moore, Tobias Rozario, Wei Jun Yeap, and Jakob Engblom2023Presentationy2023presentation
Closed-Loop Model-First SoC Development With the Intel® Simics® SimulatorKalen Brunham, Anthony Moore, Tobias Rozario, Wei Jun Yeap, and Jakob Engblom2023Papery2023paper
Closing and AwardsAccellera Systems Initiative2022Videoy2022video
Closing Functional and Structural Coverage on RTL Generated by High-Level SynthesisB. Bowyer2015Papery2015paper
Closing Functional and Structural Coverage on RTL Generated by High-Level SynthesisBryan Bowyer2015Postery2015poster
Closing Functional Coverage With Deep Reinforcement Learning: A Compression Encoder ExampleEric Ohana2023Papery2023paper
Closing Functional Coverage With Deep Reinforcement Learning A Compression Encoder ExampleEric Ohana2023Presentationy2023presentation
Closing the gap between requirement management and system design by requirement tracingHayri Verner Hasou, Guillermo Conde, Adrian Rolufs, Dominic Scharfe2022Papery2022paper
Closing the loop from requirements management to verification execution for automotive applicationsWalter Tibboel and Jan Vink2015Papery2015paper
Closing the loop from requirements management to verification execution for automotive applicationsWalter Tibboel and Jan Vink2015Presentationy2015presentation
Closing with AwardsAccellera Systems Initiative2022Videoy2022video
Clustering and Classification of UVM Test Failures Using Machine Learning TechniquesAndy Truong, Daniel Hellström, Harry Duque, and Lars Viklund2018Papery2018paper
Clustering and Classification of UVM Test Failures Using Machine Learning TechniquesAndy Troung, Daniel Hellström, Harry Duque, and Lars Viklund2018Presentationy2018presentation
Co-Design of Automotive Boardnet Topology and ArchitectureSebastian Post, Christoph Grimm2023Presentationy2023presentation
Co-Design of Automotive Boardnet Topology and ArchitectureSebastian Post; Christoph Grimm2023Papery2023paper
Co-Developing Firmware and IP with PSSM. Ballance2022Papery2022paper
Co-Developing IP and SoC Bring-Up Firmware with PSSMatthew Ballance, Siemens EDA2022Presentationy2022presentation
Co-Simulating Matlab/Simulink Models in a UVM EnvironmentNeal Okumura, Paul Yue, and Glenn Richards2015Presentationy2015presentation
Co-Simulating Matlab/Simulink Models in a UVM EnvironmentNeal Okumura and Glenn Richards2015Papery2015paper
Code-Test-Verify all for free – Assertions + VerilatorHemamalini Sundaram, Kasthuri Srinivas, Supriya Ummadisetty2023Presentationy2023presentation
Code-Test-Verify all for free – Assertions + VerilatorHemamalini Sundaram, Kasthuri Srinivas, Supriya Ummadisetty2023Papery2023paper
Coding Guidelines and Code GenerationJohn Aynsley and Dr. Christoph Sühnel2014Postery2014poster
Coherency Verification & Deadlock Detection Using Perspec/Portable StimulusMoonki Jang and Phu Huynh2019Presentationy2019presentation
Coherency Verification & Deadlock Detection Using Perspec/Portable StimulusMoonki Jang, Jiwoong Kim, Hyerim Chung, Phu L. Huynh, and Shai Fuss2019Papery2019paper
Combining Simulation with Formal Techniques to Reduce the Overall Verification CycleAneet Agarwal and Gaurav Gupta2010Papery2010paper
Combining Static and Dynamic Low Power Verification for the Power-Aware SoC Sign-offHimanshu Bhatt and Prashanth M2014Papery2014paper
Combining Static and Dynamic Low Power Verification for the Power-Aware SoC Sign-offHimanshu Bhatt, Prashanth M, and Adiel Khan2014Presentationy2014presentation
Command Line Debug Using UVM SequencesMark Peryer2011Papery2011paper
Common Challenges and Solutions to Integrating a UVM TestbenchFrank Verhoorn and Mike Baird2018Presentationy2018presentation
Common Challenges and Solutions to Integrating a UVM Testbench in Place of a Legacy Monolithic Testing EnvironmentFrank Verhoorn and Michael Baird2018Papery2018paper
Compact AI accelerator for embedded applicationsAlexey Shchekin2022Presentationy2022presentation
Comparison of TLM2-Quantum Keeping and TLM+-Resource Modeling with regard to Timing in Virtual PrototypesWolfgang Ecker, Volkan Esen, Rainer Findenigy, Thomas Leitnerz and Michael Velten2011Papery2011paper
Complementing EDA with Meta-Modeling and Code GenerationWolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal2014Papery2014paper
Complementing EDA with Meta-Modelling & Code GenerationWolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal2014Postery2014poster
Complementing EDA with Meta-Modelling and Code GenerationEcker Wolfgang, Michael Velten, Ajay Goyal, and Leily Zafari2014Presentationy2014presentation
Complementing Verification of Highly Configurable Design with Formal TechniquesManik Tyagi, Deepak Jindal2015Postery2015poster
Complete Formal Verification of a Family of Automotive DSPsRafal Baranowski and Marco Trunzer2016Presentationy2016presentation
Complete Formal Verification of a Family of Automotive DSPsRafal Baranowski and Marco Trunzer2016Papery2016paper
Complex Low Power Verification Challenges in NextGen SoCs : Taming the Beast!Abhinav Nawal, Gaurav Jain, and Joachim Geishauser2014Presentationy2014presentation
Complex Low Power Verification Challenges in NextGen SoCs: Taming the Beast!Abhinav Nawal and Gaurav Jain2014Papery2014paper
Complex Safety Mechanisms Require Interoperability and Automation For Validation And Metric ClosureDaeseo Cha, Vedant Garg2023Presentationy2023presentation
Complex Safety Mechanisms Require Interoperability and Automation For Validation And Metric ClosureDaeseo Cha, Vedant Garg, Ann Keffer, Arun Gogineni, James Kim, Woojoo Space Kim, Kunhyuk Kang, Seonil Brian Choi2023Papery2023paper
Compliance Driven Integrated Circuit Development Based on ISO26262Haridas Vilakathara and Manikandan Panchapakesan2014Papery2014paper
Compliance Driven Integrated Circuit Development Based on ISO26262Haridas Vilakathara, Manikantan panchapakesan2014Presentationy2014presentation
CompMon: Ensuring Rigorous Protocol Specification and IP ComplianceRobert Adler, Sava Krstic and Erik Seligman2011Papery2011paper
Comprehensive AMS Verification using Octave, Real Number Modelling and UVMJohn McGrath, Patrick Lynch, and Ali Boumaalif2015Papery2015paper
Comprehensive AMS Verification using Octave, Real Number Modelling and UVMJohn McGrath, Patrick Lynch, and Ali Boumaalif2015Presentationy2015presentation
Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain CrossingsYossi Mirsky2017Presentationy2017presentation
Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain CrossingsYossi Mirsky B.Sc, M.Sc, MBA2017Papery2017paper
Comprehensive Benchmark Results: Comparing Processing-in-Memory Architecture Effectiveness using UPMEM HardwareAmbati Rajashekar, Pranjit Das, Avi kumar Shrivastava, Partha Acharya2023Postery2023poster
Comprehensive IP to SoC CDC Verification Using Hybrid Data ModelAnwesha Choudhury and Ashish Hari2018Postery2018poster
Comprehensive IP to SoC Clock Domain Crossing Verification Using Hybrid Data ModeAnwesha Choudhury and Ashish Hari2018Papery2018paper
Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-ChipsEllie Burns, Gabriel Chidolue, and Guillaume Boillet2018Presentationy2018presentation
Comprehensive Register Description Languages: The case for standardization of RDLs across design domainsDavid C Black and Doug Smith2012Papery2012paper
Comprehensive Systemverilog-Systemc-Vhdl Mixed-Language Design MethodologyRudra Mukherjee, Gaurav Kumar Verma, and Sachin Kakkar2010Papery2010paper
Computational Logistics for Intelligent System DesignSimon Chang2021Presentationy2021presentation
Compute Link Express – CXL – CXL ConsortiumNarasimha Babu2022Presentationy2022presentation
Conditional Delays for Negative Limit Timing Checks in Event Driven SimulationNadeem Kalil and David Roberts2015Papery2015paper
Conditional Delays for Negative Limit Timing Checks in Event Driven SimulationN. Kalil and D. Roberts2015Postery2015poster
Confidently Sign-off Any low-Power Designs without ConsequencesMadhur Bhargava, Jitesh Bansal, and Progyna Khondkar2022Postery2022poster
Confidently Sign-Off Any Low-Power Designs Without ConsequencesMadhur Bharga, Jitesh Bansal and Progyna Khondkar2022Papery2022paper
Configurable Testbench (TB) for Configurable Design IPKilaru Vamsikrishna, Sushrut B Veerapur2022Papery2022paper
Configuration Conundrum: Managing Test Configuration with a Bite Sized SolutionKevin Vasconcellos, Jeff McNeal2021Papery2021paper
Configuration in UVM:The Missing ManualMark Glasser2014Presentationy2014presentation
Configuration in UVM: The Missing ManualMark Glasser2014Papery2014paper
Configuring Your Resources the UVM Way!Parag Goel, Amit Sharma, and Rajiv Hasija2012Papery2012paper
Configuring Your Resources the UVM Way!Parag Goel, Amit Sharma, and Rajiv Hasija2012Presentationy2012presentation
Connecting a Company’s Verification Methodology to Standard Concepts of UVMFrank Poppen, Marco Trunzer, and Jan‐Hendrik Oetjens2014Papery2014paper
Connecting a Company’s Verification Methodology to Standard Concepts of UVMFrank Poppen, Marco Trunzer, and Jan‐Hendrik Oetjens2014Presentationy2014presentation
Connecting Enterprise Applications to Metric Driven VerificationMatt Graham2014Papery2014paper
Connecting Enterprise Applications to Metric Driven VerificationMatt Graham2014Presentationy2014presentation
CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITYBin Ju2014Papery2014paper
CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITYBin Ju2014Postery2014poster
CONNECTING UVM WITH MIXED-SIGNAL DESIGNIvica Ignjić2017Papery2017paper
Connecting UVM with Mixed-Signal DesignIvica Ignjić2017Presentationy2017presentation
Connectivity and BeyondShahid Ikram, Joseph DErrico, Yasmin Farhan, Jim Ellis, and Tushar Parikh2019Presentationy2019presentation
Connectivity and BeyondShahid Ikram, Joseph DErrico, Yasmin Farhan, Jim Ellis, and Tushar Parikh2019Papery2019paper
Conquer the Graphics Legacy: Develop the Customized UVM VIP Embedded a Cycle-based C++ Reference ModelRoman Wang2019Postery2019poster
Conscious of Streams Managing Parallel StimulusJeff Wilcox2012Presentationy2012presentation
Conscious of Streams: Managing Parallel StimulusJeffrey Wilcox and Stephen D’Onofrio2012Papery2012paper
Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL SynthesisRainer Findenig, Thomas Leitner, and Wolfgang Ecker2011Papery2011paper
CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTIONJussi Mäkelä, Martin Fröjd, and Adiel Khan2014Presentationy2014presentation
CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTIONJussi Mäkelä, Martin Fröjd, and Adiel Khan2014Presentationy2014presentation
CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTIONMartin Fröjd, Adiel Khan, and Jussi Mäkelä2014Papery2014paper
Context-Aware DFM Rule Analysis and Scoring Using Machine LearningVikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, and Jonathan Ong2018Papery2018paper
Context-Aware DFM Rule Analysis and Scoring Using Machine LearningVikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, and Jonathan Ong2018Postery2018poster
Control Flow Analysis for Bottom-up Portable Models CreationPetr Bardonek; Marcela Zachariasova2023Papery2023paper
Conversion of Performance Model to Functional ModelH G Pavan Kumar, Sumail Singh Brar, Ashwani Aggarwal, Seonil Brian Choi, Woojoo Space Kim2021Papery2021paper
Counterintuitive approaches to have better communication between UVM and Python for registers with Single Controlling AlgorithmSougata Bhattacharjee2023Postery2023poster
Coverage Acceleration and Testcase Pruning using Smart Stimuli Generator in SOC VerificationRahul Laxkar, Naveen Srivastava, Sekhar Dangudubiyyam2023Presentationy2023presentation
Coverage Acceleration and Testcase Pruning using Smart Stimuli Generator in SOC VerificationRahul Laxkar, Naveen Srivastava, Sekhar Dangudubiyyam2023Papery2023paper
Coverage Closure – Is it a “Game of Dice” or “Top 10 Tests” or “Automated Closure”?Aditya Sharma, T. Nagasundaram, M. Nitin Kumar, Nikhita Raj J 2015Presentationy2015presentation
Coverage Data Exchange is no robbery…or is it?Darron May and Samiran Laha2015Papery2015paper
Coverage Data Exchange is no robbery…or is it?Darron May and Samiran Laha2015Postery2015poster
Coverage Driven Distribution of Constrained Random StimuliRaz Azaria, Amit Metodi, and Marat Teplitsky2015Presentationy2015presentation
Coverage Driven Distribution of Constrained Random StimuliMarat Teplitsky, Amit Metodi, and Raz Azaria2015Papery2015paper
Coverage Driven Signoff with Formal Verification on Power Management IPsBaosheng Wang and Xiaolin Chen2016Papery2016paper
Coverage Driven Signoff with Formal Verification on Power Management IPsBaosheng Wang and Xiaolin Chen2016Postery2016poster
Coverage Driven Verification of an Unmodified DUT within an OVM TestbenchMichael Baird2010Papery2010paper
Coverage Models for Formal VerificationXiushan Feng, Xiaolin Chen, and Abhishek Muchandikar2017Papery2017paper
Coverage Models for Formal VerificationXiushan Feng, Xiaolin Chen, and Abhishek Muchandikar2017Postery2017poster
COVERGATE: Coverage ExposedRich Edelman2020Postery2020poster
COVERGATE: Coverage ExposedRich Edelman2020Papery2020paper
Covering All the bases: Coverage-driven Formal Verification Sign-off of Pipelined Error Detection FilterHarbaksh Gupta, Anshul Jain2023Presentationy2023presentation
Covering All the bases: Coverage-driven Formal Verification Sign-off of Pipelined Error Detection FilterHarbaksh Gupta, Anshul Jain2023Papery2023paper
Covering the Last Mile in SoC-Level Deadlock VerificationJef Verdonck, Khaled Nsaibia, Sagar Dewangan, HarGovind Singh and Roger Sabbagh2019Presentationy2019presentation
Covering the Last Mile in SoC-Level Deadlock VerificationJef Verdonck, Dhruv Gupta, and HarGovind Singh2018Presentationy2018presentation
CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemCHoang M. Le and Rolf Drechsler2014Papery2014paper
CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemCHoang M. Le and Rolf Drechsler2014Presentationy2014presentation
Creating 5G Test Scenarios, the Constrained-Random wayKeshav Kannan, Eric P. Kim2023Presentationy2023presentation
Creating 5G Test Scenarios, the Constrained-Random wayKeshav Kannan and Eric P. Kim2023Papery2023paper
Creating a Complete Low Power Verification Strategy using the Common Power Format and UVMRobert Meyer and Joel Artmann2012Papery2012paper
Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation RequirementsDavid Lacey and Ed Powell2018Papery2018paper
Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation RequirementsDavid Lacey and Ed Powell2018Postery2018poster
Cross Coverage of Power StatesVeeresh Vikram Singh and Awashesh Kumar2016Papery2016paper
Cross-Domain Datapath Validation Using Formal Proof AcceleratorsAarti Gupta, S. S. Bindumadhava, M. Achutha KiranKumar V, Liu Jun B2014Presentationy2014presentation
Customizing UVM Agent Supporting Multi-Layered & TDM ProtocolsAmit Pessach2019Presentationy2019presentation
Customizing UVM Agent Supporting Multi-Layered & TDM ProtocolsAmit Pessach2018Presentationy2018presentation
CXL verification using portable stimulusKarthick Gururaj2023Presentationy2023presentation
Data Flow Based Memory IP Creation InfrastructureAbhilash V Nair, Praveen Buddireddy, Tor Jeremiassen, Rashmi Venkatesh, and Prajakta Bhutada2014Papery2014paper
Data path verification on cross domain with formal scoreboardLiu Jun2014Papery2014paper
Data path verification on cross domain with formal scoreboardLiu Jun2014Postery2014poster
Data-Driven Verification: Driving the next wave of productivity improvementsLarry Melling, Chris Komar, Sharon Rosenberg, Michael Young, and Hanan Moller2019Presentationy2019presentation
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Deadlock Free Design Assurance Using Architectural Formal VerificationBhushan Parikh, Shaman Narayana2023Papery2023paper
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Debug Automation with AICraig Yang, Jaw Lee, Sherwin Lai2023Papery2023paper
Debug Challenges in Low-Power Design and VerificationDurgesh Prasad, Madhur Bhargava, Jitesh Bansal, and Chuck Seeley2015Papery2015paper
Debug Challenges in Low-Power Design and VerificationDurgesh Prasad, Madhur Bhargava, Jitesh Bansal, and Chuck Seeley2015Postery2015poster
Debug Time Reduction by Automatic Generation of Waiver List Using ML TechniquesVardhana M, Akshay Jain, Kota Subba Rao Sajja2022Presentationy2022presentation
Debugging Communicating Systems: The Blame Game – Blurring the Line Between Performance Analysis and DebugRich Edelman and Raghu Ardeishar2014Papery2014paper
Debugging Functional Coverage Models Get The Most Out of Your Cover CrossesMennatallah Amer and Amr Hany2018Papery2018paper
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Debugging Linux Kernel Failures on Virtual PlatformSandeep Jain2017Presentationy2017presentation
Deep Learning for Design and Verification EngineersJohn Aynsley2018Presentationy2018presentation
Deep Learning for EngineersJohn Aynsley2019Presentationy2019presentation
Deep Predictive Coverage CollectionRajarshi Roy, Chinmay Duvedi, Saad Godil, and Mark Williams2018Papery2018paper
Deep Predictive Coverage CollectionRajarshi Roy, Chinmay Duvedi, Saad Godil, and Mark Williams2018Presentationy2018presentation
Defining TLM+Wolfgang Ecker, Volkan Esen, Robert Schwencker, and Michael Velten2010Papery2010paper
DeltaCov: Automated Stimulus Quality Monitoring SystemNimish Girdhar, Srinivas Badam2021Papery2021paper
Democratizing Digital-centric Mixed-signal Verification methodologiesSumit Vishwakarma2023Presentationy2023presentation
Democratizing Formal VerificationTobias Ludwig, Michael Schwarz, Paulius Morkunas, Silvio Santana, Dominik Stoffel, Wolfgang Kunz2021Papery2021paper
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Demystifying the UVM Configuration DatabaseVanessa R. Cooper and Paul Marriott2014Papery2014paper
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Deploying Customized Solution for Graphics Registers with UVM1.2 RALRoman Wang, Nigel Wang, Lunping Guo, Robert Liu, and Jia Zhu2018Presentationy2018presentation
Deploying Customized Solution for Graphics Registers with UVM1.2 RALRoman Wang, Nigel Wang, Lunping Guo, Robert Liu, and Jia Zhu2018Papery2018paper
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Deploying Parameterized Interface with UVMWayne Yun and Shihua Zhang2013Papery2013paper
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Design & Verify Virtual Platform with reusable TLM 2.0Ankush Kumar2015Presentationy2015presentation
Design and verification in ARMHobson Bullman2016Presentationy2016presentation
Design and Verification of a Multichip Coherence ProtocolShahid Ikram, Isam Akkawi, Richard Kessler, Jim Ellis, and David Asher2015Papery2015paper
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Design and Verification of an Image Processing CPU using UVMMilos Becvar and Greg Tumbush2013Papery2013paper
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Design and Verification of the PLL using the new DCO and Its Applications to Built-In Speed Grading of Arithmetic CircuitsYi-Sheng Wang, Hsiang-Kai Teng, Shi-Yu Huang2023Papery2023paper
Design Guidelines for Formal VerificationAnamaya Sullerey2015Presentationy2015presentation
Design Guidelines for Formal VerificationAnamaya Sullerey2015Papery2015paper
Design Methodology for Highly Cycle Accurate SystemC Models with Better PerformanceSimranjit Singh, Prasanth Sasidharan, Sameer Deshpande, and Sandeep Puttappa2014Papery2014paper
Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012Eldon Nelson M.S. P.E.2016Papery2016paper
Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012Eldon Nelson2016Presentationy2016presentation
Design space exploration of PIM (Processing in Memory) & PNC (Processing Near Memory) based on workload characterizationAmarnath, Judhajit2022Presentationy2022presentation
Design verification of a cascaded mmWave FMCW RadarShweta Pujar, Vijay M, Sainath Karlapalem, Dharani Sharavanan, Kavya P S2023Postery2023poster
Design Verification of the Quantum Control StackSeyed Amir Alavi, Samin Ishtiaq, Nick Johnson, Rojalin Mishra, Dwaraka O N, Asher Pearl and Jan Snoeijs2023Papery2023paper
Designers Work Less with Quality Formal Equivalence CheckingOrly Cohen, Moran Gordon, Michael Lifshits, Alexander Nadel, and Vadim Ryvchin2010Papery2010paper
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Designing A PSS Reuse StrategyMatthew Ballance2019Papery2019paper
Designing Portable UVM Test Benches for Reusable IPsXiaoning Zhang, Baosheng Wang, and Terry Li2015Papery2015paper
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Designing PSS Environment Integration for Maximum ReuseMatthew Ballance2020Presentationy2020presentation
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Designing the Future with Efficiency Guidance to Adopting SystemVerilog for Design!Axel Scherer and Junette Tan2015Papery2015paper
Designing, Verifying and Building an Advanced L2 Cache Sub-System using SystemCThomas Tessier, Dr. Hai Lin, Daniel Ringoen, Eileen Hickey, and Steven Anderson2012Papery2012paper
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Detecting Circular Dependencies in Forward Progress CheckersSaurabh Chaurdia, Arun Khurana, Naveen Kumar, Aditya Chaurasiya, Yogesh Mahajan, Prasenjit Biswas2021Papery2021paper
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Detecting Harmful Race Conditions in SystemC Models Using Formal TechniquesSven Beyer and Dominik Strasser2015Papery2015paper
Detection of glitch-prone clock and reset propagation with automated formal analysisKaushal Shah, Sulabh Kumar Khare2021Papery2021paper
Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog AssertionsKelly D. Larson2014Papery2014paper
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Detoxify Your Schedule With A Low-Fat UVM EnvironmentNihar Shah2016Papery2016paper
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Developing & Testing Automotive Software on Multi SoC ECU Architectures using Virtual PrototypingSam Tennent2018Presentationy2018presentation
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Did Power Management Break My CDC Logic? An Integrated Approach to Power Domain and Clock Domain Crossing VerificationAshish Amonkar, Kurt Takara, and Avinash Agrawal2020Presentationy2020presentation
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Digital Eye For Aid of Blind PeopleJagu Naveen Kumar, Pabbuleti Venu2023Postery2023poster
Digital mixed-signal low power verification with Unified Power Format (UPF)Srilakshmi D R and Geeta Krishna Chaitanya Puli2021Postery2021poster
Digital mixed-signal low power verification with Unified power format (UPF)Srilakshmi D R and Geeta Krishna Chaitanya Puli2021Presentationy2021presentation
Digital Transformation of EDA Environments To Accelerate Semiconductor InnovationGuru Charan Prasad Jonnalagadda2022Presentationy2022presentation
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Do You Know What Your Assertions Are up To? A New Approach to Safety Critical VerificationLee C. Smith2016Presentationy2016presentation
Do You Know What Your Assertions Are Up To? A New Approach to Safety Critical VerificationLee C. Smith2016Papery2016paper
Do You Verify Your Verification Components?Josh Rensch and Neil Johnson2016Postery2016poster
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Doing the Impossible: Using Formal Verification on Packet Based Data PathsDoug Smith 2023Papery2023paper
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Don’t delay catching bugs: Using UVM based architecture to model external board delaysAmit Paunikar, Saurabh Arya, Vikas Makhija, and Shaily Khare2018Postery2018poster
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in SiliconAbdelouahab Ayari, Sukriti Bisht, Sulabh Kumar Khare and Kurt Takara2019Presentationy2019presentation
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in SiliconAbdelouahab Ayari, Sukriti Bisht, Sulabh Kumar Khare, and Kurt Takara2018Presentationy2018presentation
Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to SimulationJonathan Bromley2015Presentationy2015presentation
Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to SimulationJonathan Bromley2015Papery2015paper
DPI Redux. Functionality. Speed. Optimization.Rich Edelman, Rohit Jain, and Hui Yin2017Papery2017paper
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