DVCon: United States

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TitleAuthor(s)YearTypeLinkhf:tax:event_yearhf:tax:document_type
“Bounded Proof” sign-off with formal coverageAbhishek Anand, Chinyu Chen, Bathri Narayanan Subramanian, Joe Hupcey2021Papery2021paper
“C” you on the faster side: Accelerating SV DPI based co-simulationParag Goel, Amit Sharma, and Hari Vinodh Balisetty2014Papery2014paper
“C” you on the faster side: Accelerating SV DPI based co-simulationHari Vinod Balisetty, Parag Goel, and Amit Sharma2014Presentationy2014presentation
“In-Emulator” UVM++ Randomized Testbenches for High Performance Functional VerificationAdnan Hamid and David Kelf2022Presentationy2022presentation
“Shift left” Hierarchical Low-Power Static Verification Using SAMBharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal2020Postery2020poster
“Shift left” Hierarchical Low-Power Static Verification Using SAMBharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal2020Papery2020paper
A 30 Minute Project Makeover Using Continuous IntegrationJL Gray2012Papery2012paper
A 30 Minute Project Makeover Using Continuous IntegrationJL Gray and Gordon McGregor2012Presentationy2012presentation
A 360 Degree View of UVM Events – A Case StudyDeepak Kumar E V, Sathish Dadi, and Vikas Billa2016Papery2016paper
A 360 Degree View of UVM Events (A Case Study)Deepak Kumar E V, Sathish Dadi, and Vikas Billa2016Presentationy2016presentation
A Client-Server Method for Register Design and DocumentationScott D Orangio and Julien Gagnon2016Papery2016paper
A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISC V CoreJunaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, Aashir Ahsan2022Presentationy2022presentation
A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISCV CoreJunaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, and Aashir Ahsan2022Papery2022paper
A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance AnalysisBishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel2016Postery2016poster
A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance Analysis.Bishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel2016Papery2016paper
A Coverage-Driven Formal Methodology for Verification Sign-offAng Li, Hao Chen, Jason K Yu, Ee Loon Teoh, and Iswerya Prem Anand2019Papery2019paper
A Coverage-Driven Formal Methodology for Verification Sign-offAng Li, Hao Chen, Jason K Yu, Ee Loon Teoh and, Iswerya Prem Anand2019Presentationy2019presentation
A Dyadic Transformation Based Methodology To Achieve Coverage Driven Verification GoalSwapnajit Mitra2017Presentationy2017presentation
A Dyadic Transformation Based Methodology to Achieve Coverage Driven Verification GoalSwapnajit Mitra2017Papery2017paper
A Dynamic Approach Towards Register Coverage Generation and Collection to Reduce Compilation Overhead of Traditional UVM Register LayersSubham Banerjee2020Presentationy2020presentation
A Formal Verification App Towards Efficient Chip-Wide Clock Gating VerificationProsenjit Chatterjee, Scott Fields, and Syed Suhaib2014Presentationy2014presentation
A Formal Verification App Towards Efficient, Chip-Wide Clock Gating VerificationProsenjit Chatterjee, Scott Fields, and Syed Suhaib2014Papery2014paper
A Guide To Using Continuous Integration Within The Verification EnvironmentJason Sprott2014Presentationy2014presentation
A Hardware and Software integrated power optimization approach with power aware simulations at SOCEldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2023Papery2023paper
A Hardware and Software Integrated Power Optimization Approach with Power Aware Simulations at SOCEldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2023Postery2023poster
A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power IntentVijay Kumar Sankaran, Lakshmanan Balasubramanian, Bharath Kumar Poluri, Venkatraman Ramakrishnan, Badrinarayan Zanwar, and Qingyu Lin2016Papery2016paper
A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power IntentQingyu Lin2016Postery2016poster
A Holistic View of Mixed-Language IP IntegrationPankaj Singh and Gaurav Kumar Verma2010Papery2010paper
A Hybrid Verification Solution to RISC V Vector ExtensionChenghuan Li, Yanhua Feng, Liam Li2022Presentationy2022presentation
A Hybrid Verification Solution to RISC-V Vector ExtensionChenghuan Li, Yanhua Feng, and Liam Li2022Papery2022paper
A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance CorrelationThomas Soong, Christopher Browne, and Chenhui Huang2022Postery2022poster
A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance CorrelationThomas Soong, Chenhui Huang, and Christopher Browne2022Papery2022paper
A Methodology for Power and Energy Efficient Systems DesignMohammed Fahad2023Presentationy2023presentation
A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation AccelerationHorace Chan, Brian Vandegriend, and Efrat Shneydor2015Papery2015paper
A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation AccelerationHorace Chan, Brian Vandegriend, and Efrat Shneydor2015Presentationy2015presentation
A New Approach for Generating View GeneratorsJohannes Schreiner, Felix Willgerodt, and Wolfgang Ecker2017Papery2017paper
A New Approach for Generating View GeneratorsJohannes Schreiner, Felix Willgerodt, and Wolfgang Ecker2017Postery2017poster
A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain CrossingsOmri Dassa, Yossi Mirsky2022Presentationy2022presentation
A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain CrossingsOmri Dassa and Yossi (Joseph) Mirsky2022Papery2022paper
A New Class Of RegistersM. Peryer and D. Aerne2016Papery2016paper
A New Class Of RegistersMark Peryer and David Aerne2016Postery2016poster
A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM DomainsSubham Banerjee and Keshava Krishna Raja2017Papery2017paper
A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM Domains 2017Postery2017poster
A Novel Approach to Verify CNN Based Image Processing UnitSumit K. Kulshreshtha, Raghavendra J N2021Papery2021paper
A Novel Variation-Aware Mixed-Signal Verification Methodology to achieve High-Sigma Variation coverage at nanometer designsTibi Galambos, Sumit Vishwakarma2021Papery2021paper
A Practical Approach to Measuring and Improving the Functional Verification of Embedded SoftwareStéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès2012Papery2012paper
A Practical Approach to Measuring and Improving the Functional Verification of Embedded SoftwareStéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès2012Presentationy2012presentation
A Practical Look @ SystemVerilog Coverage – Tips, Tricks, and GotchasDoug Smith and John Aynsley2011Papery2011paper
A Reusable, Scalable Formal App for Verifying Any Configuration of 3D IC ConnectivityDaniel Han, Walter Sze, Benjamin Ting, and Darrow Chu2013Papery2013paper
A Semi-Formal Verification Methodology for Efficient Configuration Coverage of Highly Configurable Digital DesignsAman Kumar, Sebastian Simon2021Papery2021paper
A Simplified Approach Using UVM Sequence Items for Layering Protocol VerificationHaiqian Yu and Christine Thomson2017Papery2017paper
A Simplified Approach Using UVM Sequence Items for Layering Protocol VerificationChristine Thomson and Haiqian Yu2017Presentationy2017presentation
A Simulation Expert’s Guide to Formally Proving SW Status and InterruptsNeil Johnson2023Presentationy2023presentation
A Simulation Expert’s Guide to Formally Verifying Software Status and InterruptsNeil Johnson2023Papery2023paper
A single generated UVM Register Model to handle multiple DUT configurationsSalvatore Marco Rosselli and Giuseppe Falconeri2020Presentationy2020presentation
A SMART GENERATION OF DESIGN ATTRIBUTES FOR VERIFICATION CLOSURE USING SPECMANMeirav Nitzan, Yael Kinderman, and Efrat Gavish2013Postery2013poster
A Smart Synchronizer – Pragmatic way to cross asynchronous clock domainsPriyank Parakh and Steven J Kommrusch2011Papery2011paper
A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing LogicPriya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed2018Papery2018paper
A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing LogicPriya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed2018Postery2018poster
A Study on Virtual Prototyping based Design Verification MethodologyWoojoo Kim, Kunhyuk Kang, and Seonil Brian Choi.2023Papery2023paper
A Study on Virtual Prototyping based Design Verification MethodologyWoojoo Kim, Kunhyuk Kang, Seonil Brian Choi2023Postery2023poster
A Survey of Machine Learning Applications in Functional VerificationDan Yu, Harry Foster, Tom Fitzpatrick2023Papery2023paper
A Systematic Approach to Power State Table (PST) DebuggingBhaskar Pal, Suman Nandan, Kaushik De, and Rajarshi Mukherjee2013Papery2013paper
A Systematic Approach to Power State Table (PST) DebuggingBhaskar Pal2013Presentationy2013presentation
A Systematic Formal Reuse Methodology: From Blocks to SoC SystemsHao Chen, Yi Sun, Ang Li, and Dorry Cao2020Presentationy2020presentation
A Systematic Take on Addressing Dynamic CDC Verification ChallengesSukriti Bisht, Sulabh Kumar Khare, and Ashish Hari2019Presentationy2019presentation
A Systematic Take on Addressing Dynamic CDC Verification ChallengesSukriti Bisht, Sulabh Kumar Khare, and Ashish Hari2019Papery2019paper
A SystemC Library for Advanced TLM VerificationMarcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen2012Papery2012paper
A SystemC Library for Advanced Verification – Towards an Enhanced OVM/UVM for SystemCMarcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen2012Presentationy2012presentation
A SystemVerilog Framework for Easy Method Advice in Object-oriented Test BenchesEric Ohana2013Postery2013poster
A SystemVerilog Framework for Easy Method Advice in Object-oriented Test BenchesEric Ohana2013Papery2013paper
A SystemVerilog Framework for Efficient Randomization of Images with Complex Inter-Pixel DependenciesAxel Voss, Gabriel Jönsson, and Lars Viklund2020Presentationy2020presentation
A Tale of Two Languages – SystemVerilog and SystemCDavid C Black2013Papery2013paper
A Tale of Two Languages: SystemVerilog & SystemCDavid C Black2013Presentationy2013presentation
A Unified Testbench Architecture Solution for Verifying Variants of A PLL IPDeepa Ananthanarayanan and Malathi Chikkanna2015Presentationy2015presentation
A Unified Testbench Architecture Solution for Verifying Variants of the PLL IPDeepa Ananthanarayanan and Malathi Chikkanna2015Papery2015paper
A Universal DFT Verification Environment: Filling the Gap between Function Simulation and ATE TestRui Huang2016Presentationy2016presentation
A Universal DFT Verification Environment: Filling the Gap between Function Simulation and ATE TestRui Huang2016Papery2016paper
A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline ReceiversJaeha Kim2023Postery2023poster
A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline ReceiversJaeha Kim2023Presentationy2023presentation
A UVM SystemVerilog Testbench for Analog/Mixed-Signal Verification: A Digitally-Programmable Analog Filter ExampleCharles Dančak2022Papery2022paper
A UVM Testbench for Analog Verification: A Programmable Filter ExampleCharles Dančak2022Presentationy2022presentation
A UVM-based Approach for Rapidly Verifying Digital Interrupt StructuresChristoph Rumpler, Alexander W. Rath, Sebastian Simon, and Heinz Endres2016Papery2016paper
A UVM-based Approach for Rapidly Verifying Digital Interrupt StructuresChristoph Rumpler, Alexander W. Rath, and Sebastian Simon2016Presentationy2016presentation
A Volterra-Series Model in SystemVerilog/XMODEL for Nonlinear RF Low-Noise AmplifiersChan Young Park, Jaeha Kim2021Papery2021paper
A Wholistic Approach to Optimizing Your System Verification FlowRoss Dickson, Lance Tamura, Michael Young2023Presentationy2023presentation
Abstract Layer for Firmware Access: A Unique Approach for SOC Functional VerificationGupta Girish Kumar, Rugmini Navia Vishnu, Choudhary Praval, Syed Mobeenuddin2021Papery2021paper
Accelerate Coverage Closure from Day-1 with AI-driven VerificationMalay Ganai, Will Chen, Srikanth Vadanaparthi2023Presentationy2023presentation
Accelerated simulation through design partition and HDL to C++ compilationTheta Yang and Sga Sun2017Papery2017paper
Accelerated simulation through design partition and HDL to C++ compilationTheta Yang2017Presentationy2017presentation
Accelerated Verification of NAND Flash Memory using HW EmulatorSeyeol Yang, Byungwoo Kang, Seoyeon Bae, Choi Jaehyeon, Jintae Kim, Dongeun Lee, Junho Ahn2023Papery2023paper
Accelerated Verification of NAND Flash Memory using HW EmulatorSeyeol Yang, Byungwoo Kang, Seoyeon Bae, Choi Jaehyeon, Jintae Kim, Dongeun Lee, Junho Ahn2023Postery2023poster
Accelerated, High Quality SoC Memory Map Verification using Formal TechniquesCletan Sequeira, Rajesh Kedia, Lokesh Babu Pundreeka, and Bijitendra Mittra2014Papery2014paper
Accelerated, High Quality SoC Memory Map Verification using Formal TechniquesCletan Sequeira, Rajesh Kedia, Lokesh Babu Pundreeka, and Bijitendra Mittra2014Presentationy2014presentation
Accelerating CDC Verification Closure on Gate-Level DesignsAnwesha Choudhury and Ashish Hari2017Presentationy2017presentation
Accelerating CDC Verification Closure on Gate-Level DesignsAnwesha Choudhury and Ashish Hari2017Papery2017paper
Accelerating Error Handling Verification Of Complex Systems: A Formal ApproachBhushan Parikh, Peter Graniello, Neha Rajendra2022Presentationy2022presentation
Accelerating Error Handling Verification of Complex Systems: A Formal ApproachBhushan Parikh, Peter Graniello, and Neha Rajendra2022Papery2022paper
Accelerating Functional Verification Through Stabilization of Testbench Using AI/MLSrikanth Vadanaparthi, Pooja Ganesh, Dharmesh Mahay, Malay Ganai2023Papery2023paper
Accelerating Functional Verification Through Stabilization of Testbench Using AI/MLSrikanth Vadanaparthi, Pooja Ganesh, Dharmesh Mahay, Malay Ganai2023Postery2023poster
Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing ProductsYoga Priya Vadivelu, Arpan Shah, Deepinder Singh Mohoora, Ullas, and Praveen Buddireddy2022Postery2022poster
Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing ProductsYoga Priya Vadivelu, Arpan Shah, Deepinder Singh Mohoora, Ullas, and Praveen Buddireddy2022Papery2022paper
Accelerating SoC Verification Signoff using Save & Restart/Dynamic Test Reload Enhanced Regression flowVanshlata B, Divya M, Garima S, Seonil Brian Choi2021Papery2021paper
Accelerating SOC Verification Using Process Automation and IntegrationSeonghee Yim, Hanna Jang, Sunchang Choi, and Seonil Brian Choi2020Papery2020paper
Accelerating the IP Design Cycle with Formal Techniques Beyond Everyday FPVBhushan Parikh, Shaman Narayana, Buck Lem, David Cassetti2021Papery2021paper
Acceleration of Coreless SoC Design-Verification using PSS on Configurable Testbench in Multi-Link PCIe SubsystemsThanu Ganapathy, Pravin Kumar, Garima Srivastava, Seonil Brian Choi, Harish Peta2021Papery2021paper
Accellera UVM-AMS Standard UpdateTom Fitzpatrick and Tim Pylant2022Presentationy2022presentation
Ace’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power ConsumptionMehul Kumar, Tushar Mattu, and Amir Nilipour2016Papery2016paper
ACE’ing the Verification of a Coherent System Using UVMRomondy Luo, Ray Varghese, Parag Goel, Amit Sharma, Satyapriya Acharya, and Peer Mohammed2012Papery2012paper
ACE’ing the Verification of a Coherent System Using UVMParag Goel; Amit Sharma, Ray Varghese, Romondy Luo, Satyapriya Acharya, Peer Mohammed2012Presentationy2012presentation
ACE’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power ConsumptionMehul Kumar, Shawn Honess, Amir Nilipour, and Tushar Mattu2016Postery2016poster
Achieving First-Time Success with a UPF-based Low Power Verification FlowKjeld Svendsen, Chuck Seeley, and Erich Marschner2011Papery2011paper
Activity Trend Guided Efficient Approach to Peak Power Estimation Using EmulationGaurav Saharawat, Saurabh Jain, and Madhur Bhatia2016Presentationy2016presentation
Activity Trend Guided Efficient Approach to Peak Power Estimation Using EmulationGaurav Saharawat, Saurabh Jain, and Madhur Bhatia2016Papery2016paper
Adapting the UVM Register Abstraction Layer for Burst AccessMark Villalpando2016Presentationy2016presentation
Adapting the UVM Register Layer for Burst AccessM. P. Villalpando2016Papery2016paper
Adaptive Test Generation for Fast Functional Coverage ClosureAzade Nazi, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhoseini, Richard Ho2022Presentationy2022presentation
Adaptive Test Generation for Fast Functional Coverage ClosureAzade Naziz, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhosseiniz, and Richard Ho2022Papery2022paper
Addressing Challenges in Verification of DSP based Audio IPs using a Novel Hybrid-TestBench ArchitectureSuvadeep Bose, Kanak Singh Rajput, Parag S Lonkar, Somasunder K Sreenath2021Papery2021paper
Addressing HW/SW Interface Quality through StandardsDavid Murray and Sean Boyan2012Papery2012paper
Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail MacrosBrandon S. Skaggs2020Papery2020paper
Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail MacrosBrandon Skaggs2020Postery2020poster
Addressing the Challenges of Reset Verification in SoC DesignsChris Kwok, Priya Viswanathan, and Ping Yeung2015Papery2015paper
Addressing the Challenges of Reset Verification in SoC DesignsChris Kwok, Priya Viswanathan, and Ping Yeung2015Presentationy2015presentation
Addressing the verification challenge of SERDES-based FPGAs: The performance/accuracy/efficiency trade-offChris Schalick2011Papery2011paper
Adopting Accellera’s Portable Stimulus Standard: Early Development and Validation using Virtual PrototypingSimranjit Singh, Ashwani Aggarwal, Harshita Prabha, Vishnu Ramadas, Seonil Brian Choi, Woojoo Space Kim2021Papery2021paper
Advanced Digital-Centric Mixed-Signal MethodologyMichael Kontz, David Lacey, and Peter Maroni2015Papery2015paper
Advanced Digital-Centric Mixed-Signal MethodologyMichael Kontz, David Lacey, and Peter Maroni2015Presentationy2015presentation
Advanced Functional Verification for Automotive System on a ChipJaein Hong, Jieun Jeong , Namyoung Kim, Hongkyu Kim, Sungcheol Park,2022Presentationy2022presentation
Advanced Functional Verification for Automotive System on a ChipJaein Hong, Jieun Jeong, Namyoung Kim, Hongkyu Kim, and Sungcheol Park2022Papery2022paper
Advanced Functional Verification Methodology Using UVM For Complex DSP Algorithms In Mixed Signal RF SoCsSrinivas Aluri and Jaimin Mehta2014Presentationy2014presentation
Advanced Functional Verification Methodology Using UVM for complex DSP Algorithms in Mixed Signal RF SoCsSrinivas Aluri and Jaimin Mehta2014Papery2014paper
Advanced SOC Randomization Tool for Complex SOC Level VerificationMarvin Mei, Chris Weller, Michael Sedmak, and Zhiqiang Ren2020Papery2020paper
Advanced Techniques for ARM L2 Cache Verification in an Accelerated Hardware and Software environmentRob Pelt and Jay O’Donnell2012Papery2012paper
Advanced Techniques for AXI Fabric Verification in a Software/Hardware OVM EnvironmentGalen Blake and Steve Chappell2012Papery2012paper
Advanced Testbench Configuration with ResourcesMark Glasser2011Papery2011paper
Advanced Usage Models for Continuous Integration in Verification EnvironmentsJohn Dickol2015Papery2015paper
Advanced Usage Models for Continuous Integration in Verification EnvironmentsJohn Dickol2015Presentationy2015presentation
Advanced UVM Command Line ProcessorSiddharth Krishna Kumar2022Presentationy2022presentation
Advanced UVM Command Line Processor for Central Maintenance and Randomization of Control KnobsSiddharth Krishna Kumar2022Papery2022paper
Advanced UVM Register ModelingMark Litterick and Marcus Harnisch2014Papery2014paper
Advanced UVM Register ModelingMark Litterick2014Presentationy2014presentation
Advanced UVM, Multi-Interface, Reactive Stimulus TechniquesClifford E. Cummings, Stephen DOnofrio, Jeff Wilcox, Heath Chambers2021Papery2021paper
Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification CycleCharul Agrawal, Ashwin Vijayan, and Jakub Dudek2017Papery2017paper
Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification CycleCharul Agrawal, Ashwin Vijayan, and Jakub Dudek2017Presentationy2017presentation
Advancing system-level verification using UVM in SystemCMartin Barnasconi, François Pêcheux, and Thilo Vörtler2014Papery2014paper
Advancing system-level verification using UVM in SystemCMartin Barnasconi, François Pêcheux, and Thilo Vörtler2014Presentationy2014presentation
Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC.Nipun Bhatt2020Papery2020paper
Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC.Nipun Bhatt2020Postery2020poster
An Analytical View of Test Results Using CityScapesMarkus Borg, Andreas Brytting, and Daniel Hansson2018Papery2018paper
An Analytical View of Test Results Using CityScapesMarkus Borg, Andreas Brytting, and Daniel Hansson2018Postery2018poster
An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 ExperienceMahesha Shankarathota, Vybhava S, and Indrajit Dutta2013Postery2013poster
An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 ExperienceMahesha Shankarathota, Vybhava S, and Indrajit Dutta2013Papery2013paper
An Assertion Based Approach to Implement VHDL Functional CoverageSusan Eickhoff, Michael DeBole, and Tagbo Ekwueme-Okoli2014Papery2014paper
An Assertion Based Approach to Implement VHDL Functional CoverageMichael Wazlowski, Susan Eickhoff, Michael Debole, and Tagbo Ekwueme-Okoli2014Presentationy2014presentation
An Automated Validation Framework for Power Management and Data Retention Logic Kits of Standard Cell LibraryAkshay Kamath, Bharath Kumar, Sunil Aggarwal, Subramanian Parameswaran, Parag Lonkar, Debi Prasanna, Somasunder Sreenath2021Papery2021paper
An Automatic Visual System Performance Stress Test for TLM DesignsGeorge F. Frazier, Neeti Bhatnagar, and Woody Larue2011Papery2011paper
An Easy VE/DUV Integration ApproachUwe Simm2015Presentationy2015presentation
An efficient analog fault-injection flow harnessing the power of abstractionRenaud Gillon, Enrico Fraccaroliy, and Franco Fummi2019Postery2019poster
An Efficient and Modular Approach for Formally Verifying Cache ImplementationsM, Achutha KiranKumar V and Abhijith A Bharadwaj2018Papery2018paper
An Efficient and Modular Approach for Formally Verifying Cache implementationsM Achutha KiranKumar V, Abhijith A Bharadwaj, and Bindumadhava S S2018Presentationy2018presentation
An Efficient Method to Verify Dynamic IP Clock Frequency on SOC Level by Using Auto-generated Active Clock MonitorJaecheon Kim, Gyuhong Lee, Yeonho Jeong, Hyunsun Ahn, Daewoo Kim, Seonil Brian Choi2021Papery2021paper
An Enhanced DV Approach for Effectively Verifying High Speed, Low Power MIPI-MPHY 5.0 DesignsEldhose PM, Kuntal Pandya, Sagar Jayakrishanan, Suraj Vijay Shetty, Parag S Lonkar2023Postery2023poster
An Enhanced DV Approach for Effectively Verifying High Speed, Low Power MIPI-MPHY5.0 DesignsEldhose P.M, Sagar Jayakrishnan, Suraj Vijay Shetty, Kuntal Pandya, Parag S. Lonkar2023Papery2023paper
An Enhanced Stimulus and Checking Mechanism on Cache VerificationChenghuan Li, Xiaohui Zhao, and Yunyang Song2019Postery2019poster
An Equivalent Modeling Approach for High-Density DRAM Array System-Level Design-Space Exploration in SystemVerilogSeyoung Kim, Jaeha Kim2021Papery2021paper
An Experience of Complex Design Validation: How to Make Semiformal Verification WorkSabih Agbaria, Dan Carmi, Orly Cohen, Dmitry Korchemny, Michael Lifshits, and Alexander Nadel2010Papery2010paper
An experience to finish code refinement earlier at behavioral levelDae-Han Youn, Sik Kim, Byeong Min, and Kyu-Myung Choi2011Papery2011paper
An Expert System Based Tool for Pre-design Chip Power EstimationBhanu Singh, Arunprasath Shankar, Francis Wolff, and Christos Papachristou2014Presentationy2014presentation
An Expert System Based Tool for Pre-design Chip Power EstimationBhanu Singh, Arunprasath Shankar, Francis Wolff, and Christos Papachristou2014Papery2014paper
An Innovative Methodology for RTL and Verification IP Sharing Between Two ProjectsAlbert Xu and Joonyoung Kim2013Papery2013paper
An Innovative Methodology for RTL and Verification IP Sharing Between Two ProjectsAlbert Xu and Joonyoung Kim2013Postery2013poster
An Innovative Methodology for Verifying Mixed-Signal ComponentsFabian Delguste and Graeme Nunn2011Papery2011paper
An Integrated Framework for Power Aware VerificationHarsh Chilwal, Manish Jain, and Bhaskar Pal2012Papery2012paper
An Overview of Security Annotation for Electronic Design Integration (SA-EDI) StandardSohrab Aftabjahani2022Presentationy2022presentation
Analog Transaction Level Modeling for Verification of Mixed-Signal-BlocksAlexander W. Rath, Volkan Esen, and Wolfgang Ecker2012Papery2012paper
Analog Transaction Level Modeling for Verification of Mixed-Signal-BlocksAlexander W. Rath2012Presentationy2012presentation
Analysis of TLM-2.0 and it’s Applicability to Non Memory Mapped InterfacesGuillaume Delbergue, Mark Burton, and Bertrand Le Gal and Christophe Jego2016Papery2016paper
Analysis of TLM-2.0 and it’s Applicability to Non Memory Mapped InterfacesDelbergue Guillaume2016Presentationy2016presentation
Apples versus Apples HVL Comparison Finally Arrives Comparing OVM SystemVerilog to OVM eBrett Lammers and Riccardo Oddone2010Papery2010paper
Application Abstraction Layer: The Carpool Lane on the SoC Verification FreewayAbhisek Verma, Varun S, and Subramanian Kuppusamy2015Papery2015paper
Application Abstraction Layer: The Carpool Lane on the SoC Verification FreewayAbhisek Verma, Varun S, and Subramanian Kuppusamy2015Presentationy2015presentation
Application of SystemC/SystemC-AMS in 3G Virtual PrototypingTao Huang and Stefan Heinen2011Papery2011paper
Application Optimized HW/SW Design & Verification of a Machine Learning SoCLauro Rizzatti, Russell Klein, Stephen Bailey, and Andrew Meier2020Presentationy2020presentation
Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical PropertiesK. Selyunin, T. Nguyen, A.D. Basa, E. Bartocci, D. Nickovic, and R. Grosu2016Papery2016paper
Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical PropertiesKonstantin Selyunin, Thang Nguyen, Andrei-Daniel Basa, Ezio Bartocci, Dejan Nickovic, and Radu Grosu2016Presentationy2016presentation
Applying Test-Driven Development Methods to Design Verification SoftwareDoug Gibson and Mike Kontz2014Presentationy2014presentation
Applying Test-Driven Development Methods to Design Verification Software in UVM-eDoug Gibson and Mike Kontz2014Papery2014paper
Applying Transaction-level Debug and Analysis Techniques to DUT Simulated Activity Using Data- Mining TechniquesLeo Chai, Bindesh Patel, and Jun Zhao2014Papery2014paper
Applying Transaction-level Debug and Analysis Techniques to DUT Simulated Activity Using Data-Mining TechniquesLeo Chai, Jun Zhao, and Bindesh Patel2014Postery2014poster
Architecting “Checker IP” for AMBA protocolsSrinivasan Venkataramanan and Ajeetha Kumari2017Papery2017paper
Architecting “Checker IP” for AMBA protocolsAjeetha Kumari and Srinivasan Venkataramanan2017Presentationy2017presentation
Architectural Evaluation of a Programmable Accelerator for Baseband, Phy and Video Applications using High Level SynthesisAndy Fox, Tigran Sargsyan, and Steven Anderson2014Papery2014paper
Architectural Evaluation Of a Programmable Accelerator For Baseband, Phy and Video Applications Using High Level SynthesisAndy Fox, Tigran Sargsyan, and Steven Anderson2014Postery2014poster
Architectural Formal Verification of System-Level DeadlocksMandar Munishwar1, Naveed Zaman, Anshul Jain, HarGovind Singh, and Vigyan Singhal2018Papery2018paper
Architectural Formal Verification of System-Level DeadlocksMandar Munishwar and Vigyan Singhal2018Presentationy2018presentation
Are OVM & UVM Macros Evil? A Cost-Benefit AnalysisAdam Erickson2011Papery2011paper
Are you really confident that you are getting the very best from your verification resources?Darron May and Fritz Ferstl2014Postery2014poster
Are you really confident that you are getting the very best from your verification resources?Darron May and Fritz Ferstl2014Papery2014paper
Are You Safe Yet? Safety Mechanism Insertion and ValidationPing Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen2020Papery2020paper
Are You Safe Yet? Safety Mechanism Insertion and ValidationPing Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen2020Postery2020poster
Are You Smarter Than Your Testbench? With a little work you can be.Rich Edelman and Raghu Ardeishar2015Papery2015paper
Are You Smarter Than Your Testbench? With a little work you could beRich Edelman and Raghu Ardeishar2015Postery2015poster
ASIC-Strength Verification in a Fast-Moving FPGA WorldBryan Murdock2013Papery2013paper
ASIC-Strength Verification in a Fast-Moving FPGA WorldBryan Murdock2013Postery2013poster
Assertion Based Self-checking of Analog Circuits for Circuit Verification and Model Validation in SPICE and Co-simulation EnvironmentsLakshmanan Balasubramanian, Pooja Sundar, and Timothy W Fischer2011Papery2011paper
Assertion-based Verification for Analog and Mixed Signal DesignsSrinivas Aluri2017Papery2017paper
Assertion-based Verification for Analog andMixed Signal DesignsSrinivas Aluri2017Postery2017poster
Asynchronous Behaviors Meet Their Match with SystemVerilog AssertionsDoug Smith2010Papery2010paper
Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor CoreWei Foong Thoo and David A. Burgoon2012Presentationy2012presentation
Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor CoreWei Foong Thoo and David A. Burgoon2012Papery2012paper
Automated approach to Register Design and Verification of complex SOCBallori Banerjee, Subashini Rajan, and Silpa Naidu2011Papery2011paper
Automated Comparison of Analog Behavior in a UVM EnvironmentSebastian Simon2014Presentationy2014presentation
Automated Comparison of Analog Behavior in a UVM EnvironmentSebastian Simon, Alexander W. Rath, Volkan Esen, and Wolfgang Ecker2014Papery2014paper
Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal VerificationSamantha Pandez, Christopher Geen2023Papery2023paper
Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal VerificationSamantha Pandez Christopher Geen2023Postery2023poster
Automated Generation of RAL-based UVM SequencesVijayakrishnan Rousseau, Satyajit Sinari, Benjamin Applequist, Timothy McLean, and Geddy Lallathin2020Papery2020paper
Automated Generation of RAL-based UVM SequencesSatyajit Sinari, Timothy McLean, Benjamin Applequist, Vijayakrishnan Rousseau, and Geddy Lallathin2020Presentationy2020presentation
Automated Modeling Testbench Methodology Tested with four Types of PLL ModelsAutomated Modeling Testbench Methodology Tested with four Types of PLL Models2023Papery2023paper
Automated Modeling Testbench Methodology Tested with four Types of PLL ModelsJun Yan, Josh Baylor2023Presentationy2023presentation
Automated Performance Verification to Maximize your ARMv8 pulling powerNick Heaton and Simon Rance2015Papery2015paper
Automated Performance Verification to Maximize your ARMv8 pulling powerNick Heaton and Simon Rance2015Presentationy2015presentation
Automated Physical Hierarchy Generation: Tools and MethodologyAli El-Zein, Alvan Ng, Benedikt Geukes, Maya H. Safieddine, and Wolfgang Roesner2018Presentationy2018presentation
Automated Physical Hierarchy Generation: Tools and MethodologyAli El-Zein, Alvan Ng, Benedikt Geukes, Maya H. Safieddine, and Wolfgang Roesner2018Papery2018paper
Automated RTL Update for Abutted DesignWonkyung Lee, Ayoung Kwon, Soyeong Kwon, Youngsik Kim, and Seonil Brian Choi2020Papery2020paper
Automated RTL Update for Abutted DesignWonkyung Lee, Ayoung Kwon, Soyeong Kwon, Youngsik Kim, and Seonil Brian Choi2020Postery2020poster
Automated Safety Verification for Automotive MicrocontrollersH. Busch2016Papery2016paper
Automated Safety Verification for Automotive MicrocontrollersHolger Busch2016Presentationy2016presentation
Automated Seed Selection Algorithm for an Arbitrary Test SuiteDavid Crutchfield, Brian Craw, Jim Sharpe, and Brandon Skaggs2018Papery2018paper
Automated Seed Selection Algorithm for an Arbitrary Test SuiteDavid Crutchfield, Brian Craw, Jim Sharpe, and Brandon Skaggs2018Presentationy2018presentation
Automated Specification Driven Verification by Generation of SystemVerilog AssertionsFerdinando Pace2016Papery2016paper
Automated Specification Driven Verification by Generation of SystemVerilog AssertionsFerdinando Pace2016Postery2016poster
Automated Test Generation to Verify IP Modified for System Level Power ManagementChristophe Lamard2015Papery2015paper
Automated Test Generation to Verify IP Modified for System Level Power ManagementChristophe Lamard and Frederic Dupuis2015Presentationy2015presentation
Automated Thread Evaluation of Various RISC-V Alternatives using Random Instruction GenerationEndri Kaja, Nicolas Gerlin, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker2023Presentationy2023presentation
Automated Thread Evaluation of Various RISC-V Alternatives using Random Instruction GeneratorsEndri Kaja, Nicolas Gerlin, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker2023Papery2023paper
Automated traceability of requirements in the design and verification process of safety-critical mixed-signal systemsGabriel Pachiana, Maximilian Grunwald, Thomas Markwirth, Christoph Sohrmann2021Papery2021paper
Automatic Debug Down to the LineDaniel Hansson and Patrik Granath2017Postery2017poster
Automatic Debug Down to the Line of CodeDaniel Hansson and Patrik Granath2017Papery2017paper
Automatic Exploration of Hardware/Software PartitioningSyed Abbas Ali Shah, Sven Alexander Horsinka, Basitan Farkas, Rolf Meyer, and Malden Berekovic2017Papery2017paper
Automatic Exploration of Hardware/Software PartitioningSyed Abbas Ali Shah, Sven Alexander Horsinka, Basitan Farkas, Rolf Meyer, and Malden Berekovic2017Presentationy2017presentation
Automatic Generation of Formal Properties for Logic Related to Clock GatingShuqing Zhao and Shan Yan2015Presentationy2015presentation
Automatic Generation of Formal Properties for Logic Related to Clock GatingShuqing Zhao and Shan Yan2015Papery2015paper
Automatic Investigation of Power InefficienciesKuo Kai Hsieh, Li C. Wang, Wen Chen, Monica Farkash, and Jayanta Bhadra2017Presentationy2017presentation
Automatic Investigation of Power InefficiencyKuo-Kai Hsieh, Wen Chen, Monica Farkash, Jayanta Bhadra, and Li-C. Wang2017Papery2017paper
Automatic Partitioning for Multi-core HDL SimulationGaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra2015Papery2015paper
Automatic Partitioning for Multi-core HDL SimulationGaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra2015Postery2015poster
Automatic SOC Test Bench CreationDavid Crutchfield, Mark Glasser, and Stephen Roe2015Papery2015paper
Automatic SOC Test Bench CreationDavid Crutchfield, Mark Glasser, and Stephen Roe2015Presentationy2015presentation
Automatic Translation of Natural Language to SystemVerilog AssertionsAbhishek Chauhan2022Presentationy2022presentation
Automatic Translation of Natural Language to SystemVerilog AssertionsAbhishek Chauhan2022Papery2022paper
Automatic verification for Assertion Based Verification: How can a SPIRIT IP-XACT extension help?Sofiene Mejri and Mirella Negro Marcigaglia2010Papery2010paper
Automating sequence creation from a Microarchitecture specificationSubramoni Parameswaran and Ravi Ram2016Papery2016paper
Automating sequence creation from a microarchitecture specificationSubramoni Parameswaran and Ravi Ram2016Postery2016poster
Automating the formal verification sign-off flow of configurable digital IP’sGiovanni Auditore and Giuseppe Falconeri2019Presentationy2019presentation
Automating the formal verification sign-off flow of configurable digital IP’sGiovanni Auditore and Giuseppe Falconeri2019Papery2019paper
Automation for Early Detection of X-propagation in Power-Aware Simulation Verification using UPF IEEE 1801Tony Gladvin George, Ramesh Kumar, Kyuho Shim, Karan K, Wooseong Cheong, ByungChul Yoo2023Presentationy2023presentation
Automation for Early Detection of Xpropagation in Power-Aware Simulation Verification using UPF IEEE 1801Tony Gladvin George, Ramesh Kumar, Kyuho Shim, Karan K, Wooseong Cheong, ByungChul Yoo2023Papery2023paper
Automation Methodology for Bus Performance Verification using IP-XACTTaeyoung Jeon, Gunseo Koo, Youngsik Kim, Seonil Brian Cho2023Postery2023poster
Automation Methodology for Bus Performance Verification using IP-XACTTaeyoung Jeon, Gunseo Koo, Youngsik Kim, Seonil Brian Choi2023Papery2023paper
Automation of Power On Reset AssertionShang-Wei Tu, Penny Yang, Joydeep Gangopadhyay, and Amol Herlekar2015Papery2015paper
Automation of Reusable Protocol-Agnostic Performance Analysis in UVM EnvironmentsDaniel Carrington, Alan Pippin, and Timothy Pertuit2019Presentationy2019presentation
Automation of Reusable Protocol-Agnostic Performance Analysis in UVM EnvironmentsD. P. Carrington, A. J. Pippin, and T. Pertuit2019Papery2019paper
Avoiding Configuration Madness The Easy WayRich Edelman2023Presentationy2023presentation
Avoiding Configuration Madness The Easy WayRich Edelman2023Papery2023paper
Avoiding Confounding Configurations an RDC Methodology for Configurable DesignsEamonn Quigley, Jonathan Niven, and Kurt Takara2022Postery2022poster
Avoiding Confounding Configurations An RDC Methodology for Configurable DesignsEamonn Quigley, Jonathan Niven, and Kurt Takara2022Papery2022paper
BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering ProblemDebarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, Siddhanth Dhodhi, Spandan Kachhadiya2022Presentationy2022presentation
BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering ProblemDebarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, and Siddhanth Dhodhi2022Papery2022paper
Be a Sequence Pro to Avoid Bad Con SequencesJeff Vance, Jeff Montesano, Mark Litterick, and Jason Sprott2019Presentationy2019presentation
Best Practices in Verification PlanningBenjamin Ehlers and Paul Carzola2013Presentationy2013presentation
Best Practices in Verification PlanningBenjamin Ehlers, Carmen Vargas, and Paul Carzola2013Papery2013paper
Better Living Through Better Class-Based SystemVerilog DebugRich Edelman, Raghu Ardeishar, and John Amouroux2012Papery2012paper
Better Living Through Better Class-Based SystemVerilog DebugRich Edelman, Raghu Ardeishar, and John Amouroux2012Presentationy2012presentation
Beyond UVM: Creating Truly Reusable Protocol LayeringJanick Bergeron2013Presentationy2013presentation
Beyond UVM: Creating Truly Reusable Protocol LayeringJanick Bergeron, Fabian Delguste, Steve Knoeck, Steve McMaster, Aron Pratt, and Amit Sharma2013Papery2013paper
Bi-Directional UVM Agents and Complex Stimulus Generation for UDN and UPF PinsChuck McClish2021Papery2021paper
Big Data in Verification: Making Your Engineers SmarterDavid Lacey, Mike McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson2019Papery2019paper
Big Data in Verification: Making Your Engineers SmarterDavid Lacey, Michael McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson2019Presentationy2019presentation
Blending multiple metrics from multiple verification engines for improved productivityDarron May and Darren Galpin2012Papery2012paper
Boost Verification Results by Bridging the Hardware/Software Testbench GapMatthew Ballance2013Papery2013paper
Boost Verification Results by Bridging the Hw/Sw Testbench GapMatthew Ballance2013Presentationy2013presentation
BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMSAhmed Yehia2013Postery2013poster
BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMSAhmed Yehia2013Papery2013paper
Bridge the Portable Test and Stimulus to UVM Simulation EnvironmentTheta Yang and Evean Qin2018Presentationy2018presentation
Bridge the Portable Test and Stimulus to UVM Simulation EnvironmentTheta Yang and Evean Qin2018Papery2018paper
Bridging the gap between TLM-2.0 AT models and RTL – Experiments and OpportunitiesZhu Zhou, Atul Kwatra, Rajesh Gadiyar, and Paul Heraty2010Papery2010paper
Bringing Constrained Random into SoC SW-driven VerificationAlberto Allara and Fabio Brognara2013Presentationy2013presentation
Bringing Constrained Random into SoC SW-driven VerificationAlberto Allara and Fabio Brognara2013Papery2013paper
BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPSPrabal K Bhattacharya, Swapnajit Chakraborti, Scott Little, Donald O’Riordan, and Vaibhav Bhutani2012Papery2012paper
BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPSPrabal K Bhattacharya, Swapnajit Chakraborti, Donald O’Riordan, Vaibhav Bhutani, and Scott Little2012Presentationy2012presentation
Bringing Regression Systems into the 21st CenturyDavid Crutchfield2014Postery2014poster
Bringing Regression Systems into the 21st CenturyDavid Crutchfield and Thom Ellis2014Papery2014paper
Bringing Reset Domains and Power Domains together – Confronting issues due to UPF InstrumentationInayat Ali, Abdul Moyeen, Manish Bhati, Manjunatha Srinivas2021Papery2021paper
Bringing UVM to VHDLUVVM2022Presentationy2022presentation
Building a Comprehensive Hardware Security MethodologyAnders Nordstrom and Jagadish Nayak2022Presentationy2022presentation
Building Portable Stimulus Into Your IP-XACT FlowPetri Karppa, Lauri Matilainen, and Matthew Balance2018Papery2018paper
Building Portable Stimulus Into your IP-XACT FlowPetri Karppa, Lauri Matilainen, and Matthew Ballance2018Presentationy2018presentation
C through UVM: Effectively using C based models with UVM based Verification IPChris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile2013Papery2013paper
C through UVM: Effectively using C based models with UVM based Verification IPAdiel Khan, Chris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile2013Presentationy2013presentation
Caching Tool Run Results in Large Scale RTL Development ProjectsAshfaq Khan2022Presentationy2022presentation
Caching Tool Run Results in Large-Scale RTL Development ProjectsAshfaq Khan2022Papery2022paper
Calling All Checkers: Collaboratively Utilizing SVA in UVM Based SimulationHui C. K. Zhang2016Postery2016poster
Calling All Checkers: Collaboratively Utilizing SVA In UVM Based SimulationHui K. Zhang2016Papery2016paper
CAMEL – A Flexible Cache Model for Cache VerificationYue Liu, Fang Liu, Yunyang Song2022Presentationy2022presentation
CAMEL: A Flexible Cache Model for Cache VerificationYue Liu, Fang Liu, and Yunyang Song2022Papery2022paper
Can Formal Outsmart Synthesis: Improving Synthesis Quality of Results through Formal MethodsEldon Nelson2021Papery2021paper
Can My Synthesis Compiler Do That?Stuart Sutherland and Don Mills2014Papery2014paper
Can My Synthesis Compiler Do That?Stuart Sutherland and Don Mills2014Presentationy2014presentation
Can You Even Debug a 200M+ Gate Design?Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss2013Papery2013paper
Can You Even Debug a 200M+ Gate Design?Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss2013Postery2013poster
Case Study: Low-Power Verification Success Depends on Positive PessimismJohn Decker2011Papery2011paper
Case Study: Power-aware IP and Mixed-Signal VeriLuke Lang2011Papery2011paper
Case Study: Successes and Challenges of Validation Content ReuseMike Chin, Jonathan Edwards, Josh Pfrimmer, and Hooi Jing Tan2022Papery2022paper
Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation)Vikas Billa and Sundar Haran2018Papery2018paper
Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation)Vikas Billa and Sundar Haran2018Presentationy2018presentation
Challenges in UVM + Python Random Verification Environment for Digital Signal Processing Datapath DesignShabbar Vejlani and Ashok Chandran2016Presentationy2016presentation
Challenges in UVM + Python random verification environment for Digital Signal Processing datapath design.Shabbar Vejlani and Ashok Chandran2016Papery2016paper
Check Low-Power Violations by Using Machine Learning Based ClassifierChi-Ming Lee, Chung-An Wang, Cheok-Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai2023Postery2023poster
Check Low-Power Violations by Using Machine Learning Based ClassifierChi-Ming Lee, Chung-An Wang, Cheok-Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai2023Papery2023paper
Checking security path with formal verification tool: new application developmentJulia Dushina, Saumil Shah, Joerg Mueller, and Vincent Reynolds2014Papery2014paper
Checking Security Path with Formal Verification Tool: New Application DevelopmentJulia Dushina and Joerg Mueller2014Postery2014poster
Chef’s Special – an Efficient Verification Recipe for Maximizing Productivity While Using a Third Party Verification IPVarun S and Bhavik Vyas2012Papery2012paper
Cleaning Out Your Pipes – Pipeline Debug in UVM TestbenchesRich Edelman and Neil Bulman2018Papery2018paper
Cleaning Out Your Pipes – Pipeline Debug in UVM TestbenchesRich Edelman and Neil Bulman2018Postery2018poster
CLOCK DOMAIN CROSSING CHALLENGES IN LATCH BASED DESIGNSMadan Das, PhD, Chris Kwok, and Kurt Takara2018Papery2018paper
Clock Domain Crossing Challenges in Latch Based DesignsMadan Das, Chris Kwok, and Kurt Takara2018Presentationy2018presentation
Clock Domain Crossing Verification in Transistor-level DesignHyungjung Seo, KwangSun Kim, YoungRok Choi, Jihwan Kim, and Jong-Bae Lee2019Postery2019poster
Closing Functional and Structural Coverage on RTL Generated by High-Level SynthesisBryan Bowyer2015Postery2015poster
Closing Functional and Structural Coverage on RTL Generated by High-Level SynthesisB. Bowyer2015Papery2015paper
Closing Functional Coverage With Deep Reinforcement Learning: A Compression Encoder ExampleEric Ohana2023Papery2023paper
Closing Functional Coverage With Deep Reinforcement Learning A Compression Encoder ExampleEric Ohana2023Presentationy2023presentation
Co-Developing Firmware and IP with PSSM. Ballance2022Papery2022paper
Co-Developing IP and SoC Bring-Up Firmware with PSSMatthew Ballance, Siemens EDA2022Presentationy2022presentation
Co-Simulating Matlab/Simulink Models in a UVM EnvironmentNeal Okumura, Paul Yue, and Glenn Richards2015Presentationy2015presentation
Co-Simulating Matlab/Simulink Models in a UVM EnvironmentNeal Okumura and Glenn Richards2015Papery2015paper
Coding Guidelines and Code GenerationJohn Aynsley and Dr. Christoph Sühnel2014Postery2014poster
Coherency Verification & Deadlock Detection Using Perspec/Portable StimulusMoonki Jang, Jiwoong Kim, Hyerim Chung, Phu L. Huynh, and Shai Fuss2019Papery2019paper
Coherency Verification & Deadlock Detection Using Perspec/Portable StimulusMoonki Jang and Phu Huynh2019Presentationy2019presentation
Combining Simulation with Formal Techniques to Reduce the Overall Verification CycleAneet Agarwal and Gaurav Gupta2010Papery2010paper
Command Line Debug Using UVM SequencesMark Peryer2011Papery2011paper
Common Challenges and Solutions to Integrating a UVM TestbenchFrank Verhoorn and Mike Baird2018Presentationy2018presentation
Common Challenges and Solutions to Integrating a UVM Testbench in Place of a Legacy Monolithic Testing EnvironmentFrank Verhoorn and Michael Baird2018Papery2018paper
Comparison of TLM2-Quantum Keeping and TLM+-Resource Modeling with regard to Timing in Virtual PrototypesWolfgang Ecker, Volkan Esen, Rainer Findenigy, Thomas Leitnerz and Michael Velten2011Papery2011paper
Complementing EDA with Meta-Modeling and Code GenerationWolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal2014Papery2014paper
Complementing EDA with Meta-Modelling & Code GenerationWolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal2014Postery2014poster
Complementing EDA with Meta-Modelling and Code GenerationEcker Wolfgang, Michael Velten, Ajay Goyal, and Leily Zafari2014Presentationy2014presentation
Complex Safety Mechanisms Require Interoperability and Automation For Validation And Metric ClosureDaeseo Cha, Vedant Garg, Ann Keffer, Arun Gogineni, James Kim, Woojoo Space Kim, Kunhyuk Kang, Seonil Brian Choi2023Papery2023paper
Complex Safety Mechanisms Require Interoperability and Automation For Validation And Metric ClosureDaeseo Cha, Vedant Garg2023Presentationy2023presentation
CompMon: Ensuring Rigorous Protocol Specification and IP ComplianceRobert Adler, Sava Krstic and Erik Seligman2011Papery2011paper
Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain CrossingsYossi Mirsky2017Presentationy2017presentation
Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain CrossingsYossi Mirsky B.Sc, M.Sc, MBA2017Papery2017paper
Comprehensive IP to SoC CDC Verification Using Hybrid Data ModelAnwesha Choudhury and Ashish Hari2018Postery2018poster
Comprehensive IP to SoC Clock Domain Crossing Verification Using Hybrid Data ModeAnwesha Choudhury and Ashish Hari2018Papery2018paper
Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-ChipsEllie Burns, Gabriel Chidolue, and Guillaume Boillet2018Presentationy2018presentation
Comprehensive Register Description Languages: The case for standardization of RDLs across design domainsDavid C Black and Doug Smith2012Papery2012paper
Comprehensive Systemverilog-Systemc-Vhdl Mixed-Language Design MethodologyRudra Mukherjee, Gaurav Kumar Verma, and Sachin Kakkar2010Papery2010paper
Conditional Delays for Negative Limit Timing Checks in Event Driven SimulationNadeem Kalil and David Roberts2015Papery2015paper
Conditional Delays for Negative Limit Timing Checks in Event Driven SimulationN. Kalil and D. Roberts2015Postery2015poster
Confidently Sign-off Any low-Power Designs without ConsequencesMadhur Bhargava, Jitesh Bansal, and Progyna Khondkar2022Postery2022poster
Confidently Sign-Off Any Low-Power Designs Without ConsequencesMadhur Bharga, Jitesh Bansal and Progyna Khondkar2022Papery2022paper
Configuration Conundrum: Managing Test Configuration with a Bite Sized SolutionKevin Vasconcellos, Jeff McNeal2021Papery2021paper
Configuring Your Resources the UVM Way!Parag Goel, Amit Sharma, and Rajiv Hasija2012Papery2012paper
Configuring Your Resources the UVM Way!Parag Goel, Amit Sharma, and Rajiv Hasija2012Presentationy2012presentation
CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITYBin Ju2014Papery2014paper
CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITYBin Ju2014Postery2014poster
Connecting UVM with Mixed-Signal DesignIvica Ignjić2017Presentationy2017presentation
CONNECTING UVM WITH MIXED-SIGNAL DESIGNIvica Ignjić2017Papery2017paper
Connectivity and BeyondShahid Ikram, Joseph DErrico, Yasmin Farhan, Jim Ellis, and Tushar Parikh2019Papery2019paper
Connectivity and BeyondShahid Ikram, Joseph DErrico, Yasmin Farhan, Jim Ellis, and Tushar Parikh2019Presentationy2019presentation
Conquer the Graphics Legacy: Develop the Customized UVM VIP Embedded a Cycle-based C++ Reference ModelRoman Wang2019Postery2019poster
Conscious of Streams Managing Parallel StimulusJeff Wilcox2012Presentationy2012presentation
Conscious of Streams: Managing Parallel StimulusJeffrey Wilcox and Stephen D’Onofrio2012Papery2012paper
Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL SynthesisRainer Findenig, Thomas Leitner, and Wolfgang Ecker2011Papery2011paper
CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTIONMartin Fröjd, Adiel Khan, and Jussi Mäkelä2014Papery2014paper
CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTIONJussi Mäkelä, Martin Fröjd, and Adiel Khan2014Presentationy2014presentation
CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTIONJussi Mäkelä, Martin Fröjd, and Adiel Khan2014Presentationy2014presentation
Context-Aware DFM Rule Analysis and Scoring Using Machine LearningVikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, and Jonathan Ong2018Papery2018paper
Context-Aware DFM Rule Analysis and Scoring Using Machine LearningVikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, and Jonathan Ong2018Postery2018poster
Conversion of Performance Model to Functional ModelH G Pavan Kumar, Sumail Singh Brar, Ashwani Aggarwal, Seonil Brian Choi, Woojoo Space Kim2021Papery2021paper
Coverage Data Exchange is no robbery…or is it?Darron May and Samiran Laha2015Papery2015paper
Coverage Data Exchange is no robbery…or is it?Darron May and Samiran Laha2015Postery2015poster
Coverage Driven Distribution of Constrained Random StimuliRaz Azaria, Amit Metodi, and Marat Teplitsky2015Presentationy2015presentation
Coverage Driven Distribution of Constrained Random StimuliMarat Teplitsky, Amit Metodi, and Raz Azaria2015Papery2015paper
Coverage Driven Signoff with Formal Verification on Power Management IPsBaosheng Wang and Xiaolin Chen2016Papery2016paper
Coverage Driven Signoff with Formal Verification on Power Management IPsBaosheng Wang and Xiaolin Chen2016Postery2016poster
Coverage Driven Verification of an Unmodified DUT within an OVM TestbenchMichael Baird2010Papery2010paper
Coverage Models for Formal VerificationXiushan Feng, Xiaolin Chen, and Abhishek Muchandikar2017Papery2017paper
Coverage Models for Formal VerificationXiushan Feng, Xiaolin Chen, and Abhishek Muchandikar2017Postery2017poster
COVERGATE: Coverage ExposedRich Edelman2020Papery2020paper
COVERGATE: Coverage ExposedRich Edelman2020Postery2020poster
Creating 5G Test Scenarios, the Constrained-Random wayKeshav Kannan and Eric P. Kim2023Papery2023paper
Creating 5G Test Scenarios, the Constrained-Random wayKeshav Kannan, Eric P. Kim2023Presentationy2023presentation
Creating a Complete Low Power Verification Strategy using the Common Power Format and UVMRobert Meyer and Joel Artmann2012Papery2012paper
Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation RequirementsDavid Lacey and Ed Powell2018Postery2018poster
Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation RequirementsDavid Lacey and Ed Powell2018Papery2018paper
Cross Coverage of Power StatesVeeresh Vikram Singh and Awashesh Kumar2016Papery2016paper
Data-Driven Verification: Driving the next wave of productivity improvementsLarry Melling, Chris Komar, Sharon Rosenberg, Michael Young, and Hanan Moller2019Presentationy2019presentation
DatagenDV: Python Constrained Random Test Stimulus FrameworkJon George, James Mackenzie2023Presentationy2023presentation
DatagenDV: Python Constrained Random Test Stimulus FrameworkJonathan George, James Mackenzie2023Papery2023paper
De-mystifying synchronization between various verification components by employing novel UVM classesPushpal Nautiyal and Gaurav Chugh2016Papery2016paper
De-mystifying synchronization between various verification components by employing novel UVM classesPushpal Nautiyal and Gaurav Chugh2016Postery2016poster
Deadlock Free Design Assurance Using Architectural Formal VerificationBhushan Parikh, Shaman Narayana2023Papery2023paper
Deadlock Free Design Assurance Using Architectural Formal VerificationBhushan Parikh, Shaman Narayana2023Presentationy2023presentation
Deadlock Verification For Dummies – The Easy Way of Using SVA and FormalMark Eslinger, Jeremy Levitt, and Joe Hupcey III2020Postery2020poster
Deadlock Verification For Dummies – The Easy Way Using SVA and FormalMark Eslinger, Jeremy Levitt, and Joe Hupcey III2020Papery2020paper
Dealing with Programmable IP: Where the Rubber Meets the PSS Deployment RoadKarthick Gururaj2020Presentationy2020presentation
Debarshi Chatterjee, Spandan Kachhadia, Chen Luo, Kumar Kushal, Siddhanth DhodhiMoonki Jang2023Presentationy2023presentation
Debug APIs – next wave of innovation in DV spaceSrinivasan Venkataramanan and Ajeetha Kumari2017Postery2017poster
Debug APIs – next wave of innovation in DV spaceSrinivasan Venkataramanan and Ajeetha Kumari2017Papery2017paper
Debug Challenges in Low-Power Design and VerificationDurgesh Prasad, Madhur Bhargava, Jitesh Bansal, and Chuck Seeley2015Postery2015poster
Debug Challenges in Low-Power Design and VerificationDurgesh Prasad, Madhur Bhargava, Jitesh Bansal, and Chuck Seeley2015Papery2015paper
Debugging Communicating Systems: The Blame Game – Blurring the Line Between Performance Analysis and DebugRich Edelman and Raghu Ardeishar2014Papery2014paper
Debugging Functional Coverage Models Get The Most Out of Your Cover CrossesMennatallah Amer and Amr Hany2018Presentationy2018presentation
Debugging Functional Coverage Models Get The Most Out of Your Cover CrossesMennatallah Amer and Amr Hany2018Papery2018paper
Deep Learning for Design and Verification EngineersJohn Aynsley2018Presentationy2018presentation
Deep Learning for EngineersJohn Aynsley2019Presentationy2019presentation
Deep Predictive Coverage CollectionRajarshi Roy, Chinmay Duvedi, Saad Godil, and Mark Williams2018Presentationy2018presentation
Deep Predictive Coverage CollectionRajarshi Roy, Chinmay Duvedi, Saad Godil, and Mark Williams2018Papery2018paper
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Design Guidelines for Formal VerificationAnamaya Sullerey2015Presentationy2015presentation
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Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog AssertionsKelly D. Larson2014Presentationy2014presentation
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Distributed Simulation of UVM TestbenchTheta Yang2016Postery2016poster
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Fast Track Formal Verification SignoffMandar Munishwar, Xiaolin Chen, Arunava Saha, and Sandeep Jana2018Postery2018poster
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Finding a Needle in a Haystack: A Novel Log Analysis Method with Test Clustering in Distributed SystemsJin Choi, Sangwoo Noh, Sooncheol Hong, Hanna Jang, Seonghee Yim, and Seonil Brian Choi2022Papery2022paper
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Flexible Checker: A one-stop shop for all your checkers and a methodology for elastic scoreboardingSaad Zahid, Chandra Veedhi, and Sumit Dhamanwala2019Postery2019poster
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Fnob: Command Line-Dynamic Random GeneratorHaoxiang Hu, Tuo Wang2022Presentationy2022presentation
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FORMAL ARCHITECUTRAL SPECIFICATION AND VERIFICATION OF A COMPLEX SOCShahid Ikram, Isam Akkawi, David Asher, and Jim Ellis2018Papery2018paper
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Formal Methods to Verify the Power Manager for an Embedded Multiprocessor ClusterKesava R. Talu2010Papery2010paper
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Formal Verification of Connections at SoC-levelPenny Yang, Prasun Das, Yuya Kao, and Mingchu Kuo2018Papery2018paper
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Formal Verification of Macro-op Cache for Arm Cortex-A77, and its Successor CPUVaibhav Agrawal2020Presentationy2020presentation
Formal verification of Macro-op cache for Arm Cortex-A77, and its successor CPUVaibhav Agrawal2020Papery2020paper
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Formal Verification Tutorial Breaking Through the Knowledge BarrierSean Safarpour, Iain Singleton, Shaun Feng, Syed Suhaib, and Mandar Munishwar2018Presentationy2018presentation
FPGA-based Clock Domain Crossing Validation for Safety-Critical DesignsAlexander Gnusin2019Papery2019paper
FPGA-based Clock Domain Crossing Validation for Safety-Critical DesignsAlexander Gnusin2019Presentationy2019presentation
Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPFProgyna Khondkar, Ping Yeung, Gabriel Chidolue, Joe Hupcey, Rick Koster, and Madhur Bhargava2017Papery2017paper
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fsim_logic – A VHDL type for testing of FLYTRAPJoanne E. DeGroat, Ph.D.2013Papery2013paper
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Full Flow Clock Domain Crossing – From Source to SiM. Litterick2016Papery2016paper
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Functional Instruction Set Simulator (ISS) of a Neural Network Accelerator IP with native “brain float16” formatDebajyoti Mukherjee, Arpita Sahu, Arathy B S, Saranga P Pogula2023Papery2023paper
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Generation of Constraint Random Transactions for Verification of Mixed-Signal BlocksAlexander W. Rath, Sebastian Simon, Volkan Esen, and Wolfgang Ecker2014Papery2014paper
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GIT for Hardware DesignersJeffery Scott and Sanjeev Singh2015Postery2015poster
Git for Hardware DesignersJeffery Scott and Sanjeev Singh2015Papery2015paper
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GoldMine: Automatic Assertion Generation and Coverage Closure in Design ValidationDavid Sheridan, Lingyi Liu, and Shobha Vasudevan2011Papery2011paper
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GraphCov: RTL Graph Based Test Biasing for Exploring Uncharted Coverage LandscapeDebarshi Chatterjee, Spandan Kachhadia, Chen Luo, Kumar Kushal, Siddhanth Dhodhi2023Papery2023paper
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Graphical Topology Info Structure for Constrained Random Verification in SoC/Subsystem TestsEvean Qin, Richard Bell, and David Chen2019Papery2019paper
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Guaranteed Vertical Reuse – C Execution In A UVM EnvironmentRachida El Idrissi and Alain Gonier2013Presentationy2013presentation
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Hardware Acceleration for UVM Based CLTsMohamed Saheel, Rohith M. S., and Andrew Tan2020Presentationy2020presentation
Hardware Emulation: ICE vs VirtualLauro Rizzatti2016Presentationy2016presentation
Hardware Trojan Design and Detection with Formal Verification to Deep Neural NetworkSi-Han Chen, Yu-Ting Huang, Yi-Chun Kao, Yean-Ru Chen, Shang-Wei Lin, Chia-I Chen2021Papery2021paper
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Hardware/Software Interface Formats A DiscussionRichard Weber, Jamsheed Agahi, Josh Rensch, Eric Sherk2023Presentationy2023presentation
Harnessing the Power of UVM for AMS Verification with XMODELJaeha Kim, Charles Dančak2023Presentationy2023presentation
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Hierarchical UPF: Uniform UPF across FE & BEDipankar Narendra Arya, Balaji Vishwanath Krishnamurthy, Aditi Nigam, Tahir Ali2022Presentationy2022presentation
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High-Level Synthesis Walks the Talk: Synthesizing a Complete Graphics Processing ApplicationThomas Bollaert2011Papery2011paper
High-Speed Interface IP Validation based on Virtual Emulation PlatformJaehun Lee, DaeSeo Cha, and Sungwook Moon2019Papery2019paper
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Highly Configurable UVM Environment for Parameterized IP VerificationHongLiang Liu and Karl Whiting2015Papery2015paper
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Holistic Approach to IO Timing Verification Using Portable Stimulus and AssertionsAmitesh Khandelwal and Praveen Kumar2018Postery2018poster
Holistic Approach to IO Timing Verification Using Portable Stimulus and AssertionsAmitesh Khandelwal and Praveen Kumar2018Papery2018paper
Holistic Automated Code Generation: No Headache with Last-Minute ChangesKlaus Strohmayer and Norbert Pramstaller2012Papery2012paper
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Hopscotch: A Scalable Flow-Graph Based Approach to Formally Specify and Verify Memory-Tagged Store Execution in Arm CPUsAbhinav Sethi, Madhu Iyer, Sai Komaravelli, and Vikram Khosa2022Papery2022paper
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How HLS and SystemC is Delivering on its Promise of Design and Verification ProductivityStuart Swan, Mike Meredith, Matthew Bone, and Rangharajan Venkatesan2020Presentationy2020presentation
How I Learned to Stop Worrying and Love Benchmarking Functional Verification!Mike Bartley2012Presentationy2012presentation
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How to Kill 4 Birds with 1 Stone: Using Formal Verification to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software SpecificationsSaurabh Shrivastava, Kavita Dangi, Darrow Chu, and Mukesh Sharma2013Presentationy2013presentation
How to Kill 4 Birds with 1 Stone: Using Formal Verification to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software SpecificationsSaurabh Shrivastava, Kavita Dangi, Darrow Chu, and Mukesh Sharma2013Papery2013paper
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How to Succeed Against Increasing Pressure: Automated Techniques for Unburdening Verification EngineersJames Pascoe, Pierre Kuhn, and Steve Hobbs2013Papery2013paper
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Hybrid Approach to Testbench and Software Driven Verification on EmulationDebdutta Bhattacharya and Ayub Khan2018Papery2018paper
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Hybrid Emulation: Accelerating Software Driven Verification and DebugIssac P Zacharia and Jitendra Aggarwal2022Postery2022poster
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I’m Still In Love With My X! (but, do I want my X to be an optimist, a pessimist, or eliminated?)Stuart Sutherland2013Presentationy2013presentation
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IEEE-Compatible UVM Reference Implementation and Verification ComponentsJustin Refice, Mark Strickland, Mark Peryer, Uwe Simm, and Srivatsa Vasudevan2018Presentationy2018presentation
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Improving Verification Predictability and Efficiency Using Big DataDarron May2018Postery2018poster
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Introducing your team to an IDES. Dawson and M. Ballance2019Postery2019poster
Introduction to the 5 Levels of RISC-V Processor VerificationSimon Davidmann and Lee Moore2022Presentationy2022presentation
Introspection Into Systemverilog Without Turning It Inside OutDave Rich2016Postery2016poster
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Jump-Start Software-Driven Hardware Verification with a Verification FrameworkMatthew Ballance2015Papery2015paper
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Low Power Apps (Shaping the Future of Low Power Verification)Awashesh Kumar, Madhur Bhargava, Vinay Kumar Singh, and Pankaj Gairola2018Presentationy2018presentation
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Low Power SoC Verification: IP Reuse and Hierarchical Composition using UPFAmit Srivastava, Rudra Mukherjee, Erich Marschner, and Chuck Seeley2012Papery2012paper
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Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design VerificationH. Lin, Z. Ye, and A. M. Khan2017Papery2017paper
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Machine Learning-Guided Stimulus Generation for Functional VerificationS. Gogri, J. Hu, A. Tyagi, M. Quinn S. Ramachandran, F. Batool, and A. Jagadeesh2020Presentationy2020presentation
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Managing Highly Configurable Design and VerificationJ. Ridgeway2018Papery2018paper
Marrying Simulation and Formal Made Easier!Lun Li, Durga Rangarajan, Christopher Starr, and James Greene2016Papery2016paper
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Memory Debugging of Virtual PlatformsGeorge F. Frazier, Neeti Bhatnagar, Qizhang Chao, and Kathy Lang2012Presentationy2012presentation
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Methodology for Separation of Design Concerns Using Conservative RTL Flipflop InferenceMaya H. Safieddine, Fadi A. Zaraket, and Rouwaida Kanj2015Papery2015paper
Metric Driven Mixed-Signal Verification Methodology and Practices for Complex Mixed-signal ASSPsFrank Yang, Andy Sha, Morton Zhao, and Yanping Sha2014Papery2014paper
Metric Driven Mixed-Signal Verification Methodology and Practices for Complex Mixed-signal ASSPsFrank Yang, Andy Sha, Morton Zhao, and Yanping Sha2014Postery2014poster
Metric Driven Verification of Mixed-Signal DesignsNeyaz Khan, Yaron Kashai, and Hao Fang2011Papery2011paper
Metrics Driven Sign-off for SoC Specific Logic (SSL) Using Formal TechniquesAbhinav Gaur, Gaurav Jain, Ruchi Singh2021Papery2021paper
Metrics in SoC VerificationAndreas Meyer and Harry Foster2012Papery2012paper
Micro-processor verification using a C++11 sequence-based stimulus engine.Stephan Bourduas and Chris Mikulis2017Papery2017paper
Micro-processor verification using a C++11 sequence-based stimulus engine.Stephan Bourduas and Chris Mikulis2017Presentationy2017presentation
Migrating from OVM to UVM The Definitive GuideAdiel Khan2013Presentationy2013presentation
Migrating from UVM to UVM-AMSTom Fitzpatrick, Abhijit Madhu Kumar2023Presentationy2023presentation
Migrating to UVM : Conquering LegacySantosh Sarma, Amit Sharma, and Adiel Khan2013Papery2013paper
Mind the Gap(s): Creating & Closing Gaps Between Design and VerificationChris Giles and Kurt Takara2020Presentationy2020presentation
Mining Coverage Data for Test Set Coverage EfficiencyMonica Farkash, Bryan Hickerson, Mike Behm, and Balavinayagam Samynathan2015Papery2015paper
Mining Coverage Data for Test Set Coverage EfficiencyBryan Hickerson, Mike Behm, Balavinayagam Samynathan, and Monica Farkash2015Presentationy2015presentation
Mixed Signal Assertion-Based VerificationPrabal Bhattacharya, Don O’Riordan, and Walter Hartong2011Papery2011paper
Mixed Signal Design Verification: Leveraging the Best of AMS and DMSRock Z. Shi, Padmashree Bhinge, Preston Birdsong, Geeta Chaitanya, and Kunal Jani2022Presentationy2022presentation
Mixed Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP SimulationS. Do, J. Park, D. Kim, and J. Jang2022Presentationy2022presentation
Mixed Signal Verification of a Voltage Regulator using a State Space Approach and the SV-DC extensionsRajat Mitra2016Papery2016paper
Mixed Signal Verification of Dynamic Adaptive Power Management in Low Power SoCNeyaz Khan2010Papery2010paper
Mixed Signal Verification of UPF based designs A Practical ExampleAndrew Milne and Damian Roberts2015Papery2015paper
Mixed Signal Verification of UPF based designs A Practical ExampleAndrew Milne and Damian Roberts2015Presentationy2015presentation
Mixed-abstraction Modeling Approach with Fault Injection for Hardware-Firmware Co-design and Functional Co-verification of an Automotive Airbag System on Chip ProductThang Nguyen, Dipl.-Ing.-Dr. and Dieter Haerle, Dipl.-Ing.2013Presentationy2013presentation
Mixed-abstraction Modeling Approach with Fault Injection for Hardware-Firmware Co-design and Functional Co-verification of an Automotive Airbag System on Chip ProductDipl.-Ing. Dr.-techn. Thang Nguyen, Dipl.-Ing. and Dieter Haerle2013Papery2013paper
Mixed-Signal Design Verification: Leveraging the Best of AMS and DMSRock Z. Shi, Padmashree Bhinge, Preston Birdsong, Geeta Chaitanya, and Kunal Jani2022Papery2022paper
Mixed-Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP SimulationS. Do, J. Park, D. Kim, and J. Jang2022Papery2022paper
Mixed-Signal Systems-on-Chip Design Verification With Automatic Real-Number AbstractionNancy Qiu, Frank Yang, and Himadri De2016Papery2016paper
Mixed-Signal Verification Methodology to Verify Type-C USBVarun R, Vinayak Hegde, and Somasunder Kattepura Sreenath2017Papery2017paper
Mixed-Signal Verification Methodology to Verify USB Type-CVarun R, Vinayak Hegde ans Somasunder Kattepura Sreenath2017Postery2017poster
ML-Based Verification and Regression AutomationAbhishek Chauhan, Asif Ahmad2021Papery2021paper
Modeling a Hierarchical Register Scheme with UVMJoshua Hardy2017Papery2017paper
Modeling a Hierarchical Register Scheme with UVMJoshua Hardy2017Presentationy2017presentation
Modeling Analog Devices Using SV-RNMMariam Maurice2022Postery2022poster
Modeling Analog Devices using SV-RNMMariam Maurice2022Papery2022paper
Modeling Analog Systems Using Full Digital Simulations (A State Space Approach)Rajat K Mitra 2016Presentationy2016presentation
Modeling Memory Coherency During Concurrent/Simultaneous AccessesSubramoni Parameswaran2022Papery2022paper
Modeling Memory Coherency for concurrent/parallel accessesSubramoni Parameswaran2022Presentationy2022presentation
Modeling Memory Coherency for Concurrent/Parallel AccessesSubramoni Parameswaran2022Presentationy2022presentation
Molding Functional Coverage for Highly Configurable IPJ. Ridgeway, K. Chaturvedula, and K. Dhruv2016Papery2016paper
Molding Functional Coverage for Highly Configurable IPJeremy Ridgeway, Kavitha Chaturvedula, and Karishma Dhruv2016Postery2016poster
Monitors, Monitors Everywhere – Who Is Monitoring the MonitorsRich Edelman and Raghu Ardeishar2013Papery2013paper
Monitors, Monitors Everywhere …Rich Edelman and Raghu Ardeishar2013Postery2013poster
Moving beyond Assertions: An Innovative approach to Low-Power Checking using UPF Tcl AppsMadhur Bhargava2019Postery2019poster
MS-SoC Best Practices – Advanced Modeling & Verification Techniques for first-pass successNeyaz Khan, Greg Glennon, and Dan Romaine2013Papery2013paper
Multi-Domain Verification: When Clock, Power and Reset Domains CollidePing Yeung, Erich Marschner, and Kaowen Liu2015Papery2015paper
Multi-Domain Verification: When Clock, Power and Reset Domains CollidePing Yeung, Erich Marschner, and Kaowen Liu2015Presentationy2015presentation
Multi-Language Verification: Solutions for Real World ProblemsBryan Sniderman and Vitaly Yankelevich2014Papery2014paper
Multi-Language Verification: Solutions for Real World ProblemsBryan Sniderman and Vitaly Yankelevich2014Presentationy2014presentation
Multimedia IP DMA verification platformSuhyung Kim, Sangkyu Park, Myungwoo Seo, Sangjin Lee, and Jiyeon Park2020Postery2020poster
Multimedia IP DMA verification platformSuhyung Kim, Sangkyu Park, Myungwoo Seo, Sangjin Lee, and Jiyeon Park2020Papery2020paper
Multiplier-Adder-Converter Linear Piecewise Approximation for Low Power Graphics ApplicationsDina M. Ellaithy, Magdy A. El-Moursy, Amal Zaki, and Abdelhalim Zekry2019Postery2019poster
Multithreading a UVM Testbench for Faster SimulationBenjamin Applequist, Vijayakrishnan Rousseau, Andrew Tan, and Jayasrinivas Sesham2020Presentationy2020presentation
My Testbench Used to Break! Now it Bends (Adapting to Changing Design Configurations)Jeff Vance, Jeff Montesano, Kevin Vasconcellos, and Kevin Johnston2018Presentationy2018presentation
My Testbench Used to Break! Now it Bends: Adapting to Changing Design ConfigurationsJeff Vance, Jeff Montesano, Kevin Vasconcellos, and Kevin Johnston2018Papery2018paper
Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage ModelingJason Sprott, Paul Marriott, and Matt Graham2015Papery2015paper
Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage ModelingJason Sprott, Paul Marriott, and Matt Graham2015Presentationy2015presentation
Never Too Late With Formal: Stepwise Guide for Applying Formal Verification in Post-Silicon Phase to Avoid Re-SpinsAnshul Jain, Aarti Gupta, Achutha KiranKumar V M, Bindumadhava Ss, Shivakumar S Kolar, and Siva Gadey NV2022Papery2022paper
Never Too Late with Formal: Stepwise Guide for Applying FV in Post Si Phase to Avoid Re-SpinsAnshul Jain, Aarti Gupta, Achutha KiranKumar V M, Bindumadhava Ss, Shivakumar S Kolar, Siva Gadey NV2022Presentationy2022presentation
New and active ways to bind to your designKaiming Ho2013Presentationy2013presentation
New and Active Ways to Bind to Your DesignsKaiming Ho2013Papery2013paper
New Challenges in Verification of Mixed-Signal IP and SoC DesignLuke Lang and Christina Chu2012Papery2012paper
New Constrained Random and Metric-Driven Verification Methodology using PythonMarek Cieplucha and Witold A. Pleskacz2017Papery2017paper
New Constrained Random and Metric-Driven Verification Methodology using PythonMarek Ciepłucha and Witold Pleskacz2017Presentationy2017presentation
Next Frontier in Formal VerificationPing Yeung, Rajesh Rathi, Vaibhav Kumar, Puneet Anand, Ravindra Aneja2023Presentationy2023presentation
Next Gen System Design and Verification for TransportationDavid Aerne, Jacob Wiltgen, and Richard Pugh2019Presentationy2019presentation
Next Generation Verification for the Era of AI/ML and 5GFrank Schirrmeister, Pete Hardee, Larry Melling, Amit Dua, and Moshik Rubin2020Presentationy2020presentation
Next-generation Power Aware CDC Verification – What have we learned?Kurt Takara, Chris Kwok, Naman Jain, and Ashish Hari2015Papery2015paper
Next-generation Power Aware CDC Verification What have we learned?Kurt Takara, Chris Kwok, Naman Jain, and Ashish Hari2015Poster