| “Bounded Proof” sign-off with formal coverage | Abhishek Anand, Chinyu Chen, Bathri Narayanan Subramanian, Joe Hupcey | 2021 | Paper | | y2021 | paper |
| “C” you on the faster side: Accelerating SV DPI based co-simulation | Parag Goel, Amit Sharma, and Hari Vinodh Balisetty | 2014 | Paper | | y2014 | paper |
| “C” you on the faster side: Accelerating SV DPI based co-simulation | Hari Vinod Balisetty, Parag Goel, and Amit Sharma | 2014 | Presentation | | y2014 | presentation |
| “In-Emulator” UVM++ Randomized Testbenches for High Performance Functional Verification | Adnan Hamid and David Kelf | 2022 | Presentation | | y2022 | presentation |
| “Shift left” Hierarchical Low-Power Static Verification Using SAM | Bharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal | 2020 | Paper | | y2020 | paper |
| “Shift left” Hierarchical Low-Power Static Verification Using SAM | Bharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal | 2020 | Poster | | y2020 | poster |
| A 30 Minute Project Makeover Using Continuous Integration | JL Gray | 2012 | Paper | | y2012 | paper |
| A 30 Minute Project Makeover Using Continuous Integration | JL Gray and Gordon McGregor | 2012 | Presentation | | y2012 | presentation |
| A 360 Degree View of UVM Events – A Case Study | Deepak Kumar E V, Sathish Dadi, and Vikas Billa | 2016 | Paper | | y2016 | paper |
| A 360 Degree View of UVM Events (A Case Study) | Deepak Kumar E V, Sathish Dadi, and Vikas Billa | 2016 | Presentation | | y2016 | presentation |
| A Client-Server Method for Register Design and Documentation | Scott D Orangio and Julien Gagnon | 2016 | Paper | | y2016 | paper |
| A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISC V Core | Junaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, Aashir Ahsan | 2022 | Presentation | | y2022 | presentation |
| A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISCV Core | Junaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, and Aashir Ahsan | 2022 | Paper | | y2022 | paper |
| A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance Analysis | Bishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel | 2016 | Poster | | y2016 | poster |
| A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance Analysis. | Bishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel | 2016 | Paper | | y2016 | paper |
| A Coverage-Driven Formal Methodology for Verification Sign-off | Ang Li, Hao Chen, Jason K Yu, Ee Loon Teoh, and Iswerya Prem Anand | 2019 | Paper | | y2019 | paper |
| A Coverage-Driven Formal Methodology for Verification Sign-off | Ang Li, Hao Chen, Jason K Yu, Ee Loon Teoh and, Iswerya Prem Anand | 2019 | Presentation | | y2019 | presentation |
| A Dyadic Transformation Based Methodology To Achieve Coverage Driven Verification Goal | Swapnajit Mitra | 2017 | Presentation | | y2017 | presentation |
| A Dyadic Transformation Based Methodology to Achieve Coverage Driven Verification Goal | Swapnajit Mitra | 2017 | Paper | | y2017 | paper |
| A Dynamic Approach Towards Register Coverage Generation and Collection to Reduce Compilation Overhead of Traditional UVM Register Layers | Subham Banerjee | 2020 | Presentation | | y2020 | presentation |
| A Formal Verification App Towards Efficient Chip-Wide Clock Gating Verification | Prosenjit Chatterjee, Scott Fields, and Syed Suhaib | 2014 | Presentation | | y2014 | presentation |
| A Formal Verification App Towards Efficient, Chip-Wide Clock Gating Verification | Prosenjit Chatterjee, Scott Fields, and Syed Suhaib | 2014 | Paper | | y2014 | paper |
| A Guide To Using Continuous Integration Within The Verification Environment | Jason Sprott | 2014 | Presentation | | y2014 | presentation |
| A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power Intent | Vijay Kumar Sankaran, Lakshmanan Balasubramanian, Bharath Kumar Poluri, Venkatraman Ramakrishnan, Badrinarayan Zanwar, and Qingyu Lin | 2016 | Paper | | y2016 | paper |
| A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power Intent | Qingyu Lin | 2016 | Poster | | y2016 | poster |
| A Holistic View of Mixed-Language IP Integration | Pankaj Singh and Gaurav Kumar Verma | 2010 | Paper | | y2010 | paper |
| A Hybrid Verification Solution to RISC V Vector Extension | Chenghuan Li, Yanhua Feng, Liam Li | 2022 | Presentation | | y2022 | presentation |
| A Hybrid Verification Solution to RISC-V Vector Extension | Chenghuan Li, Yanhua Feng, and Liam Li | 2022 | Paper | | y2022 | paper |
| A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation | Thomas Soong, Christopher Browne, and Chenhui Huang | 2022 | Poster | | y2022 | poster |
| A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation | Thomas Soong, Chenhui Huang, and Christopher Browne | 2022 | Paper | | y2022 | paper |
| A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation Acceleration | Horace Chan, Brian Vandegriend, and Efrat Shneydor | 2015 | Paper | | y2015 | paper |
| A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation Acceleration | Horace Chan, Brian Vandegriend, and Efrat Shneydor | 2015 | Presentation | | y2015 | presentation |
| A New Approach for Generating View Generators | Johannes Schreiner, Felix Willgerodt, and Wolfgang Ecker | 2017 | Paper | | y2017 | paper |
| A New Approach for Generating View Generators | Johannes Schreiner, Felix Willgerodt, and Wolfgang Ecker | 2017 | Poster | | y2017 | poster |
| A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain Crossings | Omri Dassa, Yossi Mirsky | 2022 | Presentation | | y2022 | presentation |
| A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain Crossings | Omri Dassa and Yossi (Joseph) Mirsky | 2022 | Paper | | y2022 | paper |
| A New Class Of Registers | Mark Peryer and David Aerne | 2016 | Poster | | y2016 | poster |
| A New Class Of Registers | M. Peryer and D. Aerne | 2016 | Paper | | y2016 | paper |
| A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM Domains | Subham Banerjee and Keshava Krishna Raja | 2017 | Paper | | y2017 | paper |
| A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM Domains | | 2017 | Poster | | y2017 | poster |
| A Novel Approach to Verify CNN Based Image Processing Unit | Sumit K. Kulshreshtha, Raghavendra J N | 2021 | Paper | | y2021 | paper |
| A Novel Variation-Aware Mixed-Signal Verification Methodology to achieve High-Sigma Variation coverage at nanometer designs | Tibi Galambos, Sumit Vishwakarma | 2021 | Paper | | y2021 | paper |
| A Practical Approach to Measuring and Improving the Functional Verification of Embedded Software | Stéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès | 2012 | Paper | | y2012 | paper |
| A Practical Approach to Measuring and Improving the Functional Verification of Embedded Software | Stéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès | 2012 | Presentation | | y2012 | presentation |
| A Practical Look @ SystemVerilog Coverage – Tips, Tricks, and Gotchas | Doug Smith and John Aynsley | 2011 | Paper | | y2011 | paper |
| A Reusable, Scalable Formal App for Verifying Any Configuration of 3D IC Connectivity | Daniel Han, Walter Sze, Benjamin Ting, and Darrow Chu | 2013 | Paper | | y2013 | paper |
| A Semi-Formal Verification Methodology for Efficient Configuration Coverage of Highly Configurable Digital Designs | Aman Kumar, Sebastian Simon | 2021 | Paper | | y2021 | paper |
| A Simplified Approach Using UVM Sequence Items for Layering Protocol Verification | Haiqian Yu and Christine Thomson | 2017 | Paper | | y2017 | paper |
| A Simplified Approach Using UVM Sequence Items for Layering Protocol Verification | Christine Thomson and Haiqian Yu | 2017 | Presentation | | y2017 | presentation |
| A single generated UVM Register Model to handle multiple DUT configurations | Salvatore Marco Rosselli and Giuseppe Falconeri | 2020 | Presentation | | y2020 | presentation |
| A SMART GENERATION OF DESIGN ATTRIBUTES FOR VERIFICATION CLOSURE USING SPECMAN | Meirav Nitzan, Yael Kinderman, and Efrat Gavish | 2013 | Poster | | y2013 | poster |
| A Smart Synchronizer – Pragmatic way to cross asynchronous clock domains | Priyank Parakh and Steven J Kommrusch | 2011 | Paper | | y2011 | paper |
| A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic | Priya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed | 2018 | Paper | | y2018 | paper |
| A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic | Priya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed | 2018 | Poster | | y2018 | poster |
| A Systematic Approach to Power State Table (PST) Debugging | Bhaskar Pal, Suman Nandan, Kaushik De, and Rajarshi Mukherjee | 2013 | Paper | | y2013 | paper |
| A Systematic Approach to Power State Table (PST) Debugging | Bhaskar Pal | 2013 | Presentation | | y2013 | presentation |
| A Systematic Formal Reuse Methodology: From Blocks to SoC Systems | Hao Chen, Yi Sun, Ang Li, and Dorry Cao | 2020 | Presentation | | y2020 | presentation |
| A Systematic Take on Addressing Dynamic CDC Verification Challenges | Sukriti Bisht, Sulabh Kumar Khare, and Ashish Hari | 2019 | Paper | | y2019 | paper |
| A Systematic Take on Addressing Dynamic CDC Verification Challenges | Sukriti Bisht, Sulabh Kumar Khare, and Ashish Hari | 2019 | Presentation | | y2019 | presentation |
| A SystemC Library for Advanced TLM Verification | Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen | 2012 | Paper | | y2012 | paper |
| A SystemC Library for Advanced Verification – Towards an Enhanced OVM/UVM for SystemC | Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen | 2012 | Presentation | | y2012 | presentation |
| A SystemVerilog Framework for Easy Method Advice in Object-oriented Test Benches | Eric Ohana | 2013 | Poster | | y2013 | poster |
| A SystemVerilog Framework for Easy Method Advice in Object-oriented Test Benches | Eric Ohana | 2013 | Paper | | y2013 | paper |
| A SystemVerilog Framework for Efficient Randomization of Images with Complex Inter-Pixel Dependencies | Axel Voss, Gabriel Jönsson, and Lars Viklund | 2020 | Presentation | | y2020 | presentation |
| A Tale of Two Languages – SystemVerilog and SystemC | David C Black | 2013 | Paper | | y2013 | paper |
| A Tale of Two Languages: SystemVerilog & SystemC | David C Black | 2013 | Presentation | | y2013 | presentation |
| A Unified Testbench Architecture Solution for Verifying Variants of A PLL IP | Deepa Ananthanarayanan and Malathi Chikkanna | 2015 | Presentation | | y2015 | presentation |
| A Unified Testbench Architecture Solution for Verifying Variants of the PLL IP | Deepa Ananthanarayanan and Malathi Chikkanna | 2015 | Paper | | y2015 | paper |
| A Universal DFT Verification Environment: Filling the Gap between Function Simulation and ATE Test | Rui Huang | 2016 | Presentation | | y2016 | presentation |
| A Universal DFT Verification Environment: Filling the Gap between Function Simulation and ATE Test | Rui Huang | 2016 | Paper | | y2016 | paper |
| A UVM SystemVerilog Testbench for Analog/Mixed-Signal Verification: A Digitally-Programmable Analog Filter Example | Charles Dančak | 2022 | Paper | | y2022 | paper |
| A UVM Testbench for Analog Verification: A Programmable Filter Example | Charles Dančak | 2022 | Presentation | | y2022 | presentation |
| A UVM-based Approach for Rapidly Verifying Digital Interrupt Structures | Christoph Rumpler, Alexander W. Rath, and Sebastian Simon | 2016 | Presentation | | y2016 | presentation |
| A UVM-based Approach for Rapidly Verifying Digital Interrupt Structures | Christoph Rumpler, Alexander W. Rath, Sebastian Simon, and Heinz Endres | 2016 | Paper | | y2016 | paper |
| A Volterra-Series Model in SystemVerilog/XMODEL for Nonlinear RF Low-Noise Amplifiers | Chan Young Park, Jaeha Kim | 2021 | Paper | | y2021 | paper |
| Abstract Layer for Firmware Access: A Unique Approach for SOC Functional Verification | Gupta Girish Kumar, Rugmini Navia Vishnu, Choudhary Praval, Syed Mobeenuddin | 2021 | Paper | | y2021 | paper |
| Accelerated simulation through design partition and HDL to C++ compilation | Theta Yang | 2017 | Presentation | | y2017 | presentation |
| Accelerated simulation through design partition and HDL to C++ compilation | Theta Yang and Sga Sun | 2017 | Paper | | y2017 | paper |
| Accelerated, High Quality SoC Memory Map Verification using Formal Techniques | Cletan Sequeira, Rajesh Kedia, Lokesh Babu Pundreeka, and Bijitendra Mittra | 2014 | Paper | | y2014 | paper |
| Accelerated, High Quality SoC Memory Map Verification using Formal Techniques | Cletan Sequeira, Rajesh Kedia, Lokesh Babu Pundreeka, and Bijitendra Mittra | 2014 | Presentation | | y2014 | presentation |
| Accelerating CDC Verification Closure on Gate-Level Designs | Anwesha Choudhury and Ashish Hari | 2017 | Presentation | | y2017 | presentation |
| Accelerating CDC Verification Closure on Gate-Level Designs | Anwesha Choudhury and Ashish Hari | 2017 | Paper | | y2017 | paper |
| Accelerating Error Handling Verification Of Complex Systems: A Formal Approach | Bhushan Parikh, Peter Graniello, Neha Rajendra | 2022 | Presentation | | y2022 | presentation |
| Accelerating Error Handling Verification of Complex Systems: A Formal Approach | Bhushan Parikh, Peter Graniello, and Neha Rajendra | 2022 | Paper | | y2022 | paper |
| Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing Products | Yoga Priya Vadivelu, Arpan Shah, Deepinder Singh Mohoora, Ullas, and Praveen Buddireddy | 2022 | Poster | | y2022 | poster |
| Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing Products | Yoga Priya Vadivelu, Arpan Shah, Deepinder Singh Mohoora, Ullas, and Praveen Buddireddy | 2022 | Paper | | y2022 | paper |
| Accelerating SoC Verification Signoff using Save & Restart/Dynamic Test Reload Enhanced Regression flow | Vanshlata B, Divya M, Garima S, Seonil Brian Choi | 2021 | Paper | | y2021 | paper |
| Accelerating SOC Verification Using Process Automation and Integration | Seonghee Yim, Hanna Jang, Sunchang Choi, and Seonil Brian Choi | 2020 | Paper | | y2020 | paper |
| Accelerating the IP Design Cycle with Formal Techniques Beyond Everyday FPV | Bhushan Parikh, Shaman Narayana, Buck Lem, David Cassetti | 2021 | Paper | | y2021 | paper |
| Acceleration of Coreless SoC Design-Verification using PSS on Configurable Testbench in Multi-Link PCIe Subsystems | Thanu Ganapathy, Pravin Kumar, Garima Srivastava, Seonil Brian Choi, Harish Peta | 2021 | Paper | | y2021 | paper |
| Accellera UVM-AMS Standard Update | Tom Fitzpatrick and Tim Pylant | 2022 | Presentation | | y2022 | presentation |
| Ace’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power Consumption | Mehul Kumar, Tushar Mattu, and Amir Nilipour | 2016 | Paper | | y2016 | paper |
| ACE’ing the Verification of a Coherent System Using UVM | Romondy Luo, Ray Varghese, Parag Goel, Amit Sharma, Satyapriya Acharya, and Peer Mohammed | 2012 | Paper | | y2012 | paper |
| ACE’ing the Verification of a Coherent System Using UVM | Parag Goel; Amit Sharma, Ray Varghese, Romondy Luo, Satyapriya Acharya, Peer Mohammed | 2012 | Presentation | | y2012 | presentation |
| ACE’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power Consumption | Mehul Kumar, Shawn Honess, Amir Nilipour, and Tushar Mattu | 2016 | Poster | | y2016 | poster |
| Achieving First-Time Success with a UPF-based Low Power Verification Flow | Kjeld Svendsen, Chuck Seeley, and Erich Marschner | 2011 | Paper | | y2011 | paper |
| Activity Trend Guided Efficient Approach to Peak Power Estimation Using Emulation | Gaurav Saharawat, Saurabh Jain, and Madhur Bhatia | 2016 | Presentation | | y2016 | presentation |
| Activity Trend Guided Efficient Approach to Peak Power Estimation Using Emulation | Gaurav Saharawat, Saurabh Jain, and Madhur Bhatia | 2016 | Paper | | y2016 | paper |
| Adapting the UVM Register Abstraction Layer for Burst Access | Mark Villalpando | 2016 | Presentation | | y2016 | presentation |
| Adapting the UVM Register Layer for Burst Access | M. P. Villalpando | 2016 | Paper | | y2016 | paper |
| Adaptive Test Generation for Fast Functional Coverage Closure | Azade Nazi, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhoseini, Richard Ho | 2022 | Presentation | | y2022 | presentation |
| Adaptive Test Generation for Fast Functional Coverage Closure | Azade Naziz, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhosseiniz, and Richard Ho | 2022 | Paper | | y2022 | paper |
| Addressing Challenges in Verification of DSP based Audio IPs using a Novel Hybrid-TestBench Architecture | Suvadeep Bose, Kanak Singh Rajput, Parag S Lonkar, Somasunder K Sreenath | 2021 | Paper | | y2021 | paper |
| Addressing HW/SW Interface Quality through Standards | David Murray and Sean Boyan | 2012 | Paper | | y2012 | paper |
| Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail Macros | Brandon S. Skaggs | 2020 | Paper | | y2020 | paper |
| Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail Macros | Brandon Skaggs | 2020 | Poster | | y2020 | poster |
| Addressing the Challenges of Reset Verification in SoC Designs | Chris Kwok, Priya Viswanathan, and Ping Yeung | 2015 | Paper | | y2015 | paper |
| Addressing the Challenges of Reset Verification in SoC Designs | Chris Kwok, Priya Viswanathan, and Ping Yeung | 2015 | Presentation | | y2015 | presentation |
| Addressing the verification challenge of SERDES-based FPGAs: The performance/accuracy/efficiency trade-off | Chris Schalick | 2011 | Paper | | y2011 | paper |
| Adopting Accellera’s Portable Stimulus Standard: Early Development and Validation using Virtual Prototyping | Simranjit Singh, Ashwani Aggarwal, Harshita Prabha, Vishnu Ramadas, Seonil Brian Choi, Woojoo Space Kim | 2021 | Paper | | y2021 | paper |
| Advanced Digital-Centric Mixed-Signal Methodology | Michael Kontz, David Lacey, and Peter Maroni | 2015 | Presentation | | y2015 | presentation |
| Advanced Digital-Centric Mixed-Signal Methodology | Michael Kontz, David Lacey, and Peter Maroni | 2015 | Paper | | y2015 | paper |
| Advanced Functional Verification for Automotive System on a Chip | Jaein Hong, Jieun Jeong , Namyoung Kim, Hongkyu Kim, Sungcheol Park, | 2022 | Presentation | | y2022 | presentation |
| Advanced Functional Verification for Automotive System on a Chip | Jaein Hong, Jieun Jeong, Namyoung Kim, Hongkyu Kim, and Sungcheol Park | 2022 | Paper | | y2022 | paper |
| Advanced Functional Verification Methodology Using UVM for complex DSP Algorithms in Mixed Signal RF SoCs | Srinivas Aluri and Jaimin Mehta | 2014 | Paper | | y2014 | paper |
| Advanced Functional Verification Methodology Using UVM For Complex DSP Algorithms In Mixed Signal RF SoCs | Srinivas Aluri and Jaimin Mehta | 2014 | Presentation | | y2014 | presentation |
| Advanced SOC Randomization Tool for Complex SOC Level Verification | Marvin Mei, Chris Weller, Michael Sedmak, and Zhiqiang Ren | 2020 | Paper | | y2020 | paper |
| Advanced Techniques for ARM L2 Cache Verification in an Accelerated Hardware and Software environment | Rob Pelt and Jay O’Donnell | 2012 | Paper | | y2012 | paper |
| Advanced Techniques for AXI Fabric Verification in a Software/Hardware OVM Environment | Galen Blake and Steve Chappell | 2012 | Paper | | y2012 | paper |
| Advanced Testbench Configuration with Resources | Mark Glasser | 2011 | Paper | | y2011 | paper |
| Advanced Usage Models for Continuous Integration in Verification Environments | John Dickol | 2015 | Paper | | y2015 | paper |
| Advanced Usage Models for Continuous Integration in Verification Environments | John Dickol | 2015 | Presentation | | y2015 | presentation |
| Advanced UVM Command Line Processor | Siddharth Krishna Kumar | 2022 | Presentation | | y2022 | presentation |
| Advanced UVM Command Line Processor for Central Maintenance and Randomization of Control Knobs | Siddharth Krishna Kumar | 2022 | Paper | | y2022 | paper |
| Advanced UVM Register Modeling | Mark Litterick and Marcus Harnisch | 2014 | Paper | | y2014 | paper |
| Advanced UVM Register Modeling | Mark Litterick | 2014 | Presentation | | y2014 | presentation |
| Advanced UVM, Multi-Interface, Reactive Stimulus Techniques | Clifford E. Cummings, Stephen DOnofrio, Jeff Wilcox, Heath Chambers | 2021 | Paper | | y2021 | paper |
| Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification Cycle | Charul Agrawal, Ashwin Vijayan, and Jakub Dudek | 2017 | Paper | | y2017 | paper |
| Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification Cycle | Charul Agrawal, Ashwin Vijayan, and Jakub Dudek | 2017 | Presentation | | y2017 | presentation |
| Advancing system-level verification using UVM in SystemC | Martin Barnasconi, François Pêcheux, and Thilo Vörtler | 2014 | Presentation | | y2014 | presentation |
| Advancing system-level verification using UVM in SystemC | Martin Barnasconi, François Pêcheux, and Thilo Vörtler | 2014 | Paper | | y2014 | paper |
| Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC. | Nipun Bhatt | 2020 | Paper | | y2020 | paper |
| Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC. | Nipun Bhatt | 2020 | Poster | | y2020 | poster |
| An Analytical View of Test Results Using CityScapes | Markus Borg, Andreas Brytting, and Daniel Hansson | 2018 | Paper | | y2018 | paper |
| An Analytical View of Test Results Using CityScapes | Markus Borg, Andreas Brytting, and Daniel Hansson | 2018 | Poster | | y2018 | poster |
| An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 Experience | Mahesha Shankarathota, Vybhava S, and Indrajit Dutta | 2013 | Poster | | y2013 | poster |
| An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 Experience | Mahesha Shankarathota, Vybhava S, and Indrajit Dutta | 2013 | Paper | | y2013 | paper |
| An Assertion Based Approach to Implement VHDL Functional Coverage | Susan Eickhoff, Michael DeBole, and Tagbo Ekwueme-Okoli | 2014 | Paper | | y2014 | paper |
| An Assertion Based Approach to Implement VHDL Functional Coverage | Michael Wazlowski, Susan Eickhoff, Michael Debole, and Tagbo Ekwueme-Okoli | 2014 | Presentation | | y2014 | presentation |
| An Automated Validation Framework for Power Management and Data Retention Logic Kits of Standard Cell Library | Akshay Kamath, Bharath Kumar, Sunil Aggarwal, Subramanian Parameswaran, Parag Lonkar, Debi Prasanna, Somasunder Sreenath | 2021 | Paper | | y2021 | paper |
| An Automatic Visual System Performance Stress Test for TLM Designs | George F. Frazier, Neeti Bhatnagar, and Woody Larue | 2011 | Paper | | y2011 | paper |
| An Easy VE/DUV Integration Approach | Uwe Simm | 2015 | Presentation | | y2015 | presentation |
| An efficient analog fault-injection flow harnessing the power of abstraction | Renaud Gillon, Enrico Fraccaroliy, and Franco Fummi | 2019 | Poster | | y2019 | poster |
| An Efficient and Modular Approach for Formally Verifying Cache Implementations | M, Achutha KiranKumar V and Abhijith A Bharadwaj | 2018 | Paper | | y2018 | paper |
| An Efficient and Modular Approach for Formally Verifying Cache implementations | M Achutha KiranKumar V, Abhijith A Bharadwaj, and Bindumadhava S S | 2018 | Presentation | | y2018 | presentation |
| An Efficient Method to Verify Dynamic IP Clock Frequency on SOC Level by Using Auto-generated Active Clock Monitor | Jaecheon Kim, Gyuhong Lee, Yeonho Jeong, Hyunsun Ahn, Daewoo Kim, Seonil Brian Choi | 2021 | Paper | | y2021 | paper |
| An Enhanced Stimulus and Checking Mechanism on Cache Verification | Chenghuan Li, Xiaohui Zhao, and Yunyang Song | 2019 | Poster | | y2019 | poster |
| An Equivalent Modeling Approach for High-Density DRAM Array System-Level Design-Space Exploration in SystemVerilog | Seyoung Kim, Jaeha Kim | 2021 | Paper | | y2021 | paper |
| An Experience of Complex Design Validation: How to Make Semiformal Verification Work | Sabih Agbaria, Dan Carmi, Orly Cohen, Dmitry Korchemny, Michael Lifshits, and Alexander Nadel | 2010 | Paper | | y2010 | paper |
| An experience to finish code refinement earlier at behavioral level | Dae-Han Youn, Sik Kim, Byeong Min, and Kyu-Myung Choi | 2011 | Paper | | y2011 | paper |
| An Expert System Based Tool for Pre-design Chip Power Estimation | Bhanu Singh, Arunprasath Shankar, Francis Wolff, and Christos Papachristou | 2014 | Paper | | y2014 | paper |
| An Expert System Based Tool for Pre-design Chip Power Estimation | Bhanu Singh, Arunprasath Shankar, Francis Wolff, and Christos Papachristou | 2014 | Presentation | | y2014 | presentation |
| An Innovative Methodology for RTL and Verification IP Sharing Between Two Projects | Albert Xu and Joonyoung Kim | 2013 | Poster | | y2013 | poster |
| An Innovative Methodology for RTL and Verification IP Sharing Between Two Projects | Albert Xu and Joonyoung Kim | 2013 | Paper | | y2013 | paper |
| An Innovative Methodology for Verifying Mixed-Signal Components | Fabian Delguste and Graeme Nunn | 2011 | Paper | | y2011 | paper |
| An Integrated Framework for Power Aware Verification | Harsh Chilwal, Manish Jain, and Bhaskar Pal | 2012 | Paper | | y2012 | paper |
| An Overview of Security Annotation for Electronic Design Integration (SA-EDI) Standard | Sohrab Aftabjahani | 2022 | Presentation | | y2022 | presentation |
| Analog Transaction Level Modeling for Verification of Mixed-Signal-Blocks | Alexander W. Rath, Volkan Esen, and Wolfgang Ecker | 2012 | Paper | | y2012 | paper |
| Analog Transaction Level Modeling for Verification of Mixed-Signal-Blocks | Alexander W. Rath | 2012 | Presentation | | y2012 | presentation |
| Analysis of TLM-2.0 and it’s Applicability to Non Memory Mapped Interfaces | Delbergue Guillaume | 2016 | Presentation | | y2016 | presentation |
| Analysis of TLM-2.0 and it’s Applicability to Non Memory Mapped Interfaces | Guillaume Delbergue, Mark Burton, and Bertrand Le Gal and Christophe Jego | 2016 | Paper | | y2016 | paper |
| Apples versus Apples HVL Comparison Finally Arrives Comparing OVM SystemVerilog to OVM e | Brett Lammers and Riccardo Oddone | 2010 | Paper | | y2010 | paper |
| Application Abstraction Layer: The Carpool Lane on the SoC Verification Freeway | Abhisek Verma, Varun S, and Subramanian Kuppusamy | 2015 | Paper | | y2015 | paper |
| Application Abstraction Layer: The Carpool Lane on the SoC Verification Freeway | Abhisek Verma, Varun S, and Subramanian Kuppusamy | 2015 | Presentation | | y2015 | presentation |
| Application of SystemC/SystemC-AMS in 3G Virtual Prototyping | Tao Huang and Stefan Heinen | 2011 | Paper | | y2011 | paper |
| Application Optimized HW/SW Design & Verification of a Machine Learning SoC | Lauro Rizzatti, Russell Klein, Stephen Bailey, and Andrew Meier | 2020 | Presentation | | y2020 | presentation |
| Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical Properties | Konstantin Selyunin, Thang Nguyen, Andrei-Daniel Basa, Ezio Bartocci, Dejan Nickovic, and Radu Grosu | 2016 | Presentation | | y2016 | presentation |
| Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical Properties | K. Selyunin, T. Nguyen, A.D. Basa, E. Bartocci, D. Nickovic, and R. Grosu | 2016 | Paper | | y2016 | paper |
| Applying Test-Driven Development Methods to Design Verification Software | Doug Gibson and Mike Kontz | 2014 | Presentation | | y2014 | presentation |
| Applying Test-Driven Development Methods to Design Verification Software in UVM-e | Doug Gibson and Mike Kontz | 2014 | Paper | | y2014 | paper |
| Applying Transaction-level Debug and Analysis Techniques to DUT Simulated Activity Using Data- Mining Techniques | Leo Chai, Bindesh Patel, and Jun Zhao | 2014 | Paper | | y2014 | paper |
| Applying Transaction-level Debug and Analysis Techniques to DUT Simulated Activity Using Data-Mining Techniques | Leo Chai, Jun Zhao, and Bindesh Patel | 2014 | Poster | | y2014 | poster |
| Architecting “Checker IP” for AMBA protocols | Srinivasan Venkataramanan and Ajeetha Kumari | 2017 | Paper | | y2017 | paper |
| Architecting “Checker IP” for AMBA protocols | Ajeetha Kumari and Srinivasan Venkataramanan | 2017 | Presentation | | y2017 | presentation |
| Architectural Evaluation of a Programmable Accelerator for Baseband, Phy and Video Applications using High Level Synthesis | Andy Fox, Tigran Sargsyan, and Steven Anderson | 2014 | Paper | | y2014 | paper |
| Architectural Evaluation Of a Programmable Accelerator For Baseband, Phy and Video Applications Using High Level Synthesis | Andy Fox, Tigran Sargsyan, and Steven Anderson | 2014 | Poster | | y2014 | poster |
| Architectural Formal Verification of System-Level Deadlocks | Mandar Munishwar1, Naveed Zaman, Anshul Jain, HarGovind Singh, and Vigyan Singhal | 2018 | Paper | | y2018 | paper |
| Architectural Formal Verification of System-Level Deadlocks | Mandar Munishwar and Vigyan Singhal | 2018 | Presentation | | y2018 | presentation |
| Are OVM & UVM Macros Evil? A Cost-Benefit Analysis | Adam Erickson | 2011 | Paper | | y2011 | paper |
| Are you really confident that you are getting the very best from your verification resources? | Darron May and Fritz Ferstl | 2014 | Paper | | y2014 | paper |
| Are you really confident that you are getting the very best from your verification resources? | Darron May and Fritz Ferstl | 2014 | Poster | | y2014 | poster |
| Are You Safe Yet? Safety Mechanism Insertion and Validation | Ping Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen | 2020 | Paper | | y2020 | paper |
| Are You Safe Yet? Safety Mechanism Insertion and Validation | Ping Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen | 2020 | Poster | | y2020 | poster |
| Are You Smarter Than Your Testbench? With a little work you can be. | Rich Edelman and Raghu Ardeishar | 2015 | Paper | | y2015 | paper |
| Are You Smarter Than Your Testbench? With a little work you could be | Rich Edelman and Raghu Ardeishar | 2015 | Poster | | y2015 | poster |
| ASIC-Strength Verification in a Fast-Moving FPGA World | Bryan Murdock | 2013 | Poster | | y2013 | poster |
| ASIC-Strength Verification in a Fast-Moving FPGA World | Bryan Murdock | 2013 | Paper | | y2013 | paper |
| Assertion Based Self-checking of Analog Circuits for Circuit Verification and Model Validation in SPICE and Co-simulation Environments | Lakshmanan Balasubramanian, Pooja Sundar, and Timothy W Fischer | 2011 | Paper | | y2011 | paper |
| Assertion-based Verification for Analog and Mixed Signal Designs | Srinivas Aluri | 2017 | Paper | | y2017 | paper |
| Assertion-based Verification for Analog andMixed Signal Designs | Srinivas Aluri | 2017 | Poster | | y2017 | poster |
| Asynchronous Behaviors Meet Their Match with SystemVerilog Assertions | Doug Smith | 2010 | Paper | | y2010 | paper |
| Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor Core | Wei Foong Thoo and David A. Burgoon | 2012 | Presentation | | y2012 | presentation |
| Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor Core | Wei Foong Thoo and David A. Burgoon | 2012 | Paper | | y2012 | paper |
| Automated approach to Register Design and Verification of complex SOC | Ballori Banerjee, Subashini Rajan, and Silpa Naidu | 2011 | Paper | | y2011 | paper |
| Automated Comparison of Analog Behavior in a UVM Environment | Sebastian Simon, Alexander W. Rath, Volkan Esen, and Wolfgang Ecker | 2014 | Paper | | y2014 | paper |
| Automated Comparison of Analog Behavior in a UVM Environment | Sebastian Simon | 2014 | Presentation | | y2014 | presentation |
| Automated Generation of RAL-based UVM Sequences | Vijayakrishnan Rousseau, Satyajit Sinari, Benjamin Applequist, Timothy McLean, and Geddy Lallathin | 2020 | Paper | | y2020 | paper |
| Automated Generation of RAL-based UVM Sequences | Satyajit Sinari, Timothy McLean, Benjamin Applequist, Vijayakrishnan Rousseau, and Geddy Lallathin | 2020 | Presentation | | y2020 | presentation |
| Automated Performance Verification to Maximize your ARMv8 pulling power | Nick Heaton and Simon Rance | 2015 | Paper | | y2015 | paper |
| Automated Performance Verification to Maximize your ARMv8 pulling power | Nick Heaton and Simon Rance | 2015 | Presentation | | y2015 | presentation |
| Automated Physical Hierarchy Generation: Tools and Methodology | Ali El-Zein, Alvan Ng, Benedikt Geukes, Maya H. Safieddine, and Wolfgang Roesner | 2018 | Paper | | y2018 | paper |
| Automated Physical Hierarchy Generation: Tools and Methodology | Ali El-Zein, Alvan Ng, Benedikt Geukes, Maya H. Safieddine, and Wolfgang Roesner | 2018 | Presentation | | y2018 | presentation |
| Automated RTL Update for Abutted Design | Wonkyung Lee, Ayoung Kwon, Soyeong Kwon, Youngsik Kim, and Seonil Brian Choi | 2020 | Paper | | y2020 | paper |
| Automated RTL Update for Abutted Design | Wonkyung Lee, Ayoung Kwon, Soyeong Kwon, Youngsik Kim, and Seonil Brian Choi | 2020 | Poster | | y2020 | poster |
| Automated Safety Verification for Automotive Microcontrollers | Holger Busch | 2016 | Presentation | | y2016 | presentation |
| Automated Safety Verification for Automotive Microcontrollers | H. Busch | 2016 | Paper | | y2016 | paper |
| Automated Seed Selection Algorithm for an Arbitrary Test Suite | David Crutchfield, Brian Craw, Jim Sharpe, and Brandon Skaggs | 2018 | Paper | | y2018 | paper |
| Automated Seed Selection Algorithm for an Arbitrary Test Suite | David Crutchfield, Brian Craw, Jim Sharpe, and Brandon Skaggs | 2018 | Presentation | | y2018 | presentation |
| Automated Specification Driven Verification by Generation of SystemVerilog Assertions | Ferdinando Pace | 2016 | Poster | | y2016 | poster |
| Automated Specification Driven Verification by Generation of SystemVerilog Assertions | Ferdinando Pace | 2016 | Paper | | y2016 | paper |
| Automated Test Generation to Verify IP Modified for System Level Power Management | Christophe Lamard and Frederic Dupuis | 2015 | Presentation | | y2015 | presentation |
| Automated Test Generation to Verify IP Modified for System Level Power Management | Christophe Lamard | 2015 | Paper | | y2015 | paper |
| Automated traceability of requirements in the design and verification process of safety-critical mixed-signal systems | Gabriel Pachiana, Maximilian Grunwald, Thomas Markwirth, Christoph Sohrmann | 2021 | Paper | | y2021 | paper |
| Automatic Debug Down to the Line | Daniel Hansson and Patrik Granath | 2017 | Poster | | y2017 | poster |
| Automatic Debug Down to the Line of Code | Daniel Hansson and Patrik Granath | 2017 | Paper | | y2017 | paper |
| Automatic Exploration of Hardware/Software Partitioning | Syed Abbas Ali Shah, Sven Alexander Horsinka, Basitan Farkas, Rolf Meyer, and Malden Berekovic | 2017 | Paper | | y2017 | paper |
| Automatic Exploration of Hardware/Software Partitioning | Syed Abbas Ali Shah, Sven Alexander Horsinka, Basitan Farkas, Rolf Meyer, and Malden Berekovic | 2017 | Presentation | | y2017 | presentation |
| Automatic Generation of Formal Properties for Logic Related to Clock Gating | Shuqing Zhao and Shan Yan | 2015 | Presentation | | y2015 | presentation |
| Automatic Generation of Formal Properties for Logic Related to Clock Gating | Shuqing Zhao and Shan Yan | 2015 | Paper | | y2015 | paper |
| Automatic Investigation of Power Inefficiencies | Kuo Kai Hsieh, Li C. Wang, Wen Chen, Monica Farkash, and Jayanta Bhadra | 2017 | Presentation | | y2017 | presentation |
| Automatic Investigation of Power Inefficiency | Kuo-Kai Hsieh, Wen Chen, Monica Farkash, Jayanta Bhadra, and Li-C. Wang | 2017 | Paper | | y2017 | paper |
| Automatic Partitioning for Multi-core HDL Simulation | Gaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra | 2015 | Paper | | y2015 | paper |
| Automatic Partitioning for Multi-core HDL Simulation | Gaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra | 2015 | Poster | | y2015 | poster |
| Automatic SOC Test Bench Creation | David Crutchfield, Mark Glasser, and Stephen Roe | 2015 | Paper | | y2015 | paper |
| Automatic SOC Test Bench Creation | David Crutchfield, Mark Glasser, and Stephen Roe | 2015 | Presentation | | y2015 | presentation |
| Automatic Translation of Natural Language to SystemVerilog Assertions | Abhishek Chauhan | 2022 | Presentation | | y2022 | presentation |
| Automatic Translation of Natural Language to SystemVerilog Assertions | Abhishek Chauhan | 2022 | Paper | | y2022 | paper |
| Automatic verification for Assertion Based Verification: How can a SPIRIT IP-XACT extension help? | Sofiene Mejri and Mirella Negro Marcigaglia | 2010 | Paper | | y2010 | paper |
| Automating sequence creation from a microarchitecture specification | Subramoni Parameswaran and Ravi Ram | 2016 | Poster | | y2016 | poster |
| Automating sequence creation from a Microarchitecture specification | Subramoni Parameswaran and Ravi Ram | 2016 | Paper | | y2016 | paper |
| Automating the formal verification sign-off flow of configurable digital IP’s | Giovanni Auditore and Giuseppe Falconeri | 2019 | Paper | | y2019 | paper |
| Automating the formal verification sign-off flow of configurable digital IP’s | Giovanni Auditore and Giuseppe Falconeri | 2019 | Presentation | | y2019 | presentation |
| Automation of Power On Reset Assertion | Shang-Wei Tu, Penny Yang, Joydeep Gangopadhyay, and Amol Herlekar | 2015 | Paper | | y2015 | paper |
| Automation of Reusable Protocol-Agnostic Performance Analysis in UVM Environments | D. P. Carrington, A. J. Pippin, and T. Pertuit | 2019 | Paper | | y2019 | paper |
| Automation of Reusable Protocol-Agnostic Performance Analysis in UVM Environments | Daniel Carrington, Alan Pippin, and Timothy Pertuit | 2019 | Presentation | | y2019 | presentation |
| Avoiding Confounding Configurations an RDC Methodology for Configurable Designs | Eamonn Quigley, Jonathan Niven, and Kurt Takara | 2022 | Poster | | y2022 | poster |
| Avoiding Confounding Configurations An RDC Methodology for Configurable Designs | Eamonn Quigley, Jonathan Niven, and Kurt Takara | 2022 | Paper | | y2022 | paper |
| BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering Problem | Debarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, Siddhanth Dhodhi, Spandan Kachhadiya | 2022 | Presentation | | y2022 | presentation |
| BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering Problem | Debarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, and Siddhanth Dhodhi | 2022 | Paper | | y2022 | paper |
| Be a Sequence Pro to Avoid Bad Con Sequences | Jeff Vance, Jeff Montesano, Mark Litterick, and Jason Sprott | 2019 | Presentation | | y2019 | presentation |
| Best Practices in Verification Planning | Benjamin Ehlers, Carmen Vargas, and Paul Carzola | 2013 | Paper | | y2013 | paper |
| Best Practices in Verification Planning | Benjamin Ehlers and Paul Carzola | 2013 | Presentation | | y2013 | presentation |
| Better Living Through Better Class-Based SystemVerilog Debug | Rich Edelman, Raghu Ardeishar, and John Amouroux | 2012 | Paper | | y2012 | paper |
| Better Living Through Better Class-Based SystemVerilog Debug | Rich Edelman, Raghu Ardeishar, and John Amouroux | 2012 | Presentation | | y2012 | presentation |
| Beyond UVM: Creating Truly Reusable Protocol Layering | Janick Bergeron, Fabian Delguste, Steve Knoeck, Steve McMaster, Aron Pratt, and Amit Sharma | 2013 | Paper | | y2013 | paper |
| Beyond UVM: Creating Truly Reusable Protocol Layering | Janick Bergeron | 2013 | Presentation | | y2013 | presentation |
| Bi-Directional UVM Agents and Complex Stimulus Generation for UDN and UPF Pins | Chuck McClish | 2021 | Paper | | y2021 | paper |
| Big Data in Verification: Making Your Engineers Smarter | David Lacey, Mike McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson | 2019 | Paper | | y2019 | paper |
| Big Data in Verification: Making Your Engineers Smarter | David Lacey, Michael McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson | 2019 | Presentation | | y2019 | presentation |
| Blending multiple metrics from multiple verification engines for improved productivity | Darron May and Darren Galpin | 2012 | Paper | | y2012 | paper |
| Boost Verification Results by Bridging the Hardware/Software Testbench Gap | Matthew Ballance | 2013 | Paper | | y2013 | paper |
| Boost Verification Results by Bridging the Hw/Sw Testbench Gap | Matthew Ballance | 2013 | Presentation | | y2013 | presentation |
| BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMS | Ahmed Yehia | 2013 | Poster | | y2013 | poster |
| BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMS | Ahmed Yehia | 2013 | Paper | | y2013 | paper |
| Bridge the Portable Test and Stimulus to UVM Simulation Environment | Theta Yang and Evean Qin | 2018 | Paper | | y2018 | paper |
| Bridge the Portable Test and Stimulus to UVM Simulation Environment | Theta Yang and Evean Qin | 2018 | Presentation | | y2018 | presentation |
| Bridging the gap between TLM-2.0 AT models and RTL – Experiments and Opportunities | Zhu Zhou, Atul Kwatra, Rajesh Gadiyar, and Paul Heraty | 2010 | Paper | | y2010 | paper |
| Bringing Constrained Random into SoC SW-driven Verification | Alberto Allara and Fabio Brognara | 2013 | Paper | | y2013 | paper |
| Bringing Constrained Random into SoC SW-driven Verification | Alberto Allara and Fabio Brognara | 2013 | Presentation | | y2013 | presentation |
| BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPS | Prabal K Bhattacharya, Swapnajit Chakraborti, Scott Little, Donald O’Riordan, and Vaibhav Bhutani | 2012 | Paper | | y2012 | paper |
| BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPS | Prabal K Bhattacharya, Swapnajit Chakraborti, Donald O’Riordan, Vaibhav Bhutani, and Scott Little | 2012 | Presentation | | y2012 | presentation |
| Bringing Regression Systems into the 21st Century | David Crutchfield and Thom Ellis | 2014 | Paper | | y2014 | paper |
| Bringing Regression Systems into the 21st Century | David Crutchfield | 2014 | Poster | | y2014 | poster |
| Bringing Reset Domains and Power Domains together – Confronting issues due to UPF Instrumentation | Inayat Ali, Abdul Moyeen, Manish Bhati, Manjunatha Srinivas | 2021 | Paper | | y2021 | paper |
| Bringing UVM to VHDL | UVVM | 2022 | Presentation | | y2022 | presentation |
| Building a Comprehensive Hardware Security Methodology | Anders Nordstrom and Jagadish Nayak | 2022 | Presentation | | y2022 | presentation |
| Building Portable Stimulus Into Your IP-XACT Flow | Petri Karppa, Lauri Matilainen, and Matthew Balance | 2018 | Paper | | y2018 | paper |
| Building Portable Stimulus Into your IP-XACT Flow | Petri Karppa, Lauri Matilainen, and Matthew Ballance | 2018 | Presentation | | y2018 | presentation |
| C through UVM: Effectively using C based models with UVM based Verification IP | Adiel Khan, Chris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile | 2013 | Presentation | | y2013 | presentation |
| C through UVM: Effectively using C based models with UVM based Verification IP | Chris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile | 2013 | Paper | | y2013 | paper |
| Caching Tool Run Results in Large Scale RTL Development Projects | Ashfaq Khan | 2022 | Presentation | | y2022 | presentation |
| Caching Tool Run Results in Large-Scale RTL Development Projects | Ashfaq Khan | 2022 | Paper | | y2022 | paper |
| Calling All Checkers: Collaboratively Utilizing SVA In UVM Based Simulation | Hui K. Zhang | 2016 | Paper | | y2016 | paper |
| Calling All Checkers: Collaboratively Utilizing SVA in UVM Based Simulation | Hui C. K. Zhang | 2016 | Poster | | y2016 | poster |
| CAMEL – A Flexible Cache Model for Cache Verification | Yue Liu, Fang Liu, Yunyang Song | 2022 | Presentation | | y2022 | presentation |
| CAMEL: A Flexible Cache Model for Cache Verification | Yue Liu, Fang Liu, and Yunyang Song | 2022 | Paper | | y2022 | paper |
| Can Formal Outsmart Synthesis: Improving Synthesis Quality of Results through Formal Methods | Eldon Nelson | 2021 | Paper | | y2021 | paper |
| Can My Synthesis Compiler Do That? | Stuart Sutherland and Don Mills | 2014 | Presentation | | y2014 | presentation |
| Can My Synthesis Compiler Do That? | Stuart Sutherland and Don Mills | 2014 | Paper | | y2014 | paper |
| Can You Even Debug a 200M+ Gate Design? | Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss | 2013 | Poster | | y2013 | poster |
| Can You Even Debug a 200M+ Gate Design? | Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss | 2013 | Paper | | y2013 | paper |
| Case Study: Low-Power Verification Success Depends on Positive Pessimism | John Decker | 2011 | Paper | | y2011 | paper |
| Case Study: Power-aware IP and Mixed-Signal Veri | Luke Lang | 2011 | Paper | | y2011 | paper |
| Case Study: Successes and Challenges of Validation Content Reuse | Mike Chin, Jonathan Edwards, Josh Pfrimmer, and Hooi Jing Tan | 2022 | Paper | | y2022 | paper |
| Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation) | Vikas Billa and Sundar Haran | 2018 | Paper | | y2018 | paper |
| Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation) | Vikas Billa and Sundar Haran | 2018 | Presentation | | y2018 | presentation |
| Challenges in UVM + Python Random Verification Environment for Digital Signal Processing Datapath Design | Shabbar Vejlani and Ashok Chandran | 2016 | Presentation | | y2016 | presentation |
| Challenges in UVM + Python random verification environment for Digital Signal Processing datapath design. | Shabbar Vejlani and Ashok Chandran | 2016 | Paper | | y2016 | paper |
| Checking Security Path with Formal Verification Tool: New Application Development | Julia Dushina and Joerg Mueller | 2014 | Poster | | y2014 | poster |
| Checking security path with formal verification tool: new application development | Julia Dushina, Saumil Shah, Joerg Mueller, and Vincent Reynolds | 2014 | Paper | | y2014 | paper |
| Chef’s Special – an Efficient Verification Recipe for Maximizing Productivity While Using a Third Party Verification IP | Varun S and Bhavik Vyas | 2012 | Paper | | y2012 | paper |
| Cleaning Out Your Pipes – Pipeline Debug in UVM Testbenches | Rich Edelman and Neil Bulman | 2018 | Paper | | y2018 | paper |
| Cleaning Out Your Pipes – Pipeline Debug in UVM Testbenches | Rich Edelman and Neil Bulman | 2018 | Poster | | y2018 | poster |
| CLOCK DOMAIN CROSSING CHALLENGES IN LATCH BASED DESIGNS | Madan Das, PhD, Chris Kwok, and Kurt Takara | 2018 | Paper | | y2018 | paper |
| Clock Domain Crossing Challenges in Latch Based Designs | Madan Das, Chris Kwok, and Kurt Takara | 2018 | Presentation | | y2018 | presentation |
| Clock Domain Crossing Verification in Transistor-level Design | Hyungjung Seo, KwangSun Kim, YoungRok Choi, Jihwan Kim, and Jong-Bae Lee | 2019 | Poster | | y2019 | poster |
| Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis | Bryan Bowyer | 2015 | Poster | | y2015 | poster |
| Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis | B. Bowyer | 2015 | Paper | | y2015 | paper |
| Co-Developing Firmware and IP with PSS | M. Ballance | 2022 | Paper | | y2022 | paper |
| Co-Developing IP and SoC Bring-Up Firmware with PSS | Matthew Ballance, Siemens EDA | 2022 | Presentation | | y2022 | presentation |
| Co-Simulating Matlab/Simulink Models in a UVM Environment | Neal Okumura and Glenn Richards | 2015 | Paper | | y2015 | paper |
| Co-Simulating Matlab/Simulink Models in a UVM Environment | Neal Okumura, Paul Yue, and Glenn Richards | 2015 | Presentation | | y2015 | presentation |
| Coding Guidelines and Code Generation | John Aynsley and Dr. Christoph Sühnel | 2014 | Poster | | y2014 | poster |
| Coherency Verification & Deadlock Detection Using Perspec/Portable Stimulus | Moonki Jang and Phu Huynh | 2019 | Presentation | | y2019 | presentation |
| Coherency Verification & Deadlock Detection Using Perspec/Portable Stimulus | Moonki Jang, Jiwoong Kim, Hyerim Chung, Phu L. Huynh, and Shai Fuss | 2019 | Paper | | y2019 | paper |
| Combining Simulation with Formal Techniques to Reduce the Overall Verification Cycle | Aneet Agarwal and Gaurav Gupta | 2010 | Paper | | y2010 | paper |
| Command Line Debug Using UVM Sequences | Mark Peryer | 2011 | Paper | | y2011 | paper |
| Common Challenges and Solutions to Integrating a UVM Testbench | Frank Verhoorn and Mike Baird | 2018 | Presentation | | y2018 | presentation |
| Common Challenges and Solutions to Integrating a UVM Testbench in Place of a Legacy Monolithic Testing Environment | Frank Verhoorn and Michael Baird | 2018 | Paper | | y2018 | paper |
| Comparison of TLM2-Quantum Keeping and TLM+-Resource Modeling with regard to Timing in Virtual Prototypes | Wolfgang Ecker, Volkan Esen, Rainer Findenigy, Thomas Leitnerz and Michael Velten | 2011 | Paper | | y2011 | paper |
| Complementing EDA with Meta-Modeling and Code Generation | Wolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal | 2014 | Paper | | y2014 | paper |
| Complementing EDA with Meta-Modelling & Code Generation | Wolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal | 2014 | Poster | | y2014 | poster |
| Complementing EDA with Meta-Modelling and Code Generation | Ecker Wolfgang, Michael Velten, Ajay Goyal, and Leily Zafari | 2014 | Presentation | | y2014 | presentation |
| CompMon: Ensuring Rigorous Protocol Specification and IP Compliance | Robert Adler, Sava Krstic and Erik Seligman | 2011 | Paper | | y2011 | paper |
| Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain Crossings | Yossi Mirsky | 2017 | Presentation | | y2017 | presentation |
| Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain Crossings | Yossi Mirsky B.Sc, M.Sc, MBA | 2017 | Paper | | y2017 | paper |
| Comprehensive IP to SoC CDC Verification Using Hybrid Data Model | Anwesha Choudhury and Ashish Hari | 2018 | Poster | | y2018 | poster |
| Comprehensive IP to SoC Clock Domain Crossing Verification Using Hybrid Data Mode | Anwesha Choudhury and Ashish Hari | 2018 | Paper | | y2018 | paper |
| Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-Chips | Ellie Burns, Gabriel Chidolue, and Guillaume Boillet | 2018 | Presentation | | y2018 | presentation |
| Comprehensive Register Description Languages: The case for standardization of RDLs across design domains | David C Black and Doug Smith | 2012 | Paper | | y2012 | paper |
| Comprehensive Systemverilog-Systemc-Vhdl Mixed-Language Design Methodology | Rudra Mukherjee, Gaurav Kumar Verma, and Sachin Kakkar | 2010 | Paper | | y2010 | paper |
| Conditional Delays for Negative Limit Timing Checks in Event Driven Simulation | Nadeem Kalil and David Roberts | 2015 | Paper | | y2015 | paper |
| Conditional Delays for Negative Limit Timing Checks in Event Driven Simulation | N. Kalil and D. Roberts | 2015 | Poster | | y2015 | poster |
| Confidently Sign-off Any low-Power Designs without Consequences | Madhur Bhargava, Jitesh Bansal, and Progyna Khondkar | 2022 | Poster | | y2022 | poster |
| Confidently Sign-Off Any Low-Power Designs Without Consequences | Madhur Bharga, Jitesh Bansal and Progyna Khondkar | 2022 | Paper | | y2022 | paper |
| Configuration Conundrum: Managing Test Configuration with a Bite Sized Solution | Kevin Vasconcellos, Jeff McNeal | 2021 | Paper | | y2021 | paper |
| Configuring Your Resources the UVM Way! | Parag Goel, Amit Sharma, and Rajiv Hasija | 2012 | Paper | | y2012 | paper |
| Configuring Your Resources the UVM Way! | Parag Goel, Amit Sharma, and Rajiv Hasija | 2012 | Presentation | | y2012 | presentation |
| CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITY | Bin Ju | 2014 | Paper | | y2014 | paper |
| CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITY | Bin Ju | 2014 | Poster | | y2014 | poster |
| Connecting UVM with Mixed-Signal Design | Ivica Ignjić | 2017 | Presentation | | y2017 | presentation |
| CONNECTING UVM WITH MIXED-SIGNAL DESIGN | Ivica Ignjić | 2017 | Paper | | y2017 | paper |
| Connectivity and Beyond | Shahid Ikram, Joseph DErrico, Yasmin Farhan, Jim Ellis, and Tushar Parikh | 2019 | Presentation | | y2019 | presentation |
| Connectivity and Beyond | Shahid Ikram, Joseph DErrico, Yasmin Farhan, Jim Ellis, and Tushar Parikh | 2019 | Paper | | y2019 | paper |
| Conquer the Graphics Legacy: Develop the Customized UVM VIP Embedded a Cycle-based C++ Reference Model | Roman Wang | 2019 | Poster | | y2019 | poster |
| Conscious of Streams Managing Parallel Stimulus | Jeff Wilcox | 2012 | Presentation | | y2012 | presentation |
| Conscious of Streams: Managing Parallel Stimulus | Jeffrey Wilcox and Stephen D’Onofrio | 2012 | Paper | | y2012 | paper |
| Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL Synthesis | Rainer Findenig, Thomas Leitner, and Wolfgang Ecker | 2011 | Paper | | y2011 | paper |
| CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTION | Martin Fröjd, Adiel Khan, and Jussi Mäkelä | 2014 | Paper | | y2014 | paper |
| CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTION | Jussi Mäkelä, Martin Fröjd, and Adiel Khan | 2014 | Presentation | | y2014 | presentation |
| CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTION | Jussi Mäkelä, Martin Fröjd, and Adiel Khan | 2014 | Presentation | | y2014 | presentation |
| Context-Aware DFM Rule Analysis and Scoring Using Machine Learning | Vikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, and Jonathan Ong | 2018 | Paper | | y2018 | paper |
| Context-Aware DFM Rule Analysis and Scoring Using Machine Learning | Vikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, and Jonathan Ong | 2018 | Poster | | y2018 | poster |
| Conversion of Performance Model to Functional Model | H G Pavan Kumar, Sumail Singh Brar, Ashwani Aggarwal, Seonil Brian Choi, Woojoo Space Kim | 2021 | Paper | | y2021 | paper |
| Coverage Data Exchange is no robbery…or is it? | Darron May and Samiran Laha | 2015 | Paper | | y2015 | paper |
| Coverage Data Exchange is no robbery…or is it? | Darron May and Samiran Laha | 2015 | Poster | | y2015 | poster |
| Coverage Driven Distribution of Constrained Random Stimuli | Raz Azaria, Amit Metodi, and Marat Teplitsky | 2015 | Presentation | | y2015 | presentation |
| Coverage Driven Distribution of Constrained Random Stimuli | Marat Teplitsky, Amit Metodi, and Raz Azaria | 2015 | Paper | | y2015 | paper |
| Coverage Driven Signoff with Formal Verification on Power Management IPs | Baosheng Wang and Xiaolin Chen | 2016 | Paper | | y2016 | paper |
| Coverage Driven Signoff with Formal Verification on Power Management IPs | Baosheng Wang and Xiaolin Chen | 2016 | Poster | | y2016 | poster |
| Coverage Driven Verification of an Unmodified DUT within an OVM Testbench | Michael Baird | 2010 | Paper | | y2010 | paper |
| Coverage Models for Formal Verification | Xiushan Feng, Xiaolin Chen, and Abhishek Muchandikar | 2017 | Paper | | y2017 | paper |
| Coverage Models for Formal Verification | Xiushan Feng, Xiaolin Chen, and Abhishek Muchandikar | 2017 | Poster | | y2017 | poster |
| COVERGATE: Coverage Exposed | Rich Edelman | 2020 | Paper | | y2020 | paper |
| COVERGATE: Coverage Exposed | Rich Edelman | 2020 | Poster | | y2020 | poster |
| Creating a Complete Low Power Verification Strategy using the Common Power Format and UVM | Robert Meyer and Joel Artmann | 2012 | Paper | | y2012 | paper |
| Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation Requirements | David Lacey and Ed Powell | 2018 | Paper | | y2018 | paper |
| Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation Requirements | David Lacey and Ed Powell | 2018 | Poster | | y2018 | poster |
| Cross Coverage of Power States | Veeresh Vikram Singh and Awashesh Kumar | 2016 | Paper | | y2016 | paper |
| Data-Driven Verification: Driving the next wave of productivity improvements | Larry Melling, Chris Komar, Sharon Rosenberg, Michael Young, and Hanan Moller | 2019 | Presentation | | y2019 | presentation |
| De-mystifying synchronization between various verification components by employing novel UVM classes | Pushpal Nautiyal and Gaurav Chugh | 2016 | Poster | | y2016 | poster |
| De-mystifying synchronization between various verification components by employing novel UVM classes | Pushpal Nautiyal and Gaurav Chugh | 2016 | Paper | | y2016 | paper |
| Deadlock Verification For Dummies – The Easy Way of Using SVA and Formal | Mark Eslinger, Jeremy Levitt, and Joe Hupcey III | 2020 | Poster | | y2020 | poster |
| Deadlock Verification For Dummies – The Easy Way Using SVA and Formal | Mark Eslinger, Jeremy Levitt, and Joe Hupcey III | 2020 | Paper | | y2020 | paper |
| Dealing with Programmable IP: Where the Rubber Meets the PSS Deployment Road | Karthick Gururaj | 2020 | Presentation | | y2020 | presentation |
| Debug APIs – next wave of innovation in DV space | Srinivasan Venkataramanan and Ajeetha Kumari | 2017 | Poster | | y2017 | poster |
| Debug APIs – next wave of innovation in DV space | Srinivasan Venkataramanan and Ajeetha Kumari | 2017 | Paper | | y2017 | paper |
| Debug Challenges in Low-Power Design and Verification | Durgesh Prasad, Madhur Bhargava, Jitesh Bansal, and Chuck Seeley | 2015 | Paper | | y2015 | paper |
| Debug Challenges in Low-Power Design and Verification | Durgesh Prasad, Madhur Bhargava, Jitesh Bansal, and Chuck Seeley | 2015 | Poster | | y2015 | poster |
| Debugging Communicating Systems: The Blame Game – Blurring the Line Between Performance Analysis and Debug | Rich Edelman and Raghu Ardeishar | 2014 | Paper | | y2014 | paper |
| Debugging Functional Coverage Models Get The Most Out of Your Cover Crosses | Mennatallah Amer and Amr Hany | 2018 | Paper | | y2018 | paper |
| Debugging Functional Coverage Models Get The Most Out of Your Cover Crosses | Mennatallah Amer and Amr Hany | 2018 | Presentation | | y2018 | presentation |
| Deep Learning for Design and Verification Engineers | John Aynsley | 2018 | Presentation | | y2018 | presentation |
| Deep Learning for Engineers | John Aynsley | 2019 | Presentation | | y2019 | presentation |
| Deep Predictive Coverage Collection | Rajarshi Roy, Chinmay Duvedi, Saad Godil, and Mark Williams | 2018 | Paper | | y2018 | paper |
| Deep Predictive Coverage Collection | Rajarshi Roy, Chinmay Duvedi, Saad Godil, and Mark Williams | 2018 | Presentation | | y2018 | presentation |
| Defining TLM+ | Wolfgang Ecker, Volkan Esen, Robert Schwencker, and Michael Velten | 2010 | Paper | | y2010 | paper |
| DeltaCov: Automated Stimulus Quality Monitoring System | Nimish Girdhar, Srinivas Badam | 2021 | Paper | | y2021 | paper |
| Demystifying the UVM Configuration Database | Vanessa R. Cooper and Paul Marriott | 2014 | Paper | | y2014 | paper |
| Demystifying the UVM Configuration Database | Vanessa R. Cooper and Paul Marriott | 2014 | Poster | | y2014 | poster |
| Deploying Customized Solution for Graphics Registers with UVM1.2 RAL | Roman Wang, Nigel Wang, Lunping Guo, Robert Liu, and Jia Zhu | 2018 | Paper | | y2018 | paper |
| Deploying Customized Solution for Graphics Registers with UVM1.2 RAL | Roman Wang, Nigel Wang, Lunping Guo, Robert Liu, and Jia Zhu | 2018 | Presentation | | y2018 | presentation |
| DEPLOYING PARAMETERIZED INTERFACE WITH UVM | Wayne Yun and Shihua Zhang | 2013 | Poster | | y2013 | poster |
| Deploying Parameterized Interface with UVM | Wayne Yun and Shihua Zhang | 2013 | Paper | | y2013 | paper |
| Design and Verification of a Multichip Coherence Protocol | Shahid Ikram, Isam Akkawi, Richard Kessler, Jim Ellis, and David Asher | 2015 | Poster | | y2015 | poster |
| Design and Verification of a Multichip Coherence Protocol | Shahid Ikram, Isam Akkawi, Richard Kessler, Jim Ellis, and David Asher | 2015 | Paper | | y2015 | paper |
| Design and Verification of an Image Processing CPU using UVM | Milos Becvar and Greg Tumbush | 2013 | Paper | | y2013 | paper |
| Design and Verification of an Image Processing CPU Using UVM | Greg Tumbush and Milos Becvar | 2013 | Presentation | | y2013 | presentation |
| Design Guidelines for Formal Verification | Anamaya Sullerey | 2015 | Presentation | | y2015 | presentation |
| Design Guidelines for Formal Verification | Anamaya Sullerey | 2015 | Paper | | y2015 | paper |
| Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012 | Eldon Nelson | 2016 | Presentation | | y2016 | presentation |
| Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012 | Eldon Nelson M.S. P.E. | 2016 | Paper | | y2016 | paper |
| Designers Work Less with Quality Formal Equivalence Checking | Orly Cohen, Moran Gordon, Michael Lifshits, Alexander Nadel, and Vadim Ryvchin | 2010 | Paper | | y2010 | paper |
| Designing Portable UVM Test Benches for Reusable IPs | Xiaoning Zhang, Baosheng Wang, and Terry Li | 2015 | Paper | | y2015 | paper |
| Designing Portable UVM Test Benches for Reusable IPs | XIAONING ZHANG and BAOSHENG WANG | 2015 | Poster | | y2015 | poster |
| Designing PSS Environment Integration for Maximum Reuse | Matthew Ballance | 2020 | Paper | | y2020 | paper |
| Designing PSS Environment Integration for Maximum Reuse | Matthew Ballance | 2020 | Presentation | | y2020 | presentation |
| Designing, Verifying and Building an Advanced L2 Cache Sub-System using SystemC | Thomas Tessier, Dr. Hai Lin, Daniel Ringoen, Eileen Hickey, and Steven Anderson | 2012 | Paper | | y2012 | paper |
| Designing, Verifying and Building an Advanced L2 Cache Subsystem using SystemC | Steve Frank, Thomas Tessier, Dr. Hai Lin, Daniel Ringoen, Eileen Hickey, and Steven Anderson | 2012 | Presentation | | y2012 | presentation |
| Detecting Circular Dependencies in Forward Progress Checkers | Saurabh Chaurdia, Arun Khurana, Naveen Kumar, Aditya Chaurasiya, Yogesh Mahajan, Prasenjit Biswas | 2021 | Paper | | y2021 | paper |
| Detecting Harmful Race Conditions in SystemC Models Using Formal Techniques | Sven Beyer and Dominik Strasser | 2015 | Presentation | | y2015 | presentation |
| Detecting Harmful Race Conditions in SystemC Models Using Formal Techniques | Sven Beyer and Dominik Strasser | 2015 | Paper | | y2015 | paper |
| Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions | Kelly D. Larson | 2014 | Paper | | y2014 | paper |
| Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions | Kelly D. Larson | 2014 | Presentation | | y2014 | presentation |
| Detoxify Your Schedule With A Low-Fat UVM Environment | Nihar Shah | 2016 | Paper | | y2016 | paper |
| Detoxify Your Schedule With A Low-Fat UVM Environment A success story on using self-checking stimulus instead of a scoreboard to reduce development time | Nihar Shah | 2016 | Poster | | y2016 | poster |
| Developing a Portable Block Testbench and Reusable SOC Verification Scenarios Using IP XACT Based Automation | Taejin Kim, Minjae Kim, Yonghyun Yang, Hyundon Kim, Daewoo Kim, Tae Hee Han, and Seonil Brian Choi | 2020 | Presentation | | y2020 | presentation |
| Did Power Management Break My CDC Logic? An Integrated Approach to Power Domain and Clock Domain Crossing Verification | Ashish Amonkar, Kurt Takara, and Avinash Agrawal | 2020 | Presentation | | y2020 | presentation |
| Digitizing Mixed Signal Verification | David Brownell and Courtney Schmitt | 2014 | Paper | | y2014 | paper |
| Digitizing Mixed Signal Verification: Digital Verification Techniques Applied to Mixed Signal and Analog Blocks on the LMA Project | David Brownell and Courtney Schmitt | 2014 | Presentation | | y2014 | presentation |
| Distributed Simulation of UVM Testbench | Theta Yang | 2016 | Poster | | y2016 | poster |
| Distributed Simulation of UVM Testbench | Theta Yang | 2016 | Paper | | y2016 | paper |
| Do You Know What Your Assertions Are up To? A New Approach to Safety Critical Verification | Lee C. Smith | 2016 | Presentation | | y2016 | presentation |
| Do You Know What Your Assertions Are Up To? A New Approach to Safety Critical Verification | Lee C. Smith | 2016 | Paper | | y2016 | paper |
| Do You Verify Your Verification Components? | Josh Rensch and Neil Johnson | 2016 | Poster | | y2016 | poster |
| Doing Funny Stuff with the UVM Register Layer: Experiences Using Front Door Sequences, Predictors, and Callbacks | John Aynsley | 2017 | Presentation | | y2017 | presentation |
| Doing Funny Stuff with the UVM Register Layer: Experiences Using Front Door Sequences, Predictors, and Callbacks | John Aynsley | 2017 | Paper | | y2017 | paper |
| Don’t delay catching bugs: Using UVM based architecture to model external board delays | Amit Paunikar, Saurabh Arya, Vikas Makhija, and Shaily Khare | 2018 | Poster | | y2018 | poster |
| Don’t delay catching bugs: Using UVM based architecture to model external board delays | Amit Paunikar, Saurabh Arya, Vikas Makhija, and Shaily Khare | 2018 | Paper | | y2018 | paper |
| Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to Simulation | Jonathan Bromley | 2015 | Presentation | | y2015 | presentation |
| Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to Simulation | Jonathan Bromley | 2015 | Paper | | y2015 | paper |
| DPI Redux. Functionality. Speed. Optimization. | Rich Edelman, Rohit Jain, and Hui Yin | 2017 | Paper | | y2017 | paper |
| DPI Redux. Functionality. Speed. Optimization. | Rich Edelman, Rohit Jain, and Hui Yin | 2017 | Presentation | | y2017 | presentation |
| DVCon U.S 2021 Proceedings | Accellera Systems Initiative | 2021 | Program | | y2021 | program |
| DVCon U.S. 2021 Proceedings | Accellera Systems Initiative | 2021 | Video | | y2021 | video |
| DVCon U.S. 2022 Proceedings | Accellera Systems Initiative | 2022 | Video | | y2022 | video |
| DVCon US 2022 Proceedings | Accellera Systems Initiative | 2022 | Program | | y2022 | program |
| DVS Interface Element – A Novel Approach in Multi-Power Domain, Mixed-Signal Design Verification | Vijay Kumar Sankaran, Ji Du, Qingyu Lin, Arumugan A, and Badrinarayan Zanwar | 2016 | Paper | | y2016 | paper |
| DVS Interface Element—A Novel Approach in Multi-Power Domain, Mixed-Signal Design Verification | Shekar Chetput | 2016 | Poster | | y2016 | poster |
| Dynamic and Scalable OVM Stimulus for Accelerated Functional Coverage | Michael J Castle | 2012 | Paper | | y2012 | paper |
| Dynamic Control Over UVM Register Backdoor Hierarchy | Roy Vincent, Unnikrishnan Nath, and Ashok Chandran | 2019 | Poster | | y2019 | poster |
| Dynamic Regression Suite Generation Using Coverage-Based Clustering | Shahid Ikram and Jim Ellis | 2017 | Presentation | | y2017 | presentation |
| Dynamic Regression Suite Generation Using Coverage-Based Clustering | Shahid Ikram and Jim Ellis | 2017 | Paper | | y2017 | paper |
| Dynamically Optimized Test Generation Using Machine Learning | Rajarshi Roy, Mukhdeep Singh Benipal, Saad Godil | 2021 | Paper | | y2021 | paper |
| e/eRM to SystemVerilog/UVM: Mind the Gap, But Don’t Miss the Train | Avidan Efody and Michael Horn | 2012 | Paper | | y2012 | paper |
| e/eRM to SystemVerilog/UVM: Mind the Gap, But Don’t Miss the Train | Michael Horn | 2012 | Presentation | | y2012 | presentation |
| EARLY SOFTWARE DEVELOPMENT AND VERIFICATION METHODOLOGY USING HYBRID EMULATION PLATFORM | Woojoo Kim, Haemin Park, Hyundon Kim, Seonil Brian Choi, and SukWon Kim | 2017 | Paper | | y2017 | paper |
| EASI2L: A Specification Format for Automated Block Interface Generation and Verification | Chintan Kaur, Ravi Narayanaswami, and Richard Ho | 2016 | Paper | | y2016 | paper |
| Easier SystemVerilog with UVM: Taming the Beast | John Aynsley | 2012 | Paper | | y2012 | paper |
| Easier SystemVerilog with UVM: Taming the Beast | John Aynsley | 2012 | Presentation | | y2012 | presentation |
| Easier UVM – Coding Guidelines and Code Generation | John Aynsley and Dr. Christoph Sühnel | 2014 | Paper | | y2014 | paper |
| Easier UVM for Functional Verification by Mainstream Users | John Aynsley | 2011 | Paper | | y2011 | paper |
| Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI | Dave Rich | 2013 | Paper | | y2013 | paper |
| Easy uvm_config_db use: A simplified and reusable uvm_config_db methodology for environment developers and test writers | Bob Oden | 2015 | Paper | | y2015 | paper |
| Easy uvm_config_db use: A simplified and reusable uvm_config_db methodology for environment developers and test writers | Bob Oden | 2015 | Poster | | y2015 | poster |
| Effects of Abstraction in Stimulus Generation of Layered Protocols within OVM | Josh Rensch and Jesse Prusi | 2010 | Paper | | y2010 | paper |
| Efficient and Exhaustive Floating Point Verification Using Sequential Equivalence Checking | Travis W. Pouarz and Vaibhav Agrawal | 2017 | Paper | | y2017 | paper |
| Efficient and Exhaustive Floating Point Verification Using Sequential Equivalence Checking | Travis Pouarz and Vaibhav Agrawal | 2017 | Presentation | | y2017 | presentation |
| Efficient Bug-Hunting Techniques Using Graph-Based Stimulus Models | Nguyen Le and Mike Andrews | 2016 | Presentation | | y2016 | presentation |
| Efficient Bug-Hunting Techniques Using Graph-Based Stimulus Models | Nguyen Le and Mike Andrews | 2016 | Paper | | y2016 | paper |
| Efficient distribution of video frames to achieve better throughput | Bhavik Vyas and Suruchi Jain | 2012 | Paper | | y2012 | paper |
| Efficient hierarchical low power verification of custom designs using static and dynamic techniques | Himanshu Bhatt, Archanna Srinivasan, and Chong Lee Kuay | 2019 | Poster | | y2019 | poster |
| Efficient Methods for Display Power Estimation & Visualization | Srikanth Reddy Rolla and Aakash Modi | 2020 | Poster | | y2020 | poster |
| Efficient Methods for Display Power Estimation and Visualization | Srikanth Reddy Rolla and Aakash Modi | 2020 | Paper | | y2020 | paper |
| Efficient SCE-MI Usage to Accelerate TBA Performance | Ponnambalam Lakshmanan, Prashantkumar Ravindra, and Rajarathinam Susaimanickam | 2017 | Paper | | y2017 | paper |
| Efficient Simulation Based Verification by Reordering | Chao Ya and Kevin Jones | 2010 | Paper | | y2010 | paper |
| Efficient SoC Level Mixed Signal Frontend Verification using Wreal Models | Anu Marisha, Nayana Prakash, Udit Kumar, Rajesh Tiwari, and Vijay Kumar Birange | 2014 | Paper | | y2014 | paper |
| Efficient SoC Level Mixed Signal Frontend Verification using Wreal Models | Anu Marisha, Nayana Prakash, Udit Kumar, and Rajesh Tiwari | 2014 | Presentation | | y2014 | presentation |
| Efficient Standard Co-Emulation Modeling Interface (SCE-MI) Usage to Accelerate TBA Performance | Ponnambalam Lakshmanan | 2017 | Presentation | | y2017 | presentation |
| EMULATION BASED FULL CHIP LEVEL LOW POWER VALIDATION AT PRE-SILICON STAGE | Kyoungmin Park, Jaegeun Song, Hyundon Kim, Seonil Brian Choi, and Suk Won Kim | 2017 | Paper | | y2017 | paper |
| Emulation Based Power and Performance Workloads on ML NPUs | Pragati Mishra, Ritu Suresh, Issac Zacharia, and Jitendra Aggarwal | 2022 | Poster | | y2022 | poster |
| Emulation Based Power and Performance Workloads on ML NPUs | Pragati Mishra, Ritu Suresh, Issac Zacharia, and Jitendra Aggarwal | 2022 | Paper | | y2022 | paper |
| Emulation Testbench Optimizations for better Hardware Software Co-Validation | Vijayakrishnan Rousseau, Suresh Balasubramanian, Srikanth Reddy Rolla, and Mohamed Saheel Nandikotkur Hussainsaheb | 2019 | Poster | | y2019 | poster |
| End to End Formal Verification Strategies for IP Verification | Jacob Ryan Maas, Nirabh Regmi, Ashish Kulkarni, and Krishnan Palaniswami | 2017 | Paper | | y2017 | paper |
| End to End Formal Verification Strategies for IP Verification | Jacob Ryan Maas, Nirabh Regmi, Krishnan Palaniswami, and Ashish Kulkarni | 2017 | Poster | | y2017 | poster |
| Engineered SystemVerilog Constraints | Jeremy Ridgeway | 2015 | Presentation | | y2015 | presentation |
| Engineered SystemVerilog Constraints | Jeremy Ridgeway | 2015 | Paper | | y2015 | paper |
| Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software Verification | Victor Besyakov | 2022 | Poster | | y2022 | poster |
| Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software Verification | Victor Besyakov | 2022 | Paper | | y2022 | paper |
| Environment for efficient and reusable SystemC module level verification | Flavia Gontia | 2014 | Paper | | y2014 | paper |
| Environment for efficient and reusable SystemC module level verification | Flavia Gonția | 2014 | Presentation | | y2014 | presentation |
| Equivalence Validation of Analog Behavioral Models | Hardik Parekh, Manish Kumar Karna, Mohit Jain, Atul Pandey, and Sandeep Mittal | 2014 | Paper | | y2014 | paper |
| Equivalence Validation of Analog Behavioral Models | Hardik Parekh, Manish Kumar Karna, Mohit Jain, Atul Pandey, and Sandeep Mittal | 2014 | Poster | | y2014 | poster |
| Equivalence Validation of Analog Behavioral Models | Manish Kumar Karna, Hardik Parekh, Mohit Jain, Atul Pandey, and Sandeep Mittal | 2014 | Poster | | y2014 | poster |
| Eradicating X-bugs and Achieving Higher Design Quality Using Static X-propagation Sign-off | Sanjay Thatte, Andrew Guyler, Nikhil Rahagude, and Savitha Raghunath | 2020 | Presentation | | y2020 | presentation |
| Error Injection in a Subsystem Level Constrained Random UVM Testbench | J. Ridgeway and H. Nguyen | 2018 | Paper | | y2018 | paper |
| Error Injection in a Subsystem Level Constrained Random UVM Testbench | Jeremy Ridgeway and Hoe Nguyen | 2018 | Presentation | | y2018 | presentation |
| Error Injection: When Good Input Goes Bad | Kurt Schwartz and Tim Corcoran | 2017 | Paper | | y2017 | paper |
| Error Injection: When Good Input Goes Bad | Kurt Schwartz and Tim Corcoran | 2017 | Presentation | | y2017 | presentation |
| Estimating Power Dissipation of End-User Application on RTL | Magdy El-Moursy | 2022 | Presentation | | y2022 | presentation |
| Evaluating the Feasibility of a RISC V Core for Real Time Applications Using a Virtual Prototype | J. Santana , G. Pachiana, T. Markwirth, C. Sohrmann, B. Fischer, M. Matschnig | 2022 | Presentation | | y2022 | presentation |
| Evaluating the Feasibility of a RISCV Core for Real-Time Applications Using a Virtual Prototype | Juan Santana, Gabriel Pachiana, Thomas Markwirth, Christoph Sohrmann, Bernhard Fischer, and Martin Matschnig | 2022 | Paper | | y2022 | paper |
| Every Cloud – Post-Silicon Bug Spurs Formal Verification Adoption | Blaine Hsieh, Stewart Li, and Mark Eslinger | 2015 | Presentation | | y2015 | presentation |
| Every Cloud – Post-Silicon Bug Spurs Formal Verification Adoption | Blaine Hsieh, Stewart Li, and Mark Eslinger | 2015 | Paper | | y2015 | paper |
| Evolution of CDC recipe: Learning through real case studies and methodology improvements | Amit Kulkarni, Suhas DS, Deepmala Sachan | 2021 | Paper | | y2021 | paper |
| Evolution of Triage: Real-time Improvements in Debug Productivity | Gordon Allan | 2016 | Paper | | y2016 | paper |
| Exhaustive Equivalence Checking on AMD’s Next-generation Microprocessor Core | Baosheng Wang, Brian McMinn, Borhan Roohipour, Ashok Venkatachar, Arun Chandra, Richard Bartolotti, and Lerzan Celikkanat | 2011 | Paper | | y2011 | paper |
| Exhaustive Latch Flow – Through Verification with Formal Methods | Baosheng Wang, Sean Ater, Baris Piyade, Brian McMinn, and Borhan Roohipour | 2012 | Presentation | | y2012 | presentation |
| Exhaustive Latch Flow-through Verification with Formal Methods | Baosheng Wang, Sean Ater, Baris Piyade, Brian McMinn, and Borhan Roohipour | 2012 | Paper | | y2012 | paper |
| Experience with OVM-Based Mixed-Signal Verification of the Impedance Calibration Block for a DDR Interface | Harry Wang, Wessam El-Naji, and Kenneth Bakalar | 2012 | Paper | | y2012 | paper |
| Experience with OVM-Based Mixed-Signal Verification of the Impedance Calibration Block for a DDR Interface | Harry Wang, Wessam El-Naji, and Kenneth Bakalar | 2012 | Presentation | | y2012 | presentation |
| Experiences in Migrating a Chip-Level Verification Environment from UVM EA to UVM 1.1 | Ashish Kumar, Dave Stang, Dudyala Sasidhar, S, Manikandan, and Thirumalai Srishan | 2012 | Paper | | y2012 | paper |
| Experiences in Migrating a Chip-Level Verification Environment from UVM-EA to UVM-1.x | Ashish Kumar, S Manikandan, Sasidhar Dudyala, Srishan Thirumalai, and Dave Stang | 2012 | Presentation | | y2012 | presentation |
| Experiencing Checkers for a Cache Controller Design | Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari, and Lisa Piper | 2010 | Paper | | y2010 | paper |
| Exquisite modeling of verification IP: Challenges and Recommendations | Anuradha Tambad, Subashini Rajan, Shivani Upasani, Prashanth Srinivasa, Imran Ali, and Adiel Khan | 2012 | Paper | | y2012 | paper |
| Exquisite Modeling of VIP | Adiel Khan, Anuradha Tambad, Imran Ali, Prashanth Srinivasa, Shivani Upasani, and Subashini Rajan | 2012 | Presentation | | y2012 | presentation |
| Extendable Messaging Techniques for Debugging and Analyzing UVM Testbench Structure and Transaction Flow | Jun Zhao, Bindesh Patel, and Rex Chen | 2013 | Presentation | | y2013 | presentation |
| Extendable Messaging Techniques for Debugging and Analyzing UVM Testbench Structure and Transaction Flow | Jun Zhao, Bindesh Patel, and Rex Chen | 2013 | Paper | | y2013 | paper |
| Extension of the Power-Aware IP Reuse Approach to ESL | Antonio Genov, Loic Leconte, Fran ç ois Verdier | 2022 | Presentation | | y2022 | presentation |
| Fabric Verification | Galen Blake and Steve Chappell | 2012 | Presentation | | y2012 | presentation |
| Failure Triage: The Neglected Debugging Problem | Sean Safarpour, Evean Qin, Yu-Shen Yang, and Brian Keng | 2012 | Paper | | y2012 | paper |
| Failure Triage: The Neglected Debugging Problem | Sean Safarpour, Evean Qin, Yu-Sheng Yang, and Brian Keng | 2012 | Presentation | | y2012 | presentation |
| Fast Track Formal Verification Signoff | Mandar Munishwar, Xiaolin Chen, Arunava Saha, and Sandeep Jana | 2018 | Poster | | y2018 | poster |
| Fast Track Formal Verification Signoff | Mandar Munishwar, Xiaolin Chen, Arunava Saha, and Sandeep Jana | 2018 | Paper | | y2018 | paper |
| Fault-Effect Analysis on Multiple Abstraction Levels in Hardware Modeling | B-A. Tabacaru, M. Chaari, W. Ecker, T. Kruse, and C. Novello | 2016 | Presentation | | y2016 | presentation |
| Fault-Effect Analysis on Multiple Abstraction Levels in Hardware Modeling | Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, and Cristiano Novello | 2016 | Paper | | y2016 | paper |
| Finding a Needle in a Haystack: A Novel Log Analysis Method with Test Clustering in Distributed System | Jin Choi | 2022 | Presentation | | y2022 | presentation |
| Finding a Needle in a Haystack: A Novel Log Analysis Method with Test Clustering in Distributed Systems | Jin Choi, Sangwoo Noh, Sooncheol Hong, Hanna Jang, Seonghee Yim, and Seonil Brian Choi | 2022 | Paper | | y2022 | paper |
| Finding Hidden Bugs In Deep Cycles: Advanced Debug Methodologies for Software-first System Validation | Youcef Qassid and Andy Jolley | 2022 | Presentation | | y2022 | presentation |
| Finding the Last Bug in a CNN DMA Unit | Bruno Lavigueur, Dean Ke, Eric Rao, Fergus Casey, Achin Mittal, Pallavi Kumari, Michael Thompson, and Roger Sabbagh | 2020 | Paper | | y2020 | paper |
| Finding the Last Bug in a CNN DMA Unit | Bruno Lavigueur, Dean Ke, Eric Rao, Fergus Casey, Achin Mittal, Pallavi Kumari, Michael Thompson, and Roger Sabbagh | 2020 | Presentation | | y2020 | presentation |
| First Reports from the UVM Trenches: User-friendly, Versatile and Malleable, or just the Emperor’s New Methodology? | Jonathan Bromley | 2011 | Paper | | y2011 | paper |
| Flattening the UVM Learning Curve Automated Solutions for DSP Filter Verification | Avinash Lakshminarayana, Eric Jackowski, Eric Cigan, and Mark Lin | 2022 | Paper | | y2022 | paper |
| Flattening the UVM Learning Curve: Automated Solutions for DSP Filter Verification | Avinash Lakshminarayana, Eric Jackowski,Eric Cigan, Mark Lin | 2022 | Presentation | | y2022 | presentation |
| Flexible Checker: A one-stop shop for all your checkers and a methodology for elastic scoreboarding | Saad Zahid, Chandra Veedhi, and Sumit Dhamanwala | 2019 | Poster | | y2019 | poster |
| Flexible Indirect Registers with UVM | Uwe Simm | 2017 | Presentation | | y2017 | presentation |
| Fnob: Command Line-Dynamic Random Generator | Haoxiang Hu, Tuo Wang | 2022 | Presentation | | y2022 | presentation |
| Fnob: Command Line-Dynamic Random Generator | Haoxiang Hu and Tuo Wang | 2022 | Paper | | y2022 | paper |
| Formal Architectural Specification and Verification of A Complex SOC | Shahid Ikram, Isam Akkawi, David Asher, and Jim Ellis | 2018 | Presentation | | y2018 | presentation |
| FORMAL ARCHITECUTRAL SPECIFICATION AND VERIFICATION OF A COMPLEX SOC | Shahid Ikram, Isam Akkawi, David Asher, and Jim Ellis | 2018 | Paper | | y2018 | paper |
| Formal Bug Hunting with “River Fishing” Techniques | Mark Eslinger and Ping Yeung | 2019 | Presentation | | y2019 | presentation |
| Formal Bug Hunting with “River Fishing” Techniques | Mark Eslinger and Ping Yeung | 2019 | Paper | | y2019 | paper |
| Formal Methods to Verify the Power Manager for an Embedded Multiprocessor Cluster | Kesava R. Talu | 2010 | Paper | | y2010 | paper |
| Formal Proof for GPU Resource Management | Jia Zhu, Chuanqin Yan, and Nigel Wang | 2017 | Presentation | | y2017 | presentation |
| Formal Proof for GPU Resource Management | Jia Zhu, Chuanqin Yan, and Nigel Wang | 2017 | Paper | | y2017 | paper |
| Formal Verification Bootcamp | Mike Bartley | 2019 | Presentation | | y2019 | presentation |
| Formal Verification by The Book: Error Detection and Correction Codes | K. Devarajegowda, V. Hiltl, T. Rabenalt, D. Stoffel, W. Kunz, and W. Ecker | 2020 | Presentation | | y2020 | presentation |
| Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt | Ping Yeung, Mark Eslinger, Jin Hou | 2021 | Paper | | y2021 | paper |
| Formal Verification in the Real World | Jonathan Bromley and Jason Sprott | 2018 | Presentation | | y2018 | presentation |
| Formal Verification of Connections at SoC-level | Penny Yang, Prasun Das, Yuya Kao, and Mingchu Kuo | 2018 | Paper | | y2018 | paper |
| Formal Verification of Connections at SoC-level | Penny Yang, Prasun Das, Yuya Kao, and Mingchu Kuo | 2018 | Presentation | | y2018 | presentation |
| FORMAL VERIFICATION OF FLOATING-POINT HARDWARE WITH ASSERTION-BASED VIP | Ravi Ram, Adam Elkins, Adnan Pratama, Sasa Stamenkovic, Sven Beyer, and Sergio Marchese | 2018 | Paper | | y2018 | paper |
| Formal Verification of Floating-Point Hardware with Assertion-Based VIP | Ravi Ram, Adam Elkins, Adnan Pratama, Sasa Stamenkovic, Sven Beyer, and Sergio Marchese | 2018 | Presentation | | y2018 | presentation |
| Formal verification of Macro-op cache for Arm Cortex-A77, and its successor CPU | Vaibhav Agrawal | 2020 | Paper | | y2020 | paper |
| Formal Verification of Macro-op Cache for Arm Cortex-A77, and its Successor CPU | Vaibhav Agrawal | 2020 | Presentation | | y2020 | presentation |
| Formal Verification of Silicon for Software Defined Networking | Saurabh Shrivastava, Keqin Han, Anh Tran, Chirag Agarwal, Ankit Saxena, Achin Mittal, Anshul Jain, and Roger Sabbagh | 2018 | Paper | | y2018 | paper |
| Formal Verification on Deep Learning Instructions of GPU | Jian (Jeffrey) Wang and Jia Zhu | 2018 | Paper | | y2018 | paper |
| Formal Verification Tutorial Breaking Through the Knowledge Barrier | Sean Safarpour, Iain Singleton, Shaun Feng, Syed Suhaib, and Mandar Munishwar | 2018 | Presentation | | y2018 | presentation |
| FPGA-based Clock Domain Crossing Validation for Safety-Critical Designs | Alexander Gnusin | 2019 | Paper | | y2019 | paper |
| FPGA-based Clock Domain Crossing Validation for Safety-Critical Designs | Alexander Gnusin | 2019 | Presentation | | y2019 | presentation |
| Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF | Progyna Khondkar, Ping Yeung, Gabriel Chidolue, Joe Hupcey, Rick Koster, and Madhur Bhargava | 2017 | Paper | | y2017 | paper |
| Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF | Progyna Khondkar, Ping Yeung, Gabriel Chidolue, Joe Hupcey, Rick Koster, and Madhur Bhargava | 2017 | Poster | | y2017 | poster |
| From Spec to Verification Closure: a case study of applying UVM-MS for first pass success to a complex Mixed-Signal SoC design | Neyaz Khan and Yaron Kashai | 2012 | Paper | | y2012 | paper |
| From Spec to Verification Closure: A case study of applying UVM-MS for first pass success to a complex MS-SoC design | Neyaz Khan and Yaron Kashai | 2012 | Presentation | | y2012 | presentation |
| From the Magician’s Hat: Developing a Multi-Methodology PCIe Gen2 VIP | Amit Sharma, Abhisek Verma, Varun S., and Anoop Kumar | 2011 | Paper | | y2011 | paper |
| fsim_logic – A VHDL type for testing of FLYTRAP | Joanne E. DeGroat, Ph.D. | 2013 | Paper | | y2013 | paper |
| fsim_logic – A VHDL type for testing of FLYTRAP | Joanne E. DeGroat, Ph.D. | 2013 | Presentation | | y2013 | presentation |
| Full Flow Clock Domain Crossing – From Source To Si | Mark Litterick | 2016 | Presentation | | y2016 | presentation |
| Full Flow Clock Domain Crossing – From Source to Si | M. Litterick | 2016 | Paper | | y2016 | paper |
| Fully Automated Functional Coverage Closure | Manohar Kodi, Sagar Sudam Patil, and Ranjith Nair | 2019 | Paper | | y2019 | paper |
| Fully Automated Functional Coverage Closure | Manohar Kodi, Sagar Sudam Patil, and Ranjith Nair | 2019 | Presentation | | y2019 | presentation |
| Fully Hierarchical CDC Analysis Using Comprehensive CDC Meta Database | Youngchan Lee, Youngsik Kim, Soenil Brian Choi, and Vikas Sachdeva | 2019 | Paper | | y2019 | paper |
| Fully Hierarchical CDC Analysis Using Comprehensive CDC Meta-Database | Youngchan Lee, Youngsik Kim, and Seonil Brian Choi | 2019 | Presentation | | y2019 | presentation |
| Fun with UVM Sequences – Coding and Debugging | Rich Edelman | 2019 | Paper | | y2019 | paper |
| Fun with UVM Sequences Coding and Debugging | Rich Edelman | 2019 | Presentation | | y2019 | presentation |
| Functional Coverage – without SystemVerilog! | Alan Fitch and Doug Smith | 2010 | Paper | | y2010 | paper |
| Functional Coverage Collection for Analog Circuits – Enabling Seamless Collaboration between Design and Verification | Z. Ye, H. Lin and A. M. Khan | 2016 | Paper | | y2016 | paper |
| Functional Coverage Collection for Analog Circuits –Enabling Seamless Collaboration between Design and Verification | Zhipeng Ye, Honghuang Lin and Asad Khan | 2016 | Presentation | | y2016 | presentation |
| FUNCTIONAL COVERAGE OF REGISTER ACCESS VIA SERIAL BUS INTERFACE USING UVM | Darko M. Tomušilovic | 2017 | Poster | | y2017 | poster |
| Functional Coverage of Register Access via Serial Bus Interface using UVM | D. M. Tomušilović | 2017 | Paper | | y2017 | paper |
| Functional coverage-driven verification with SystemC on multiple level of abstraction | Christoph Kuznik and Wolfgang M¨uller | 2011 | Paper | | y2011 | paper |
| Functional Safety Verification For ISO 26262 | Kevin Rich, Shekhar Mahatme, and Meirav Nitzan | 2018 | Presentation | | y2018 | presentation |
| Generation of Constraint Random Transactions for Verification of Mixed-Signal Blocks | Alexander W. Rath, Sebastian Simon, Volkan Esen, and Wolfgang Ecker | 2014 | Paper | | y2014 | paper |
| Generic Programming in SystemVerilog | Mark Glasser | 2016 | Paper | | y2016 | paper |
| Generic SCSI-Based Host Controller Verification Framework Using SystemVerilog | Mohamed Rayan, Mohamed Samy, Haytham Ashour, Ashraf Salem | 2021 | Paper | | y2021 | paper |
| Getting Rid of False Errors when Verifying LSI Designs Including Non-Determinism | Matthieu Parizy and Hiroaki Iwashita | 2011 | Paper | | y2011 | paper |
| Git for Hardware Designers | Jeffery Scott and Sanjeev Singh | 2015 | Paper | | y2015 | paper |
| GIT for Hardware Designers | Jeffery Scott and Sanjeev Singh | 2015 | Poster | | y2015 | poster |
| Goldilocks and System Performance Modeling | Rich Edelman and Shashi Bhutada | 2015 | Paper | | y2015 | paper |
| Goldilocks and System Performance Modelling A SystemVerilog Adaptive Rate Control (ARC) Stimulus Generation Methodology | Rich Edelman and Shashi Bhutada | 2015 | Poster | | y2015 | poster |
| GoldMine: Automatic Assertion Generation and Coverage Closure in Design Validation | David Sheridan, Lingyi Liu, and Shobha Vasudevan | 2011 | Paper | | y2011 | paper |
| Graph-IC Verification | Dennis Ramaekers and Grégory Faux | 2012 | Paper | | y2012 | paper |
| Graph-IC Verification | Gregory Faux and Dennis Ramaekers | 2012 | Presentation | | y2012 | presentation |
| Graphical Topology Info Structure for Constrained Random Verification in SoC/Subsystem Tests | Evean Qin, Richard Bell, and David Chen | 2019 | Presentation | | y2019 | presentation |
| Graphical Topology Info Structure for Constrained Random Verification in SoC/Subsystem Tests | Evean Qin, Richard Bell, and David Chen | 2019 | Paper | | y2019 | paper |
| Guaranteed Vertical Reuse – C Execution In A UVM Environment | Rachida El Idrissi and Alain Gonier | 2013 | Presentation | | y2013 | presentation |
| Guaranteed Vertical Reuse – C Execution In a UVM Environment | Rachida El Idrissi and Alain Gonier | 2013 | Paper | | y2013 | paper |
| Hardware Acceleration for UVM Based CLTs | Mohamed Saheel, Rohith M. S., and Andrew Tan | 2020 | Presentation | | y2020 | presentation |
| Hardware Emulation: ICE vs Virtual | Lauro Rizzatti | 2016 | Presentation | | y2016 | presentation |
| Hardware Trojan Design and Detection with Formal Verification to Deep Neural Network | Si-Han Chen, Yu-Ting Huang, Yi-Chun Kao, Yean-Ru Chen, Shang-Wei Lin, Chia-I Chen | 2021 | Paper | | y2021 | paper |
| Hardware/Software co-verification using Specman and SystemC with TLM ports | Horace Chan and Brian Vandegriend | 2012 | Paper | | y2012 | paper |
| Hardware/Software Co-Verification Using Specman and SystemC with TLM Ports | Horace Chan | 2012 | Presentation | | y2012 | presentation |
| Hierarchical UPF: Uniform UPF across FE & BE | Dipankar Narendra Arya, Balaji Vishwanath Krishnamurthy, Aditi Nigam, Tahir Ali | 2022 | Presentation | | y2022 | presentation |
| Hierarchical UPF: Uniform UPF across FE & BE | Dipankar Narendra Arya, Balaji Vishwanath Krishnamurthy, Aditi Nigam, and Ali Tahir | 2022 | Paper | | y2022 | paper |
| High-Level Synthesis Walks the Talk: Synthesizing a Complete Graphics Processing Application | Thomas Bollaert | 2011 | Paper | | y2011 | paper |
| High-Speed Interface IP Validation based on Virtual Emulation Platform | Jaehun Lee, DaeSeo Cha, and Sungwook Moon | 2019 | Paper | | y2019 | paper |
| High-Speed Interface IP Validation based on Virtual Emulation Platform | Jaehun Lee, Daeseo Cha, and Sungwook Moon | 2019 | Presentation | | y2019 | presentation |
| Highly Configurable UVM Environment for Parameterized IP Verification | HongLiang Liu and Karl Whiting | 2015 | Paper | | y2015 | paper |
| Highly Configurable UVM Environment for Parameterized IP Verification | HongLiang Liu and Karl Whiting | 2015 | Poster | | y2015 | poster |
| Holistic Approach to IO Timing Verification Using Portable Stimulus and Assertions | Amitesh Khandelwal and Praveen Kumar | 2018 | Poster | | y2018 | poster |
| Holistic Approach to IO Timing Verification Using Portable Stimulus and Assertions | Amitesh Khandelwal and Praveen Kumar | 2018 | Paper | | y2018 | paper |
| Holistic Automated Code Generation: No Headache with Last-Minute Changes | Klaus Strohmayer and Norbert Pramstaller | 2012 | Paper | | y2012 | paper |
| Holistic Automated Code Generation: No Headache with Last-Minute Changes | Klaus Strohmayer and Norbert Pramstaller | 2012 | Presentation | | y2012 | presentation |
| Hopscotch: A Scalable Flow-Graph Based Approach to Formally Specify and Verify Memory-Tagged Store Execution in Arm CPUs | Abhinav Sethi, Madhu Iyer, Sai Komaravelli, and Vikram Khosa | 2022 | Paper | | y2022 | paper |
| Hopscotch: A Scalable Flow-Graph Based Approach to Verify CPU Store Execution | Abhinav Sethi, Madhu Iyer, Sai Komaravelli, and Vikram Khosa | 2022 | Presentation | | y2022 | presentation |
| How Do You Verify Your Verification Components? | Josh Rensch and Neil Johnson | 2016 | Paper | | y2016 | paper |
| How Far Can You Take UVM Code Generation and Why Would You Want To? | John Aynsley | 2016 | Presentation | | y2016 | presentation |
| How Far Can You Take UVM Code Generation and Why Would You Want To? | John Aynsley | 2016 | Paper | | y2016 | paper |
| How HLS and SystemC is Delivering on its Promise of Design and Verification Productivity | Stuart Swan, Mike Meredith, Matthew Bone, and Rangharajan Venkatesan | 2020 | Presentation | | y2020 | presentation |
| How I Learned to Stop Worrying and Love Benchmarking Functional Verification! | Mike Bartley | 2012 | Presentation | | y2012 | presentation |
| How I Learned to Stop Worrying and Love Benchmarking Functional Verification! | Mike Bartley and Mike Benjamin | 2012 | Paper | | y2012 | paper |
| How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage | Mark Eslinger, Joseph V Hupcey III, and Nicolae Tusinschi | 2022 | Paper | | y2022 | paper |
| How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage | Mark Eslinger, Joseph V Hupcey III, and Nicolae Tusinschi | 2022 | Presentation | | y2022 | presentation |
| How to Create Reusable Portable Testing and Stimulus Standard (PSS) Verification IP | Sharon Rosenberg | 2019 | Poster | | y2019 | poster |
| How to Kill 4 Birds with 1 Stone: Using Formal Verification to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software Specifications | Saurabh Shrivastava, Kavita Dangi, Darrow Chu, and Mukesh Sharma | 2013 | Presentation | | y2013 | presentation |
| How to Kill 4 Birds with 1 Stone: Using Formal Verification to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software Specifications | Saurabh Shrivastava, Kavita Dangi, Darrow Chu, and Mukesh Sharma | 2013 | Paper | | y2013 | paper |
| How to Overcome Editor Envy: Why Can’t My Editor Do That? | Dillan Mills, Chuck McClish | 2021 | Paper | | y2021 | paper |
| How to Stay Out of the News with ISO26262-Compliant Verification | Charles Battikha and Doug Smith | 2018 | Presentation | | y2018 | presentation |
| How to Succeed Against Increasing Pressure: Automated Techniques for Unburdening Verification Engineers | James Pascoe and Steve Hobbs | 2013 | Presentation | | y2013 | presentation |
| How to Succeed Against Increasing Pressure: Automated Techniques for Unburdening Verification Engineers | James Pascoe, Pierre Kuhn, and Steve Hobbs | 2013 | Paper | | y2013 | paper |
| How to test the whole firmware/software when the RTL can’t fit the emulator | Horace Chan and Byron Watt | 2019 | Paper | | y2019 | paper |
| How to test the whole firmware/software when the RTL can’t fit the emulator | Horace Chan and Byron Watt | 2019 | Presentation | | y2019 | presentation |
| How UPF 3.1 Reduces the Complexities of Reusing PA Macros | Madhusudhana Reddy Lebaka, Abraham Guizer, and Progyna Khondkar | 2020 | Poster | | y2020 | poster |
| How UPF 3.1 Reduces the Complexities of Reusing Power Aware Macros | Madhusudhana Reddy Lebaka, Abraham Guizer, and Progyna Khondkar | 2020 | Paper | | y2020 | paper |
| HSI Issues – Fake News or Not? How Hardware/Software Interface Impacts Tape-Outs | Gary Stringham, Rich Weber, and Jamsheed Agahi | 2020 | Presentation | | y2020 | presentation |
| Hybrid Approach to Testbench and Software Driven Verification on Emulation | Debdutta Bhattacharya and Ayub Khan | 2018 | Paper | | y2018 | paper |
| Hybrid Approach to Testbench and Software Driven Verification on Emulation | Debdutta Bhattacharya and Ayub Khan | 2018 | Poster | | y2018 | poster |
| Hybrid Emulation: Accelerating Software Driven Verification and Debug | Issac P Zacharia and Jitendra Aggarwal | 2022 | Poster | | y2022 | poster |
| Hybrid Emulation: Accelerating Software Driven Verification and Debug | Issac P Zacharia and Jitendra Aggarwal | 2022 | Paper | | y2022 | paper |
| I created the Verification Gap | Ram Narayan and Tom Symons | 2015 | Paper | | y2015 | paper |
| I created the Verification Gap | Ram Narayan and Tom Symons | 2015 | Presentation | | y2015 | presentation |
| I’m Still In Love With My X! (but, do I want my X to be an optimist, a pessimist, or eliminated?) | Stuart Sutherland | 2013 | Paper | | y2013 | paper |
| I’m Still In Love With My X! (but, do I want my X to be an optimist, a pessimist, or eliminated?) | Stuart Sutherland | 2013 | Presentation | | y2013 | presentation |
| IDeALS for all – Intelligent Detection and Accurate Localization of Stalls | Pallavi Jesrani | 2020 | Paper | | y2020 | paper |
| IDeALS For All – Intelligent Detection and Accurate Localization of Stalls | Pallavi Jesrani | 2020 | Poster | | y2020 | poster |
| IDEs Should be Available to Hardware Engineers Too! | Syed Daniyal Khurram and Horace Chan | 2018 | Paper | | y2018 | paper |
| IDEs SHOULD BE AVAILABLE TO HARDWARE ENGINEERS TOO! | Syed Daniyal Khurram and Horace Chan | 2018 | Presentation | | y2018 | presentation |
| IEEE 1800-2009 SystemVerilog: Assertion-based Checker Libraries | Eduard Cerny and Dmitry Korchemny | 2010 | Paper | | y2010 | paper |
| IEEE 1800.2 UVM – Changes Useful UVM Tricks & Techniques | Clifford E. Cummings | 2019 | Presentation | | y2019 | presentation |
| IEEE-Compatible UVM Reference Implementation and Verification Components | Justin Refice, Mark Strickland, Mark Peryer, Uwe Simm, and Srivatsa Vasudevan | 2018 | Presentation | | y2018 | presentation |
| Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation | Eldon Nelson M.S. P.E. | 2017 | Paper | | y2017 | paper |
| Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation | Eldon Nelson M.S. P.E. | 2017 | Presentation | | y2017 | presentation |
| Improving Software Testing Speed by 100X with SystemC Virtualization in IoT Devices | David Barahona, Motaz Thiab, Isael Díaz, Joakim Urdahl, and Milica Orlandic | 2021 | Paper | | y2021 | paper |
| Improving the UVM Register Model: Adding Product Feature based API for Easier Test Programming | Krishnan Balakrishnan, Courtney Fricano, and Kaushal Modi | 2016 | Poster | | y2016 | poster |
| Improving the UVM Register Model: Adding Product Feature based API for Easier Test Programming | Krishnan Balakrishnan, Courtney Fricano, and Kaushal Modi | 2016 | Paper | | y2016 | paper |
| Improving Verification Predictability and Efficiency Using Big Data | Darron May | 2018 | Poster | | y2018 | poster |
| Improving Verification Predictability and Efficiency Using Big Data | Darron K. May | 2018 | Paper | | y2018 | paper |
| In pursuit of Faster Register Abstract Layer (RAL) Model | Anmol Rana, Bhagwan Jha, and Harjeet Singh Sanga | 2019 | Poster | | y2019 | poster |
| Incomplete Low-Power Verification Flow & the oncoming Internet of Things (IoT) Tsunami! | Neyaz Khan and Kamran Haqqani | 2016 | Paper | | y2016 | paper |
| Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee | Thomas Ellis | 2017 | Paper | | y2017 | paper |
| Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee | Thom Ellis | 2017 | Poster | | y2017 | poster |
| Increasing Regression Efficiency with Portable Stimulus | Niyaz. K. Zubair and Subba Kota Rao Sajja | 2020 | Paper | | y2020 | paper |
| Innovative Techniques to Solve Complex RDC Challenges | Rohit Kumar Sinha | 2020 | Presentation | | y2020 | presentation |
| Innovative Uses of SystemVerilog Bind Statements within Formal Verification | Xiushan Feng and Christopher Starr | 2022 | Paper | | y2022 | paper |
| Innovative Uses of SystemVerilog Bind Statements within Formal Verification | Xiushan Feng and Christopher Starr | 2022 | Presentation | | y2022 | presentation |
| Integration of HDL Logic inside SystemVerilog UVM based Verification IP | Aleksandra Panajotu | 2020 | Paper | | y2020 | paper |
| Integration of HDL Logic inside SystemVerilog UVM based Verification IP | Aleksandra Panajotu | 2020 | Poster | | y2020 | poster |
| Interface Centric UVM Acceleration for Rapid SOC Verification | Jiwoong Kim, Yoona Lhim, Hyungjin Park, Hyunsun Ahn, and Seonil Brian Choi | 2020 | Presentation | | y2020 | presentation |
| Interfacing Python with a Systemverilog Test Bench | Lakshay Grover and Kaushal Modi | 2019 | Poster | | y2019 | poster |
| INTERPRETING UPF FOR A MIXED-SIGNAL DESIGN UNDER TEST | Kenneth Bakalar and Eric Jeandeau | 2014 | Paper | | y2014 | paper |
| Interpreting UPF for aMixed‐Signal Design Under Test | | 2014 | Presentation | | y2014 | presentation |
| Introducing your team to an IDE | S. Dawson and M. Ballance | 2019 | Poster | | y2019 | poster |
| Introduction to the 5 Levels of RISC-V Processor Verification | Simon Davidmann and Lee Moore | 2022 | Presentation | | y2022 | presentation |
| Introspection Into Systemverilog Without Turning It Inside Out | Dave Rich | 2016 | Poster | | y2016 | poster |
| INTROSPECTION INTO SYSTEMVERILOG WITHOUT TURNING IT INSIDE OUT. | Dave Rich | 2016 | Paper | | y2016 | paper |
| IP Security Assurance Workshop: Introduction | Mike Borza, Ambar Sarkar, Adam Sherer, and Brent Sherman (in spirit) | 2020 | Presentation | | y2020 | presentation |
| IP-XACT based SoC Interconnect Verification Automation | YoungRae Cho, YoungSik Kim, and Seonil Brian Choi | 2018 | Paper | | y2018 | paper |
| IP-XACT based SoC Interconnect Verification Automation | YoungRae Cho, YoungSik Kim, and Seonil Brian Choi | 2018 | Presentation | | y2018 | presentation |
| IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 90 minutes! | Nikita Gulliya, Neena Chandawale, and Anupam Bakshi | 2022 | Presentation | | y2022 | presentation |
| Ironic But Effective: How Formal Analysis Can Perfect Your Simulation Constraints | Penny Yang, Jin Hou, Yuya Kao, Nan-Sheng Huang, Ping Yeung, and Joe Hupcey | 2017 | Presentation | | y2017 | presentation |
| Ironic But Effective: How Formal Analysis Can Perfect Your Simulation Constraints | Penny Yang, Jin Hou, Yuya Kao, Nan-Sheng Huang, Ping Yeung, and Joe Hupcey | 2017 | Paper | | y2017 | paper |
| Is It a Software Bug? Is It a Hardware Bug? | Horace Chan, Mame Maria Mbaye, and Sim Ang | 2022 | Paper | | y2022 | paper |
| Is It a Software Bug? It Is a Hardware Bug? | Horace Chan, Maria Mbaye, and Sim Ang | 2022 | Presentation | | y2022 | presentation |
| Is Power State Table (PST) Golden? | Ankush Bagotra, Neha Bajaj, and Harsha Vardhan | 2012 | Presentation | | y2012 | presentation |
| Is Power State Table Golden? | Harsha Vardhan, Ankush Bagotra, and Neha Bajaj | 2012 | Paper | | y2012 | paper |
| Is Specman Still Relevant? Using UVM-ML to Take Advantage of Multiple Verification Languages | Timothy Pertuit, David Lacey, and Doug Gibson | 2018 | Poster | | y2018 | poster |
| Is Specman Still Relevant? Using UVM-ML to Take Advantage of Multiple Verification Languages | Timothy Pertuit, Doug Gibson, and David Lacey | 2018 | Paper | | y2018 | paper |
| Is the simulator behavior wrong for my SystemVerilog code? | Weihua Han | 2017 | Paper | | y2017 | paper |
| Is The Simulator Behavior Wrong With My SystemVerilog Code | Weihua Han | 2017 | Presentation | | y2017 | presentation |
| Is Your Hardware Dependable? | DARPA, AMD, Arm Research, and Synopsys | 2022 | Presentation | | y2022 | presentation |
| Is your Power Aware design really x-aware? | Durgesh Prasad and Jitesh Bansal | 2014 | Paper | | y2014 | paper |
| Is your Power Aware design really x-aware? | Durgesh Prasad and Jitesh Bansal | 2014 | Poster | | y2014 | poster |
| ISO 26262 Dependent Failure Analysis using PSS | Moonki Jang, Jiwoong Kim, and Dongjoo Kim | 2020 | Paper | | y2020 | paper |
| ISO 26262 Dependent Failure Analysis Using PSS | Moonki Jang | 2020 | Presentation | | y2020 | presentation |
| It Should Just Work! Tips and Tricks for Creating Flexible, Vendor Agnostic Analog Behavioral Models | Chuck McClish | 2020 | Presentation | | y2020 | presentation |
| It’s Been 24 Hours –Should I Kill My Formal Run? | Mark Eslinger, Jin Hou, Joe Hupcey III, and Jeremy Levitt | 2019 | Presentation | | y2019 | presentation |
| JESD204B Deterministic Latency Verification with UVM Constrained Random Approaches | Girish Nadiger and Ashok Chandran | 2016 | Poster | | y2016 | poster |
| JESD204B Deterministic Latency Verification with UVM Constrained Random Approaches | Girish Nadiger and Ashok Chandran | 2016 | Paper | | y2016 | paper |
| Jump start your RISCV project with OpenHW | Mike Thompson, Jingliang (Leo) Wang, Steve Richmond, Lee Moore, David McConnell, Greg Tumbush | 2021 | Paper | | y2021 | paper |
| Jump-Start Portable Stimulus Test Creation with SystemVerilog Reuse | Matthew Ballance | 2016 | Poster | | y2016 | poster |
| Jump-Start Portable Stimulus Test Creation with SystemVerilog Reuse | Matthew Ballance | 2016 | Paper | | y2016 | paper |
| Jump-Start Software-Driven Hardware Verification with a Verification Framework | Matthew Ballance | 2015 | Poster | | y2015 | poster |
| Jump-Start Software-Driven Hardware Verification with a Verification Framework | Matthew Ballance | 2015 | Paper | | y2015 | paper |
| Just do it! Who cares if a Structural Analysis tool is using Formal Verification | Scott Aron Bloom | 2018 | Presentation | | y2018 | presentation |
| Keeping Score, Part 1 of 2 – Architectural Considerations for Scoreboard Design | Gordon Allan | 2012 | Paper | | y2012 | paper |
| Keeping Up with Chip — the Proposed SystemVerilog 2012 Standard Makes Verifying Ever-increasing Design Complexity More Efficient | Stuart Sutherland and Tom Fitzpatrick | 2012 | Paper | | y2012 | paper |
| Keeping Up with Chip — the Proposed SystemVerilog 2012 Standard Makes Verifying Ever-increasing Design Complexity More Efficient | Stuart Sutherland | 2012 | Presentation | | y2012 | presentation |
| Keeping Your Sequences Relevant | Nicholas Zicha and Eric Combes | 2017 | Paper | | y2017 | paper |
| Key Gochas in implementing CDC for various Bus Protocols | Nikita Gulliya, Mukesh Kumar Singh, and Abhishek Bora | 2020 | Paper | | y2020 | paper |
| Key Gochas in implementing CDC for various Bus Protocols | Nikita Gulliya, Mukesh Kumar Singh, and Abhishek Bora | 2020 | Poster | | y2020 | poster |
| Lay it On Me: Creating Layered Constraints | Bryan Morris | 2021 | Paper | | y2021 | paper |
| Leaping Left: Seamless IP to SoC Hand off | Swetha Thiagarajan, Rashika Madan, Hiran Morar, and Sangeivi Sivagnanasundaram | 2022 | Presentation | | y2022 | presentation |
| Leaping Left: Seamless IP to SoC Hand-off | Swetha Thiagarajan, Rashika Madan, Hiran Morar, and Sangeivi Sivagnanasundaram | 2022 | Paper | | y2022 | paper |
| Learning From Advanced Hardware Verification for Hardware Dependent Software | Simond Davidmann and Duncan Graham | 2014 | Paper | | y2014 | paper |
| Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges | Kotha Kavya and Sinha Rohit Kumar | 2022 | Poster | | y2022 | poster |
| Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges | Rohit Kumar Sinha and Kavya Kotha | 2022 | Paper | | y2022 | paper |
| Lessons from the field – IP/SoC integration techniques that work | David Murray and Sean Boylan | 2013 | Paper | | y2013 | paper |
| Lessons from the field IP/SoC integration techniques that work | David Murray | 2013 | Presentation | | y2013 | presentation |
| Let’s be Formal While Talking About Verification Quality: A Novel Approach to Qualify Assertion Based VIPs | Sachin Scaria, Surinder Sood, and Erik Seligman | 2018 | Paper | | y2018 | paper |
| Let’s DisCOVER Power States | Pankaj Kumar Dwivedi, Amit Srivastava, and Veeresh Vikram Singh | 2015 | Paper | | y2015 | paper |
| Lets be Formal While Talking About Verification Quality: A Novel Approach Of Qualifying Assertion Based IPs | Surinder Sood, Sachin Scaria, and Erik Seligman | 2018 | Presentation | | y2018 | presentation |
| Lets disCOVER Power States | Pankaj Kumar Dwivedi, Amit Srivastava, and Veeresh Vikram Singh | 2015 | Poster | | y2015 | poster |
| Leveraging Formal to Verify SoC Register Map | Abdul Elaydi and Jose Barandiaran | 2014 | Paper | | y2014 | paper |
| Leveraging Formal to Verify SoC Register Map | Abdul Elaydi and Jose Barandiaran | 2014 | Presentation | | y2014 | presentation |
| Leveraging IP-XACT standardized IP interfaces for rapid IP integration | David Murray and Simon Rance | 2014 | Paper | | y2014 | paper |
| Leveraging IP-XACT Standardized IP Interfaces for Rapid IP Integration | David Murray | 2014 | Presentation | | y2014 | presentation |
| Leveraging more from GLS: Using metric driven GLS stimuli to boost Timing Verification | Sowmya Ega, Richardson Jeyapaul, and Kunal Jani | 2018 | Paper | | y2018 | paper |
| Leveraging more from GLS: Using metric driven GLS stimuli to boost timing verification | Sowmya Ega, Richardson Jeyapaul, and Kunal Jani | 2018 | Presentation | | y2018 | presentation |
| Leveraging Virtual Platform ESL and TLM SystemVerification in RTL using UVM | Ashok Mehta, Albert Chiang, and Wei-Hua Han | 2012 | Paper | | y2012 | paper |
| Lies, Damned Lies, and Coverage | Mark Litterick | 2015 | Paper | | y2015 | paper |
| Lies, Damned Lies, and Coverage | Mark Litterick | 2015 | Presentation | | y2015 | presentation |
| Low Power Apps (Shaping the Future of Low Power Verification) | Awashesh Kumar, Madhur Bhargava, Vinay Kumar Singh, and Pankaj Gairola | 2018 | Presentation | | y2018 | presentation |
| Low Power Apps: Shaping the Future of Low Power Verification | Awashesh Kumar, Madhur Bhargava, Vinay Singh, and Pankaj Gairola | 2018 | Paper | | y2018 | paper |
| Low Power Coverage: The Missing Piece in Dynamic Simulation | Progyna Khondkar, Gabriel Chidolue, and Ping Yeung | 2018 | Paper | | y2018 | paper |
| Low Power Coverage: The Missing Piece in Dynamic Simulation | Progyna Khondkar | 2018 | Presentation | | y2018 | presentation |
| Low Power SoC Verification: IP Reuse and Hierarchical Composition using UPF | Amit Srivastava, Rudra Mukherjee, Erich Marschner, and Chuck Seeley | 2012 | Presentation | | y2012 | presentation |
| Low Power SoC Verification: IP Reuse and Hierarchical Composition using UPF | Amit Srivastava, Rudra Mukherjee, Erich Marschner, and Chuck Seeley | 2012 | Paper | | y2012 | paper |
| Low Power Static Verification- Beyond Linting and Corruption Semantics | Kaustav Guha , Ankush Bagotra, and Neha Bajaj | 2011 | Paper | | y2011 | paper |
| Low Power Verification With LDO | Shang-Wei Tu, Amol Herlekar, and Yu-Juei Chen | 2016 | Paper | | y2016 | paper |
| Low Power Verification with LDO | Shang-Wei Tu and Amol Herlekar | 2016 | Poster | | y2016 | poster |
| Low Power Verification with UPF: Principle and Practice | Jianfeng Liu, Mi-Sook Hong, Bong Hyun Lee JungYun Choi, HyoSig Won, Kyu-Myung Choi, Harsha Vardhan, and Aditya Kher | 2010 | Paper | | y2010 | paper |
| Low-Power Verification at Gate Level for Zen Microprocessor Core | Baosheng Wang, Keerthi Mullangi, Raluca Stan, and Diana Irimia | 2020 | Presentation | | y2020 | presentation |
| Low-Power Verification Automation – A Practical Approach | Shaji Kunjumohamed and Hendy Kosasih | 2013 | Paper | | y2013 | paper |
| LOW-POWER VERIFICATION AUTOMATION: A PRACTICAL APPROACH | Shaji K. Kunjumohamed and Hendy Kosasih | 2013 | Poster | | y2013 | poster |
| Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design Verification | Honghuang Lin, Zhipeng Ye, and Asad Khan | 2017 | Presentation | | y2017 | presentation |
| Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design Verification | H. Lin, Z. Ye, and A. M. Khan | 2017 | Paper | | y2017 | paper |
| Machine Learning Based Verification Planning Methodology Using Design and Verification Data | Hanna Jang, Seonghee Yim, Sunchang Choi, and Seonil Brian Choi | 2022 | Paper | | y2022 | paper |
| Machine Learning Based Verification Planning Methodology Using Design and Verification Data | Hanna Jang, Seonghee Yim | 2022 | Presentation | | y2022 | presentation |
| Machine Learning Driven Verification A Step Function in Productivity and Throughput | Daniel Hansson, John Rose, and Matt Graham | 2022 | Presentation | | y2022 | presentation |
| Machine Learning-Guided Stimulus Generation for Functional Verification | Saumil Gogri, Jiang Hu, Aakash Tyagi, Mike Quinn, Swati Ramachandran, Fazia Batool, and Amrutha Jagadeesh | 2020 | Paper | | y2020 | paper |
| Machine Learning-Guided Stimulus Generation for Functional Verification | S. Gogri, J. Hu, A. Tyagi, M. Quinn S. Ramachandran, F. Batool, and A. Jagadeesh | 2020 | Presentation | | y2020 | presentation |
| Making Autonomous Cars Safer – One chip at a time | Apurva Kalia and Ann Keffer | 2018 | Presentation | | y2018 | presentation |
| Making Formal Property Verification Mainstream: An Intel Graphics Experience | M Achutha KiranKumar V, Erik Seligman, Aarti Gupta, Ss Bindumadhava, and Abhijith Bharadwaj | 2017 | Paper | | y2017 | paper |
| Making Formal Property Verification Mainstream: An Intel® Graphics Experience | M Achutha Kiran, Kumar V., Erik Seligman, Aarti Gupta, Bindumadhava S. S., and Abhijith A. Bharadwaj | 2017 | Presentation | | y2017 | presentation |
| Making Legacy Portable with the Portable Stimulus Specification | Matthew Ballance | 2017 | Presentation | | y2017 | presentation |
| Making Legacy Portable with the Portable Stimulus Specification | Matthew Ballance | 2017 | Paper | | y2017 | paper |
| Making RAL Jump, an Introspection | Jeremy Ridgeway, Karishma Dhruv, and Manmohan Singh | 2014 | Paper | | y2014 | paper |
| Making RAL Jump, an Introspection | Jeremy Ridgeway, Karishma Dhruv, and Manmohan Singh | 2014 | Poster | | y2014 | poster |
| Making Security Verification “SECURE” | NAGESH RANGANATH and SUBIN THYKKOOTTATHIL | 2018 | Poster | | y2018 | poster |
| Making Security Verification “SECURE” | Subin Thykkoottathil and Nagesh Ranganath | 2018 | Paper | | y2018 | paper |
| Making Your DPI-C Interface a Fast River of Data | Rich Edelman | 2021 | Paper | | y2021 | paper |
| Managing and Automating Hw/Sw Tests from IP to SoC | Matthew Ballance | 2018 | Poster | | y2018 | poster |
| MANAGING AND AUTOMATING HW/SW TESTS FROM IP TO SOC | Matthew Ballance | 2018 | Paper | | y2018 | paper |
| Managing Highly Configurable Design and Verification | J. Ridgeway | 2018 | Paper | | y2018 | paper |
| Managing Highly Configurable Design and Verification | Jeremy Ridgeway | 2018 | Presentation | | y2018 | presentation |
| Marrying Simulation and Formal Made Easier! | Lun Li, Durga Rangarajan, Christopher Starr, and James Greene | 2016 | Paper | | y2016 | paper |
| Matrix Math package for VHDL | David W. Bishop | 2015 | Poster | | y2015 | poster |
| Matrix Math package for VHDL | David W. Bishop | 2015 | Paper | | y2015 | paper |
| Maximize Vertical Reuse, Building Module to System Verification Environments with UVM e | Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss | 2013 | Paper | | y2013 | paper |
| Maximize Vertical Reuse, Building Module to System Verification Environments with UVMe | Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss | 2013 | Poster | | y2013 | poster |
| Maximizing Formal ROI through Accelerated IP Verification Sign-off | Scott Peverelle, Hao Chen, Kamakshi Sarat Vallabhapurapu, Rosanna Yee, Hee Chul Kim, Johann Te, and Jacob Hotz | 2022 | Presentation | | y2022 | presentation |
| Maximizing Formal ROI through Accelerated IP Verification Sign-off | Hao Chen, Kamakshi Sarat Vallabhapurapu, Scott Peverelle, Rosanna Yee, Hee Chul Kim, Johann Te, and Jacob Hotz | 2022 | Paper | | y2022 | paper |
| May the powers be with you! – Unleashing powerful new features in UPF IEEE 1801 | Srinivasan Venkataramanan and Ajeetha Kumari | 2020 | Presentation | | y2020 | presentation |
| Mechanism to Generate FIFO VC Dependency Graph and Its Application to System Level Deadlock Verification | Debarshi Chatterjee, Chad Parsons, Siddhanth Dhodhi | 2021 | Paper | | y2021 | paper |
| Media Performance Validation in Emulation and Post Silicon Using Portable Stimulus Standard | Suresh Vasu, Nithin Venkatesh, Joydeep Maitra | 2021 | Paper | | y2021 | paper |
| Melioration of Enhanced Low Power Memory Retention and Low Power Feature Validation Using API’s | Nithin Venkatesh, Akula Hareesh | 2021 | Paper | | y2021 | paper |
| Melting Verification Pot: Integrating RVM/VMM and UVM, a Practical Guide and Lessons Learned. | Mark A. Azadpour | 2012 | Paper | | y2012 | paper |
| Melting Verification Pot: Integrating RVM/VMM and UVM, a Practical Guide and Lessons Learned. | Mark Azadpour | 2012 | Presentation | | y2012 | presentation |
| Memory Debugging of Virtual Platforms | George F. Frazier, Neeti Bhatnagar, Qizhang Chao, and Kathy Lang | 2012 | Presentation | | y2012 | presentation |
| Memory Debugging of Virtual Prototypes with TLM 2.0 | George F. Frazier, Qizhang Chao, Neeti Bhatnagar, and Kathy Lang | 2012 | Paper | | y2012 | paper |
| Memory Subsystem Verification – Can it be taken for granted? | Shivani Upasani | 2013 | Presentation | | y2013 | presentation |
| Memory Subsystem Verification: Can it be taken for granted? | Shivani Upasani and Prashanth Srinivasa | 2013 | Paper | | y2013 | paper |
| Meta Design Framework | Sanjeev Singh and Jonathan Sadowsky | 2015 | Poster | | y2015 | poster |
| Meta Design Framework: Building Designs Programmatically | Sanjeev Singh and Jonathan Sadowsky | 2015 | Paper | | y2015 | paper |
| Metadata Based Testbench Generation | Daeseo Cha, Soonoh Kwon, and Ahhyung Shin | 2022 | Presentation | | y2022 | presentation |
| Metadata Based Testbench Generation Automation | Daeseo Cha, Soonoh Kwon, Ahhyung Shin, Youngnam Youn, Youngsik Kim, and Seonil Brian Choi | 2022 | Paper | | y2022 | paper |
| Method for Generating Unique Coverage Classes to Enable Meaningful Covergroup Merges Across Testbenches | Eldon Nelson, MS, PE | 2015 | Paper | | y2015 | paper |
| Method for Generating Unique Coverage Classes to Enable Meaningful Covergroup Merges Across Testbenches | Eldon Nelson, M.S., P.E. | 2015 | Presentation | | y2015 | presentation |
| Methodology for automating coverage-driven interrupt testing of instruction sets | David McConnell, Greg Tumbush | 2021 | Paper | | y2021 | paper |
| Methodology for Separation of Design Concerns Using Conservative RTL Flipflop Inference | Maya H. Safieddine, Fadi A. Zaraket, and Rouwaida Kanj | 2015 | Presentation | | y2015 | presentation |
| Methodology for Separation of Design Concerns Using Conservative RTL Flipflop Inference | Maya H. Safieddine, Fadi A. Zaraket, and Rouwaida Kanj | 2015 | Paper | | y2015 | paper |
| Metric Driven Mixed-Signal Verification Methodology and Practices for Complex Mixed-signal ASSPs | Frank Yang, Andy Sha, Morton Zhao, and Yanping Sha | 2014 | Paper | | y2014 | paper |
| Metric Driven Mixed-Signal Verification Methodology and Practices for Complex Mixed-signal ASSPs | Frank Yang, Andy Sha, Morton Zhao, and Yanping Sha | 2014 | Poster | | y2014 | poster |
| Metric Driven Verification of Mixed-Signal Designs | Neyaz Khan, Yaron Kashai, and Hao Fang | 2011 | Paper | | y2011 | paper |
| Metrics Driven Sign-off for SoC Specific Logic (SSL) Using Formal Techniques | Abhinav Gaur, Gaurav Jain, Ruchi Singh | 2021 | Paper | | y2021 | paper |
| Metrics in SoC Verification | Andreas Meyer and Harry Foster | 2012 | Paper | | y2012 | paper |
| Micro-processor verification using a C++11 sequence-based stimulus engine. | Stephan Bourduas and Chris Mikulis | 2017 | Paper | | y2017 | paper |
| Micro-processor verification using a C++11 sequence-based stimulus engine. | Stephan Bourduas and Chris Mikulis | 2017 | Presentation | | y2017 | presentation |
| Migrating from OVM to UVM The Definitive Guide | Adiel Khan | 2013 | Presentation | | y2013 | presentation |
| Migrating to UVM : Conquering Legacy | Santosh Sarma, Amit Sharma, and Adiel Khan | 2013 | Paper | | y2013 | paper |
| Mind the Gap(s): Creating & Closing Gaps Between Design and Verification | Chris Giles and Kurt Takara | 2020 | Presentation | | y2020 | presentation |
| Mining Coverage Data for Test Set Coverage Efficiency | Monica Farkash, Bryan Hickerson, Mike Behm, and Balavinayagam Samynathan | 2015 | Paper | | y2015 | paper |
| Mining Coverage Data for Test Set Coverage Efficiency | Bryan Hickerson, Mike Behm, Balavinayagam Samynathan, and Monica Farkash | 2015 | Presentation | | y2015 | presentation |
| Mixed Signal Assertion-Based Verification | Prabal Bhattacharya, Don O’Riordan, and Walter Hartong | 2011 | Paper | | y2011 | paper |
| Mixed Signal Design Verification: Leveraging the Best of AMS and DMS | Rock Z. Shi, Padmashree Bhinge, Preston Birdsong, Geeta Chaitanya, and Kunal Jani | 2022 | Presentation | | y2022 | presentation |
| Mixed Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP Simulation | S. Do, J. Park, D. Kim, and J. Jang | 2022 | Presentation | | y2022 | presentation |
| Mixed Signal Verification of a Voltage Regulator using a State Space Approach and the SV-DC extensions | Rajat Mitra | 2016 | Paper | | y2016 | paper |
| Mixed Signal Verification of Dynamic Adaptive Power Management in Low Power SoC | Neyaz Khan | 2010 | Paper | | y2010 | paper |
| Mixed Signal Verification of UPF based designs A Practical Example | Andrew Milne and Damian Roberts | 2015 | Presentation | | y2015 | presentation |
| Mixed Signal Verification of UPF based designs A Practical Example | Andrew Milne and Damian Roberts | 2015 | Paper | | y2015 | paper |
| Mixed-abstraction Modeling Approach with Fault Injection for Hardware-Firmware Co-design and Functional Co-verification of an Automotive Airbag System on Chip Product | Dipl.-Ing. Dr.-techn. Thang Nguyen, Dipl.-Ing. and Dieter Haerle | 2013 | Paper | | y2013 | paper |
| Mixed-abstraction Modeling Approach with Fault Injection for Hardware-Firmware Co-design and Functional Co-verification of an Automotive Airbag System on Chip Product | Thang Nguyen, Dipl.-Ing.-Dr. and Dieter Haerle, Dipl.-Ing. | 2013 | Presentation | | y2013 | presentation |
| Mixed-Signal Design Verification: Leveraging the Best of AMS and DMS | Rock Z. Shi, Padmashree Bhinge, Preston Birdsong, Geeta Chaitanya, and Kunal Jani | 2022 | Paper | | y2022 | paper |
| Mixed-Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP Simulation | S. Do, J. Park, D. Kim, and J. Jang | 2022 | Paper | | y2022 | paper |
| Mixed-Signal Systems-on-Chip Design Verification With Automatic Real-Number Abstraction | Nancy Qiu, Frank Yang, and Himadri De | 2016 | Paper | | y2016 | paper |
| Mixed-Signal Verification Methodology to Verify Type-C USB | Varun R, Vinayak Hegde, and Somasunder Kattepura Sreenath | 2017 | Paper | | y2017 | paper |
| Mixed-Signal Verification Methodology to Verify USB Type-C | Varun R, Vinayak Hegde ans Somasunder Kattepura Sreenath | 2017 | Poster | | y2017 | poster |
| ML-Based Verification and Regression Automation | Abhishek Chauhan, Asif Ahmad | 2021 | Paper | | y2021 | paper |
| Modeling a Hierarchical Register Scheme with UVM | Joshua Hardy | 2017 | Presentation | | y2017 | presentation |
| Modeling a Hierarchical Register Scheme with UVM | Joshua Hardy | 2017 | Paper | | y2017 | paper |
| Modeling Analog Devices Using SV-RNM | Mariam Maurice | 2022 | Poster | | y2022 | poster |
| Modeling Analog Devices using SV-RNM | Mariam Maurice | 2022 | Paper | | y2022 | paper |
| Modeling Analog Systems Using Full Digital Simulations (A State Space Approach) | Rajat K Mitra | 2016 | Presentation | | y2016 | presentation |
| Modeling Memory Coherency During Concurrent/Simultaneous Accesses | Subramoni Parameswaran | 2022 | Paper | | y2022 | paper |
| Modeling Memory Coherency for concurrent/parallel accesses | Subramoni Parameswaran | 2022 | Presentation | | y2022 | presentation |
| Modeling Memory Coherency for Concurrent/Parallel Accesses | Subramoni Parameswaran | 2022 | Presentation | | y2022 | presentation |
| Molding Functional Coverage for Highly Configurable IP | J. Ridgeway, K. Chaturvedula, and K. Dhruv | 2016 | Paper | | y2016 | paper |
| Molding Functional Coverage for Highly Configurable IP | Jeremy Ridgeway, Kavitha Chaturvedula, and Karishma Dhruv | 2016 | Poster | | y2016 | poster |
| Monitors, Monitors Everywhere – Who Is Monitoring the Monitors | Rich Edelman and Raghu Ardeishar | 2013 | Paper | | y2013 | paper |
| Monitors, Monitors Everywhere … | Rich Edelman and Raghu Ardeishar | 2013 | Poster | | y2013 | poster |
| Moving beyond Assertions: An Innovative approach to Low-Power Checking using UPF Tcl Apps | Madhur Bhargava | 2019 | Poster | | y2019 | poster |
| MS-SoC Best Practices – Advanced Modeling & Verification Techniques for first-pass success | Neyaz Khan, Greg Glennon, and Dan Romaine | 2013 | Paper | | y2013 | paper |
| Multi-Domain Verification: When Clock, Power and Reset Domains Collide | Ping Yeung, Erich Marschner, and Kaowen Liu | 2015 | Paper | | y2015 | paper |
| Multi-Domain Verification: When Clock, Power and Reset Domains Collide | Ping Yeung, Erich Marschner, and Kaowen Liu | 2015 | Presentation | | y2015 | presentation |
| Multi-Language Verification: Solutions for Real World Problems | Bryan Sniderman and Vitaly Yankelevich | 2014 | Paper | | y2014 | paper |
| Multi-Language Verification: Solutions for Real World Problems | Bryan Sniderman and Vitaly Yankelevich | 2014 | Presentation | | y2014 | presentation |
| Multimedia IP DMA verification platform | Suhyung Kim, Sangkyu Park, Myungwoo Seo, Sangjin Lee, and Jiyeon Park | 2020 | Paper | | y2020 | paper |
| Multimedia IP DMA verification platform | Suhyung Kim, Sangkyu Park, Myungwoo Seo, Sangjin Lee, and Jiyeon Park | 2020 | Poster | | y2020 | poster |
| Multiplier-Adder-Converter Linear Piecewise Approximation for Low Power Graphics Applications | Dina M. Ellaithy, Magdy A. El-Moursy, Amal Zaki, and Abdelhalim Zekry | 2019 | Poster | | y2019 | poster |
| Multithreading a UVM Testbench for Faster Simulation | Benjamin Applequist, Vijayakrishnan Rousseau, Andrew Tan, and Jayasrinivas Sesham | 2020 | Presentation | | y2020 | presentation |
| My Testbench Used to Break! Now it Bends (Adapting to Changing Design Configurations) | Jeff Vance, Jeff Montesano, Kevin Vasconcellos, and Kevin Johnston | 2018 | Presentation | | y2018 | presentation |
| My Testbench Used to Break! Now it Bends: Adapting to Changing Design Configurations | Jeff Vance, Jeff Montesano, Kevin Vasconcellos, and Kevin Johnston | 2018 | Paper | | y2018 | paper |
| Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage Modeling | Jason Sprott, Paul Marriott, and Matt Graham | 2015 | Paper | | y2015 | paper |
| Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage Modeling | Jason Sprott, Paul Marriott, and Matt Graham | 2015 | Presentation | | y2015 | presentation |
| Never Too Late With Formal: Stepwise Guide for Applying Formal Verification in Post-Silicon Phase to Avoid Re-Spins | Anshul Jain, Aarti Gupta, Achutha KiranKumar V M, Bindumadhava Ss, Shivakumar S Kolar, and Siva Gadey NV | 2022 | Paper | | y2022 | paper |
| Never Too Late with Formal: Stepwise Guide for Applying FV in Post Si Phase to Avoid Re-Spins | Anshul Jain, Aarti Gupta, Achutha KiranKumar V M, Bindumadhava Ss, Shivakumar S Kolar, Siva Gadey NV | 2022 | Presentation | | y2022 | presentation |
| New and active ways to bind to your design | Kaiming Ho | 2013 | Presentation | | y2013 | presentation |
| New and Active Ways to Bind to Your Designs | Kaiming Ho | 2013 | Paper | | y2013 | paper |
| New Challenges in Verification of Mixed-Signal IP and SoC Design | Luke Lang and Christina Chu | 2012 | Paper | | y2012 | paper |
| New Constrained Random and Metric-Driven Verification Methodology using Python | Marek Ciepłucha and Witold Pleskacz | 2017 | Presentation | | y2017 | presentation |
| New Constrained Random and Metric-Driven Verification Methodology using Python | Marek Cieplucha and Witold A. Pleskacz | 2017 | Paper | | y2017 | paper |
| Next Gen System Design and Verification for Transportation | David Aerne, Jacob Wiltgen, and Richard Pugh | 2019 | Presentation | | y2019 | presentation |
| Next Generation Verification for the Era of AI/ML and 5G | Frank Schirrmeister, Pete Hardee, Larry Melling, Amit Dua, and Moshik Rubin | 2020 | Presentation | | y2020 | presentation |
| Next-generation Power Aware CDC Verification – What have we learned? | Kurt Takara, Chris Kwok, Naman Jain, and Ashish Hari | 2015 | Paper | | y2015 | paper |
| Next-generation Power Aware CDC Verification What have we learned? | Kurt Takara, Chris Kwok, Naman Jain, and Ashish Hari | 2015 | Poster | | y2015 | poster |
| No RTL Yet? No Problem UVM Testing a SystemVerilog Fabric Model | Rich Edelman | 2016 | Presentation | | y2016 | presentation |
| No RTL Yet? No Problem UVM Testing a SystemVerilog Fabric Model | Rich Edelman | 2016 | Paper | | y2016 | paper |
| NOT JUST FOR HARDWARE DEBUG: PROTOTYPE DEBUGGERS FOR SYSTEM VALIDATION AND OPTIMIZATION | Michael Sachtjen and Joe Gaubatz | 2015 | Poster | | y2015 | poster |
| Not Just for Hardware Debug: Prototype Debuggers for System Validation and Optimization | Michael Sachtjen and Joe Gaubatz | 2015 | Paper | | y2015 | paper |
| Novel Approach to ASIC Prototyping | Mohamed Saheel, Suresh Balasubramanian, and Vijayakrishnan Rousseau | 2019 | Poster | | y2019 | poster |
| Novel Approaches for C vs. RTL Formal Verification of Vertex Attribute Address Generator Unit | Nianchen Wu, Christopher Starr, and Xiushan Feng | 2020 | Presentation | | y2020 | presentation |
| Novel GUI Based UVM Test Bench Template Builder | Vignesh Manoharan | 2022 | Poster | | y2022 | poster |
| Novel GUI Based UVM Test Bench Template Builder | Vignesh Manoharan | 2022 | Paper | | y2022 | paper |
| Novel Mixed Signal Verification Methodology using complex UDNs | Rakesh Dama, Ravi Reddy, and Andy Vitek | 2019 | Paper | | y2019 | paper |
| Novel Mixed Signal Verification Methodology Using Complex UDNs | Rakesh Dama, Ravi Reddy, and Andy Vitek | 2019 | Presentation | | y2019 | presentation |
| Novel Paradigm in Formally Verifying Complex Algorithms | M Achutha KiranKumar V, Disha Puri, Mohit Choradia, Paras Gupta | 2021 | Paper | | y2021 | paper |
| Novel Test Case Design Techniques for Logical Specifications of Safety Critical Systems Software in Aerial Vehicle | Lakshmi KVNS and Sanjeev Kumar | 2017 | Paper | | y2017 | paper |
| Novel Verification Techniques for ARM A15 Multi-core Subsystem Using IEEE 1647 | Vaibhav Mahimkar, Akshit Dayal, Tomas Huynh, Van Huynh, and Erwin Hermanto | 2014 | Poster | | y2014 | poster |
| Novel Verification Techniques for ARM A15 Multi-core Subsystem Using IEEE 1647 | Vaibhav Mahimkar, Akshit Dayal, Tomas Huynh, Van Huynh, and Erwin Hermanto. | 2014 | Paper | | y2014 | paper |
| Novelty-Driven Verification: Using Machine Learning to Identify Novel Stimuli and Close Coverage | Tim Blackmore, Rhys Hodson, Sebastian Schaal | 2021 | Paper | | y2021 | paper |
| NVMe Development and Debug for a 16 x Multicore System | Soummya Mallick, Raj Mathur, Arindam Guha, and Frank Schirrmeister | 2019 | Paper | | y2019 | paper |
| Of Camels and Committees | Tom Fitzpatrick and Dave Rich | 2014 | Paper | | y2014 | paper |
| Of Camels and Committees: Standardization Should Enable Innovation, Not Strangle It | Tom Fitzpatrick and Dave Rich | 2014 | Presentation | | y2014 | presentation |
| Off To The Races With Your Accelerated SystemVerilog Testbench (A Methodology for Hardware-Assisted Acceleration of SystemVerilog Testbenches) | Hans van der Schoot, Anoop Saha, Ankit Garg, and Krishnamurthy Suresh | 2011 | Paper | | y2011 | paper |
| On Verification Coverage Metrics in Formal Verification and Speeding Verification Closure with UCIS Coverage Interoperability Standard | Rajeev Ranjan, PhD, Ross Weber, and Ziyad Hanna, PhD | 2013 | Paper | | y2013 | paper |
| One Compile to Rule them All: An elegant solution for OVM/UVM Testbench Topologies | Galen Blake and Steve Chappell | 2013 | Presentation | | y2013 | presentation |
| One Compile to Rule Them All: An Elegant Solution for OVM/UVM Testbench Topologies | Galen Blake and Steve Chappell | 2013 | Paper | | y2013 | paper |
| One Stop Solution for DFT Register Modelling in UVM | Rui Huang | 2017 | Paper | | y2017 | paper |
| One Stop Solution of DFT Register Modelling in UVM | Rui Huang | 2017 | Presentation | | y2017 | presentation |
| Open-source Framework for Co-emulation using PYNQ | Ioana-Cătălina Cristea, Dragoș Dospinescu | 2021 | Paper | | y2021 | paper |
| Optimal Usage of the Computer Farm for Regression Testing | Daniel Hansson and Patrik Granath | 2016 | Presentation | | y2016 | presentation |
| Optimal Usage of the Computer Farm for Regression Testing | Daniel Hansson and Patrik Granath | 2016 | Paper | | y2016 | paper |
| Optimizing Area and Power Using Formal Method | Alan Carlin, Chris Komar Cadence, and Anuj Singhania | 2011 | Paper | | y2011 | paper |
| Optimizing Random Test Constraints Using Machine Learning Algorithms | Stan Sokorac | 2017 | Presentation | | y2017 | presentation |
| Optimizing Random Test Constraints Using Machine Learning Algorithms | Stan Sokorac | 2017 | Paper | | y2017 | paper |
| Optimizing Turnaround Times In A CI Flow Using a Scheduler Implementation | Robert Strong | 2022 | Presentation | | y2022 | presentation |
| Optimizing Turnaround Times in a Continuous Integration Flow Using a Scheduler Based Implementation | Robert Strong | 2022 | Paper | | y2022 | paper |
| OS aware IP Development Methodology | Hyunjae Woo, Woojoo Kim, Youngsik Kim, and Seonil Brian Choi | 2019 | Presentation | | y2019 | presentation |
| OS-aware IP Development Methodology | Hyunjae Woo, Woojoo Kim, Youngsik Kim, and Seonil Brian Choi | 2019 | Paper | | y2019 | paper |
| OS-aware Performance and Power Analysis Methodology | Hyunjae Woo, HojinJo, Woojoo Kim, and Seonil Brian Choi | 2020 | Presentation | | y2020 | presentation |
| Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath Scoreboards | Bochra El-Meray and Jörg Müller | 2013 | Presentation | | y2013 | presentation |
| Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath Scoreboards | Bochra Elmaray and Joerg Mueller | 2013 | Paper | | y2013 | paper |
| OVM & UVM Techniques for On-the-fly Reset | Muralidhara Ramalingaiah and Boobalan Anantharaman | 2012 | Paper | | y2012 | paper |
| OVM & UVM Techniques for On-the-fly Reset | Muralidhara Ramalingaiah and Boobalan Anantharaman | 2012 | Presentation | | y2012 | presentation |
| OVM & UVM Techniques for Terminating Tests | Clifford E. Cummings and Tom Fitzpatrick | 2011 | Paper | | y2011 | paper |
| OVM TO UVM DEFINITIVE GUIDE PART 1 | Adiel Khan, Justin Refice, and Warren Stapleton | 2013 | Paper | | y2013 | paper |
| PA-APIs: Looking beyond power intent specification formats | Amit Srivastava and Awashesh Kumar | 2015 | Paper | | y2015 | paper |
| PA-APIs: Looking beyond power intent specification formats | Amit Srivastava and Awashesh Kumar | 2015 | Poster | | y2015 | poster |
| Panning for Gold in RTL Using Transactions | Rich Edelman, Raghu Ardeishar, Akshay Sarup, and Suman Kasam | 2011 | Paper | | y2011 | paper |
| Parallel Computing for Functional Verification and Compute Farms: The Holy Matrimony | Amit Sharma, Shekhar Basavanna, and Srinivasan Venkataramanan | 2011 | Paper | | y2011 | paper |
| Parameter Passing From SystemVerilog to SystemC | Bishnupriya Bhattacharya, Samik Das, Zhiting Duan, Chandra Sekhar Katuri, and Pradipta Laha | 2015 | Presentation | | y2015 | presentation |
| Parameter Passing from SystemVerilog to SystemC for Highly Configurable Mixed-Language Designs | Bishnupriya Bhattacharya, Samik Das, Zhiting Duan, Chandra Sekhar Katuri, and Pradipta Laha | 2015 | Paper | | y2015 | paper |
| Parameterize Like a Pro: Handling Parameterized RTL in your UVM Testbench | Jeff Montesano | 2020 | Presentation | | y2020 | presentation |
| Parameterized and Re-usable Jitter Model for Serial and Parallel Interfaces | Amlan Chakrabarti and Malathi Chikkanna | 2015 | Paper | | y2015 | paper |
| Parameterized and Re-usable Jitter Model for Serial and Parallel Interfaces | Malathi Chikkanna and Amlan Chakrabarti | 2015 | Presentation | | y2015 | presentation |
| Parameters and OVM — Can’t They Just Get Along? | Bryan Ramirez and Michael Horn | 2011 | Paper | | y2011 | paper |
| Parameters, UVM, Coverage & Emulation – Take Two and Call Me in the Morning | Michael Horn, Bryan Ramirez, and Hans van der Schoot | 2016 | Paper | | y2016 | paper |
| Path-based UPF Strategies: Optimally Manage Power on your Designs | Progyna Khondkar | 2022 | Presentation | | y2022 | presentation |
| Path-Based UPF Strategies: Optimally Manage Power on Your Designs | Progyna Khondkar | 2022 | Paper | | y2022 | paper |
| Pay Me Now or Pay Me Later Exploring the Implementation and Analysis Cost Trade-Offs of Coverage Model Design | Paul Graykowski and Andrew Piziali | 2011 | Paper | | y2011 | paper |
| Plan & Metric Driven Mixed-Signal Verification for Medical Devices | Gregg Sarkinen | 2011 | Paper | | y2011 | paper |
| Plugging the Holes: SystemC and VHDL Functional Coverage Methodology | Pankaj Singh and Gaurav Kumar Verma | 2011 | Paper | | y2011 | paper |
| Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication bridge | Andrei Vintila and Ionut Tolea | 2019 | Presentation | | y2019 | presentation |
| Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication bridge | Andrei Vintila and Ionut Tolea | 2019 | Paper | | y2019 | paper |
| Portable Stimulus Models for C/SystemC, UVM and Emulation | Mike Andrews and Boris Hristov | 2015 | Paper | | y2015 | paper |
| Portable Stimulus Models for C/SystemC, UVM and Emulation | Mike Andrews and Boris Hristov | 2015 | Presentation | | y2015 | presentation |
| Portable Stimulus Standard Update: PSS in the Real World | Accellera Portable Stimulus Working Group | 2022 | Presentation | | y2022 | presentation |
| Portable Stimulus Standard: The Promises and Pitfalls of Early Adoption | Mike Bartley | 2019 | Presentation | | y2019 | presentation |
| Portable Stimulus Standard’s Hardware Software Interface (HSI) to validate 4G 5G Forward Error Correction Encoder/Decoder IP in Emulation Silicon | Joydeep Maitra, Suresh Vasu, Nithin Venkatesh, Suhas Reddy, Luis Campos, Vinit Shenoy | 2022 | Presentation | | y2022 | presentation |
| Portable Stimulus vs Formal vs UVM: A Comparative Analysis of Verification Methodologies Throughout the Life of an IP Block | Gaurav Bhatnagar and David Brownell | 2018 | Paper | | y2018 | paper |
| Portable Stimulus vs Formal vs UVM: A Comparative Analysis of Verification Methodologies Throughout the Life of an IP Block | Gaurav Bhatnagar | 2018 | Presentation | | y2018 | presentation |
| Portable Stimulus: What’s Coming in 1.1 and What it Means For You | Portable Stimulus Working Group | 2020 | Presentation | | y2020 | presentation |
| Portable Test and Stimulus: The Next Level of Verification Productivity is Here | Accellera Portable Stimulus Working Group | 2018 | Presentation | | y2018 | presentation |
| Post Silicon Performance Validation Using PSS | Dayoung Kim, Jaehun Lee, Daeseo Cha, Phu L. Huynh, and Jake Kim | 2020 | Presentation | | y2020 | presentation |
| Post-Silicon Performance Validation Using PSS | Dayoung Kim, Jaehun Lee, and Daeseo Cha | 2020 | Paper | | y2020 | paper |
| Power Aware CDC Analysis at Top Level Using SOC Abstract Flow | Venkatesh Ranga and Pramod Rajan K S | 2017 | Paper | | y2017 | paper |
| Power Aware CDC Analysis at Top Level Using SOC Abstract Flow | Venkatesh Ranga and Pramod Rajan K S | 2017 | Poster | | y2017 | poster |
| Power Aware Verification Strategy for SoCs | Boobalan Anantharaman and Arunkumar Narayanamurthy | 2013 | Presentation | | y2013 | presentation |
| Power Aware Verification Strategy for SoCs | Boobalan Anantharaman and Arunkumar Narayanamurthy | 2013 | Paper | | y2013 | paper |
| Power estimation – what to expect what not to expect | Prakash Parikh | 2014 | Presentation | | y2014 | presentation |
| Power Estimation Techniques – what to expect, what not to expect | Prakash Parikh | 2014 | Paper | | y2014 | paper |
| Power Management Verification for SoC ICs | David Akselrod, Alex Miretsky, Sergey Golubkov, Pearl Liu, Afshin Parvaresh, Shu Wang, and Feng Yan | 2016 | Poster | | y2016 | poster |
| Power Management Verification for SOC ICs | David Akselrod, Alex Miretsky, Sergey Golubkov, Pearl Liu, Afshin Parvaresh, Shu Wang, and Feng Yan | 2016 | Paper | | y2016 | paper |
| Power State to PST Conversion: Simplifying static analysis and debugging of power aware designs | Madhur Bhargava and Pankaj Gairola | 2016 | Poster | | y2016 | poster |
| Power State to PST Conversion: Simplifying static analysis and debugging of power aware designs | Madhur Bhargava and Pankaj Gairola | 2016 | Paper | | y2016 | paper |
| Practical Applications of the Portable Testing and Stimulus Standard (PSS) | Sharon Rosenberg | 2019 | Presentation | | y2019 | presentation |
| Practical Approach Using a Formal App to Detect X-Optimism-Related RTL Bugs | Shuqing Zhao, Shan Yan, and Yafang Feng | 2014 | Paper | | y2014 | paper |
| Practical Approach Using a Formal App to Detect X-Optimism-Related RTL Bugs | Shuqing Zhao, Shan Yan, and Yafang Feng | 2014 | Presentation | | y2014 | presentation |
| Practical Considerations for Real Valued Modeling of High Performance Analog Systems | Dushyant Juneja, Siddharth Prabhu, and Syam Veluri | 2016 | Presentation | | y2016 | presentation |
| Practical Considerations for Real Valued Modeling of High Performance Analog Systems | Dushyant Juneja, Siddharth Prabhu, and Syam Veluri | 2016 | Poster | | y2016 | poster |
| Practical Considerations for Real Valued Modeling of High Performance Analog Systems | Dushyant Juneja, Siddharth Prabhu, and Syam Veluri | 2016 | Paper | | y2016 | paper |
| Practical Considerations for Real Valued Modeling of High Performance Analog Systems | Dushyant Juneja, Siddharth Prabhu, and Syam Veluri | 2016 | Paper | | y2016 | paper |
| Practical Issues in Implementing Fast and Accurate SystemC-Constructed Virtual Platform Simulation | Yu-Fu Yeh and Chung-Yang (Ric) Huang | 2013 | Paper | | y2013 | paper |
| Practical Issues in Implementing Fast and Accurate SystemC-Constructed Virtual Platform Simulation | Yu-Fu Yeh and Chung-Yang (Ric) Huang | 2013 | Presentation | | y2013 | presentation |
| Practical Scheme to Enhance Verification Turn-Around-Time by Using Reusable Harness Interface (RHI) | Jongpil Jung, Hyunju Lee, Jaejin Ha, and Yonghee Im | 2018 | Paper | | y2018 | paper |
| Practical Scheme to Enhance Verification Turn-Around-Time by Using Reusable Harness Interface (RHI) | Jong pil Jung, Hyunju Lee, Jaejin Ha, and Yonghee Im | 2018 | Presentation | | y2018 | presentation |
| Practical Schemes to Enhance Vertical, Horizontal and Platform Reusability of Verification Components in AMBA Based SoC Design | Ieryung Park, Nara Cho and Yonghee Im | 2017 | Presentation | | y2017 | presentation |
| PRACTICAL SCHEMES TO ENHANCE VERTICAL, HORIZONTAL AND PLATFORM REUSABILITY OF VERIFICATION COMPONENTS IN AMBA BASED SOC DESIGN | Ieryung Park, Nara Cho, and Yonghee Im | 2017 | Paper | | y2017 | paper |
| Pragmatic Verification Reuse in a Vertical World | Mark Litterick | 2013 | Poster | | y2013 | poster |
| Pragmatic Verification Reuse in a Vertical World | Mark Litterick | 2013 | Paper | | y2013 | paper |
| Pre-Silicon Power Management Verification of Complex SOCs: Experiences with Intel Moorefield | Rajeev Muralidhar, Nivedha Krishnakumar, Bryan Morgan, Robert Karas, Billy Dennie, and Neil Rosenberg | 2016 | Paper | | y2016 | paper |
| Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads using Hybrid System Level Emulation SoC Platform | Neeraj Gupta, Reddaiah Yedoti, Dixit Sethi, and Sarvesh Kumar Pandey | 2022 | Poster | | y2022 | poster |
| Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads Using Hybrid System Level Emulation SoC Platform | Neeraj Gupta, Reddaiah Yedoti, Dixit Sethi, and Sarvesh Kumar Pandey | 2022 | Paper | | y2022 | paper |
| Predicting Bad Commits | Christian Graber, Daniel Hansson, and Adam Tornhill | 2019 | Poster | | y2019 | poster |
| Preventing Chip-Killing Glitches on CDC Paths with Automated Formal Analysis | Jackie Hsiung, Ashish Hari, and Sulabh Kumar Khare | 2018 | Paper | | y2018 | paper |
| Preventing Chip-Killing Glitches on CDC Paths with Automated Formal Analysis | Jackie Hsiung, Sulabh Kumar Khare, and Ashish Hari | 2018 | Poster | | y2018 | poster |
| Preventing Glitch Nightmares on CDC Paths: The Three Witches | Jian-Hua Yan, Ping Yeung, Stewart Li, Sulabh-Kumar Khare | 2021 | Paper | | y2021 | paper |
| Primary, Anonymous, or What? The Destiny of Ports from Design Top that Ultimately are Driven from Off-Chip… | Brandon Skaggs, Progyna Khondkar | 2021 | Paper | | y2021 | paper |
| Problematic Bi-Directional Port Connections: How Well is Your Simulator Filling the UPF LRM Void? | Brandon Skaggs | 2022 | Presentation | | y2022 | presentation |
| Problematic Bi-Directional Port Connections: How Well Is Your Simulator Filling the UPF LRM Void? | Brandon Skaggs | 2022 | Paper | | y2022 | paper |
| Product Life Cycle of an Interconnect Bus: A Portable Stimulus Methodology for Performance Modeling, Design Verification, and Post-Silicon Validation | Gaurav Bhatnagar and Courtney Fricano | 2019 | Paper | | y2019 | paper |
| Product Life Cycle of Interconnect Bus:A Portable Stimulus Methodology for Performance Modeling, Design Verification, and Post-Silicon Validation | Gaurav Bhatnagar and Courtney Fricano | 2019 | Presentation | | y2019 | presentation |
| Programming Model Inheritance and Sequence Reuse | Aji Varghese | 2016 | Paper | | y2016 | paper |
| Proper probing: Flexibility on the TLM level | Gergő V kony | 2018 | Paper | | y2018 | paper |
| Proper Probing: Flexibility on the TLM Level | Gergö Vékony | 2018 | Poster | | y2018 | poster |
| Property-Driven Development of a RISC-V CPU | Tobias Ludwig, Michael Schwarz, Joakim Urdahl, Lucas Deutschmann, Salaheddin Hetalani, Dominik Stoffel, and Wolfgang Kunz | 2019 | Paper | | y2019 | paper |
| Property-Driven Development of a RISC-V CPU | Tobias Ludwig | 2019 | Presentation | | y2019 | presentation |
| Proven Strategies for Better Verification Planning: DVCon 2022 Workshop | Paul Marriott, Jeff Vance, and Jeff McNeal | 2022 | Presentation | | y2022 | presentation |
| PSL/SVA Assertions in SPICE | Donald O’Riordan and Prabal Bhattacharya | 2012 | Paper | | y2012 | paper |
| PSS Action Sequence Modeling Using Machine Learning | Moonki Jang | 2022 | Presentation | | y2022 | presentation |
| PSS Action Sequence Modeling Using Machine Learning | Moonki Jang, Myeongwhan Hyun, Hyunkyu Ahn, Jiwoong Kim, Yunwhan Kim, and Dongjoo Kim | 2022 | Paper | | y2022 | paper |
| PSS: The Promises and Pitfalls of Early Adoption | Mike Bartley | 2019 | Paper | | y2019 | paper |
| Qualification of Formal Properties for Productive Automotive Microcontroller Verification | Holger Busch | 2013 | Paper | | y2013 | paper |
| Quantification of Formal Properties for Productive Automotive Microcontroller Verification | Holger Busch | 2013 | Presentation | | y2013 | presentation |
| Raising the level of Formal Signoff with End to End Checking Methodology | Ping Yeung, Arun Khurana, Dhruv Gupta, Ashutosh Prasad, Achin Mittal | 2022 | Presentation | | y2022 | presentation |
| Raising the Level of Formal Signoff with End-to-End Checking Methodology | Ping Yeung, Arun Khurana, Dhruv Gupta, Ashutosh Prasad, and Achin Mittal | 2022 | Paper | | y2022 | paper |
| Random Directed Low Power Coverage Methodology: A Smart Approach to Power Aware Verification Closure | Awashesh Kumar and Madhur Bhargava | 2017 | Paper | | y2017 | paper |
| Random Directed Low Power Coverage Methodology:(A Smart Approach to Power Aware Verification Closure) | Awashesh Kumar and Madhur Bhargava | 2017 | Presentation | | y2017 | presentation |
| Randomizing UVM Config DB Parameters | Jeremy Ridgeway | 2015 | Paper | | y2015 | paper |
| Randomizing UVM Config DB Parameters | Jeremy Ridgeway | 2015 | Poster | | y2015 | poster |
| Real Number Modeling | Tom Cole, Wes Queen, Mark Kautzman, and Dan Romaine | 2013 | Paper | | y2013 | paper |
| Real Number Modeling Enables Fast, Accurate Functional Verification | Wes Queen, Tom Cole, and Dan Romaine | 2013 | Poster | | y2013 | poster |
| Real Number Modeling for RF Circuits | Jakub Dudek, Joshua Nekl and Keith O’Donoghue | 2017 | Presentation | | y2017 | presentation |
| Real Number Modeling of RF Circuits | Jakub Dudek, Joshua Nekl, and Keith O’Donoghue | 2017 | Paper | | y2017 | paper |
| Recipe for bug hunting: Tips & Tricks for Low power silicon sign-off | Monika Rawat, Dipankar Narendra Arya, Anuroop R, Deepmala Sachan | 2021 | Paper | | y2021 | paper |
| RegAnalyzer – A tool for programming analysis and debug for verification and validation | Suresh Vasu | 2020 | Poster | | y2020 | poster |
| RegAnalyzer -A tool for programming analysis and debug for verification and validation | Suresh Vasu | 2020 | Paper | | y2020 | paper |
| Register This! Experiences Applying UVM Registers | Sharon Rosenberg | 2012 | Paper | | y2012 | paper |
| Register This! Experiences Applying UVM Registers | Kathleen Meade | 2012 | Presentation | | y2012 | presentation |
| Register Verification: Do We Have Reliable Specification? | NamDo Kim, Junhyuk Park, Byeong Min, and Wesley Park | 2013 | Poster | | y2013 | poster |
| Register Verification: Do We Have Reliable Specification? | NamDo Kim, Junhyuk Park, Byeong Min, and Wesley Park | 2013 | Paper | | y2013 | paper |
| Registering the standard: Migrating to the UVM_REG code base | Sachin Patel, Amit Sharma, and Adiel Khan | 2012 | Paper | | y2012 | paper |
| Regressions in the 21st Century – Tools for Global Surveillance | David Crutchfield, Tushar Grupta, Frank Roberts, and Venkataramanan Srinivasan | 2016 | Presentation | | y2016 | presentation |
| Regressions in the 21st Century – Tools for Global Surveillance | David Crutchfield, Tushar Grupta, Frank Roberts, and Venkataramanan Srinivasan | 2016 | Paper | | y2016 | paper |
| Relieving the Parameterized Coverage Headache | Christine Lovett, Bryan Ramirez, Stacey Secatch, and Michael Horn | 2012 | Paper | | y2012 | paper |
| Relieving the Parameterized Coverage Headache | Christine Lovett | 2012 | Presentation | | y2012 | presentation |
| Reset and Initialization, the Good, the Bad and the Ugly | Ping Yeung and Kaowen Liu | 2016 | Paper | | y2016 | paper |
| Reset and Initialization, the Good, the Bad and the Ugly | Ping Yeung and Kaowen Liu | 2016 | Poster | | y2016 | poster |
| Reset and Initialization: the Good, the Bad and the Ugly | Ping Yeung and Kaowen Liu | 2016 | Presentation | | y2016 | presentation |
| Reset Domain Crossing for designs with set-reset flops | Abdul Moyeen, Inayat Ali | 2021 | Paper | | y2021 | paper |
| Resetting Anytime with the Cadence UVM Reset Package | Courtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm | 2014 | Poster | | y2014 | poster |
| Resetting Anytime with the Cadence UVM Reset Package | Courtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm | 2014 | Paper | | y2014 | paper |
| Results Checking Strategies with Portable Stimulus | Tom Fitzpatrick and Matthew Balance | 2019 | Presentation | | y2019 | presentation |
| Results Checking Strategies with Portable Stimulus | Tom Fitzpatrick and Matthew Ballance | 2019 | Paper | | y2019 | paper |
| Reusable System-Level Power-Aware IP Modeling Approach | Antonio Genov, Francois Verdier, and Loic Leconte | 2022 | Paper | | y2022 | paper |
| REUSABLE UPF: Transitioning from RTL to Gate Level Verification | Durgesh Prasad, Jitesh Bansal, and Madhur Bhargava | 2018 | Poster | | y2018 | poster |
| REUSABLE UPF: Transitioning from RTL to Gate Level Verification | Durgesh Prasad, Jitesh Bansal, and Madhur Bhargava | 2018 | Paper | | y2018 | paper |
| Reuse C test and UVM sequence utilizing TLM2, register model and interrupt handler | HongLiang Liu and Teng-Fei Gao | 2015 | Presentation | | y2015 | presentation |
| Reuse C test and UVM sequence utilizing TLM2, register model and interrupt handler | Liu HongLiang and Gao Teng-Fei | 2015 | Paper | | y2015 | paper |
| Reusing Testbench Components in a Hybrid Simulation-Formal Environment | Ritero Chi and Xiaolin Chen | 2010 | Paper | |
