DVCon: United States

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TitleAuthor(s)YearTypeLinkhf:tax:event_yearhf:tax:document_type
“Bounded Proof” sign-off with formal coverageAbhishek Anand, Chinyu Chen, Bathri Narayanan Subramanian, Joe Hupcey2021Papery2021paper
“C” you on the faster side: Accelerating SV DPI based co-simulationParag Goel, Amit Sharma, and Hari Vinodh Balisetty2014Papery2014paper
“C” you on the faster side: Accelerating SV DPI based co-simulationHari Vinod Balisetty, Parag Goel, and Amit Sharma2014Presentationy2014presentation
“In-Emulator” UVM++ Randomized Testbenches for High Performance Functional VerificationAdnan Hamid and David Kelf2022Presentationy2022presentation
“Shift left” Hierarchical Low-Power Static Verification Using SAMBharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal2020Postery2020poster
“Shift left” Hierarchical Low-Power Static Verification Using SAMBharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal2020Papery2020paper
A 30 Minute Project Makeover Using Continuous IntegrationJL Gray2012Papery2012paper
A 30 Minute Project Makeover Using Continuous IntegrationJL Gray and Gordon McGregor2012Presentationy2012presentation
A 360 Degree View of UVM Events – A Case StudyDeepak Kumar E V, Sathish Dadi, and Vikas Billa2016Papery2016paper
A 360 Degree View of UVM Events (A Case Study)Deepak Kumar E V, Sathish Dadi, and Vikas Billa2016Presentationy2016presentation
A Client-Server Method for Register Design and DocumentationScott D Orangio and Julien Gagnon2016Papery2016paper
A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISC V CoreJunaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, Aashir Ahsan2022Presentationy2022presentation
A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISCV CoreJunaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, and Aashir Ahsan2022Papery2022paper
A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance AnalysisBishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel2016Postery2016poster
A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance Analysis.Bishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel2016Papery2016paper
A Comprehensive High Speed Link Verification Test Bench Harnessing Scripting to Achieve Faster Functional Coverage Closure.Piyush Tankwal, Arnab Ghosh, Piyush Agnihotri, Mukesh Gandhi, Parag S Lonkar2024Papery2024paper
A Configurable, Re-usable UVM Environment Coupled with Advanced Spice Simulator for Analog and Mixed-Signal Verification of a Display PMIC2024Papery2024paper
A Coverage-Driven Formal Methodology for Verification Sign-offAng Li, Hao Chen, Jason K Yu, Ee Loon Teoh, and Iswerya Prem Anand2019Papery2019paper
A Coverage-Driven Formal Methodology for Verification Sign-offAng Li, Hao Chen, Jason K Yu, Ee Loon Teoh and, Iswerya Prem Anand2019Presentationy2019presentation
A Dyadic Transformation Based Methodology To Achieve Coverage Driven Verification GoalSwapnajit Mitra2017Presentationy2017presentation
A Dyadic Transformation Based Methodology to Achieve Coverage Driven Verification GoalSwapnajit Mitra2017Papery2017paper
A Dynamic Approach Towards Register Coverage Generation and Collection to Reduce Compilation Overhead of Traditional UVM Register LayersSubham Banerjee2020Presentationy2020presentation
A Formal Verification App Towards Efficient Chip-Wide Clock Gating VerificationProsenjit Chatterjee, Scott Fields, and Syed Suhaib2014Presentationy2014presentation
A Formal Verification App Towards Efficient, Chip-Wide Clock Gating VerificationProsenjit Chatterjee, Scott Fields, and Syed Suhaib2014Papery2014paper
A Guide To Using Continuous Integration Within The Verification EnvironmentJason Sprott2014Presentationy2014presentation
A Hardware and Software integrated power optimization approach with power aware simulations at SOCEldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2023Papery2023paper
A Hardware and Software Integrated Power Optimization Approach with Power Aware Simulations at SOCEldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2023Postery2023poster
A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power IntentVijay Kumar Sankaran, Lakshmanan Balasubramanian, Bharath Kumar Poluri, Venkatraman Ramakrishnan, Badrinarayan Zanwar, and Qingyu Lin2016Papery2016paper
A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power IntentQingyu Lin2016Postery2016poster
A Holistic View of Mixed-Language IP IntegrationPankaj Singh and Gaurav Kumar Verma2010Papery2010paper
A Hybrid Verification Solution to RISC V Vector ExtensionChenghuan Li, Yanhua Feng, Liam Li2022Presentationy2022presentation
A Hybrid Verification Solution to RISC-V Vector ExtensionChenghuan Li, Yanhua Feng, and Liam Li2022Papery2022paper
A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance CorrelationThomas Soong, Christopher Browne, and Chenhui Huang2022Postery2022poster
A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance CorrelationThomas Soong, Chenhui Huang, and Christopher Browne2022Papery2022paper
A Methodology for Power and Energy Efficient Systems DesignMohammed Fahad2023Presentationy2023presentation
A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation AccelerationHorace Chan, Brian Vandegriend, and Efrat Shneydor2015Papery2015paper
A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation AccelerationHorace Chan, Brian Vandegriend, and Efrat Shneydor2015Presentationy2015presentation
A New Approach for Generating View GeneratorsJohannes Schreiner, Felix Willgerodt, and Wolfgang Ecker2017Papery2017paper
A New Approach for Generating View GeneratorsJohannes Schreiner, Felix Willgerodt, and Wolfgang Ecker2017Postery2017poster
A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain CrossingsOmri Dassa, Yossi Mirsky2022Presentationy2022presentation
A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain CrossingsOmri Dassa and Yossi (Joseph) Mirsky2022Papery2022paper
A New Class Of RegistersM. Peryer and D. Aerne2016Papery2016paper
A New Class Of RegistersMark Peryer and David Aerne2016Postery2016poster
A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM DomainsSubham Banerjee and Keshava Krishna Raja2017Papery2017paper
A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM Domains 2017Postery2017poster
A Novel Approach to Verify CNN Based Image Processing UnitSumit K. Kulshreshtha, Raghavendra J N2021Papery2021paper
A Novel Variation-Aware Mixed-Signal Verification Methodology to achieve High-Sigma Variation coverage at nanometer designsTibi Galambos, Sumit Vishwakarma2021Papery2021paper
A Practical Approach to Measuring and Improving the Functional Verification of Embedded SoftwareStéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès2012Papery2012paper
A Practical Approach to Measuring and Improving the Functional Verification of Embedded SoftwareStéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès2012Presentationy2012presentation
A Practical Look @ SystemVerilog Coverage – Tips, Tricks, and GotchasDoug Smith and John Aynsley2011Papery2011paper
A Reusable, Scalable Formal App for Verifying Any Configuration of 3D IC ConnectivityDaniel Han, Walter Sze, Benjamin Ting, and Darrow Chu2013Papery2013paper
A Semi-Formal Verification Methodology for Efficient Configuration Coverage of Highly Configurable Digital DesignsAman Kumar, Sebastian Simon2021Papery2021paper
A Simplified Approach Using UVM Sequence Items for Layering Protocol VerificationHaiqian Yu and Christine Thomson2017Papery2017paper
A Simplified Approach Using UVM Sequence Items for Layering Protocol VerificationChristine Thomson and Haiqian Yu2017Presentationy2017presentation
A Simulation Expert’s Guide to Formally Proving SW Status and InterruptsNeil Johnson2023Presentationy2023presentation
A Simulation Expert’s Guide to Formally Verifying Software Status and InterruptsNeil Johnson2023Papery2023paper
A single generated UVM Register Model to handle multiple DUT configurationsSalvatore Marco Rosselli and Giuseppe Falconeri2020Presentationy2020presentation
A SMART GENERATION OF DESIGN ATTRIBUTES FOR VERIFICATION CLOSURE USING SPECMANMeirav Nitzan, Yael Kinderman, and Efrat Gavish2013Postery2013poster
A Smart Synchronizer – Pragmatic way to cross asynchronous clock domainsPriyank Parakh and Steven J Kommrusch2011Papery2011paper
A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing LogicPriya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed2018Papery2018paper
A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing LogicPriya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed2018Postery2018poster
A Statistical and Model-Driven Approach for Comprehensive Fault Propagation Analysis of RISC-V VariantsEndri Kaja, Nicolas Gerlin, Ungsang Yun, Jad Al Halabi, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker2024Postery2024poster
A Statistical and Model-Driven Approach for Comprehensive Fault Propagation Analysis of RISC-V VariantsEndri Kaja, Nicolas Gerlin, Ungsang Yun, Jad Al Halabi, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker2024Papery2024paper
A Study on Virtual Prototyping based Design Verification MethodologyWoojoo Kim, Kunhyuk Kang, and Seonil Brian Choi.2023Papery2023paper
A Study on Virtual Prototyping based Design Verification MethodologyWoojoo Kim, Kunhyuk Kang, Seonil Brian Choi2023Postery2023poster
A Survey of Machine Learning Applications in Functional VerificationDan Yu, Harry Foster, Tom Fitzpatrick2023Papery2023paper
A Systematic Approach to Power State Table (PST) DebuggingBhaskar Pal2013Presentationy2013presentation
A Systematic Approach to Power State Table (PST) DebuggingBhaskar Pal, Suman Nandan, Kaushik De, and Rajarshi Mukherjee2013Papery2013paper
A Systematic Formal Reuse Methodology: From Blocks to SoC SystemsHao Chen, Yi Sun, Ang Li, and Dorry Cao2020Presentationy2020presentation
A Systematic Take on Addressing Dynamic CDC Verification ChallengesSukriti Bisht, Sulabh Kumar Khare, and Ashish Hari2019Presentationy2019presentation
A Systematic Take on Addressing Dynamic CDC Verification ChallengesSukriti Bisht, Sulabh Kumar Khare, and Ashish Hari2019Papery2019paper
A SystemC Library for Advanced TLM VerificationMarcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen2012Papery2012paper
A SystemC Library for Advanced Verification – Towards an Enhanced OVM/UVM for SystemCMarcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen2012Presentationy2012presentation
A SystemVerilog Framework for Easy Method Advice in Object-oriented Test BenchesEric Ohana2013Postery2013poster
A SystemVerilog Framework for Easy Method Advice in Object-oriented Test BenchesEric Ohana2013Papery2013paper
A SystemVerilog Framework for Efficient Randomization of Images with Complex Inter-Pixel DependenciesAxel Voss, Gabriel Jönsson, and Lars Viklund2020Presentationy2020presentation
A Tale of Two Languages – SystemVerilog and SystemCDavid C Black2013Papery2013paper
A Tale of Two Languages: SystemVerilog & SystemCDavid C Black2013Presentationy2013presentation
A Unified Testbench Architecture Solution for Verifying Variants of A PLL IPDeepa Ananthanarayanan and Malathi Chikkanna2015Presentationy2015presentation
A Unified Testbench Architecture Solution for Verifying Variants of the PLL IPDeepa Ananthanarayanan and Malathi Chikkanna2015Papery2015paper
A Universal DFT Verification Environment: Filling the Gap between Function Simulation and ATE TestRui Huang2016Papery2016paper
A Universal DFT Verification Environment: Filling the Gap between Function Simulation and ATE TestRui Huang2016Presentationy2016presentation
A UVM Multi-Agent Verification IP architecture to enable Next-Gen protocols with enhanced reusability, controllability and observabilityPrathik R, Ramesh Madatha, Girish Gupta, Tony George2024Presentationy2024presentation
A UVM Multi-Agent Verification IP architecture to enable Next-Gen protocols with enhanced reusability, controllability and observabilityPrathik R, Ramesh Madatha, Girish Kumar Gupta, Tony Gladvin George2024Papery2024paper
A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline ReceiversJaeha Kim2023Postery2023poster
A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline ReceiversJaeha Kim2023Presentationy2023presentation
A UVM SystemVerilog Testbench for Analog/Mixed-Signal Verification: A Digitally-Programmable Analog Filter ExampleCharles Dančak2022Papery2022paper
A UVM SystemVerilog Testbench for Directed & Random Testing of an AMS LDO Voltage RegulatorCharles Dančak2024Postery2024poster
A UVM SystemVerilog Testbench for Directed & Random Testing of an AMS LDO Voltage RegulatorCharles Dančak2024Presentationy2024presentation
A UVM SystemVerilog Testbench for Directed and Random Testing of an AMS Low-Dropout Voltage RegulatorCharles Dančak2024Papery2024paper
A UVM Testbench for Analog Verification: A Programmable Filter ExampleCharles Dančak2022Presentationy2022presentation
A UVM-based Approach for Rapidly Verifying Digital Interrupt StructuresChristoph Rumpler, Alexander W. Rath, and Sebastian Simon2016Presentationy2016presentation
A UVM-based Approach for Rapidly Verifying Digital Interrupt StructuresChristoph Rumpler, Alexander W. Rath, Sebastian Simon, and Heinz Endres2016Papery2016paper
A Volterra-Series Model in SystemVerilog/XMODEL for Nonlinear RF Low-Noise AmplifiersChan Young Park, Jaeha Kim2021Papery2021paper
A Wholistic Approach to Optimizing Your System Verification FlowRoss Dickson, Lance Tamura, Michael Young2023Presentationy2023presentation
Abstract Layer for Firmware Access: A Unique Approach for SOC Functional VerificationGupta Girish Kumar, Rugmini Navia Vishnu, Choudhary Praval, Syed Mobeenuddin2021Papery2021paper
Accelerate Coverage Closure from Day-1 with AI-driven VerificationMalay Ganai, Will Chen, Srikanth Vadanaparthi2023Presentationy2023presentation
Accelerated simulation through design partition and HDL to C++ compilationTheta Yang and Sga Sun2017Papery2017paper
Accelerated simulation through design partition and HDL to C++ compilationTheta Yang2017Presentationy2017presentation
Accelerated Verification of NAND Flash Memory using HW EmulatorSeyeol Yang, Byungwoo Kang, Seoyeon Bae, Choi Jaehyeon, Jintae Kim, Dongeun Lee, Junho Ahn2023Papery2023paper
Accelerated Verification of NAND Flash Memory using HW EmulatorSeyeol Yang, Byungwoo Kang, Seoyeon Bae, Choi Jaehyeon, Jintae Kim, Dongeun Lee, Junho Ahn2023Postery2023poster
Accelerated, High Quality SoC Memory Map Verification using Formal TechniquesCletan Sequeira, Rajesh Kedia, Lokesh Babu Pundreeka, and Bijitendra Mittra2014Papery2014paper
Accelerated, High Quality SoC Memory Map Verification using Formal TechniquesCletan Sequeira, Rajesh Kedia, Lokesh Babu Pundreeka, and Bijitendra Mittra2014Presentationy2014presentation
Accelerating CDC Verification Closure on Gate-Level DesignsAnwesha Choudhury and Ashish Hari2017Presentationy2017presentation
Accelerating CDC Verification Closure on Gate-Level DesignsAnwesha Choudhury and Ashish Hari2017Papery2017paper
Accelerating Error Handling Verification Of Complex Systems: A Formal ApproachBhushan Parikh, Peter Graniello, Neha Rajendra2022Presentationy2022presentation
Accelerating Error Handling Verification of Complex Systems: A Formal ApproachBhushan Parikh, Peter Graniello, and Neha Rajendra2022Papery2022paper
Accelerating Functional Verification Through Stabilization of Testbench Using AI/MLSrikanth Vadanaparthi, Pooja Ganesh, Dharmesh Mahay, Malay Ganai2023Papery2023paper
Accelerating Functional Verification Through Stabilization of Testbench Using AI/MLSrikanth Vadanaparthi, Pooja Ganesh, Dharmesh Mahay, Malay Ganai2023Postery2023poster
Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing ProductsYoga Priya Vadivelu, Arpan Shah, Deepinder Singh Mohoora, Ullas, and Praveen Buddireddy2022Postery2022poster
Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing ProductsYoga Priya Vadivelu, Arpan Shah, Deepinder Singh Mohoora, Ullas, and Praveen Buddireddy2022Papery2022paper
Accelerating SoC Verification Signoff using Save & Restart/Dynamic Test Reload Enhanced Regression flowVanshlata B, Divya M, Garima S, Seonil Brian Choi2021Papery2021paper
Accelerating SOC Verification Using Process Automation and IntegrationSeonghee Yim, Hanna Jang, Sunchang Choi, and Seonil Brian Choi2020Papery2020paper
Accelerating the IP Design Cycle with Formal Techniques Beyond Everyday FPVBhushan Parikh, Shaman Narayana, Buck Lem, David Cassetti2021Papery2021paper
Acceleration of Coreless SoC Design-Verification using PSS on Configurable Testbench in Multi-Link PCIe SubsystemsThanu Ganapathy, Pravin Kumar, Garima Srivastava, Seonil Brian Choi, Harish Peta2021Papery2021paper
Accellera Functional Safety Working Group Update and Next StepsAlessandra Nardi2024Presentationy2024presentation
Accellera UVM-AMS Standard UpdateTom Fitzpatrick and Tim Pylant2022Presentationy2022presentation
Ace’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power ConsumptionMehul Kumar, Tushar Mattu, and Amir Nilipour2016Papery2016paper
ACE’ing the Verification of a Coherent System Using UVMRomondy Luo, Ray Varghese, Parag Goel, Amit Sharma, Satyapriya Acharya, and Peer Mohammed2012Papery2012paper
ACE’ing the Verification of a Coherent System Using UVMParag Goel; Amit Sharma, Ray Varghese, Romondy Luo, Satyapriya Acharya, Peer Mohammed2012Presentationy2012presentation
ACE’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power ConsumptionMehul Kumar, Shawn Honess, Amir Nilipour, and Tushar Mattu2016Postery2016poster
Achieving End-to-End Formal Verification of Large Floating-Point Dot Product Accumulate Systolic UnitsEmiliano Morini, Bill Zorn, Disha Puri, Madhurima Eranki, Shravya Jampana2024Papery2024paper
Achieving End-to-End Formal Verification of Large Floating-Point Dot Product Accumulate Systolic DesignsEmiliano Morini, Bill Zorn, Disha Puri, Madhurima Eranki, Shravya Jampana 2024Postery2024poster
Achieving First-Time Success with a UPF-based Low Power Verification FlowKjeld Svendsen, Chuck Seeley, and Erich Marschner2011Papery2011paper
Activity Trend Guided Efficient Approach to Peak Power Estimation Using EmulationGaurav Saharawat, Saurabh Jain, and Madhur Bhatia2016Presentationy2016presentation
Activity Trend Guided Efficient Approach to Peak Power Estimation Using EmulationGaurav Saharawat, Saurabh Jain, and Madhur Bhatia2016Papery2016paper
Adapting the UVM Register Abstraction Layer for Burst AccessMark Villalpando2016Presentationy2016presentation
Adapting the UVM Register Layer for Burst AccessM. P. Villalpando2016Papery2016paper
Adaptive Test Generation for Fast Functional Coverage ClosureAzade Nazi, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhoseini, Richard Ho2022Presentationy2022presentation
Adaptive Test Generation for Fast Functional Coverage ClosureAzade Naziz, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhosseiniz, and Richard Ho2022Papery2022paper
Addressing Challenges in Verification of DSP based Audio IPs using a Novel Hybrid-TestBench ArchitectureSuvadeep Bose, Kanak Singh Rajput, Parag S Lonkar, Somasunder K Sreenath2021Papery2021paper
Addressing HW/SW Interface Quality through StandardsDavid Murray and Sean Boyan2012Papery2012paper
Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail MacrosBrandon S. Skaggs2020Papery2020paper
Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail MacrosBrandon Skaggs2020Postery2020poster
Addressing the Challenges of Reset Verification in SoC DesignsChris Kwok, Priya Viswanathan, and Ping Yeung2015Presentationy2015presentation
Addressing the Challenges of Reset Verification in SoC DesignsChris Kwok, Priya Viswanathan, and Ping Yeung2015Papery2015paper
Addressing the verification challenge of SERDES-based FPGAs: The performance/accuracy/efficiency trade-offChris Schalick2011Papery2011paper
Adopting Accellera’s Portable Stimulus Standard: Early Development and Validation using Virtual PrototypingSimranjit Singh, Ashwani Aggarwal, Harshita Prabha, Vishnu Ramadas, Seonil Brian Choi, Woojoo Space Kim2021Papery2021paper
Advanced Digital-Centric Mixed-Signal MethodologyMichael Kontz, David Lacey, and Peter Maroni2015Papery2015paper
Advanced Digital-Centric Mixed-Signal MethodologyMichael Kontz, David Lacey, and Peter Maroni2015Presentationy2015presentation
Advanced Functional Verification for Automotive System on a ChipJaein Hong, Jieun Jeong , Namyoung Kim, Hongkyu Kim, Sungcheol Park,2022Presentationy2022presentation
Advanced Functional Verification for Automotive System on a ChipJaein Hong, Jieun Jeong, Namyoung Kim, Hongkyu Kim, and Sungcheol Park2022Papery2022paper
Advanced Functional Verification Methodology Using UVM for complex DSP Algorithms in Mixed Signal RF SoCsSrinivas Aluri and Jaimin Mehta2014Papery2014paper
Advanced Functional Verification Methodology Using UVM For Complex DSP Algorithms In Mixed Signal RF SoCsSrinivas Aluri and Jaimin Mehta2014Presentationy2014presentation
Advanced SOC Randomization Tool for Complex SOC Level VerificationMarvin Mei, Chris Weller, Michael Sedmak, and Zhiqiang Ren2020Papery2020paper
Advanced Techniques for ARM L2 Cache Verification in an Accelerated Hardware and Software environmentRob Pelt and Jay O’Donnell2012Papery2012paper
Advanced Techniques for AXI Fabric Verification in a Software/Hardware OVM EnvironmentGalen Blake and Steve Chappell2012Papery2012paper
Advanced Testbench Configuration with ResourcesMark Glasser2011Papery2011paper
Advanced UCIe-based Chiplets verification from IP to SoCAnunay Bajaj, Moshik Rubin2024Presentationy2024presentation
Advanced Usage Models for Continuous Integration in Verification EnvironmentsJohn Dickol2015Papery2015paper
Advanced Usage Models for Continuous Integration in Verification EnvironmentsJohn Dickol2015Presentationy2015presentation
Advanced UVM Based Chip Verification Methodologies with Full Analog FunctionalitySimul Barua, FNU Farshad, Henry Chang2024Presentationy2024presentation
Advanced UVM Based Chip Verification Methodologies with Full Analog FunctionalitySimul Barua, FNU Farshad, Henry Chang2024Papery2024paper
Advanced UVM Command Line ProcessorSiddharth Krishna Kumar2022Presentationy2022presentation
Advanced UVM Command Line Processor for Central Maintenance and Randomization of Control KnobsSiddharth Krishna Kumar2022Papery2022paper
Advanced UVM Register ModelingMark Litterick and Marcus Harnisch2014Papery2014paper
Advanced UVM Register ModelingMark Litterick2014Presentationy2014presentation
Advanced UVM, Multi-Interface, Reactive Stimulus TechniquesClifford E. Cummings, Stephen DOnofrio, Jeff Wilcox, Heath Chambers2021Papery2021paper
Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification CycleCharul Agrawal, Ashwin Vijayan, and Jakub Dudek2017Papery2017paper
Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification CycleCharul Agrawal, Ashwin Vijayan, and Jakub Dudek2017Presentationy2017presentation
Advancing system-level verification using UVM in SystemCMartin Barnasconi, François Pêcheux, and Thilo Vörtler2014Papery2014paper
Advancing system-level verification using UVM in SystemCMartin Barnasconi, François Pêcheux, and Thilo Vörtler2014Presentationy2014presentation
Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC.Nipun Bhatt2020Papery2020paper
Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC.Nipun Bhatt2020Postery2020poster
AI based Media Functional Safety and Reliability verification in Safety-Critical Autonomous SystemsSuresh Vasu, Palanivel Guruvareddiar2024Papery2024paper
AI based Media Functional Safety and Reliability Verification in Safety-Critical Autonomous SystemsSuresh Vasu, Palanivel Guruvareddiar2024Presentationy2024presentation
AI-based Algorithms to Analyze and Optimize Performance Verification EffortsSaksham Mehra, Raghu Alamuri, Sharada Vajja2024Papery2024paper
All Artificial, Less Intelligence: GenAI through the Lens of Formal VerificationAman Kumar, Deepak Narayan Gadde Thomas Nalapat, Evgenii Rezunov, Fabio Cappellini2024Presentationy2024presentation
All Artificial, Less Intelligence: GenAI through the Lens of Formal VerificationDeepak Narayan Gadde, Aman Kumar, Thomas Nalapat, Evgenii Rezunov, Fabio Cappellini2024Papery2024paper
An Analytical View of Test Results Using CityScapesMarkus Borg, Andreas Brytting, and Daniel Hansson2018Papery2018paper
An Analytical View of Test Results Using CityScapesMarkus Borg, Andreas Brytting, and Daniel Hansson2018Postery2018poster
An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 ExperienceMahesha Shankarathota, Vybhava S, and Indrajit Dutta2013Papery2013paper
An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 ExperienceMahesha Shankarathota, Vybhava S, and Indrajit Dutta2013Postery2013poster
An Assertion Based Approach to Implement VHDL Functional CoverageMichael Wazlowski, Susan Eickhoff, Michael Debole, and Tagbo Ekwueme-Okoli2014Presentationy2014presentation
An Assertion Based Approach to Implement VHDL Functional CoverageSusan Eickhoff, Michael DeBole, and Tagbo Ekwueme-Okoli2014Papery2014paper
An Automated Validation Framework for Power Management and Data Retention Logic Kits of Standard Cell LibraryAkshay Kamath, Bharath Kumar, Sunil Aggarwal, Subramanian Parameswaran, Parag Lonkar, Debi Prasanna, Somasunder Sreenath2021Papery2021paper
An Automatic Visual System Performance Stress Test for TLM DesignsGeorge F. Frazier, Neeti Bhatnagar, and Woody Larue2011Papery2011paper
An Easy VE/DUV Integration ApproachUwe Simm2015Presentationy2015presentation
An efficient analog fault-injection flow harnessing the power of abstractionRenaud Gillon, Enrico Fraccaroliy, and Franco Fummi2019Postery2019poster
An Efficient and Modular Approach for Formally Verifying Cache ImplementationsM, Achutha KiranKumar V and Abhijith A Bharadwaj2018Papery2018paper
An Efficient and Modular Approach for Formally Verifying Cache implementationsM Achutha KiranKumar V, Abhijith A Bharadwaj, and Bindumadhava S S2018Presentationy2018presentation
An Efficient Method to Verify Dynamic IP Clock Frequency on SOC Level by Using Auto-generated Active Clock MonitorJaecheon Kim, Gyuhong Lee, Yeonho Jeong, Hyunsun Ahn, Daewoo Kim, Seonil Brian Choi2021Papery2021paper
An Enhanced DV Approach for Effectively Verifying High Speed, Low Power MIPI-MPHY 5.0 DesignsEldhose PM, Kuntal Pandya, Sagar Jayakrishanan, Suraj Vijay Shetty, Parag S Lonkar2023Postery2023poster
An Enhanced DV Approach for Effectively Verifying High Speed, Low Power MIPI-MPHY5.0 DesignsEldhose P.M, Sagar Jayakrishnan, Suraj Vijay Shetty, Kuntal Pandya, Parag S. Lonkar2023Papery2023paper
An Enhanced Stimulus and Checking Mechanism on Cache VerificationChenghuan Li, Xiaohui Zhao, and Yunyang Song2019Postery2019poster
An Equivalent Modeling Approach for High-Density DRAM Array System-Level Design-Space Exploration in SystemVerilogSeyoung Kim, Jaeha Kim2021Papery2021paper
An Experience of Complex Design Validation: How to Make Semiformal Verification WorkSabih Agbaria, Dan Carmi, Orly Cohen, Dmitry Korchemny, Michael Lifshits, and Alexander Nadel2010Papery2010paper
An experience to finish code refinement earlier at behavioral levelDae-Han Youn, Sik Kim, Byeong Min, and Kyu-Myung Choi2011Papery2011paper
An Expert System Based Tool for Pre-design Chip Power EstimationBhanu Singh, Arunprasath Shankar, Francis Wolff, and Christos Papachristou2014Presentationy2014presentation
An Expert System Based Tool for Pre-design Chip Power EstimationBhanu Singh, Arunprasath Shankar, Francis Wolff, and Christos Papachristou2014Papery2014paper
An Innovative Methodology for RTL and Verification IP Sharing Between Two ProjectsAlbert Xu and Joonyoung Kim2013Papery2013paper
An Innovative Methodology for RTL and Verification IP Sharing Between Two ProjectsAlbert Xu and Joonyoung Kim2013Postery2013poster
An Innovative Methodology for Verifying Mixed-Signal ComponentsFabian Delguste and Graeme Nunn2011Papery2011paper
An Integrated Framework for Power Aware VerificationHarsh Chilwal, Manish Jain, and Bhaskar Pal2012Papery2012paper
An Overview of Security Annotation for Electronic Design Integration (SA-EDI) StandardSohrab Aftabjahani2022Presentationy2022presentation
Analog Transaction Level Modeling for Verification of Mixed-Signal-BlocksAlexander W. Rath, Volkan Esen, and Wolfgang Ecker2012Papery2012paper
Analog Transaction Level Modeling for Verification of Mixed-Signal-BlocksAlexander W. Rath2012Presentationy2012presentation
Analysis of TLM-2.0 and it’s Applicability to Non Memory Mapped InterfacesGuillaume Delbergue, Mark Burton, and Bertrand Le Gal and Christophe Jego2016Papery2016paper
Analysis of TLM-2.0 and it’s Applicability to Non Memory Mapped InterfacesDelbergue Guillaume2016Presentationy2016presentation
Apples versus Apples HVL Comparison Finally Arrives Comparing OVM SystemVerilog to OVM eBrett Lammers and Riccardo Oddone2010Papery2010paper
Application Abstraction Layer: The Carpool Lane on the SoC Verification FreewayAbhisek Verma, Varun S, and Subramanian Kuppusamy2015Papery2015paper
Application Abstraction Layer: The Carpool Lane on the SoC Verification FreewayAbhisek Verma, Varun S, and Subramanian Kuppusamy2015Presentationy2015presentation
Application of SystemC/SystemC-AMS in 3G Virtual PrototypingTao Huang and Stefan Heinen2011Papery2011paper
Application Optimized HW/SW Design & Verification of a Machine Learning SoCLauro Rizzatti, Russell Klein, Stephen Bailey, and Andrew Meier2020Presentationy2020presentation
Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical PropertiesK. Selyunin, T. Nguyen, A.D. Basa, E. Bartocci, D. Nickovic, and R. Grosu2016Papery2016paper
Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical PropertiesKonstantin Selyunin, Thang Nguyen, Andrei-Daniel Basa, Ezio Bartocci, Dejan Nickovic, and Radu Grosu2016Presentationy2016presentation
Applying Test-Driven Development Methods to Design Verification SoftwareDoug Gibson and Mike Kontz2014Presentationy2014presentation
Applying Test-Driven Development Methods to Design Verification Software in UVM-eDoug Gibson and Mike Kontz2014Papery2014paper
Applying Transaction-level Debug and Analysis Techniques to DUT Simulated Activity Using Data- Mining TechniquesLeo Chai, Bindesh Patel, and Jun Zhao2014Papery2014paper
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Architecting “Checker IP” for AMBA protocolsSrinivasan Venkataramanan and Ajeetha Kumari2017Papery2017paper
Architecting “Checker IP” for AMBA protocolsAjeetha Kumari and Srinivasan Venkataramanan2017Presentationy2017presentation
Architectural Evaluation Of a Programmable Accelerator For Baseband, Phy and Video Applications Using High Level SynthesisAndy Fox, Tigran Sargsyan, and Steven Anderson2014Postery2014poster
Architectural Evaluation of a Programmable Accelerator for Baseband, Phy and Video Applications using High Level SynthesisAndy Fox, Tigran Sargsyan, and Steven Anderson2014Papery2014paper
Architectural Formal Verification of System-Level DeadlocksMandar Munishwar1, Naveed Zaman, Anshul Jain, HarGovind Singh, and Vigyan Singhal2018Papery2018paper
Architectural Formal Verification of System-Level DeadlocksMandar Munishwar and Vigyan Singhal2018Presentationy2018presentation
Are My Fault Campaigns Providing Accurate Results for ISO 26262 Certification?Hyunsun Ahn, James Kim, Arun Gogineni, Ann Keffer, MyungKyoon Yim, Soobon Kim, Youngsik Kim, Seonil Brian Choi2024Papery2024paper
Are OVM & UVM Macros Evil? A Cost-Benefit AnalysisAdam Erickson2011Papery2011paper
Are you really confident that you are getting the very best from your verification resources?Darron May and Fritz Ferstl2014Postery2014poster
Are you really confident that you are getting the very best from your verification resources?Darron May and Fritz Ferstl2014Papery2014paper
Are You Safe Yet? Safety Mechanism Insertion and ValidationPing Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen2020Papery2020paper
Are You Safe Yet? Safety Mechanism Insertion and ValidationPing Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen2020Postery2020poster
Are You Smarter Than Your Testbench? With a little work you can be.Rich Edelman and Raghu Ardeishar2015Papery2015paper
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Arithmetic Overflow Verification using Formal LINTKaiwen Chin, Esra Sahin Basaran, Kranthi Pamarthi2024Postery2024poster
Arithmetic Overflow Verification using Formal LINTKaiwen Chin, Esra Sahin Basaran, Kranthi Pamarthi2024Papery2024paper
ASIC-Strength Verification in a Fast-Moving FPGA WorldBryan Murdock2013Papery2013paper
ASIC-Strength Verification in a Fast-Moving FPGA WorldBryan Murdock2013Postery2013poster
Assertion Based Self-checking of Analog Circuits for Circuit Verification and Model Validation in SPICE and Co-simulation EnvironmentsLakshmanan Balasubramanian, Pooja Sundar, and Timothy W Fischer2011Papery2011paper
Assertion-based Verification for Analog and Mixed Signal DesignsSrinivas Aluri2017Papery2017paper
Assertion-based Verification for Analog andMixed Signal DesignsSrinivas Aluri2017Postery2017poster
Asynchronous Behaviors Meet Their Match with SystemVerilog AssertionsDoug Smith2010Papery2010paper
Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor CoreWei Foong Thoo and David A. Burgoon2012Presentationy2012presentation
Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor CoreWei Foong Thoo and David A. Burgoon2012Papery2012paper
Automated approach to Register Design and Verification of complex SOCBallori Banerjee, Subashini Rajan, and Silpa Naidu2011Papery2011paper
Automated Comparison of Analog Behavior in a UVM EnvironmentSebastian Simon2014Presentationy2014presentation
Automated Comparison of Analog Behavior in a UVM EnvironmentSebastian Simon, Alexander W. Rath, Volkan Esen, and Wolfgang Ecker2014Papery2014paper
Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal VerificationSamantha Pandez, Christopher Geen2023Papery2023paper
Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal VerificationSamantha Pandez Christopher Geen2023Postery2023poster
Automated Formal Verification of a Highly-Configurable Register GeneratorShuhang Zhang, Bryan Olmos, Basavaraj Naik2024Papery2024paper
Automated Formal Verification of a Highly-Configurable Register GeneratorShuhang Zhang, Bryan Olmos, Basavaraj Naik Infineon Technologies AG2024Presentationy2024presentation
Automated Generation of Interval Properties From Trace-Based Function ModelsRobert Kunzelmann, Aishwarya Sridhar, Daniel Gerl, Lakshmi Vidhath Boga, Wolfgang Ecker2024Papery2024paper
Automated Generation of Interval Properties From Trace-Based Function ModelsRobert Kunzelmann, Aishwarya Sridhar, Daniel Gerl, Lakshmi Vidhath Boga, Wolfgang Ecker2024Presentationy2024presentation
Automated Generation of RAL-based UVM SequencesVijayakrishnan Rousseau, Satyajit Sinari, Benjamin Applequist, Timothy McLean, and Geddy Lallathin2020Papery2020paper
Automated Generation of RAL-based UVM SequencesSatyajit Sinari, Timothy McLean, Benjamin Applequist, Vijayakrishnan Rousseau, and Geddy Lallathin2020Presentationy2020presentation
Automated Modeling Testbench Methodology Tested with four Types of PLL ModelsAutomated Modeling Testbench Methodology Tested with four Types of PLL Models2023Papery2023paper
Automated Modeling Testbench Methodology Tested with four Types of PLL ModelsJun Yan, Josh Baylor2023Presentationy2023presentation
Automated Performance Verification to Maximize your ARMv8 pulling powerNick Heaton and Simon Rance2015Papery2015paper
Automated Performance Verification to Maximize your ARMv8 pulling powerNick Heaton and Simon Rance2015Presentationy2015presentation
Automated Physical Hierarchy Generation: Tools and MethodologyAli El-Zein, Alvan Ng, Benedikt Geukes, Maya H. Safieddine, and Wolfgang Roesner2018Presentationy2018presentation
Automated Physical Hierarchy Generation: Tools and MethodologyAli El-Zein, Alvan Ng, Benedikt Geukes, Maya H. Safieddine, and Wolfgang Roesner2018Papery2018paper
Automated RTL Update for Abutted DesignWonkyung Lee, Ayoung Kwon, Soyeong Kwon, Youngsik Kim, and Seonil Brian Choi2020Papery2020paper
Automated RTL Update for Abutted DesignWonkyung Lee, Ayoung Kwon, Soyeong Kwon, Youngsik Kim, and Seonil Brian Choi2020Postery2020poster
Automated Safety Verification for Automotive MicrocontrollersH. Busch2016Papery2016paper
Automated Safety Verification for Automotive MicrocontrollersHolger Busch2016Presentationy2016presentation
Automated Seed Selection Algorithm for an Arbitrary Test SuiteDavid Crutchfield, Brian Craw, Jim Sharpe, and Brandon Skaggs2018Papery2018paper
Automated Seed Selection Algorithm for an Arbitrary Test SuiteDavid Crutchfield, Brian Craw, Jim Sharpe, and Brandon Skaggs2018Presentationy2018presentation
Automated Specification Driven Verification by Generation of SystemVerilog AssertionsFerdinando Pace2016Papery2016paper
Automated Specification Driven Verification by Generation of SystemVerilog AssertionsFerdinando Pace2016Postery2016poster
Automated Test Generation to Verify IP Modified for System Level Power ManagementChristophe Lamard2015Papery2015paper
Automated Test Generation to Verify IP Modified for System Level Power ManagementChristophe Lamard and Frederic Dupuis2015Presentationy2015presentation
Automated Thread Evaluation of Various RISC-V Alternatives using Random Instruction GenerationEndri Kaja, Nicolas Gerlin, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker2023Presentationy2023presentation
Automated Thread Evaluation of Various RISC-V Alternatives using Random Instruction GeneratorsEndri Kaja, Nicolas Gerlin, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker2023Papery2023paper
Automated traceability of requirements in the design and verification process of safety-critical mixed-signal systemsGabriel Pachiana, Maximilian Grunwald, Thomas Markwirth, Christoph Sohrmann2021Papery2021paper
Automatic Debug Down to the LineDaniel Hansson and Patrik Granath2017Postery2017poster
Automatic Debug Down to the Line of CodeDaniel Hansson and Patrik Granath2017Papery2017paper
Automatic Exploration of Hardware/Software PartitioningSyed Abbas Ali Shah, Sven Alexander Horsinka, Basitan Farkas, Rolf Meyer, and Malden Berekovic2017Papery2017paper
Automatic Exploration of Hardware/Software PartitioningSyed Abbas Ali Shah, Sven Alexander Horsinka, Basitan Farkas, Rolf Meyer, and Malden Berekovic2017Presentationy2017presentation
Automatic Generation of Formal Properties for Logic Related to Clock GatingShuqing Zhao and Shan Yan2015Papery2015paper
Automatic Generation of Formal Properties for Logic Related to Clock GatingShuqing Zhao and Shan Yan2015Presentationy2015presentation
Automatic generation of Programmer Reference Manual and Device Driver from PSSFreddy Nunez2024Presentationy2024presentation
Automatic generation of Programmer Reference Manual and Device Driver from PSSFreddy Nunez2024Presentationy2024presentation
Automatic Investigation of Power InefficienciesKuo Kai Hsieh, Li C. Wang, Wen Chen, Monica Farkash, and Jayanta Bhadra2017Presentationy2017presentation
Automatic Investigation of Power InefficiencyKuo-Kai Hsieh, Wen Chen, Monica Farkash, Jayanta Bhadra, and Li-C. Wang2017Papery2017paper
Automatic Partitioning for Multi-core HDL SimulationGaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra2015Papery2015paper
Automatic Partitioning for Multi-core HDL SimulationGaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra2015Postery2015poster
Automatic SOC Test Bench CreationDavid Crutchfield, Mark Glasser, and Stephen Roe2015Papery2015paper
Automatic SOC Test Bench CreationDavid Crutchfield, Mark Glasser, and Stephen Roe2015Presentationy2015presentation
Automatic Translation of Natural Language to SystemVerilog AssertionsAbhishek Chauhan2022Presentationy2022presentation
Automatic Translation of Natural Language to SystemVerilog AssertionsAbhishek Chauhan2022Papery2022paper
Automatic verification for Assertion Based Verification: How can a SPIRIT IP-XACT extension help?Sofiene Mejri and Mirella Negro Marcigaglia2010Papery2010paper
Automating sequence creation from a Microarchitecture specificationSubramoni Parameswaran and Ravi Ram2016Papery2016paper
Automating sequence creation from a microarchitecture specificationSubramoni Parameswaran and Ravi Ram2016Postery2016poster
Automating the Integration Workflow with IP-Centric DesignSimon Butler2024Presentationy2024presentation
Automating the Formal Verification of Firmware: A Novel Foundation and Scalable MethodologyBryan Olmos, Sanjana Sainath, Wolfgang Kunz, Djones Lettnin2024Presentationy2024presentation
Automating the Formal Verification of Firmware: A Novel Foundation and Scalable MethodologyBryan Olmos, Sanjana Sainath, Wolfgang Kunz, Djones Lettnin2024Papery2024paper
Automating the formal verification sign-off flow of configurable digital IP’sGiovanni Auditore and Giuseppe Falconeri2019Presentationy2019presentation
Automating the formal verification sign-off flow of configurable digital IP’sGiovanni Auditore and Giuseppe Falconeri2019Papery2019paper
Automation for Early Detection of X-propagation in Power-Aware Simulation Verification using UPF IEEE 1801Tony Gladvin George, Ramesh Kumar, Kyuho Shim, Karan K, Wooseong Cheong, ByungChul Yoo2023Presentationy2023presentation
Automation for Early Detection of Xpropagation in Power-Aware Simulation Verification using UPF IEEE 1801Tony Gladvin George, Ramesh Kumar, Kyuho Shim, Karan K, Wooseong Cheong, ByungChul Yoo2023Papery2023paper
Automation Methodology for Bus Performance Verification using IP-XACTTaeyoung Jeon, Gunseo Koo, Youngsik Kim, Seonil Brian Cho2023Postery2023poster
Automation Methodology for Bus Performance Verification using IP-XACTTaeyoung Jeon, Gunseo Koo, Youngsik Kim, Seonil Brian Choi2023Papery2023paper
Automation of Power On Reset AssertionShang-Wei Tu, Penny Yang, Joydeep Gangopadhyay, and Amol Herlekar2015Papery2015paper
Automation of Reusable Protocol-Agnostic Performance Analysis in UVM EnvironmentsDaniel Carrington, Alan Pippin, and Timothy Pertuit2019Presentationy2019presentation
Automation of Reusable Protocol-Agnostic Performance Analysis in UVM EnvironmentsD. P. Carrington, A. J. Pippin, and T. Pertuit2019Papery2019paper
Avoiding Configuration Madness The Easy WayRich Edelman2023Presentationy2023presentation
Avoiding Configuration Madness The Easy WayRich Edelman2023Papery2023paper
Avoiding Confounding Configurations an RDC Methodology for Configurable DesignsEamonn Quigley, Jonathan Niven, and Kurt Takara2022Postery2022poster
Avoiding Confounding Configurations An RDC Methodology for Configurable DesignsEamonn Quigley, Jonathan Niven, and Kurt Takara2022Papery2022paper
BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering ProblemDebarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, Siddhanth Dhodhi, Spandan Kachhadiya2022Presentationy2022presentation
BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering ProblemDebarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, and Siddhanth Dhodhi2022Papery2022paper
Be a Sequence Pro to Avoid Bad Con SequencesJeff Vance, Jeff Montesano, Mark Litterick, and Jason Sprott2019Presentationy2019presentation
Best Practices in Verification PlanningBenjamin Ehlers, Carmen Vargas, and Paul Carzola2013Papery2013paper
Best Practices in Verification PlanningBenjamin Ehlers and Paul Carzola2013Presentationy2013presentation
Better Living Through Better Class-Based SystemVerilog DebugRich Edelman, Raghu Ardeishar, and John Amouroux2012Papery2012paper
Better Living Through Better Class-Based SystemVerilog DebugRich Edelman, Raghu Ardeishar, and John Amouroux2012Presentationy2012presentation
Beyond UVM: Creating Truly Reusable Protocol LayeringJanick Bergeron2013Presentationy2013presentation
Beyond UVM: Creating Truly Reusable Protocol LayeringJanick Bergeron, Fabian Delguste, Steve Knoeck, Steve McMaster, Aron Pratt, and Amit Sharma2013Papery2013paper
Bi-Directional UVM Agents and Complex Stimulus Generation for UDN and UPF PinsChuck McClish2021Papery2021paper
Big Data in Verification: Making Your Engineers SmarterDavid Lacey, Mike McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson2019Papery2019paper
Big Data in Verification: Making Your Engineers SmarterDavid Lacey, Michael McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson2019Presentationy2019presentation
Blending multiple metrics from multiple verification engines for improved productivityDarron May and Darren Galpin2012Papery2012paper
Boost Verification Results by Bridging the Hardware/Software Testbench GapMatthew Ballance2013Papery2013paper
Boost Verification Results by Bridging the Hw/Sw Testbench GapMatthew Ballance2013Presentationy2013presentation
BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMSAhmed Yehia2013Postery2013poster
BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMSAhmed Yehia2013Papery2013paper
Bridge the Portable Test and Stimulus to UVM Simulation EnvironmentTheta Yang and Evean Qin2018Presentationy2018presentation
Bridge the Portable Test and Stimulus to UVM Simulation EnvironmentTheta Yang and Evean Qin2018Papery2018paper
Bridging the gap between TLM-2.0 AT models and RTL – Experiments and OpportunitiesZhu Zhou, Atul Kwatra, Rajesh Gadiyar, and Paul Heraty2010Papery2010paper
Bringing Constrained Random into SoC SW-driven VerificationAlberto Allara and Fabio Brognara2013Presentationy2013presentation
Bringing Constrained Random into SoC SW-driven VerificationAlberto Allara and Fabio Brognara2013Papery2013paper
BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPSPrabal K Bhattacharya, Swapnajit Chakraborti, Scott Little, Donald O’Riordan, and Vaibhav Bhutani2012Papery2012paper
BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPSPrabal K Bhattacharya, Swapnajit Chakraborti, Donald O’Riordan, Vaibhav Bhutani, and Scott Little2012Presentationy2012presentation
Bringing Regression Systems into the 21st CenturyDavid Crutchfield2014Postery2014poster
Bringing Regression Systems into the 21st CenturyDavid Crutchfield and Thom Ellis2014Papery2014paper
Bringing Reset Domains and Power Domains together – Confronting issues due to UPF InstrumentationInayat Ali, Abdul Moyeen, Manish Bhati, Manjunatha Srinivas2021Papery2021paper
Bringing UVM to VHDLUVVM2022Presentationy2022presentation
Building a Comprehensive Hardware Security MethodologyAnders Nordstrom and Jagadish Nayak2022Presentationy2022presentation
Building Portable Stimulus Into Your IP-XACT FlowPetri Karppa, Lauri Matilainen, and Matthew Balance2018Papery2018paper
Building Portable Stimulus Into your IP-XACT FlowPetri Karppa, Lauri Matilainen, and Matthew Ballance2018Presentationy2018presentation
Bus Trace System: Automating Bus Traffic Debugging in IP-XACT Based SoCWonyeong So, Yonghyun Yang, Sun-il Roe, Moonki Jang, Youngsik Kim, Seonil Brian Choi2024Presentationy2024presentation
Bus Trace System: Automating Bus Traffic Debugging in IP-XACT Based SoC Beyond Traditional Debugging MethodsWonyeong So, Yonghyun Yang, Sun-il Roe, Moonki Jang, Youngsik Kim, Seonil Brian Choi2024Papery2024paper
C through UVM: Effectively using C based models with UVM based Verification IPChris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile2013Papery2013paper
C through UVM: Effectively using C based models with UVM based Verification IPAdiel Khan, Chris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile2013Presentationy2013presentation
Caching Tool Run Results in Large Scale RTL Development ProjectsAshfaq Khan2022Presentationy2022presentation
Caching Tool Run Results in Large-Scale RTL Development ProjectsAshfaq Khan2022Papery2022paper
Calling All Checkers: Collaboratively Utilizing SVA In UVM Based SimulationHui K. Zhang2016Papery2016paper
Calling All Checkers: Collaboratively Utilizing SVA in UVM Based SimulationHui C. K. Zhang2016Postery2016poster
CAMEL – A Flexible Cache Model for Cache VerificationYue Liu, Fang Liu, Yunyang Song2022Presentationy2022presentation
CAMEL: A Flexible Cache Model for Cache VerificationYue Liu, Fang Liu, and Yunyang Song2022Papery2022paper
Can Formal Outsmart Synthesis: Improving Synthesis Quality of Results through Formal MethodsEldon Nelson2021Papery2021paper
Can My Synthesis Compiler Do That?Stuart Sutherland and Don Mills2014Papery2014paper
Can My Synthesis Compiler Do That?Stuart Sutherland and Don Mills2014Presentationy2014presentation
Can You Even Debug a 200M+ Gate Design?Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss2013Papery2013paper
Can You Even Debug a 200M+ Gate Design?Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss2013Postery2013poster
Case Study: Low-Power Verification Success Depends on Positive PessimismJohn Decker2011Papery2011paper
Case Study: Power-aware IP and Mixed-Signal VeriLuke Lang2011Papery2011paper
Case Study: Successes and Challenges of Validation Content ReuseMike Chin, Jonathan Edwards, Josh Pfrimmer, and Hooi Jing Tan2022Papery2022paper
Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation)Vikas Billa and Sundar Haran2018Presentationy2018presentation
Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation)Vikas Billa and Sundar Haran2018Papery2018paper
Challenges in UVM + Python Random Verification Environment for Digital Signal Processing Datapath DesignShabbar Vejlani and Ashok Chandran2016Presentationy2016presentation
Challenges in UVM + Python random verification environment for Digital Signal Processing datapath design.Shabbar Vejlani and Ashok Chandran2016Papery2016paper
Check Low-Power Violations by Using Machine Learning Based ClassifierChi-Ming Lee, Chung-An Wang, Cheok-Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai2023Postery2023poster
Check Low-Power Violations by Using Machine Learning Based ClassifierChi-Ming Lee, Chung-An Wang, Cheok-Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai2023Papery2023paper
Checking security path with formal verification tool: new application developmentJulia Dushina, Saumil Shah, Joerg Mueller, and Vincent Reynolds2014Papery2014paper
Checking Security Path with Formal Verification Tool: New Application DevelopmentJulia Dushina and Joerg Mueller2014Postery2014poster
Chef’s Special – an Efficient Verification Recipe for Maximizing Productivity While Using a Third Party Verification IPVarun S and Bhavik Vyas2012Papery2012paper
Cleaning Out Your Pipes – Pipeline Debug in UVM TestbenchesRich Edelman and Neil Bulman2018Papery2018paper
Cleaning Out Your Pipes – Pipeline Debug in UVM TestbenchesRich Edelman and Neil Bulman2018Postery2018poster
CLOCK DOMAIN CROSSING CHALLENGES IN LATCH BASED DESIGNSMadan Das, PhD, Chris Kwok, and Kurt Takara2018Papery2018paper
Clock Domain Crossing Challenges in Latch Based DesignsMadan Das, Chris Kwok, and Kurt Takara2018Presentationy2018presentation
Clock Domain Crossing Verification in Transistor-level DesignHyungjung Seo, KwangSun Kim, YoungRok Choi, Jihwan Kim, and Jong-Bae Lee2019Postery2019poster
Closing Functional and Structural Coverage on RTL Generated by High-Level SynthesisB. Bowyer2015Papery2015paper
Closing Functional and Structural Coverage on RTL Generated by High-Level SynthesisBryan Bowyer2015Postery2015poster
Closing Functional Coverage With Deep Reinforcement Learning: A Compression Encoder ExampleEric Ohana2023Papery2023paper
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Co-Developing Firmware and IP with PSSM. Ballance2022Papery2022paper
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Co-Simulating Matlab/Simulink Models in a UVM EnvironmentNeal Okumura, Paul Yue, and Glenn Richards2015Presentationy2015presentation
Co-Simulating Matlab/Simulink Models in a UVM EnvironmentNeal Okumura and Glenn Richards2015Papery2015paper
Coding Guidelines and Code GenerationJohn Aynsley and Dr. Christoph Sühnel2014Postery2014poster
Coherency Verification & Deadlock Detection Using Perspec/Portable StimulusMoonki Jang, Jiwoong Kim, Hyerim Chung, Phu L. Huynh, and Shai Fuss2019Papery2019paper
Coherency Verification & Deadlock Detection Using Perspec/Portable StimulusMoonki Jang and Phu Huynh2019Presentationy2019presentation
Combining Simulation with Formal Techniques to Reduce the Overall Verification CycleAneet Agarwal and Gaurav Gupta2010Papery2010paper
Command Line Debug Using UVM SequencesMark Peryer2011Papery2011paper
Common Challenges and Solutions to Integrating a UVM TestbenchFrank Verhoorn and Mike Baird2018Presentationy2018presentation
Common Challenges and Solutions to Integrating a UVM Testbench in Place of a Legacy Monolithic Testing EnvironmentFrank Verhoorn and Michael Baird2018Papery2018paper
Comparison of TLM2-Quantum Keeping and TLM+-Resource Modeling with regard to Timing in Virtual PrototypesWolfgang Ecker, Volkan Esen, Rainer Findenigy, Thomas Leitnerz and Michael Velten2011Papery2011paper
Complementing EDA with Meta-Modeling and Code GenerationWolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal2014Papery2014paper
Complementing EDA with Meta-Modelling & Code GenerationWolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal2014Postery2014poster
Complementing EDA with Meta-Modelling and Code GenerationEcker Wolfgang, Michael Velten, Ajay Goyal, and Leily Zafari2014Presentationy2014presentation
Complex Safety Mechanisms Require Interoperability and Automation For Validation And Metric ClosureDaeseo Cha, Vedant Garg, Ann Keffer, Arun Gogineni, James Kim, Woojoo Space Kim, Kunhyuk Kang, Seonil Brian Choi2023Papery2023paper
Complex Safety Mechanisms Require Interoperability and Automation For Validation And Metric ClosureDaeseo Cha, Vedant Garg2023Presentationy2023presentation
Complexities & Challenges of UPF Corruption Model in Low Power EmulationProgyna Khondkar, Brad Budlong2024Papery2024paper
CompMon: Ensuring Rigorous Protocol Specification and IP ComplianceRobert Adler, Sava Krstic and Erik Seligman2011Papery2011paper
Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain CrossingsYossi Mirsky2017Presentationy2017presentation
Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain CrossingsYossi Mirsky B.Sc, M.Sc, MBA2017Papery2017paper
Comprehensive IP to SoC CDC Verification Using Hybrid Data ModelAnwesha Choudhury and Ashish Hari2018Postery2018poster
Comprehensive IP to SoC Clock Domain Crossing Verification Using Hybrid Data ModeAnwesha Choudhury and Ashish Hari2018Papery2018paper
Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-ChipsEllie Burns, Gabriel Chidolue, and Guillaume Boillet2018Presentationy2018presentation
Comprehensive Register Description Languages: The case for standardization of RDLs across design domainsDavid C Black and Doug Smith2012Papery2012paper
Comprehensive Systemverilog-Systemc-Vhdl Mixed-Language Design MethodologyRudra Mukherjee, Gaurav Kumar Verma, and Sachin Kakkar2010Papery2010paper
Conditional Delays for Negative Limit Timing Checks in Event Driven SimulationNadeem Kalil and David Roberts2015Papery2015paper
Conditional Delays for Negative Limit Timing Checks in Event Driven SimulationN. Kalil and D. Roberts2015Postery2015poster
Confidently Sign-off Any low-Power Designs without ConsequencesMadhur Bhargava, Jitesh Bansal, and Progyna Khondkar2022Postery2022poster
Confidently Sign-Off Any Low-Power Designs Without ConsequencesMadhur Bharga, Jitesh Bansal and Progyna Khondkar2022Papery2022paper
Configuration Conundrum: Managing Test Configuration with a Bite Sized SolutionKevin Vasconcellos, Jeff McNeal2021Papery2021paper
Configuring Your Resources the UVM Way!Parag Goel, Amit Sharma, and Rajiv Hasija2012Papery2012paper
Configuring Your Resources the UVM Way!Parag Goel, Amit Sharma, and Rajiv Hasija2012Presentationy2012presentation
CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITYBin Ju2014Papery2014paper
CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITYBin Ju2014Postery2014poster
Connecting UVM with Mixed-Signal DesignIvica Ignjić2017Presentationy2017presentation
CONNECTING UVM WITH MIXED-SIGNAL DESIGNIvica Ignjić2017Papery2017paper
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Flexible Checker: A one-stop shop for all your checkers and a methodology for elastic scoreboardingSaad Zahid, Chandra Veedhi, and Sumit Dhamanwala2019Postery2019poster
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Fnob: Command Line-Dynamic Random GeneratorHaoxiang Hu, Tuo Wang2022Presentationy2022presentation
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Formal Methods to Verify the Power Manager for an Embedded Multiprocessor ClusterKesava R. Talu2010Papery2010paper
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Formal Verification of Macro-op Cache for Arm Cortex-A77, and its Successor CPUVaibhav Agrawal2020Presentationy2020presentation
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Formal Verification on Deep Learning Instructions of GPUJian (Jeffrey) Wang and Jia Zhu2018Papery2018paper
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Forward Progress Checks in Formal Verification: Liveness vs SafetyAnkit Garg2024Papery2024paper
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Four Problems with Policy-Based Constraints and How to Fix ThemDillan Mills, Chip Haldane2024Papery2024paper
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FPGA-based Clock Domain Crossing Validation for Safety-Critical DesignsAlexander Gnusin2019Presentationy2019presentation
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Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPFProgyna Khondkar, Ping Yeung, Gabriel Chidolue, Joe Hupcey, Rick Koster, and Madhur Bhargava2017Papery2017paper
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From Spec to Verification Closure: a case study of applying UVM-MS for first pass success to a complex Mixed-Signal SoC designNeyaz Khan and Yaron Kashai2012Papery2012paper
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Full Flow Clock Domain Crossing – From Source to SiM. Litterick2016Papery2016paper
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Functional Coverage Collection for Analog Circuits – Enabling Seamless Collaboration between Design and VerificationZ. Ye, H. Lin and A. M. Khan2016Papery2016paper
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Functional Coverage of Register Access via Serial Bus Interface using UVMD. M. Tomušilović2017Papery2017paper
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Functional Instruction Set Simulator (ISS) of a Neural Network Accelerator IP with native “brain float16” formatDebajyoti Mukherjee, Arpita Sahu, Arathy B S, Saranga P Pogula2023Papery2023paper
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Functional Verification of Analog Devices modeled using SV-RNMMariam Maurice2024Presentationy2024presentation
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Graphical Topology Info Structure for Constrained Random Verification in SoC/Subsystem TestsEvean Qin, Richard Bell, and David Chen2019Papery2019paper
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Hardware Emulation: ICE vs VirtualLauro Rizzatti2016Presentationy2016presentation
Hardware Trojan Design and Detection with Formal Verification to Deep Neural NetworkSi-Han Chen, Yu-Ting Huang, Yi-Chun Kao, Yean-Ru Chen, Shang-Wei Lin, Chia-I Chen2021Papery2021paper
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Jump start your RISCV project with OpenHWMike Thompson, Jingliang (Leo) Wang, Steve Richmond, Lee Moore, David McConnell, Greg Tumbush2021Papery2021paper
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Jump-Start Software-Driven Hardware Verification with a Verification FrameworkMatthew Ballance2015Papery2015paper
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Just do it! Who cares if a Structural Analysis tool is using Formal VerificationScott Aron Bloom2018Presentationy2018presentation
Keeping Score, Part 1 of 2 – Architectural Considerations for Scoreboard DesignGordon Allan2012Papery2012paper
Keeping Up with Chip — the Proposed SystemVerilog 2012 Standard Makes Verifying Ever-increasing Design Complexity More EfficientStuart Sutherland and Tom Fitzpatrick2012Papery2012paper
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Keeping Your Sequences RelevantNicholas Zicha and Eric Combes2017Papery2017paper
Key Gochas in implementing CDC for various Bus ProtocolsNikita Gulliya, Mukesh Kumar Singh, and Abhishek Bora2020Papery2020paper
Key Gochas in implementing CDC for various Bus ProtocolsNikita Gulliya, Mukesh Kumar Singh, and Abhishek Bora2020Postery2020poster
Large Language Model for Verification: A Review and Its Application in Data AugmentationDan Yu, Eman El Mandouh, Waseem Raslan, Harry Foster, Tom Fitzpatrick2024Presentationy2024presentation
Large Language Model for Verification: A Review and Its Application in Data AugmentationDan Yu, Eman El Mandouh, Waseem Raslan, Harry Foster, Tom Fitzpatrick2024Papery2024paper
Large Language Models to generate SystemC Model CodeShravan Belagalmath, Sandeep Pendharkar, Karthick Gururaj, Santhosh Selvin2024Presentationy2024presentation
Lay it On Me: Creating Layered ConstraintsBryan Morris2021Papery2021paper
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Leaping Left: Seamless IP to SoC Hand-offSwetha Thiagarajan, Rashika Madan, Hiran Morar, and Sangeivi Sivagnanasundaram2022Papery2022paper
Learning From Advanced Hardware Verification for Hardware Dependent SoftwareSimond Davidmann and Duncan Graham2014Papery2014paper
Left Shift Mechanism to Mitigate Gate Level Asynchronous Design ChallengesKotha Kavya and Sinha Rohit Kumar2022Postery2022poster
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Lessons from the field – IP/SoC integration techniques that workDavid Murray and Sean Boylan2013Papery2013paper
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Let’s be Formal While Talking About Verification Quality: A Novel Approach to Qualify Assertion Based VIPsSachin Scaria, Surinder Sood, and Erik Seligman2018Papery2018paper
Let’s DisCOVER Power StatesPankaj Kumar Dwivedi, Amit Srivastava, and Veeresh Vikram Singh2015Papery2015paper
Lets be Formal While Talking About Verification Quality: A Novel Approach Of Qualifying Assertion Based IPsSurinder Sood, Sachin Scaria, and Erik Seligman2018Presentationy2018presentation
Lets disCOVER Power StatesPankaj Kumar Dwivedi, Amit Srivastava, and Veeresh Vikram Singh2015Postery2015poster
Leveraging Formal to Verify SoC Register MapAbdul Elaydi and Jose Barandiaran2014Presentationy2014presentation
Leveraging Formal to Verify SoC Register MapAbdul Elaydi and Jose Barandiaran2014Papery2014paper
Leveraging Functional Safety Methodologies to Enhance Design Quality in Automotive ICGulshan Kumar Sharma, Sougata Bhattacharjee, James Kim, Wonil Cho, Akshaya Jain, Andrey Likhopoy, Arun Gogineni, Ann Keffer, Sangkyu Park, Hyeonuk Noh2024Presentationy2024presentation
Leveraging Interface Class to Improve UVM TLMN Goyal, J Refice2024Presentationy2024presentation
Leveraging Interface Classes to Improve UVM TLMN. Goyal, J. Refice2024Papery2024paper
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Leveraging Model Based Verification for Automotive SoC DevelopmentAswini Kumar Tata, Sanjay Chatterjee, Kamel Belhous, Surekha Kollepara, Bhanu Singh, Eric Cigan2024Presentationy2024presentation
Leveraging Model Based Verification for Automotive SoC DevelopmentAswini Kumar Tata, Bhanu Singh, Sanjay Chatterjee, Eric Cigan, Kamel Belhous, Surekha Kollepara2024Papery2024paper
Leveraging more from GLS: Using metric driven GLS stimuli to boost timing verificationSowmya Ega, Richardson Jeyapaul, and Kunal Jani2018Presentationy2018presentation
Leveraging more from GLS: Using metric driven GLS stimuli to boost Timing VerificationSowmya Ega, Richardson Jeyapaul, and Kunal Jani2018Papery2018paper
Leveraging Several Functional Safety Methodologies (Full Faults and SRF) to Enhance Design Quality in Automotive ICGulshan Kumar Sharma, Sougata Bhattacharjee, Wonil Cho, Akshaya Kumar Jain, James Kim, Sangkyu Park, Hyeonuk Noh, Andrey Likhopoy, Ann Keffer, Arun Gogineni2024Papery2024paper
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Leveraging UVM-based Low Power Package Library to SOC DesignsShikhadevi Katheriya, Avnita Pal, Puranapanda Sastry2023Papery2023paper
Leveraging Virtual Platform ESL and TLM SystemVerification in RTL using UVMAshok Mehta, Albert Chiang, and Wei-Hua Han2012Papery2012paper
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Liveness Assume-Guarantee Proof Schema: A step towards Liveness Full ProofsNitish Sharma, Venkata Nishanth Narisetty2024Papery2024paper
Low Power Apps (Shaping the Future of Low Power Verification)Awashesh Kumar, Madhur Bhargava, Vinay Kumar Singh, and Pankaj Gairola2018Presentationy2018presentation
Low Power Apps: Shaping the Future of Low Power VerificationAwashesh Kumar, Madhur Bhargava, Vinay Singh, and Pankaj Gairola2018Papery2018paper
Low Power Coverage: The Missing Piece in Dynamic SimulationProgyna Khondkar, Gabriel Chidolue, and Ping Yeung2018Papery2018paper
Low Power Coverage: The Missing Piece in Dynamic SimulationProgyna Khondkar2018Presentationy2018presentation
Low Power SoC Verification: IP Reuse and Hierarchical Composition using UPFAmit Srivastava, Rudra Mukherjee, Erich Marschner, and Chuck Seeley2012Papery2012paper
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Low Power Static Verification- Beyond Linting and Corruption SemanticsKaustav Guha , Ankush Bagotra, and Neha Bajaj2011Papery2011paper
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Low-Power Verification Automation – A Practical ApproachShaji Kunjumohamed and Hendy Kosasih2013Papery2013paper
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Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design VerificationHonghuang Lin, Zhipeng Ye, and Asad Khan2017Presentationy2017presentation
Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design VerificationH. Lin, Z. Ye, and A. M. Khan2017Papery2017paper
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Machine Learning Based Verification Planning Methodology Using Design and Verification DataHanna Jang, Seonghee Yim, Sunchang Choi, and Seonil Brian Choi2022Papery2022paper
Machine Learning Driven Verification A Step Function in Productivity and ThroughputDaniel Hansson, John Rose, and Matt Graham2022Presentationy2022presentation
Machine Learning-Guided Stimulus Generation for Functional VerificationS. Gogri, J. Hu, A. Tyagi, M. Quinn S. Ramachandran, F. Batool, and A. Jagadeesh2020Presentationy2020presentation
Machine Learning-Guided Stimulus Generation for Functional VerificationSaumil Gogri, Jiang Hu, Aakash Tyagi, Mike Quinn, Swati Ramachandran, Fazia Batool, and Amrutha Jagadeesh2020Papery2020paper
Making Autonomous Cars Safer – One chip at a timeApurva Kalia and Ann Keffer2018Presentationy2018presentation
Making Formal Property Verification Mainstream: An Intel Graphics ExperienceM Achutha KiranKumar V, Erik Seligman, Aarti Gupta, Ss Bindumadhava, and Abhijith Bharadwaj2017Papery2017paper
Making Formal Property Verification Mainstream: An Intel® Graphics ExperienceM Achutha Kiran, Kumar V., Erik Seligman, Aarti Gupta, Bindumadhava S. S., and Abhijith A. Bharadwaj2017Presentationy2017presentation
Making Legacy Portable with the Portable Stimulus SpecificationMatthew Ballance2017Presentationy2017presentation
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Making Security Verification “SECURE”NAGESH RANGANATH and SUBIN THYKKOOTTATHIL2018Postery2018poster
Making Security Verification “SECURE”Subin Thykkoottathil and Nagesh Ranganath2018Papery2018paper
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Managing Highly Configurable Design and VerificationJ. Ridgeway2018Papery2018paper
Marrying Simulation and Formal Made Easier!Lun Li, Durga Rangarajan, Christopher Starr, and James Greene2016Papery2016paper
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Maximize Vertical Reuse, Building Module to System Verification Environments with UVM eHorace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss2013Papery2013paper
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Maximizing Formal ROI through Accelerated IP Verification Sign-offHao Chen, Kamakshi Sarat Vallabhapurapu, Scott Peverelle, Rosanna Yee, Hee Chul Kim, Johann Te, and Jacob Hotz2022Papery2022paper
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Mechanism to Generate FIFO VC Dependency Graph and Its Application to System Level Deadlock VerificationDebarshi Chatterjee, Chad Parsons, Siddhanth Dhodhi2021Papery2021paper
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Melting Verification Pot: Integrating RVM/VMM and UVM, a Practical Guide and Lessons Learned.Mark A. Azadpour2012Papery2012paper
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Memory Debugging of Virtual PlatformsGeorge F. Frazier, Neeti Bhatnagar, Qizhang Chao, and Kathy Lang2012Presentationy2012presentation
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Memory Subsystem Verification: Can it be taken for granted?Shivani Upasani and Prashanth Srinivasa2013Papery2013paper
Meta Design FrameworkSanjeev Singh and Jonathan Sadowsky2015Postery2015poster
Meta Design Framework: Building Designs ProgrammaticallySanjeev Singh and Jonathan Sadowsky2015Papery2015paper
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Methodology for automating coverage-driven interrupt testing of instruction setsDavid McConnell, Greg Tumbush2021Papery2021paper
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Methodology for Separation of Design Concerns Using Conservative RTL Flipflop InferenceMaya H. Safieddine, Fadi A. Zaraket, and Rouwaida Kanj2015Papery2015paper
Metric Driven Microcode Verification: Navigating Microcode Coverage ComplexitiesSeungyeon Yu, Damin Son, Tony Gladvin George, Kihyun Park, Dongkun An, Wooseong Cheong, ByungChul Yoo2024Papery2024paper
Metric Driven Microcode Verification: Navigating Microcode Coverage ComplexitiesSeungyeon Yu, Damin Son, Tony Gladvin George, Kihyun Park, Dongkun An, Wooseong Cheong, ByungChul Yoo2024Presentationy2024presentation
Metric Driven Mixed-Signal Verification Methodology and Practices for Complex Mixed-signal ASSPsFrank Yang, Andy Sha, Morton Zhao, and Yanping Sha2014Papery2014paper
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Metric Driven Verification of Mixed-Signal DesignsNeyaz Khan, Yaron Kashai, and Hao Fang2011Papery2011paper
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Metrics in SoC VerificationAndreas Meyer and Harry Foster2012Papery2012paper
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Migrating from OVM to UVM The Definitive GuideAdiel Khan2013Presentationy2013presentation
Migrating from UVM to UVM-AMSTom Fitzpatrick, Abhijit Madhu Kumar2023Presentationy2023presentation
Migrating to UVM : Conquering LegacySantosh Sarma, Amit Sharma, and Adiel Khan2013Papery2013paper
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Mining Coverage Data for Test Set Coverage EfficiencyMonica Farkash, Bryan Hickerson, Mike Behm, and Balavinayagam Samynathan2015Papery2015paper
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Mixed Signal Assertion-Based VerificationPrabal Bhattacharya, Don O’Riordan, and Walter Hartong2011Papery2011paper
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Mixed Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP SimulationS. Do, J. Park, D. Kim, and J. Jang2022Presentationy2022presentation
Mixed Signal Verification of a Voltage Regulator using a State Space Approach and the SV-DC extensionsRajat Mitra2016Papery2016paper
Mixed Signal Verification of Dynamic Adaptive Power Management in Low Power SoCNeyaz Khan2010Papery2010paper
Mixed Signal Verification of UPF based designs A Practical ExampleAndrew Milne and Damian Roberts2015Papery2015paper
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Mixed-abstraction Modeling Approach with Fault Injection for Hardware-Firmware Co-design and Functional Co-verification of an Automotive Airbag System on Chip ProductThang Nguyen, Dipl.-Ing.-Dr. and Dieter Haerle, Dipl.-Ing.2013Presentationy2013presentation
Mixed-abstraction Modeling Approach with Fault Injection for Hardware-Firmware Co-design and Functional Co-verification of an Automotive Airbag System on Chip ProductDipl.-Ing. Dr.-techn. Thang Nguyen, Dipl.-Ing. and Dieter Haerle2013Papery2013paper
Mixed-Signal Design Verification: Leveraging the Best of AMS and DMSRock Z. Shi, Padmashree Bhinge, Preston Birdsong, Geeta Chaitanya, and Kunal Jani2022Papery2022paper
Mixed-Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP SimulationS. Do, J. Park, D. Kim, and J. Jang2022Papery2022paper
Mixed-Signal Systems-on-Chip Design Verification With Automatic Real-Number AbstractionNancy Qiu, Frank Yang, and Himadri De2016Papery2016paper
Mixed-Signal Verification Methodology to Verify Type-C USBVarun R, Vinayak Hegde, and Somasunder Kattepura Sreenath2017Papery2017paper
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ML-Based Verification and Regression AutomationAbhishek Chauhan, Asif Ahmad2021Papery2021paper
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mL: Shrinking the Verification volume using Machine LearningYash Phogat, Patrick Hamilton2024Postery2024poster
mL: Shrinking the Verification volume using Machine LearningYash Phogat, Patrick Hamilton2024Papery2024paper
Modeling a Hierarchical Register Scheme with UVMJoshua Hardy2017Papery2017paper
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Modeling Analog Devices Using SV-RNMMariam Maurice2022Postery2022poster
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Modeling Memory Coherency for Concurrent/Parallel AccessesSubramoni Parameswaran2022Presentationy2022presentation
Molding Functional Coverage for Highly Configurable IPJ. Ridgeway, K. Chaturvedula, and K. Dhruv2016Papery2016paper
Molding Functional Coverage for Highly Configurable IPJeremy Ridgeway, Kavitha Chaturvedula, and Karishma Dhruv2016Postery2016poster
Monitors, Monitors Everywhere – Who Is Monitoring the MonitorsRich Edelman and Raghu Ardeishar2013Papery2013paper
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MS-SoC Best Practices – Advanced Modeling & Verification Techniques for first-pass successNeyaz Khan, Greg Glennon, and Dan Romaine2013Papery2013paper
Multi-Domain Verification: When Clock, Power and Reset Domains CollidePing Yeung, Erich Marschner, and Kaowen Liu2015Papery2015paper
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Multi-Language Verification: Solutions for Real World ProblemsBryan Sniderman and Vitaly Yankelevich2014Papery2014paper
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Multimedia IP DMA verification platformSuhyung Kim, Sangkyu Park, Myungwoo Seo, Sangjin Lee, and Jiyeon Park2020Postery2020poster
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Multithreading a UVM Testbench for Faster SimulationBenjamin Applequist, Vijayakrishnan Rousseau, Andrew Tan, and Jayasrinivas Sesham2020Presentationy2020presentation
My Testbench Used to Break! Now it Bends (Adapting to Changing Design Configurations)Jeff Vance, Jeff Montesano, Kevin Vasconcellos, and Kevin Johnston2018Presentationy2018presentation
My Testbench Used to Break! Now it Bends: Adapting to Changing Design ConfigurationsJeff Vance, Jeff Montesano, Kevin Vasconcellos, and Kevin Johnston2018Papery2018paper
Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage ModelingJason Sprott, Paul Marriott, and Matt Graham2015Papery2015paper
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Never Too Late With Formal: Stepwise Guide for Applying Formal Verification in Post-Silicon Phase to Avoid Re-SpinsAnshul Jain, Aarti Gupta, Achutha KiranKumar V M, Bindumadhava Ss, Shivakumar S Kolar, and Siva Gadey NV2022Papery2022paper
Never Too Late with Formal: Stepwise Guide for Applying FV in Post Si Phase to Avoid Re-SpinsAnshul Jain, Aarti Gupta, Achutha KiranKumar V M, Bindumadhava Ss, Shivakumar S Kolar, Siva Gadey NV2022Presentationy2022presentation
New and active ways to bind to your designKaiming Ho2013Presentationy2013presentation
New and Active Ways to Bind to Your DesignsKaiming Ho2013Papery2013paper
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New Constrained Random and Metric-Driven Verification Methodology using PythonMarek Cieplucha and Witold A. Pleskacz2017Papery2017paper
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New Innovative Way to Verify Package ConnectivityMike Walsh, Jin Hou2024Papery2024paper
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Next Frontier in Formal VerificationPing Yeung, Rajesh Rathi, Vaibhav Kumar, Puneet Anand, Ravindra Aneja2023Presentationy2023presentation
Next Gen System Design and Verification for TransportationDavid Aerne, Jacob Wiltgen, and Richard Pugh2019Presentationy2019presentation
Next Generation Verification for the Era of AI/ML and 5GFrank Schirrmeister, Pete Hardee, Larry Melling, Amit Dua, and Moshik Rubin2020Presentationy2020presentation
Next-Generation Formal Property Verification: Lightweight Theorem Proving Integrated into Model CheckingErik Seligman, Karthik Baddam, Barbara Leite Almeida, Thamara Andrade, Poliana Bueno, Carla Ferreira, Matheus Fonesca, Lars Lundgren, Raquel, Lara dos Santos Pereira, Fabiano Peixoto, Vincent Reynolds2024Papery2024paper
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Next-generation Power Aware CDC Verification – What have we learned?Kurt Takara, Chris Kwok, Naman Jain, and Ashish Hari2015Papery2015paper
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No RTL Yet? No Problem UVM Testing a SystemVerilog Fabric ModelRich Edelman2016Presentationy2016presentation
No RTL Yet? No Problem UVM Testing a SystemVerilog Fabric ModelRich Edelman2016Papery2016paper
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Novel Approach to ASIC PrototypingMohamed Saheel, Suresh Balasubramanian, and Vijayakrishnan Rousseau2019Postery2019poster
Novel Approach to Automate Design Verification Cycle Using Continuous Integration-Continuous Deployment PlatformJuilly Sunilrao Videkar, Sri Harsha Reddy Kaliki, Shaik Babjan Sohail, Kannusamy Mariappan2024Papery2024paper
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Novel GUI Based UVM Test Bench Template BuilderVignesh Manoharan2022Postery2022poster
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Novel Mixed Signal Verification Methodology Using Complex UDNsRakesh Dama, Ravi Reddy, and Andy Vitek2019Presentationy2019presentation
Novel Mixed Signal Verification Methodology using complex UDNsRakesh Dama, Ravi Reddy, and Andy Vitek2019Papery2019paper
Novel Paradigm in Formally Verifying Complex AlgorithmsM Achutha KiranKumar V, Disha Puri, Mohit Choradia, Paras Gupta2021Papery2021paper
Novel Test Case Design Techniques for Logical Specifications of Safety Critical Systems Software in Aerial VehicleLakshmi KVNS and Sanjeev Kumar2017Papery2017paper
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Novelty-Driven Verification: Using Machine Learning to Identify Novel Stimuli and Close CoverageTim Blackmore, Rhys Hodson, Sebastian Schaal2021Papery2021paper
NVMe Development and Debug for a 16 x Multicore SystemSoummya Mallick, Raj Mathur, Arindam Guha, and Frank Schirrmeister2019Papery2019paper
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On Analysis of RDC issues for identifying reset tree design bugs and further strategies for noiseFarhad Ahmed, Lyle Benson, Manish Bhati2024Postery2024poster
On analysis of RDC issues for identifying reset tree design bugs and further strategies for noise reductionFarhad Ahmed, Lyle Benson, Manish Bhati2024Papery2024paper
On Verification Coverage Metrics in Formal Verification and Speeding Verification Closure with UCIS Coverage Interoperability StandardRajeev Ranjan, PhD, Ross Weber, and Ziyad Hanna, PhD2013Papery2013paper
One Compile to Rule Them All: An Elegant Solution for OVM/UVM Testbench TopologiesGalen Blake and Steve Chappell2013Papery2013paper
One Compile to Rule them All: An elegant solution for OVM/UVM Testbench TopologiesGalen Blake and Steve Chappell2013Presentationy2013presentation
One Stop Solution for DFT Register Modelling in UVMRui Huang2017Papery2017paper
One Stop Solution of DFT Register Modelling in UVMRui Huang2017Presentationy2017presentation
Open-source Framework for Co-emulation using PYNQIoana-Cătălina Cristea, Dragoș Dospinescu2021Papery2021paper
Optimal Usage of the Computer Farm for Regression TestingDaniel Hansson and Patrik Granath2016Papery2016paper
Optimal Usage of the Computer Farm for Regression TestingDaniel Hansson and Patrik Granath2016Presentationy2016presentation
Optimizing Area and Power Using Formal MethodAlan Carlin, Chris Komar Cadence, and Anuj Singhania2011Papery2011paper
Optimizing Random Test Constraints Using Machine Learning AlgorithmsStan Sokorac2017Papery2017paper
Optimizing Random Test Constraints Using Machine Learning AlgorithmsStan Sokorac2017Presentationy2017presentation
Optimizing Turnaround Times In A CI Flow Using a Scheduler ImplementationRobert Strong2022Presentationy2022presentation
Optimizing Turnaround Times in a Continuous Integration Flow Using a Scheduler Based ImplementationRobert Strong2022Papery2022paper
OS aware IP Development MethodologyHyunjae Woo, Woojoo Kim, Youngsik Kim, and Seonil Brian Choi2019Presentationy2019presentation
OS-aware IP Development MethodologyHyunjae Woo, Woojoo Kim, Youngsik Kim, and Seonil Brian Choi2019Papery2019paper
OS-aware Performance and Power Analysis MethodologyHyunjae Woo, HojinJo, Woojoo Kim, and Seonil Brian Choi2020Presentationy2020presentation
Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath ScoreboardsBochra El-Meray and Jörg Müller2013Presentationy2013presentation
Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath ScoreboardsBochra Elmaray and Joerg Mueller2013Papery2013paper
OVM & UVM Techniques for On-the-fly ResetMuralidhara Ramalingaiah and Boobalan Anantharaman2012Papery2012paper
OVM & UVM Techniques for On-the-fly ResetMuralidhara Ramalingaiah and Boobalan Anantharaman2012Presentationy2012presentation
OVM & UVM Techniques for Terminating TestsClifford E. Cummings and Tom Fitzpatrick2011Papery2011paper
OVM TO UVM DEFINITIVE GUIDE PART 1Adiel Khan, Justin Refice, and Warren Stapleton2013Papery2013paper
PA-APIs: Looking beyond power intent specification formatsAmit Srivastava and Awashesh Kumar2015Papery2015paper
PA-APIs: Looking beyond power intent specification formatsAmit Srivastava and Awashesh Kumar2015Postery2015poster
Panning for Gold in RTL Using TransactionsRich Edelman, Raghu Ardeishar, Akshay Sarup, and Suman Kasam2011Papery2011paper
Parallel Computing for Functional Verification and Compute Farms: The Holy MatrimonyAmit Sharma, Shekhar Basavanna, and Srinivasan Venkataramanan2011Papery2011paper
Parameter Passing From SystemVerilog to SystemCBishnupriya Bhattacharya, Samik Das, Zhiting Duan, Chandra Sekhar Katuri, and Pradipta Laha2015Presentationy2015presentation
Parameter Passing from SystemVerilog to SystemC for Highly Configurable Mixed-Language DesignsBishnupriya Bhattacharya, Samik Das, Zhiting Duan, Chandra Sekhar Katuri, and Pradipta Laha2015Papery2015paper
Parameterize Like a Pro: Handling Parameterized RTL in your UVM TestbenchJeff Montesano2020Presentationy2020presentation
Parameterized and Re-usable Jitter Model for Serial and Parallel InterfacesAmlan Chakrabarti and Malathi Chikkanna2015Papery2015paper
Parameterized and Re-usable Jitter Model for Serial and Parallel InterfacesMalathi Chikkanna and Amlan Chakrabarti2015Presentationy2015presentation
Parameters and OVM — Can’t They Just Get Along?Bryan Ramirez and Michael Horn2011Papery2011paper
Parameters, UVM, Coverage & Emulation – Take Two and Call Me in the MorningMichael Horn, Bryan Ramirez, and Hans van der Schoot2016Papery2016paper
Path-based UPF Strategies: Optimally Manage Power on your DesignsProgyna Khondkar2022Presentationy2022presentation
Path-Based UPF Strategies: Optimally Manage Power on Your DesignsProgyna Khondkar2022Papery2022paper
Pay Me Now or Pay Me Later Exploring the Implementation and Analysis Cost Trade-Offs of Coverage Model DesignPaul Graykowski and Andrew Piziali2011Papery2011paper
Plan & Metric Driven Mixed-Signal Verification for Medical DevicesGregg Sarkinen2011Papery2011paper
Plugging the Holes: SystemC and VHDL Functional Coverage MethodologyPankaj Singh and Gaurav Kumar Verma2011Papery2011paper
Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication bridgeAndrei Vintila and Ionut Tolea2019Presentationy2019presentation
Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication bridgeAndrei Vintila and Ionut Tolea2019Papery2019paper
Portable Stimulus Models for C/SystemC, UVM and EmulationMike Andrews and Boris Hristov2015Papery2015paper
Portable Stimulus Models for C/SystemC, UVM and EmulationMike Andrews and Boris Hristov2015Presentationy2015presentation
Portable Stimulus Standard Update: PSS in the Real WorldAccellera Portable Stimulus Working Group2022Presentationy2022presentation
Portable Stimulus Standard: The Promises and Pitfalls of Early AdoptionMike Bartley2019Presentationy2019presentation
Portable Stimulus Standard’s Hardware Software Interface (HSI) to validate 4G 5G Forward Error Correction Encoder/Decoder IP in Emulation SiliconJoydeep Maitra, Suresh Vasu, Nithin Venkatesh, Suhas Reddy, Luis Campos, Vinit Shenoy2022Presentationy2022presentation
Portable Stimulus TutorialAdnan Hamid, Tom Fitzpatrick, Matthew Ballance, Sergey Khaikin, Prabhat Gupta2024Presentationy2024presentation
Portable Stimulus vs Formal vs UVM: A Comparative Analysis of Verification Methodologies Throughout the Life of an IP BlockGaurav Bhatnagar2018Presentationy2018presentation
Portable Stimulus vs Formal vs UVM: A Comparative Analysis of Verification Methodologies Throughout the Life of an IP BlockGaurav Bhatnagar and David Brownell2018Papery2018paper
Portable Stimulus: What’s Coming in 1.1 and What it Means For YouPortable Stimulus Working Group2020Presentationy2020presentation
Portable Test and Stimulus: The Next Level of Verification Productivity is HereAccellera Portable Stimulus Working Group2018Presentationy2018presentation
Post Silicon Performance Validation Using PSSDayoung Kim, Jaehun Lee, Daeseo Cha, Phu L. Huynh, and Jake Kim2020Presentationy2020presentation
Post-Silicon Performance Validation Using PSSDayoung Kim, Jaehun Lee, and Daeseo Cha2020Papery2020paper
Power Aware CDC Analysis at Top Level Using SOC Abstract FlowVenkatesh Ranga and Pramod Rajan K S2017Postery2017poster
Power Aware CDC Analysis at Top Level Using SOC Abstract FlowVenkatesh Ranga and Pramod Rajan K S2017Papery2017paper
Power Aware Verification Strategy for SoCsBoobalan Anantharaman and Arunkumar Narayanamurthy2013Presentationy2013presentation
Power Aware Verification Strategy for SoCsBoobalan Anantharaman and Arunkumar Narayanamurthy2013Papery2013paper
Power estimation – what to expect what not to expectPrakash Parikh2014Presentationy2014presentation
Power Estimation Techniques – what to expect, what not to expectPrakash Parikh2014Papery2014paper
Power Management Verification for SOC ICsDavid Akselrod, Alex Miretsky, Sergey Golubkov, Pearl Liu, Afshin Parvaresh, Shu Wang, and Feng Yan2016Papery2016paper
Power Management Verification for SoC ICsDavid Akselrod, Alex Miretsky, Sergey Golubkov, Pearl Liu, Afshin Parvaresh, Shu Wang, and Feng Yan2016Postery2016poster
Power models & Terminal Boundary: Get your IP Ready for Low PowerProgyna K., William W., Phil G., Brandon S.2023Presentationy2023presentation
Power Models and Terminal Boundary: Get your IP Ready for Low PowerProgyna Khondkar, William Winkeler, Phil Giangarra and Brandon Skaggs2023Papery2023paper
Power State to PST Conversion: Simplifying static analysis and debugging of power aware designsMadhur Bhargava and Pankaj Gairola2016Postery2016poster
Power State to PST Conversion: Simplifying static analysis and debugging of power aware designsMadhur Bhargava and Pankaj Gairola2016Papery2016paper
Practical Applications of the Portable Testing and Stimulus Standard (PSS)Sharon Rosenberg2019Presentationy2019presentation
Practical Approach Using a Formal App to Detect X-Optimism-Related RTL BugsShuqing Zhao, Shan Yan, and Yafang Feng2014Papery2014paper
Practical Approach Using a Formal App to Detect X-Optimism-Related RTL BugsShuqing Zhao, Shan Yan, and Yafang Feng2014Presentationy2014presentation
Practical Asynchronous SystemVerilog AssertionsDoug Smith2024Papery2024paper
Practical Asynchronous SystemVerilog AssertionsDoug Smith2024Presentationy2024presentation
Practical Considerations for Real Valued Modeling of High Performance Analog SystemsDushyant Juneja, Siddharth Prabhu, and Syam Veluri2016Papery2016paper
Practical Considerations for Real Valued Modeling of High Performance Analog SystemsDushyant Juneja, Siddharth Prabhu, and Syam Veluri2016Papery2016paper
Practical Considerations for Real Valued Modeling of High Performance Analog SystemsDushyant Juneja, Siddharth Prabhu, and Syam Veluri2016Presentationy2016presentation
Practical Considerations for Real Valued Modeling of High Performance Analog SystemsDushyant Juneja, Siddharth Prabhu, and Syam Veluri2016Postery2016poster
Practical Issues in Implementing Fast and Accurate SystemC-Constructed Virtual Platform SimulationYu-Fu Yeh and Chung-Yang (Ric) Huang2013Presentationy2013presentation
Practical Issues in Implementing Fast and Accurate SystemC-Constructed Virtual Platform SimulationYu-Fu Yeh and Chung-Yang (Ric) Huang2013Papery2013paper
Practical Scheme to Enhance Verification Turn-Around-Time by Using Reusable Harness Interface (RHI)Jong pil Jung, Hyunju Lee, Jaejin Ha, and Yonghee Im2018Presentationy2018presentation
Practical Scheme to Enhance Verification Turn-Around-Time by Using Reusable Harness Interface (RHI)Jongpil Jung, Hyunju Lee, Jaejin Ha, and Yonghee Im2018Papery2018paper
Practical Schemes to Enhance Vertical, Horizontal and Platform Reusability of Verification Components in AMBA Based SoC DesignIeryung Park, Nara Cho and Yonghee Im2017Presentationy2017presentation
PRACTICAL SCHEMES TO ENHANCE VERTICAL, HORIZONTAL AND PLATFORM REUSABILITY OF VERIFICATION COMPONENTS IN AMBA BASED SOC DESIGNIeryung Park, Nara Cho, and Yonghee Im2017Papery2017paper
Pragmatic Formal Verification of Sequential Error Detection and Correction Codes (ECCs) used in Safety-Critical DesignAman Kumar2023Postery2023poster
Pragmatic Formal Verification of Sequential Error Detection and Correction Codes (ECCs) used in Safety-Critical DesignAman Kumar2023Papery2023paper
Pragmatic Verification Reuse in a Vertical WorldMark Litterick2013Papery2013paper
Pragmatic Verification Reuse in a Vertical WorldMark Litterick2013Postery2013poster
Pre-Silicon Power Management Verification of Complex SOCs: Experiences with Intel MoorefieldRajeev Muralidhar, Nivedha Krishnakumar, Bryan Morgan, Robert Karas, Billy Dennie, and Neil Rosenberg2016Papery2016paper
Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads using Hybrid System Level Emulation SoC PlatformNeeraj Gupta, Reddaiah Yedoti, Dixit Sethi, and Sarvesh Kumar Pandey2022Postery2022poster
Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads Using Hybrid System Level Emulation SoC PlatformNeeraj Gupta, Reddaiah Yedoti, Dixit Sethi, and Sarvesh Kumar Pandey2022Papery2022paper
Predicting Bad CommitsChristian Graber, Daniel Hansson, and Adam Tornhill2019Postery2019poster
Preventing Chip-Killing Glitches on CDC Paths with Automated Formal AnalysisJackie Hsiung, Ashish Hari, and Sulabh Kumar Khare2018Papery2018paper
Preventing Chip-Killing Glitches on CDC Paths with Automated Formal AnalysisJackie Hsiung, Sulabh Kumar Khare, and Ashish Hari2018Postery2018poster
Preventing Glitch Nightmares on CDC Paths: The Three WitchesJian-Hua Yan, Ping Yeung, Stewart Li, Sulabh-Kumar Khare2021Papery2021paper
Primary, Anonymous, or What? The Destiny of Ports from Design Top that Ultimately are Driven from Off-Chip…Brandon Skaggs, Progyna Khondkar2021Papery2021paper
Problematic Bi-Directional Port Connections: How Well is Your Simulator Filling the UPF LRM Void?Brandon Skaggs2022Presentationy2022presentation
Problematic Bi-Directional Port Connections: How Well Is Your Simulator Filling the UPF LRM Void?Brandon Skaggs2022Papery2022paper
Product Life Cycle of an Interconnect Bus: A Portable Stimulus Methodology for Performance Modeling, Design Verification, and Post-Silicon ValidationGaurav Bhatnagar and Courtney Fricano2019Papery2019paper
Product Life Cycle of Interconnect Bus:A Portable Stimulus Methodology for Performance Modeling, Design Verification, and Post-Silicon ValidationGaurav Bhatnagar and Courtney Fricano2019Presentationy2019presentation
Programming Model Inheritance and Sequence ReuseAji Varghese2016Papery2016paper
Proper Probing: Flexibility on the TLM LevelGergö Vékony2018Postery2018poster
Proper probing: Flexibility on the TLM levelGergő V kony2018Papery2018paper
Property-Driven Development of a RISC-V CPUTobias Ludwig, Michael Schwarz, Joakim Urdahl, Lucas Deutschmann, Salaheddin Hetalani, Dominik Stoffel, and Wolfgang Kunz2019Papery2019paper
Property-Driven Development of a RISC-V CPUTobias Ludwig2019Presentationy2019presentation
Proven Strategies for Better Verification Planning: DVCon 2022 WorkshopPaul Marriott, Jeff Vance, and Jeff McNeal 2022Presentationy2022presentation
PSL/SVA Assertions in SPICEDonald O’Riordan and Prabal Bhattacharya2012Papery2012paper
PSS Action Sequence Modeling Using Machine LearningMoonki Jang2022Presentationy2022presentation
PSS Action Sequence Modeling Using Machine LearningMoonki Jang, Myeongwhan Hyun, Hyunkyu Ahn, Jiwoong Kim, Yunwhan Kim, and Dongjoo Kim2022Papery2022paper
PSS: The Promises and Pitfalls of Early AdoptionMike Bartley2019Papery2019paper
Pushbutton Complete IP GenerationFreddy Nunez2023Presentationy2023presentation
PyRDV: a Python-based solution to the requirements traceability problemFernando Gabriel Orge2024Papery2024paper
PyRDV: a Python-based solution to the requirements traceability problemFernando Gabriel Orge, 2024Presentationy2024presentation
Qualification of Formal Properties for Productive Automotive Microcontroller VerificationHolger Busch2013Papery2013paper
Quantification of Formal Properties for Productive Automotive Microcontroller VerificationHolger Busch2013Presentationy2013presentation
Raising the level of Formal Signoff with End to End Checking MethodologyPing Yeung, Arun Khurana, Dhruv Gupta, Ashutosh Prasad, Achin Mittal2022Presentationy2022presentation
Raising the Level of Formal Signoff with End-to-End Checking MethodologyPing Yeung, Arun Khurana, Dhruv Gupta, Ashutosh Prasad, and Achin Mittal2022Papery2022paper
Random Directed Low Power Coverage Methodology: A Smart Approach to Power Aware Verification ClosureAwashesh Kumar and Madhur Bhargava2017Papery2017paper
Random Directed Low Power Coverage Methodology:(A Smart Approach to Power Aware Verification Closure)Awashesh Kumar and Madhur Bhargava2017Presentationy2017presentation
Random Testcase Generation and Verification of Debug Unit for a RISC-V Processor CoreSneha Mishra, Lu Hao, Ajay Sharma, Afshan Anjum, Lucia Franco, Sourav Roy, Jeff Scott2023Papery2023paper
Random Testcase Generation and Verification of Debug Unit for a RISC-V Processor CoreSneha Mishra, Lu Hao, Ajay Sharma, Afshan Anjum, Lucia Franco, Sourav Roy, Jeff Scott2023Presentationy2023presentation
Randomizing UVM Config DB ParametersJeremy Ridgeway2015Papery2015paper
Randomizing UVM Config DB ParametersJeremy Ridgeway2015Postery2015poster
Real Number ModelingTom Cole, Wes Queen, Mark Kautzman, and Dan Romaine2013Papery2013paper
Real Number Modeling Enables Fast, Accurate Functional VerificationWes Queen, Tom Cole, and Dan Romaine2013Postery2013poster
Real Number Modeling for RF CircuitsJakub Dudek, Joshua Nekl and Keith O’Donoghue2017Presentationy2017presentation
Real Number Modeling of RF CircuitsJakub Dudek, Joshua Nekl, and Keith O’Donoghue2017Papery2017paper
Recipe for bug hunting: Tips & Tricks for Low power silicon sign-offMonika Rawat, Dipankar Narendra Arya, Anuroop R, Deepmala Sachan2021Papery2021paper
RegAnalyzer – A tool for programming analysis and debug for verification and validationSuresh Vasu2020Postery2020poster
RegAnalyzer -A tool for programming analysis and debug for verification and validationSuresh Vasu2020Papery2020paper
Register This! Experiences Applying UVM RegistersSharon Rosenberg2012Papery2012paper
Register This! Experiences Applying UVM RegistersKathleen Meade2012Presentationy2012presentation
Register Verification: Do We Have Reliable Specification?NamDo Kim, Junhyuk Park, Byeong Min, and Wesley Park2013Postery2013poster
Register Verification: Do We Have Reliable Specification?NamDo Kim, Junhyuk Park, Byeong Min, and Wesley Park2013Papery2013paper
Registering the standard: Migrating to the UVM_REG code baseSachin Patel, Amit Sharma, and Adiel Khan2012Papery2012paper
Regressions in the 21st Century – Tools for Global SurveillanceDavid Crutchfield, Tushar Grupta, Frank Roberts, and Venkataramanan Srinivasan2016Papery2016paper
Regressions in the 21st Century – Tools for Global SurveillanceDavid Crutchfield, Tushar Grupta, Frank Roberts, and Venkataramanan Srinivasan2016Presentationy2016presentation
Regvue Modern Hardware/Software Interface (HSI) DocumentationRob Donnelly, Josh Geden2023Papery2023paper
Regvue Modern Hardware/Software Interface DocumentationRob Donnelly, Josh Geden2023Presentationy2023presentation
Relieving the Parameterized Coverage HeadacheChristine Lovett, Bryan Ramirez, Stacey Secatch, and Michael Horn2012Papery2012paper
Relieving the Parameterized Coverage HeadacheChristine Lovett2012Presentationy2012presentation
Requirements Recognition for Verification IP Design Using Large Language ModelsSiarhei Zalivaka2024Presentationy2024presentation
Requirements Recognition for Verification IP Design Using Large Language ModelsS. S. Zalivaka2024Papery2024paper
Reset and Initialization, the Good, the Bad and the UglyPing Yeung and Kaowen Liu2016Papery2016paper
Reset and Initialization, the Good, the Bad and the UglyPing Yeung and Kaowen Liu2016Postery2016poster
Reset and Initialization: the Good, the Bad and the UglyPing Yeung and Kaowen Liu2016Presentationy2016presentation
Reset Domain Crossing for designs with set-reset flopsAbdul Moyeen, Inayat Ali2021Papery2021paper
Resetting Anytime with the Cadence UVM Reset PackageCourtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm2014Papery2014paper
Resetting Anytime with the Cadence UVM Reset PackageCourtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm2014Postery2014poster
Results Checking Strategies with Portable StimulusTom Fitzpatrick and Matthew Ballance2019Papery2019paper
Results Checking Strategies with Portable StimulusTom Fitzpatrick and Matthew Balance2019Presentationy2019presentation
Reusable System-Level Power-Aware IP Modeling ApproachAntonio Genov, Francois Verdier, and Loic Leconte2022Papery2022paper
REUSABLE UPF: Transitioning from RTL to Gate Level VerificationDurgesh Prasad, Jitesh Bansal, and Madhur Bhargava2018Postery2018poster
REUSABLE UPF: Transitioning from RTL to Gate Level VerificationDurgesh Prasad, Jitesh Bansal, and Madhur Bhargava2018Papery2018paper
Reuse C test and UVM sequence utilizing TLM2, register model and interrupt handlerLiu HongLiang and Gao Teng-Fei2015Papery2015paper
Reuse C test and UVM sequence utilizing TLM2, register model and interrupt handlerHongLiang Liu and Teng-Fei Gao2015Presentationy2015presentation
Reusing Testbench Components in a Hybrid Simulation-Formal EnvironmentRitero Chi and Xiaolin Chen2010Papery2010paper
Reusing UVM Test Benches in a Cycle SimulatorKristina Hager, Carter Alvord, Andrew Lynch, and Umer Yousafzai2014Presentationy2014presentation
Reusing UVM Testbenches in a Cycle SimulatorKristina Hager, Andrew Lynch, Umer Yousafzai, and Carter Alvord2014Papery2014paper
Richard Weber, Jamsheed Agahi, Josh Rensch, Eric SherkPratik Parvati2023Presentationy2023presentation
RISC-V Core Verification: A New Normal in Verification TechniquesAdnan Hamid, John Sotiropoulos2024Presentationy2024presentation
RISC-V Processor Verification: Case StudyAdi Maymon, Shay Harari, Lee Moore, Larry Lapides2021Papery2021paper
RISC-V Security Verification using Perspec/Portable StimulusJunxia Wang, Siyan. Li, Leven. Li, A T S Prasad, Kiran Kumar Palla, Yung Cheng Chen2023Papery2023paper
RISC-V Testing – status and current state of the artJon Taylor2024Papery2024paper
RISC-V Testing Status and current state of the artJon Taylor2024Presentationy2024presentation
Robust Physical Layer IP Verification for DDR4-3DS Memory by Channel ModellingAditya S Kumar, Gowdra Bomanna Chethan, Shivani Maurya, Kumar Rajeev Ranjan, Anil Deshpande, Somasunder Kattepura Sreenath2021Papery2021paper
Rockin’ the Polymorphism for an Elegant UVM Testbench ArchitectureMike Baird and Frank Verhoorn2018Postery2018poster
Rockin’ the polymorphism for an Elegant UVM testbench Architecture for a Scalable, Highly Configurable, Extensible DUTMichael Baird and Frank Verhoorn2018Papery2018paper
Role of AI in SoC Performance Verification(PV)Sharada Vajja, Raghu Alamuri, Saksham Mehra2024Postery2024poster
Rolling the dice with random instructions is the safe bet on RISC-V verificationSimon Davidmann and Lee Moore, Richard Ho and Tao Liu, and Doug Letcher and Aimee Sutton2020Presentationy2020presentation
RTL Transformation Methods to Achieve Order of Magnitude TAT Improvement in VLSI DesignAshfaq Khan, Shuhui Lin, Dan Standring, Adam Cajiao Campos, Soowan Suh, Satish Venkatesan2024Postery2024poster
RTL Transformation Methods to Achieve Order of Magnitude TAT Improvement in VLSI DesignAshfaq Khan, Shuhui Lin, Dan Standring, Adam Cajiao Campos, Soowan Suh, Satish Venkatesan2024Papery2024paper
Run-time Configuration of a Verification Environment – A Novel Use of the OVM/UVM Analysis PatternPaul Marriott and Mark Ronan2013Papery2013paper
Run-Time Configuration of a Verification Environment: A Novel Use of the OVM/UVM Analysis PatternPaul Marriott2013Postery2013poster
Run-Time Phasing in UVM: Ready for the Big Time or Dead in the Water?John Aynsley2015Presentationy2015presentation
Run-Time Phasing in UVM: Ready for the Big Time or Dead in the Water?John Aynsley2015Papery2015paper
Safety and Security Aware Pre-silicon Concurrent Software Development and VerificationFrank Schirrmeister, Joe Fabbre, and Max Hinson2020Papery2020paper
Safety and Security Aware Pre-silicon Concurrent Software Development and VerificationFrank Schirrmeister, Joe Fabbre, and Max Hinson2020Postery2020poster
Saving and Restoring Simulation Methodology using UVM Factory Overriding to Reduce Simulation Turnaround TimeAhhyung Shin, Yungi Um, Youngsik Kim, and Seonil Brian Choi2020Papery2020paper
Saving and Restoring Simulation Methodology using UVM Factory Overriding to Reduce Simulation Turnaround TimeAhhyung Shin, Yungi Um, Youngsik Kim, and Seonil Brian Choi2020Postery2020poster
Scalable Functional Verification using Portable Stimulus StandardSantosh Kumar, Yogish Kumar Raja, Geetika Agrawal, Karthikeyan S, Arjun Ashok V, Tommy Brunansky2024Papery2024paper
Scalable Functional Verification using PSSSantosh Kumar, Yogish Kumar Raja, Geetika Agrawal, Karthikeyan S, Arjun Ashok V, Tommy Brunansky2024Postery2024poster
Scalable Reset Domain Crossing Verification Using Hierarchical Data ModelSoumya Palit, Anwesha Choudhury, and Kurt Takara2020Presentationy2020presentation
SCALABLE, RE-USABLE UVM DMS AMS BASED VERIFICATION METHODOLOGY FOR MIXED-SIGNAL SOCSNilesh Sonara, Noorulla Mohammad, Poonam Singh, David Stoops, Joseph Fernando, and Kartik Sudarshana2019Papery2019paper
Scalable, Re-usable UVM DMS AMS based Verification Methodology for Mixed-Signal SOCsNilesh Sonara, Noorulla Mohammad, Poonam Singh, David Stoops, Joseph Fernando, and Kartik Sudarshana2019Presentationy2019presentation
Second Generation Completeness Analysis of Formal Assertions on Compatibility of RISC-V CoresWayne Yun2020Presentationy2020presentation
Security Verification using Perspec/Portable StimulusJunxia Wang, Leven Li, Siyan Li, A T S Prasad, Kiran Kumar Palla, Yung Cheng Chen2023Presentationy2023presentation
Security Verification Using Portable Stimulus Driven Test Suite SynthesisAdnan Hamid and David Kelf2020Presentationy2020presentation
See the Forest for the Trees – How to Effectively Model and Randomize a Directed Rooted Tree StructureHarry Duque and Lars Viklund2023Papery2023paper
See the Forest for the Trees – How to Effectively Model and Randomize a DRT StructureHarry Duque, Lars Viklund2023Presentationy2023presentation
Sequence, Sequence on the Wall – Who’s the Fairest of Them All?Rich Edelman and Raghu Ardeishar2013Papery2013paper
Seven Separate Sequence Styles Speed Stimulus ScenariosMark Peryer2013Papery2013paper
Seven Separate Sequence Styles Speed Stimulus ScenariosMark Peryer2013Postery2013poster
SGEN2: Evolution of a Sequence-Based Stimulus Engine for Micro-Processor VerificationStephan Bourduas and Christopher Mikulis2018Postery2018poster
SGEN2: Evolution of a sequence-based stimulus engine for micro-processor verification.Stephan Bourduas and Chris Mikulis2018Papery2018paper
Shaping Formal Traces without Constraints: A Case Study in Closing Code Coverage on a Crypto Engine Using Formal VerificationDavid N. Goldberg, Adriana Maggiore, and David J. Simpson2012Papery2012paper
Shaping Formal Traces without Constraints: A Case Study in Closing Code Coverage on a Crypto Engine using Formal VerificationDavid N. Goldberg, Adriana Maggiore, and David J. Simpson2012Presentationy2012presentation
Sharing Generic Class Libraries in SystemVerilog Makes Coding Fun AgainKeisuke Shimizu2014Papery2014paper
Sharing Generic Class Libraries in SystemVerilog Makes Coding Fun AgainKeisuke Shimizu2014Presentationy2014presentation
Shift-Left on Timing Constraints Verification: Beyond Typical Front-End ExecutionVineeth B, Deepmala Sachan, Ritesh Jain2024Postery2024poster
Shift-Left on Timing Constraints Verification: Beyond Typical Front-End ExecutionVineeth B, Deepmala Sachan, Ritesh Jain2024Papery2024paper
Sign-off with Bounded Formal Verification ProofsNamDo Kim, Junhyuk Park, HarGovind Singh, and Vigyan Singhal2014Papery2014paper
Sign-off with Bounded Formal Verification ProofsNAMDO KIM, JUNHYUK PARK, HARGOVIND SINGH, and VIGYAN SINGHAL2014Presentationy2014presentation
Simple & Rapid Design Verification using SystemVerilog Testbench on Intel’s Next-Generation MicroprocessorThomas Alsop, Wayne Clift, Luke Hood, and Jeff Gray2011Papery2011paper
Simpler Register ModelSanjeev Singh2018Presentationy2018presentation
Simpler Register Model Package for UVM Testbenches.Sanjeev Singh2018Papery2018paper
Simulation Acceleration with ZeBu to Speed IP and Platform VerificationHillel Miller and Wei-Hua Han2019Presentationy2019presentation
Simulation Runtime Optimization of Constrained Random Verification using Machine Learning AlgorithmsSarath Mohan Ambalakkat and Eldon Nelson2019Papery2019paper
Simulation Runtime Optimization of Constrained Random Verification using Machine Learning AlgorithmsSarath Mohan Ambalakkat M.S. and Eldon Nelson M.S. P.E.2019Presentationy2019presentation
Single Source Register Sequencing Toolkit and Methodology for FW and Verification Co-DevelopmentJosh Loo, Anthony Cabrera, Kiel Boyle, and Scott R. Nelson2020Presentationy2020presentation
Slaying the UVM Reuse DragonMike Baird and Bob Oden2016Postery2016poster
Slaying the UVM Reuse Dragon Issues and Strategies for Achieving UVM ReuseMike Baird and Bob Oden2016Papery2016paper
Smart Formal for Scalable VerificationAshish Darbari2019Presentationy2019presentation
Smart Formal for Scalable VerificationAshish Darbari2019Papery2019paper
So There’s My Bug! Debugging Universal Verification Methodology (UVM) EnvironmentsMike Floyd2011Papery2011paper
So you think you have good stimulus: System-level distributed metrics analysis and resultsAndreas Meyer2014Papery2014paper
So you think you have good stimulus: System-level distributed metrics analysis and resultsAndreas Meyer2014Postery2014poster
SoC Firmware Debugging Tracer in Emulation PlatformKubendra Kumbar, Sandeep Vallabhaneni, Ken Joseph Kannampuzha, Hojun Shim, and Byung Chul Yoo2020Papery2020paper
SoC Firmware Debugging Tracer in Emulation PlatformKubendra Kumbar, Sandeep Vallabhaneni, Ken Joseph Kannampuzha, Hojun Shim, and Byung Chul Yoo2020Postery2020poster
SoC Verification of Analog IP Integration through Automated, Formal-Based, Rule-driven Spec GenerationMurugesh Palaniswamy, Ravi Kalyanaraman, Gargi Sharma, and Bharat Baliga-Savel2018Papery2018paper
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SoC Verification Speed – More is BetterFernanda Braga, John Rose, William Winkeler, Sharon Rosenberg, and Frank Schirrmeister2018Presentationy2018presentation
SoC Verification using OVM : Leveraging OVM Constructs to Perform Processor Centric VerificationCedric Macadangdang and Paul Yue2012Papery2012paper
Soft Constraints in SV: Semantics and ChallengesMark Strickland2012Presentationy2012presentation
Soft Constraints in SystemVerilog Semantics and ChallengesMark Strickland, Joseph Hanli Zhang, Jason Chen, Dhiraj Goswami, and Alex Wakefield2012Papery2012paper
Solving Next Generation IP ConfigurabilityDavid Murray and Simon Rance2014Presentationy2014presentation
Solving Next Generation IP ConfigurabilityDavid Murray and Simon Rance2014Papery2014paper
Source Control…$100 Regression Script…$500 Good Automated Release Steps…$PricelessJeffrey Wren2010Papery2010paper
Specification Driven Analog and Mixed-Signal VerificationHenry Chang and Ken Kundert2015Papery2015paper
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Standard Regression Testing Does not WorkDaniel Hansson2015Papery2015paper
Standard Regression Testing Does Not WorkDaniel Hansson2015Presentationy2015presentation
Static power-management verification of Cypress’s PSoC® Programmable System-on-Chip for embedded systemsJohnie Au and Prapanna Tiwari2010Papery2010paper
Static Sign-Off Best Practices Learnings and Experiences from Industry Use CasesVikas Sachdeva2023Presentationy2023presentation
Statically Dynamic or Dynamically Static? Exploring the power of classes and enumerations in SystemVerilog Assertions for reusability and scalabilitySachin Scaria, Sreenu Yerabolu, and Don Mills2017Presentationy2017presentation
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Stepwise Refinement and Reuse: The Key to ESLAshok B. Mehta, Mark Glasser, Shabtay Matalon, and Dan Gardner2011Papery2011paper
Stimulating Scenarios in the OVM and VMMJL Gray and Scott Roland2010Papery2010paper
Strategies and Methods of using PSS2.0 high level modeling techniques to augment UVM verificationSwami Venkatesan2021Papery2021paper
Strategies on CDC False Alarm Rapid LocationJianhua Yan, Meiling Qi, Yunyang Song2021Papery2021paper
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Strategy and Environment for SOC Mixed-Signal Validation: A Case StudyErik A McShane and Intel2010Papery2010paper
Streamlining Low Power Verification: From UPF to SignoffGodwin Maben, Santhana Krishnan, Neeraj Mishra, Nishant Patel, Bhaumik Matholia2024Presentationy2024presentation
Sub-design Interface Aware Top Only Static Low Power VerificationHeichang Lee, Nikhil Amin, Jianfeng Liu, Minyoung Mo, and Dongkwan Han2018Papery2018paper
Successes and Challenges of Validation Content ReuseMike Chin, Jonathan Edwards, Josh Pfrimmer, and Hooi Jing Tan2022Postery2022poster
Successive Refinement – An Approach to Decouple Front End and Back End Power IntentSinha Rohit Kumar and Kotha Kavya2022Papery2022paper
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Successive Refinement of UPF Power SwitchesPrabhakar Satya Ayyagari, William G Crocco2023Papery2023paper
Successive Refinement: A Methodology for Incremental Specification of Power IntentAdnan Khan, John Biggs, Eamonn Quigley, and Erich Marschner2015Papery2015paper
Successive Refinement: A Methodology for Incremental Specification of Power IntentAdnan Khan, Eamonn Quigley, John Biggs, and Erich Marschner2015Postery2015poster
Successive Refinement: A Methodology for Incremental Specification of Power IntentAdnan Khan, Eamonn Quigley, John Biggs, and Erich Marschner2015Presentationy2015presentation
Supercharge Your Verification Using Rapid Expression Coverage as the Basis of a MC/DC-Compliant Coverage MethodologyGaurav Kumar Verma and Doug Warmke2014Papery2014paper
Supercharge Your Verification Using Rapid Expression Coverage as the Basis of a MC/DC-Compliant Coverage MethodologyGaurav Kumar Verma and Doug Warmke2014Postery2014poster
Supplementing Simulation of a Microcontroller Flash Memory Subsystem with Formal Veri cationOthmane Bahlous and Abdelouahab Ayari2012Papery2012paper
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Supply network connectivity: An imperative part in low power gate-level verificationGabriel Chidolue, Vinay Singh, and Divyeshkumar Dhanjibhaiv Vora2019Presentationy2019presentation
Supply network connectivity: An imperative part in low power gate-level verificationVinay Kumar Singh and Gabriel Chidolue2019Papery2019paper
Supporting root cause analysis of inaccurate bug prediction based on machine learning – Lessons learned when interweaving training data and source codeOscar Werneman, Markus Borg, Daniel Hansson2021Papery2021paper
Survey of Machine Learning (ML) Applications in Functional Verification (FV)Dan Yu, Harry Foster, Tom Fitzpatrick2023Presentationy2023presentation
SV_LUT: A SystemVerilog Look Up Table package for developing complex AMS Real Number ModelingFNU Farshad, Shafaitul Islam Surush, Simul Barua2024Presentationy2024presentation
SV_LUT: A SystemVerilog Look Up Table package for developing complex AMS Real Number ModelingFNU Farshad, Shafaitul Islam Surush, Simul Barua2024Papery2024paper
SVA Encapsulation in UVM: enabling phase and configuration aware assertionsMark Litterick2013Presentationy2013presentation
SVA Encapsulation in UVM: enabling phase and configuration aware assertionsMark Litterick2013Papery2013paper
Switch the Gears of the UVM Register Package to cruise through the street named “Register Verification”.Amit Sharma, Varun S, Abhisek Verma, and Gaurav Gupta2013Papery2013paper
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Synchronicity: Bringing Order to SystemVerilog/UVM Synchronizing ChaosBryan Morris and P. Eng2019Papery2019paper
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Synthesis of Decoder Tables using Formal Verification ToolsKeerthikumara Devarajegowda, Johannes Schreiner, and Wolfgang Ecker2018Presentationy2018presentation
Synthesis of Decoder Tables using Formal Verification ToolsKeerthikumara Devarajegowda, Johannes Schreiner, and Wolfgang Ecker2018Papery2018paper
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Synthesizable Random Testbench for Multimedia IP VerificationSanggyu Park2021Papery2021paper
Synthetic Traffic based SOC Performance Verification MethodologyJeonggu Lee, Taewon Park, Hyungtae Park, Taeyoung Jeon, Hyunjae Woo, Youngsik Kim, Seonil Brian Choi2024Postery2024poster
Synthetic Traffic based SOC Performance Verification MethodologyJeonggu Lee, Taewon Park, Hyungtae Park, Taeyoung Jeon, Hyunjae Woo, Youngsik Kim, Seonil Brian Choi2024Papery2024paper
SYSTEM LEVEL FAULT INJECTION SIMULATION USING SIMULINKWai Yuen Tang, Marcelo Mizuki, Mitch Norcross, and Fengying Qiao2017Papery2017paper
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System level random verification: How it should be doneMadhusudan Rathi and Ashok Chandran2019Presentationy2019presentation
System Model – A Testbench Library Component Aided for Emulating User InteractionHussain Wadia2019Postery2019poster
System Responsiveness Verification of large Multi Processor System Configurations using Micro Benchmarks and a Multi Level AnalysisDr. Ralf Winkelmann, Edward Chencinski, Hanno Eichelberger, Michael Fee, Carsten Otte, and Christoph Raisch2017Postery2017poster
System Responsiveness Verification of large Multi-Processor System Configurations using Micro-Benchmarks and a Multi-Level AnalysisDr. Ralf Winkelmann, Edward Chencinski, Hanno Eichelberger, Michael Fee, Carsten Otte, Christoph Raisch2017Papery2017paper
System to catch Implementation gotchas in the RTL Restructuring processAnmol Rattan, Satinder Malhi, and Balwinder Soni2016Papery2016paper
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System Verification with MatchLibRussell Klein2022Presentationy2022presentation
System Verilog Assertion Linting: Closing Potentially Critical Verification HolesErik Seligman, Laurence Bisht, and Dmitry Korchemny2012Presentationy2012presentation
System-Level Power Estimation of SSDs under Real Workloads using EmulationSangmin Kim, Kwanghyo Ahn, Changhoon Han, Hyunsik Kim, Jaewoo Im2023Postery2023poster
System-Level Power Estimation of SSDs under Real Workloads using EmulationSangmin Kim, Kwanghyo Ahn, Changhoon Han, Hyunsik Kim, Jaewoo Im2023Papery2023paper
System-Level Random Verification: How it should be doneMadhusudan Rathi and Ashok Chandran2019Papery2019paper
System-Level Security Verification Starts with the Hardware Root of TrustDr. Jason Oberg2019Presentationy2019presentation
Systematic Application of UCIS to Improve the Automation on Verification ClosureChristoph Kuznik, Marcio F. S. Oliveira, Gilles Bertrand Defo, and Wolfgang Mueller2013Presentationy2013presentation
Systematic Application of UCIS to Improve the Automation on Verification ClosureChristoph Kuznik, Marcio F. S. Oliveira, Gilles Bertrand Defo, and Wolfgang Mueller2013Papery2013paper
Systematic Constraint Relaxation (SCR): Hunting for Over Constrained StimulusDebarshi Chatterjee, Spandan Kachhadia, Ismet Bayraktaroglu, Siddhanth Dhodhi2022Presentationy2022presentation
Systematic Constraint Relaxation (SCR): Hunting for Over-Constrained StimulusDebarshi Chatterjee, Spandan Kachhadiya, Ismet Bayraktaroglu, and Siddhanth Dhodhi2022Papery2022paper
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Systematically Achieving CDC Verification Closure based on Coverage Models and Coverage MetricsAshish Hari and Yogesh Badaya2012Papery2012paper
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SystemC FMU for Verification of Advanced Driver Assistance SystemsKeroles Khalil and Magdy A. El-Moursy2019Postery2019poster
SystemC Virtual Prototype: Ride the Earliest Train for Time-To-MarketShweta Saxena and Mahantesh Danagouda2022Presentationy2022presentation
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SystemRDL to PSS BASIC TO PROAnupam Bakshi and Amanjyot Kaur2020Presentationy2020presentation
SystemVerilog Assertion Linting: Closing Potentially Critical Verification HolesLaurence S. Bisht, Dmitry Korchemny, and Erik Seligman2012Papery2012paper
SystemVerilog Assertions for Clock-Domain-Crossing Data PathsDon Mills2015Papery2015paper
SystemVerilog Assertions for Clock-Domain-Crossing Data PathsDon Mills2015Presentationy2015presentation
SystemVerilog Checkers: Key Building Blocks for Verification IPLaurence Bisht, Dmitry Korchemny, and Erik Seligman2012Papery2012paper
SystemVerilog Configurations and Tool Flow Using SCons (an Improved Make)Don Mills and Dillan Mills2020Presentationy2020presentation
SystemVerilog Constraint Layering via Reusable Randomization Policy ClassesJohn Dickol2015Postery2015poster
SystemVerilog Constraint Layering via Reusable Randomization Policy ClassesJohn Dickol2015Papery2015paper
SystemVerilog Constraints: Appreciating What You Forgot In School to Get Better ResultsDave Rich2020Presentationy2020presentation
SystemVerilog Format of Portable StimulusWayne Yun, David Chen, Theta Yang, and Evean Qin2019Postery2019poster
SystemVerilog FrameWorksTM Scoreboard: An Open Source Implementation Using UVMAmbar Sarkar2011Papery2011paper
SystemVerilog Interface Classes – More Useful Than You ThoughtStan Sokorac2016Papery2016paper
SystemVerilog Interface Classes More Useful Than You ThoughtStan Sokorac2016Presentationy2016presentation
SystemVerilog Interface CookbookPaul Egan and Kathleen Otten2014Papery2014paper
SystemVerilog Interface CookbookPaul Egan and Kathleen Otten2014Presentationy2014presentation
SystemVerilog Meets C++: Re-use of Existing C/C++ Models Just Got EasierJohn Aynsley2010Papery2010paper
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SystemVerilog-2009 Enhancements: Priority/Unique/UniqueClifford E. Cummings2010Papery2010paper
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Table-based Functional Coverage Management for SOC ProtocolsShahid Ikram, Jack Perveiler, Isam Akkawi, Jim Ellis, and David Asher2015Papery2015paper
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Tackling Missing Bins: Refining Functional Coverage in SystemVerilog for Deterministic Coverage ClosureJikjoo Lee, Tony Gladvin George, Kihyun Park, Dongkun An, Wooseong Cheong, ByungChul Yoo2024Papery2024paper
Tackling Missing Bins: Refining Functional Coverage in SystemVerilog for Deterministic Coverage ClosureJikjoo Lee, Tony Gladvin George, Kihyun Park, Dongkun An, Wooseong Cheong, ByungChul Yood2024Presentationy2024presentation
Tackling Random Blind Spots with Strategy-Driven GenerationMatthew Ballance2014Postery2014poster
Tackling Random Blind Spots with Strategy-Driven Stimulus GenerationMatthew Ballance2014Papery2014paper
Tackling Register Aliasing Verification Challenges in Complex ASIC DesignShan Yan, Jie Wu, and Jing Li2017Papery2017paper
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Tackling the challenge of simulating multi-rail macros in a power aware flowHimanshu Bhatt, Amol Herlekar, Vikas Grover, and Subhadip Nath2014Papery2014paper
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Tackling the Complexity Problem in Control and Datapath Designs with Formal VerificationRavindra Aneja, Ashish Darbari, Nitin Mhaske, and Per Bjesse2019Presentationy2019presentation
Take AIM! Introducing the Analog Information ModelChuck McClish2023Papery2023paper
Take AIM! Introducing the Analog Information ModelChuck McClish2023Presentationy2023presentation
Taking Real-Value Modeling to the next level: Power-aware verification of mixed-signal designsSubin Thykkoottathil, Jakub Dudek, Nagesh Ranganath, Nimay Shah, and Santosh Singh2019Papery2019paper
Taking RNM Model to the Next Level: Power-Aware Verification of Mixed-Signal DesignsSubin Thykkoottathil, Nagesh Ranganath, Santosh Singh, Jakub Dudek, and Nimay Shah2019Presentationy2019presentation
Taming a Complex UVM EnvironmentManjunath Shetty, and Ramamurthy Gorti2015Postery2015poster
Taming a Complex UVM EnvironmentManjunath Shetty and Ramamurthy Gorti2015Papery2015paper
Taming the beast: A smart generation of Design Attributes (Parameters) for Verification Closure Using SpecmanMeirav Nitzan, Yael Kinderman, and Efrat Gavish2013Papery2013paper
Test driving Portable Stimulus at AMDPrabhat Gupta and Matan Vax2019Presentationy2019presentation
Test Parameter Tuning with Blackbox Optimization: A Simple Yet Effective Way to Improve CoverageQijing Huang*, Hamid Shojaei, Fred Zyda, Azade Nazi, Shobha Vasudevan, Sat Chatterjee, Richard Ho2022Presentationy2022presentation
Test Parameter Tuning with Blackbox Optimization: A Simple Yet Effective Way to Improve CoverageQijing Huang, Hamid Shojaei, Fred Zyda, Azade Nazi, Shobha Vasudevan, Sat Chatterjee, Richard Ho2022Papery2022paper
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Testbench Configuration MantraStephen D’Onofrio2010Papery2010paper
Testing the TestbenchStan Sokorac2016Postery2016poster
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Testpoint Synthesis Using Symbolic SimulationKai-Hui Chang, Yen-Ting Liu and Chris Browy2015Papery2015paper
Testpoint Synthesis Using Symbolic SimulationKai-Hui Chang, Yen-Ting Liu and Chris Browy2015Postery2015poster
The Art of Portable and Reusable UVM Shared System Memory Model Verification Methodology across Multiple Verification PlatformsRoman Wang, Thomas Bodmer, and Beryl Chen2016Papery2016paper
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The beginning of new norm: CDC/RDC constraints signoff through functional simulationSuhas D S, Ponsankar Arumugam, Deepmala Sachan, Ritesh Jain2024Papery2024paper
The beginning of new norm: CDC/RDC constraints signoff through functional simulationSuhas D S, Ponsankar Arumugam, Deepmala Sachan, Ritesh Jain2024Postery2024poster
The Best Verification Strategy You’ve Never Heard OfDavid Aerne, Amir Attarha, Harry Foster, and Kurt Takara2022Presentationy2022presentation
The Big Brain Theory – Visualizing SoC Design & Verification DataGordon Allan2015Postery2015poster
The Big Brain Theory: Visualizing SoC Design & Verification DataGordon Allan2015Papery2015paper
The Case for Low-Power Simulation-to-Implementation Equivalence CheckingHimanshu Bhatt, John Decker, and Hiral Desai2012Papery2012paper
The Case for Low-Power Simulation-to-Implementation Equivalence CheckingHimanshu Bhatt, John Decker, and Hiral Desai2012Presentationy2012presentation
The CHIPS ACT and Its Impact On The Design & Verification MarketsBOB SMITH2023Presentationy2023presentation
The Cost of SoC BugsKen Albin2016Papery2016paper
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The Finer Points of UVM: Tasting Tips for the ConnoisseurJohn Aynsley2013Presentationy2013presentation
The Finer Points of UVM: Tasting Tips for the ConnoisseurJohn Aynsley2013Papery2013paper
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The Importance of Complete Signoff Methodology for Formal VerificationIain Singleton, Mahesh Parmer, and Geogy Jacob2020Presentationy2020presentation
The Importance of Complete Signoff Methodology for Formal VerificationMahesh Parmar, Iain Singleton, Geogy Jacob2020Papery2020paper
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The UPF 2.1 Library Commands: Truly Unifying the Power Specification FormatsAmit Srivastava, Awashesh Kumar, and Vinay Singh2015Postery2015poster
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Timing Coverage: An Approach to Analyzing Performance HolesSurbhi Kalia, Shubhadeep Karmakar, Vikas Makhija, and Apoorva Mathur2019Postery2019poster
Tips for Developing Performance Efficient Verification EnvironmentsPrashanth Srinivasa, Sarath Chandrababu Valapala, and Varun S2012Papery2012paper
Title: Using Test-IP Based Verification Techniques in a UVM EnvironmentVidya Bellippady, Sundar Haran, and Jay O’Donnell2014Papery2014paper
TLM-2.0 in SystemVerilogMark Glasser and Janick Bergeron,2011Papery2011paper
To Infinity And Beyond – Streaming Data Sequences in UVMMark Litterick, Jeff Vance, Jeff Montesano2021Papery2021paper
Tough Verification Challenges: Data Visualization to the RescueShaji Kunjumohamed2016Papery2016paper
Towards Efficient Design Verification – PyUVM & PyVSCDeepak Narayan Gadde, Suruchi Kumari, Aman Kumar2024Postery2024poster
Towards Efficient Design Verification – Constrained Random Verification using PyUVMDeepak Narayan Gadde, Suruchi Kumari, Aman Kumar2024Papery2024paper
Towards Provable Protocol Conformance of Serial Automotive Communication IPJens E. Becker, Oliver Sander, Alexander Klimm, J¨urgen Becker, Katharina Weinberger, and Slava Bulach2011Papery2011paper
Traditional top level static low power rule check 2018Postery2018poster
Traffic Profiling and Performance Instrumentation For On-Chip InterconnectsMark Peryer and Bruce Mathewson2013Papery2013paper
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Transaction Recording Anywhere AnytimeRich Edelman2019Postery2019poster
Transaction-Based Acceleration—Strong Ammunition In Any Verification ArsenalChandrasekhar Poorna, Varun Gupta, and Raj Mathur2011Papery2011paper
Transaction-Level Friending: An Open-Source, Standards-Based Library for Connecting TLM Models in SystemC and SystemVerilogAdam Erickson2013Papery2013paper
Transaction-Level State Charts in UML and SystemC with Zero-Time EvaluationRainer Findenig , Thomas Leitner, Michael Velten, and Wolfgang Ecker2010Papery2010paper
Translating and Adapting to the “real” world: SerDes Mixed Signal Verification using UVMAkhila Madhu Kumar and Karl Herterich2019Papery2019paper
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Transparent SystemC Model Factory for Scripting LanguagesRolf Meyer, Bastian Farkas, Syed Abbas Ali Shah, and Mladen Berekovic2017Papery2017paper
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Transparently Checkpointing Software Test Benches to Improve Productivity of SOC Verification in an Emulation EnvironmentAnkit Garg, K. Suresh, Jeff Evans, Gene Cooperman, and Rohan Garg2018Presentationy2018presentation
Transparently Checkpointing Software Test Benches to Improve Productivity of SoC Verification in an Emulation EnvironmentAnkit Garg, K. Suresh, Gene Cooperman, Rohan Garg, and Jeff Evans2018Papery2018paper
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Tree Data Framework for Code Generation: Application of Generating UVM Testbench for Complex DesignsChenhui Huang, Yu Sun, Divyang Agrawal2023Papery2023paper
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Trends in Functional Verification: A 2016 Industry StudyHarry D. Foster2017Papery2017paper
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Tried and Tested Speedups for SW-driven SoC SimulationGordon Allan2014Presentationy2014presentation
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UCIS APPLICATIONS: IMPROVING VERIFICATION PRODUCTIVITY, SIMULATION THROUGHPUT, AND COVERAGE CLOSURE PROCESSAhmed Yehia2013Papery2013paper
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Unifying Hardware-Assisted Verification and Validation Using UVM and EmulationHemant Sharma, Hans van der Schoot, and Achutam Murarka2013Papery2013paper
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Unique Verification Case Studies of Low Power Mixed Signal ChipsVenkatesh Ranga, Madhusudhan Subramanya, Anand Shirwal, Pramod Rajan K S, and Jeff Goswick2016Papery2016paper
Unique Verification Case Studies of Low Power Mixed Signal ChipsJeff Goswick, Venkatesh Ranga, Madhusudhan Subramanya, Anand Shirwal, and Pramod Rajan K S2016Presentationy2016presentation
Unleashing Portable Stimulus Productivity with a PSS Reuse StrategyM. Ballance2019Papery2019paper
Unleashing Portable Stimulus Productivity with a Reuse StrategyMatthew Balance2019Presentationy2019presentation
Unleashing the Full Power of UPF Power StatesErich Marschner and John Biggs2015Presentationy2015presentation
Unleashing the Full Power of UPF Power StatesErich Marschner and John Biggs2015Papery2015paper
Unleashing the Power of Whisper for block-level verification in high performance RISC-VChenhui Huang, Yu Sun ysun, Joe Rahmeh2024Papery2024paper
Unleashing the Power of Whisper for block-level verification in high performance RISC-V CPUChenhui Huang, Yu Sun, Joe Rahmeh2024Presentationy2024presentation
Unraveling the Complexities of Functional Coverage: An advanced guide to simplify your use modelThomas Ellis and Rohit Jain2018Papery2018paper
Unraveling the Complexities of Functional Coverage: An advanced guide to simplify your use modelThom Ellis and Rohit Jain2018Postery2018poster
Unveil the Mystery of Code Coverage in Low Power Designs (Achieving Power Aware Verification Closure)Madhur Bhargava, Durgesh Prasad, and Pavan Rangudu2018Presentationy2018presentation
Unveil the Mystery of Code Coverage in Low-Power Designs: Achieving Power Aware Verification ClosureMadhur Bhargava, Durgesh Prasad, and Pavan Rangudu2018Papery2018paper
UPF 1.0, UPF 2.0, UPF 2.1, UPF 3.0, and now UPF 3.1: The big Q “Which is the Right Standard for My Design”?Madhur Bhargava2020Presentationy2020presentation
UPF Code Coverage and Corresponding Power Domain Hierarchical Tree for DebuggingShang-Wei Tu, Tom Lin, Archie Feng, and Chen Ya Ping2015Papery2015paper
UPF GENERIC REFERENCES: UNLEASHING THE FULL POTENTIALDurgesh Prasad and Jitesh Bansal2016Papery2016paper
UPF Generic References: Unleashing the Full PotentialJitesh Bansal and Durgesh Prasad2016Presentationy2016presentation
Use of Aliasing in SystemVerilog Verification EnvironmentEvean Qin2020Papery2020paper
Use of Aliasing in SystemVerilog Verification EnvironmentEvean Qin2020Postery2020poster
Use of Portable Stimulus to Verify Task Dispatching and Scheduling Functions in an LTE SwitchAdnan Hamid2017Papery2017paper
User Experiences with the Portable Stimulus StandardTom Fitzpatrick, Prabhat Gupta, Mike Chin2023Presentationy2023presentation
User Experiences with the Portable Stimulus StandardTom Fitzpatrick, Prabhat Gupta, Mike Chin2023Presentationy2023presentation
USF-based FMEDA-driven Functional Safety VerificationFrancesco Lertora, Mangesh Mukundrao Pande, Pete Hardee2024Presentationy2024presentation
Using a modern build system to speed up complex hardware designVarun Koyyalagunta2023Presentationy2023presentation
Using a modern software build system to speed up complex hardware designVarun Koyyalagunta2023Papery2023paper
Using Advanced OOP Concepts To Integrate Templatized Algorithms for Standard Protocols With UVMAnunay Bajaj and Gaurav Chugh2013Papery2013paper
Using Advanced OOP Concepts To Integrate Templatized Algorithms for Standard Protocols With UVMAnunay Bajaj and Gaurav Chugh2013Presentationy2013presentation
Using Assertions in an Active W ay to Design and Verify Interface between Analog and Digital B locksHyunDon Kim, Jiang Long, Wesley Park, ChiHo Cha, JaeBeom Kim, Byeong Min, and KyuMyung Choi2010Papery2010paper
Using Automation to Close the Loop Between Functional Requirements and Their VerificationBrian Craw, David Crutchfield, Martin Oberkoenig, Markus Heigl, and Martin O’Keeffe2018Papery2018paper
Using Automation to Close the Loop Between Functional Requirements and Their VerificationBrian Craw, David Crutchfield, Martin Oberkoenig, Markus Heigl, and Martin O’Keeffe2018Presentationy2018presentation
Using Formal Applications to Create Pristine IPsLee Burns, David Crutchfield, and Hithesh Velkooru2017Presentationy2017presentation
Using Formal Applications to Create Pristine IPsLee Burns, David Crutchfield, Bob Metzler, and Hithesh Velkooru2017Papery2017paper
Using Formal Techniques to Verify SoC Reset SchemesKaowen Liu, Penny Yang, Mark Eslinger, Jeremy Levitt, and Matt Berman2013Postery2013poster
Using Formal Techniques to Verify System on Chip Reset SchemesKaowen Liu, Penny Yang, Jeremy Levitt, Matt Berman, and Mark Eslinger2013Papery2013paper
Using Formal to Exaustively Determine Unsafe Clock Ratios Between Asynchronous BlocksEric Hendrickson, Bill Au, Richard Llaca, and Joe Hupcey III2018Papery2018paper
Using Formal to Exhaustively Determine Unsafe Clock Ratios Between Asynchronous BlocksEric Hendrickson, Bill Au, Richard Llaca, and Joe Hupcey III2018Presentationy2018presentation
Using Formal Verification to Exhaustively Verify SoC AssembliesKenny Ranerup and Mark Handover2013Papery2013paper
Using Formal Verification to Exhaustively Verify SoC AssembliesMark Handover and Kenny Ranerup2013Presentationy2013presentation
Using Machine Learning in Register Automation and VerificationNikita Gulliya, Abhishek Bora, Nitin Chaudhary, and Amanjyot Kaur2019Papery2019paper
Using Machine Learning in Register Automation and VerificationNikita Gulliya, Abhishek Bora, Nitin Chaudhary, and Amanjyot Kaur2019Presentationy2019presentation
Using Modal Analysis to Increase Clock Domain Crossing (CDC) Analysis Efficiency and AccuracyKurt Takara, Gargi Sharma, Ajay Thadhlani, and Bhrugurajsinh Chudasama2019Presentationy2019presentation
Using Modal Analysis to Increase Clock Domain Crossing (CDC) Analysis Efficiency and AccuracyKurt Takara, Gargi Sharma, Ajay Thadhlani, and Bhrugurajsinh Chudasama2019Papery2019paper
Using Model Checking to Prove Constraints of Combinational Equivalence CheckingXiushan Feng, Joseph Gutierrez, Mel Pratt, Mark Eslinger, and Noam Farkash2010Papery2010paper
Using Mutation Coverage for Advanced Bug HuntingVladislav Palfy and Nicolae Tusinschi2018Presentationy2018presentation
Using Portable Stimulus to Verify an ARMv8 Sub-System SoC IntegrationMike Baird and Aileen Honess2019Presentationy2019presentation
Using Portable Stimulus to Verify an LTE Base-Station SwitchAdnan Hamid2017Postery2017poster
Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoCAdnan Hamid, David Koogler, and Thomas L. Anderson2016Papery2016paper
Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoCAdnan Hamid and Raja Pantangi2016Presentationy2016presentation
Using PSS-2.0 Hardware-Software Interface to validate 4G/5G Forward Error Correction Encoder/Decoder IP in Emulation & SiliconVinit Shenoy, Suresh Vasu, Nithin Venkatesh, Suhas Reddy, Joydeep Maitra2022Papery2022paper
Using Save/Restore is Easy, Right? A User’s Perspective on Deploying Save/Restore in a Mature Verification MethodologyEd Powell, Ron Thurgood, and Aneesh Samudrala2019Papery2019paper
Using Save/Restore is easy, Right?A User’s Perspective on Deploying Save/RestoreRon Thurgood, Ed Powell, and Aneesh Samudrala2019Presentationy2019presentation
Using Static RTL Analysis to Accelerate Satellite FPGA VerificationAdam Taylor and Dave Wallace2020Presentationy2020presentation
Using SystemVerilog “Interfaces” as Object-Oriented RTL ModulesGeoff Barnes2010Papery2010paper
Using SystemVerilog Interfaces and Structs for RTL DesignTom Symons and Nihar Shah2014Presentationy2014presentation
Using SystemVerilog Interfaces and Structs for RTL DesignTom Symons and Nihar Shah2014Papery2014paper
Using SystemVerilog Packages in Real Verification ProjKaiming Ho2010Papery2010paper
Using Test-IP Based Verification Techniques in a UVM EnvironmentVidya Bellippady, Sundar Haran, and Jay O’Donnell2014Postery2014poster
Using UPF Information Model APIs to write re-usable Low Power Testbenches and customized coverage models for Low PowerShreedhar Ramachandra and Himanshu Bhatt2019Postery2019poster
Using UVM Virtual Sequencers & Virtual SequencesClifford E. Cummings and Janick Bergeron2016Papery2016paper
Using UVM: The Condensed Guide For Designers, Debuggers, Test-Writers And Other SkepticsGordon Allan2013Presentationy2013presentation
Using UVM: The Condensed Guide For Designers, Debuggers, Test-Writers And Other SkepticsGordon Allan2013Papery2013paper
Utilizing Technology Implementation Data in blended hardware/software power optimization.Theodore Wilson and Frank Schirrmeister2019Postery2019poster
UVM – Stop Hitting Your Brother Coding GuidelinesRich Edelman and Chris Spear2020Papery2020paper
UVM – Stop Hitting Your Brother Coding GuidelinesChris Spear and Rich Edelman2020Presentationy2020presentation
UVM Acceleration using Hardware Emulator at Pre-silicon StageSunil Roe, YunGi Um, Hyunwoo Koh, Hyunsun Ahn, Youngsik Kim, and Seonil Brian Choi2018Presentationy2018presentation
UVM Acceleration Using Hardware Emulator at Pre-silicon StageSunil Roe, YunGi Um, Hyunwoo Koh, Hyunsun Ahn, Youngsik Kim, and Seonil Brian Choi2018Papery2018paper
UVM and C – Perfect TogetherRich Edelman2018Papery2018paper
UVM and C – Perfect TogetherRich Edelman2018Presentationy2018presentation
UVM and SystemC Transactions – An UpdateDavid Long and John Aynsley2016Papery2016paper
UVM and SystemC Transactions – An UpdateDavid Long2016Presentationy2016presentation
UVM and UPF: an application of UPF Information ModelAmit Srivastava, Harsh Chilwal, and Srivatsa Vasudevan2019Presentationy2019presentation
UVM and UPF: an application of UPF Information ModelAmit Srivastava, Harsh Chilwal, and Srivatsa Vasudevan2019Papery2019paper
UVM Based Approach To Model Validation For SV-RNM Behavioral ModelsDonald Lewis and Courtney Fricano2016Postery2016poster
UVM Based Approach To Model Validation For SV-RNM Behavioral ModelsDonald Lewis and Courtney Fricano2016Papery2016paper
UVM Based Mixed-Signal Verification of a Display PMIC Designed for OLED Display ApplicationsVijay Kumar & Adnan Malik2023Postery2023poster
UVM Based Mixed-Signal Verification of a Display PMIC Designed for OLED Display ApplicationsVijay Kumar & Adnan Malik2023Papery2023paper
UVM Do’s and Don’ts for Effective VerificationKathleen Meade and Sharon Rosenberg2012Papery2012paper
UVM for HLS: An Expedient Approach to the Functional Verification of HLS DesignsDave Burgoon and Robert Havlik2018Papery2018paper
UVM for HLS: An Expedient Approach to the Functional Verification of HLS DesignsDave Burgoon and Robert Havlik2018Presentationy2018presentation
UVM IEEE Shiny ObjectRich Edelman2019Presentationy2019presentation
UVM IEEE Shiny ObjectRich Edelman and Moses Satyasekaran2019Papery2019paper
UVM Interactive Debug Library: Shortening the Debug Turnaround TimeHorace Chan2017Papery2017paper
UVM Interactive Debug Library: Shortening the Debug Turnaround TimeHorace Chan2017Presentationy2017presentation
UVM Layering for Protocol Modeling Using State PatternTony George, Girish Gupta, Shim Hojun, and Byung C. Yoo2020Presentationy2020presentation
UVM Random StabilityAvidan Efody2012Papery2012paper
UVM Rapid Adoption: A Practical Subset of UVMStuart Sutherland and Tom Fitzpatrick2015Papery2015paper
UVM Rapid Adoption: A Practical Subset of UVMStuart Sutherland and Tom Fitzpatrick2015Presentationy2015presentation
UVM Reactive Stimulus TechniquesCliff Cummings, Heath Chambers, and Stephen Donofrio2020Presentationy2020presentation
UVM Register Modelling at the Integration- Level TestbenchWayne Yun2016Papery2016paper
UVM Sans UVM An approach to automating UVM testbench writingRich Edelman and Shashi Bhutada2015Presentationy2015presentation
UVM Sans UVM: An approach to automating UVM testbench writingRich Edelman and Shashi Bhutada2015Papery2015paper
UVM SchmooVM – I Want My C Tests!Rich Edelman and Raghu Ardeishar2014Papery2014paper
UVM SchmooVM! – I Want My C Tests!Rich Edelman and Raghu Ardeishar2014Postery2014poster
UVM Testbench Automation for AMS DesignsJonathan David, Henry Chang2024Presentationy2024presentation
UVM Testbench Automation for AMS DesignsJ. B. David, H. Chang2024Papery2024paper
UVM Testbench Considerations for AccelerationKathleen A Meade2014Papery2014paper
UVM Testbench Considerations for AccelerationKathleen A Meade2014Presentationy2014presentation
UVM testbench design for ISA functional verification of a microprocessorGabriel Wang, Hongtao Ma, and Maoduo Sun2018Postery2018poster
UVM testbench design for ISA functional verification of a microprocessorGabriel Wang, Hongtao Ma, and Maoduo Sun2018Papery2018paper
UVM Transaction Recording EnhancementsRex Chen, Bindesh Patel, and Jun Zhao2011Papery2011paper
UVM UpdateSrivatsa Vasudevan2024Presentationy2024presentation
UVM Verification Environment Based on Software Design PatternsDarko M. Tomušilović and Hagai Arbel2018Presentationy2018presentation
UVM Verification Environment Based on Software Design PatternsD. M. Tomušilović and H. J. Arbel2018Papery2018paper
UVM Working Group Releases 1800.2-2020-2.0 LibrarySrivatsa Vasudevan, Jamsheed Agahi, Mark Strickland2023Presentationy2023presentation
UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration LayerMarcela Zachariasova, Lubos Moravec, John Stickley, Hans van der Schoot, and Shakeel Jeeawoody2018Papery2018paper
UVM-based verification of a RISC-V Processor Core Using a Golden predictor model and a Configuration LayerMarcela Zachariasova, Lubos Moravec, John Stickley, Hans van der Schoot, and Shakeel Jeeawoody2018Presentationy2018presentation
UVM-FM: Reusable Extension Layer for UVM to Simplify Functional ModelingAhmed Kamal2018Papery2018paper
UVM-FM: Reusable Extension Layer for UVMto Simplify Functional ModelingAhmed Kamal2018Postery2018poster
UVM-SV Feedback Loop – The Foundation of Self-Improving TestbenchesAndrei Vintila, Sergiu Duda2023Papery2023paper
UVM-SV Feedback Loop – The foundation of Self-Improving TestbenchesAndrei Vintila, Sergiu Duda2023Presentationy2023presentation
UVM: Conquering LegacySantosh Sarma, Amit Sharma, and Adiel Khan2013Postery2013poster
UVM’s MAM to the RescueMichael Baird2015Papery2015paper
UVM’s MAM to the RescueMichael Baird2015Presentationy2015presentation
UVM/SystemVerilog based infrastructure and testbench automation using scriptsPrakash Parikh2014Presentationy2014presentation
UVM/SystemVerilog based infrastructure and testbench automation using scriptsPrakash Parikh2014Papery2014paper
Variation-Aware Modeling Method for MRAM Behavior Model using System-VerilogS. Do, S. Shin, J. Jang, D. Kim2024Papery2024paper
Variation-Aware Modeling Method for MRAM Behavior Model using System-VerilogS. Do, S. Shin, J. Jang, D. Kim2024Presentationy2024presentation
Verification 2.0 – Multi-Engine, Multi-Run AI Driven VerificationMatt Graham2023Presentationy2023presentation
Verification Environment Automation from RTLZhidong Chen, Yunyang Song, Wenting Hou, Junna Qiao, Junxia Wang, Ling Bai, and Kei-Wang Yiu2015Postery2015poster
Verification Environment Automation from RTLZhidong Chen, Yunyang Song, Wenting Hou, Junna Qiao, Junxia Wang, Ling Bai, and Kei-Wang Yiu2015Papery2015paper
Verification Learns a New Language: – An IEEE 1800.2 ImplementationRay Salemi, Tom Fitzpatrick2021Papery2021paper
Verification Macros: Maintain the integrity of verifiable IP UPF through integrationAmit Srivastava, Shreedhar Ramachandra2023Papery2023paper
Verification Macros: Maintain the integrity of verifiable IP UPF through integrationAmit Srivastava, Shreedhar Ramachandra2023Postery2023poster
Verification Mind GamesJeffrey Montesano and Mark Litterick2014Papery2014paper
Verification Mind GamesJeffrey Montesano and Mark Litterick2014Postery2014poster
Verification of Accelerators in System ContextRussell A. Klein2019Postery2019poster
Verification of an Image Processing Mixed-Signal ASICKevin Buescher, Milos Becvar, Greg Tumbush, and David Jenkins2016Papery2016paper
Verification of Clock Domain Crossing Jitter and Metastability Tolerance using EmulationAshish Hari, Suresh Krishnamurthy, Amit Jain, and Yogesh Badaya2012Papery2012paper
Verification of Inferencing Algorithm AcceleratorsRussell Klein, Petri Solanti2023Presentationy2023presentation
Verification Patterns – Taking Reuse to the Next LevelHarry Foster, Michael Horn, Bob Oden, Pradeep Salla, and Hans van der Schoot2016Papery2016paper
Verification Patterns in the Multicore SoC DomainGordon Allan2011Papery2011paper
Verification Plan in Requirements Management Tool: Simple Traceability and Automated Interface to Regression ManagerJan Kreisinger, Sanjay Chatterjee2024Papery2024paper
Verification Plan in Requirements Management Tool: Simple Traceability and Automated Interface to Regression ManagerJan Kreisinger, Sanjay Chatterjee Allegro MicroSystems2024Presentationy2024presentation
Verification Reuse for a Non-Transaction Based Design across Multiple PlatformsLuis Li, Pablo Salazar, and Andrés Cordero2019Postery2019poster
Verification strategy for pipeline type of designDjuro Grubor2018Papery2018paper
Verification Strategy for Pipeline Type of DesignDjuro Grubor2018Postery2018poster
Verification with multi-core parallel simulations: Have you found your sweet spot yet?Rohit K Jain and Shobana Sudhakar2016Papery2016paper
Verification with multi-core parallel simulations: Have you found your sweet spot yet?Rohit K Jain and Shobana Sudhakar2016Postery2016poster
Verifying clock-domain crossing at RTL IP level using coverage-driven methodologyJean-François Vizier, Dennis Ramaekers, and Zheng Hai Zhou2010Papery2010paper
Verifying functionality is simply not enoughRajesh Bawankule2013Postery2013poster
Verifying functionality is simply not enoughRajesh Bawankule2013Papery2013paper
Verifying Layered Protocols – Leveraging Advanced UVM CapabilitiesParag Goel and Amit Sharma2013Papery2013paper
Verifying Layered Protocols – Leveraging Advanced UVM CapabilitiesParag Goel2013Presentationy2013presentation
Verifying Multiple DUV Representations with a Single UVM-e TestbenchMatt Graham2014Papery2014paper
Verifying Multiple DUV Representations with a Single UVM-e TestbenchMatt Graham2014Postery2014poster
Verifying RO registers: Challenges and the solutionIvana Dobrilovic2023Papery2023paper
Verifying RO registers: Challenges and the solutionIvana Dobrilovic2023Presentationy2023presentation
Versatile UVM ScoreboardingJacob Andersen, Peter Jensen, and Kevin Steffensen2015Postery2015poster
Versatile UVM ScoreboardingJacob Andersen, Peter Jensen, and Kevin Steffensen2015Papery2015paper
VHDL 2018 New and NoteworthyHendrik Eeckhaut and Lieven Lemiengre2018Presentationy2018presentation
VHDL 2018: New and NoteworthyL. Lemiengre and H. Eeckhaut2018Papery2018paper
VIP ShieldingJeremy Ridgeway and Karishma Dhruv2014Papery2014paper
VIP ShieldingJeremy Ridgeway and Karishma Dhruv2014Postery2014poster
Virtual Platforms to Shift-Left Software Development and System VerificationRoss Dickson and Pankaj Kakkar2022Presentationy2022presentation
Virtual Sequencers & Virtual SequencesClifford E. Cummings and Janick Bergeron2016Presentationy2016presentation
Virtual Test: Simulating ATE Vectors in a SystemVerilog Testbench for Faster Time to MarketJohn Mackintosh, Matthew Borto, Cecil Stone, David Brownell, and Courtney Fricano2015Papery2015paper
Virtual Test: Simulating ATE Vectors in a SystemVerilog Testbench for Faster Time to MarketJohn Mackintosh, Matthew Borto, Cecil Stone, David Brownell, and Courtney Fricano2015Postery2015poster
Want a Boost in your Regression Throughput? Simulate common setup phase only once.Rohit K Jain and Shobana Sudhakar2015Postery2015poster
Want a Boost in your Regression Throughput? Simulate common setup phase only once.Rohit K Jain and Shobana Sudhakar2015Papery2015paper
Watch Out! Generating Coordinated Random Traffic in UVMNigasan Ragunathan, Christine Thomson2021Papery2021paper
Weathering the Verification Storm: Methodology Enhancements used on a Next Generation Weather Satellite C&DH ProgramMichael Donnelly and Michael Horn2013Papery2013paper
Weathering the Verification Storm: Methodology Enhancements used on a Next Generation Weather Satellite CDH ProgramMichael Horn2013Presentationy2013presentation
What Does The Sequence Say? Powering Productivity with PolymorphismRich Edelman2022Presentationy2022presentation
What Does The Sequence Say? Powering Productivity with PolymorphismRich Edelman2022Papery2022paper
What Ever Happened to AOP?James Strober, P.Eng, and Corey Goss2015Papery2015paper
What Ever Happened to AOP?James Strober, P.Eng, and Corey Goss2015Presentationy2015presentation
What I Wish My Regression Run Manager’s Vendor Knew!David Crutchfield, Brian Craw, Jason Lambirth2023Papery2023paper
What I Wish My Regression Run Manager’s Vendor Knew!Brian Craw, David Crutchfield, Jason Lambirth2023Presentationy2023presentation
What is new in IP-XACT Std. IEEE 1685-2022?Richard Weber, Edwin Dankert2023Presentationy2023presentation
What Time Is It: Implementing a SystemVerilog Object-Oriented Wrapper for Interacting with the C Library timeEldon Nelson M.S. P.E.2018Papery2018paper
What Time Is It: Implementing a SystemVerilog Object-Oriented Wrapper for Interacting with the C Library timeEldon Nelson M.S. P.E.2018Postery2018poster
What Your Software Team Would Like the RTL Team to Know.Josh Rensch2020Presentationy2020presentation
What’s Next for SystemVerilog in the Upcoming IEEE 1800 standardDave Rich2023Presentationy2023presentation
What’s Next for SystemVerilog in the Upcoming IEEE 1800 standardDave Rich2023Papery2023paper
Where OOP Falls Short of Hardware Verification NeedsMatan Vax2010Papery2010paper
Who’s Watching the Watchmen? The Time has Come to Objectively Measure the Quality of Your VerificationDavid Brownell2013Presentationy2013presentation
Who’s Watching the Watchmen? The Time has Come to Objectively Measure the Quality of Your Verification EnvironmentDavid Brownell2013Papery2013paper
Whose Fault Is It Formally? Formal Techniques for Optimizing ISO 26262 Fault Analysis.Ping Yeung, Doug Smith, and Abdelouahab Ayari2018Presentationy2018presentation
Whose Fault Is It Formally? Formal Techniques for Optimizing ISO 26262 Fault Analysis.Ping Yeung, Doug Smith, and Abdelouahab Ayari2018Papery2018paper
Whose fault is it? Advanced techniques for optimizing ISO 26262 fault analysisAvidan Efody2016Papery2016paper
Whose fault is it? Advanced techniques for optimizing ISO 26262 fault analysisAvidan Efody2016Presentationy2016presentation
Why Not “Connect” Using UVM Connect: Mixed Language Communication Got Easier with UVMCVishal Baskar2022Postery2022poster
Why Not “Connect” Using UVM Connect: Mixed Language Communication Got Easier with UVMCVishal Baskar2022Papery2022paper
Wiretap your SoCAvidan Efody2014Papery2014paper
Wiretap your SoC: Why scattering Verification IPs throughout your design is a smart thing to doAvidan Efody2014Presentationy2014presentation
With Great Power Comes Great Responsibility A method to verify PMICs with UVM-MSDor Spigel and Moshik Hershcovitch2014Presentationy2014presentation
With great power comes great responsibility: A method to verify PMICs using UVM-MSDor Spigel and Moshik Hershcovitch2014Papery2014paper
Without Objection – Touring the uvm_objection implementations – uses and improvementsRich Edelman2024Presentationy2024presentation
Without Objection – Touring the uvm_objection implementation – uses and improvementsRich Edelman2024Papery2024paper
Working within the Parameters that System Verilog has constrained us toSalman Tanvir, David Crutchfield, Markus Brosch2024Presentationy2024presentation
Working within the Parameters that SystemVerilog has constrained us toSalman Tanvir, David Crutchfield2024Papery2024paper
Wrapping Verilog Bus Functional Model (BFM) and RTL as Drivers in Customized UVM VIP Using Abstract ClassesRoman Wang and Thomas Bodmer2015Papery2015paper
Wrapping Verilog Bus Functional Model (BFM) and RTL as Drivers in Customized UVM VIP Using Abstract ClassesRoman Wang and Thomas Bodmer2015Postery2015poster
X-Propagation Woes: Masking Bugs at RTL and Unnecessary Debug at the NetlistLisa Piper and Vishnu Vimjam2012Papery2012paper
X-propagation Woes: Masking Bugs at RTL and Unnecessary Debug at the NetlistLisa Piper2012Presentationy2012presentation
YAMM Yet Another Memory ManagerAndrei Vintila, Ionut Tolea, and Teodor Vasilache2017Presentationy2017presentation
Yet Another Memory Manager (YAMM)Ionut Tolea, Andrei Vintila, and Cosmin-Teodor Vasilache2017Papery2017paper
Yikes! Why is My SystemVerilog Still So Slooooow?Cliff Cummings, John Rose, and Adam Sherer2019Papery2019paper
Yikes! Why is My SystemVerilog Testbench So Slooooow?Frank Kampf2012Papery2012paper
Yikes! Why is my SystemVerilog Testbench So Slooooow?Justin Sprague2012Presentationy2012presentation
You Are In a Maze of Twisty Little Sequences, All Alike – or Layering Sequences for Stimulus AbstractionRich Edelman, Adam Rose, Andreas Meyer, Raghu Ardeishar, and Jason Polychronopoulos2010Papery2010paper
Your SoC, Your Topology: Interconnects used within SoCsAmi Pathak, Matt Mangan2024Presentationy2024presentation