DVCon: United States

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“Bounded Proof” sign-off with formal coverageAbhishek Anand, Chinyu Chen, Bathri Narayanan Subramanian, Joe Hupcey2021Paper2021paper
“C” you on the faster side: Accelerating SV DPI based co-simulationParag Goel, Amit Sharma, and Hari Vinodh Balisetty2014Paper2014paper
“C” you on the faster side: Accelerating SV DPI based co-simulationHari Vinod Balisetty, Parag Goel, and Amit Sharma2014Presentation2014presentation
“In-Emulator” UVM++ Randomized Testbenches for High Performance Functional VerificationAdnan Hamid and David Kelf2022Presentation2022presentation
“Shift left” Hierarchical Low-Power Static Verification Using SAMBharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal2020Paper2020paper
“Shift left” Hierarchical Low-Power Static Verification Using SAMBharani Ellore, Parag Mandrekar, Himanshu Bhatt, Susantha Wijesekara, and Bhaskar Pal2020Poster2020poster
A 30 Minute Project Makeover Using Continuous IntegrationJL Gray2012Paper2012paper
A 30 Minute Project Makeover Using Continuous IntegrationJL Gray and Gordon McGregor2012Presentation2012presentation
A 360 Degree View of UVM Events – A Case StudyDeepak Kumar E V, Sathish Dadi, and Vikas Billa2016Paper2016paper
A 360 Degree View of UVM Events (A Case Study)Deepak Kumar E V, Sathish Dadi, and Vikas Billa2016Presentation2016presentation
A Client-Server Method for Register Design and DocumentationScott D Orangio and Julien Gagnon2016Paper2016paper
A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISC V CoreJunaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, Aashir Ahsan2022Presentation2022presentation
A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISCV CoreJunaid Ahmed, Waleed Bin Ehsan, Laraib Khan, Asad Aleem, Agha Ali Zeb, Sarmad Paracha, Abdul Hameed Akram, and Aashir Ahsan2022Paper2022paper
A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance AnalysisBishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel2016Poster2016poster
A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance Analysis.Bishnupriya Bhattacharya, Chandra Sekhar Katuri, and Vincent Motel2016Paper2016paper
A Coverage-Driven Formal Methodology for Verification Sign-offAng Li, Hao Chen, Jason K Yu, Ee Loon Teoh, and Iswerya Prem Anand2019Paper2019paper
A Coverage-Driven Formal Methodology for Verification Sign-offAng Li, Hao Chen, Jason K Yu, Ee Loon Teoh and, Iswerya Prem Anand2019Presentation2019presentation
A Dyadic Transformation Based Methodology To Achieve Coverage Driven Verification GoalSwapnajit Mitra2017Presentation2017presentation
A Dyadic Transformation Based Methodology to Achieve Coverage Driven Verification GoalSwapnajit Mitra2017Paper2017paper
A Dynamic Approach Towards Register Coverage Generation and Collection to Reduce Compilation Overhead of Traditional UVM Register LayersSubham Banerjee2020Presentation2020presentation
A Formal Verification App Towards Efficient Chip-Wide Clock Gating VerificationProsenjit Chatterjee, Scott Fields, and Syed Suhaib2014Presentation2014presentation
A Formal Verification App Towards Efficient, Chip-Wide Clock Gating VerificationProsenjit Chatterjee, Scott Fields, and Syed Suhaib2014Paper2014paper
A Guide To Using Continuous Integration Within The Verification EnvironmentJason Sprott2014Presentation2014presentation
A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power IntentVijay Kumar Sankaran, Lakshmanan Balasubramanian, Bharath Kumar Poluri, Venkatraman Ramakrishnan, Badrinarayan Zanwar, and Qingyu Lin2016Paper2016paper
A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power IntentQingyu Lin2016Poster2016poster
A Holistic View of Mixed-Language IP IntegrationPankaj Singh and Gaurav Kumar Verma2010Paper2010paper
A Hybrid Verification Solution to RISC V Vector ExtensionChenghuan Li, Yanhua Feng, Liam Li2022Presentation2022presentation
A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance CorrelationThomas Soong, Christopher Browne, and Chenhui Huang2022Poster2022poster
A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance CorrelationThomas Soong, Chenhui Huang, and Christopher Browne2022Paper2022paper
A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation AccelerationHorace Chan, Brian Vandegriend, and Efrat Shneydor2015Paper2015paper
A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation AccelerationHorace Chan, Brian Vandegriend, and Efrat Shneydor2015Presentation2015presentation
A New Approach for Generating View GeneratorsJohannes Schreiner, Felix Willgerodt, and Wolfgang Ecker2017Paper2017paper
A New Approach for Generating View GeneratorsJohannes Schreiner, Felix Willgerodt, and Wolfgang Ecker2017Poster2017poster
A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain CrossingsOmri Dassa, Yossi Mirsky2022Presentation2022presentation
A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain CrossingsOmri Dassa and Yossi (Joseph) Mirsky2022Paper2022paper
A New Class Of RegistersMark Peryer and David Aerne2016Poster2016poster
A New Class Of RegistersM. Peryer and D. Aerne2016Paper2016paper
A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM DomainsSubham Banerjee and Keshava Krishna Raja2017Paper2017paper
A novel approach to create multiple domain based DV architecture to address typical Verification challenges, for the DUT with mutual exclusive functionalities, using UVM Domains2017Poster2017poster
A Novel Approach to Verify CNN Based Image Processing UnitSumit K. Kulshreshtha, Raghavendra J N2021Paper2021paper
A Novel Variation-Aware Mixed-Signal Verification Methodology to achieve High-Sigma Variation coverage at nanometer designsTibi Galambos, Sumit Vishwakarma2021Paper2021paper
A Practical Approach to Measuring and Improving the Functional Verification of Embedded SoftwareStéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès2012Paper2012paper
A Practical Approach to Measuring and Improving the Functional Verification of Embedded SoftwareStéphane Bouvier, Nicolas Sauzède, Florian Letombe, and Julien Torrès2012Presentation2012presentation
A Practical Look @ SystemVerilog Coverage – Tips, Tricks, and GotchasDoug Smith and John Aynsley2011Paper2011paper
A Reusable, Scalable Formal App for Verifying Any Configuration of 3D IC ConnectivityDaniel Han, Walter Sze, Benjamin Ting, and Darrow Chu2013Paper2013paper
A Semi-Formal Verification Methodology for Efficient Configuration Coverage of Highly Configurable Digital DesignsAman Kumar, Sebastian Simon2021Paper2021paper
A Simplified Approach Using UVM Sequence Items for Layering Protocol VerificationHaiqian Yu and Christine Thomson2017Paper2017paper
A Simplified Approach Using UVM Sequence Items for Layering Protocol VerificationChristine Thomson and Haiqian Yu2017Presentation2017presentation
A single generated UVM Register Model to handle multiple DUT configurationsSalvatore Marco Rosselli and Giuseppe Falconeri2020Presentation2020presentation
A SMART GENERATION OF DESIGN ATTRIBUTES FOR VERIFICATION CLOSURE USING SPECMANMeirav Nitzan, Yael Kinderman, and Efrat Gavish2013Poster2013poster
A Smart Synchronizer – Pragmatic way to cross asynchronous clock domainsPriyank Parakh and Steven J Kommrusch2011Paper2011paper
A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing LogicPriya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed2018Paper2018paper
A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing LogicPriya Viswanathan, Kurt Takara, Chris Kwok, and Islam Ahmed2018Poster2018poster
A Systematic Approach to Power State Table (PST) DebuggingBhaskar Pal, Suman Nandan, Kaushik De, and Rajarshi Mukherjee2013Paper2013paper
A Systematic Approach to Power State Table (PST) DebuggingBhaskar Pal2013Presentation2013presentation
A Systematic Formal Reuse Methodology: From Blocks to SoC SystemsHao Chen, Yi Sun, Ang Li, and Dorry Cao2020Presentation2020presentation
A Systematic Take on Addressing Dynamic CDC Verification ChallengesSukriti Bisht, Sulabh Kumar Khare, and Ashish Hari2019Paper2019paper
A Systematic Take on Addressing Dynamic CDC Verification ChallengesSukriti Bisht, Sulabh Kumar Khare, and Ashish Hari2019Presentation2019presentation
A SystemC Library for Advanced TLM VerificationMarcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen2012Paper2012paper
A SystemC Library for Advanced Verification – Towards an Enhanced OVM/UVM for SystemCMarcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Wolfgang Ecker, and Volkan Esen2012Presentation2012presentation
A SystemVerilog Framework for Easy Method Advice in Object-oriented Test BenchesEric Ohana2013Poster2013poster
A SystemVerilog Framework for Easy Method Advice in Object-oriented Test BenchesEric Ohana2013Paper2013paper
A SystemVerilog Framework for Efficient Randomization of Images with Complex Inter-Pixel DependenciesAxel Voss, Gabriel Jönsson, and Lars Viklund2020Presentation2020presentation
A Tale of Two Languages – SystemVerilog and SystemCDavid C Black2013Paper2013paper
A Tale of Two Languages: SystemVerilog & SystemCDavid C Black2013Presentation2013presentation
A Unified Testbench Architecture Solution for Verifying Variants of A PLL IPDeepa Ananthanarayanan and Malathi Chikkanna2015Presentation2015presentation
A Unified Testbench Architecture Solution for Verifying Variants of the PLL IPDeepa Ananthanarayanan and Malathi Chikkanna2015Paper2015paper
A Universal DFT Verification Environment: Filling the Gap between Function Simulation and ATE TestRui Huang2016Presentation2016presentation
A Universal DFT Verification Environment: Filling the Gap between Function Simulation and ATE TestRui Huang2016Paper2016paper
A UVM SystemVerilog Testbench for Analog/Mixed-Signal Verification: A Digitally-Programmable Analog Filter ExampleCharles Dančak2022Paper2022paper
A UVM Testbench for Analog Verification: A Programmable Filter ExampleCharles Dančak2022Presentation2022presentation
A UVM-based Approach for Rapidly Verifying Digital Interrupt StructuresChristoph Rumpler, Alexander W. Rath, and Sebastian Simon2016Presentation2016presentation
A UVM-based Approach for Rapidly Verifying Digital Interrupt StructuresChristoph Rumpler, Alexander W. Rath, Sebastian Simon, and Heinz Endres2016Paper2016paper
A Volterra-Series Model in SystemVerilog/XMODEL for Nonlinear RF Low-Noise AmplifiersChan Young Park, Jaeha Kim2021Paper2021paper
Abstract Layer for Firmware Access: A Unique Approach for SOC Functional VerificationGupta Girish Kumar, Rugmini Navia Vishnu, Choudhary Praval, Syed Mobeenuddin2021Paper2021paper
Accelerated simulation through design partition and HDL to C++ compilationTheta Yang2017Presentation2017presentation
Accelerated simulation through design partition and HDL to C++ compilationTheta Yang and Sga Sun2017Paper2017paper
Accelerated, High Quality SoC Memory Map Verification using Formal TechniquesCletan Sequeira, Rajesh Kedia, Lokesh Babu Pundreeka, and Bijitendra Mittra2014Paper2014paper
Accelerated, High Quality SoC Memory Map Verification using Formal TechniquesCletan Sequeira, Rajesh Kedia, Lokesh Babu Pundreeka, and Bijitendra Mittra2014Presentation2014presentation
Accelerating CDC Verification Closure on Gate-Level DesignsAnwesha Choudhury and Ashish Hari2017Presentation2017presentation
Accelerating CDC Verification Closure on Gate-Level DesignsAnwesha Choudhury and Ashish Hari2017Paper2017paper
Accelerating Error Handling Verification Of Complex Systems: A Formal ApproachBhushan Parikh, Peter Graniello, Neha Rajendra2022Presentation2022presentation
Accelerating Error Handling Verification of Complex Systems: A Formal ApproachBhushan Parikh, Peter Graniello, and Neha Rajendra2022Paper2022paper
Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing ProductsYoga Priya Vadivelu, Arpan Shah, Deepinder Singh Mohoora, Ullas, and Praveen Buddireddy2022Poster2022poster
Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing ProductsYoga Priya Vadivelu, Arpan Shah, Deepinder Singh Mohoora, Ullas, and Praveen Buddireddy2022Paper2022paper
Accelerating SoC Verification Signoff using Save & Restart/Dynamic Test Reload Enhanced Regression flowVanshlata B, Divya M, Garima S, Seonil Brian Choi2021Paper2021paper
Accelerating SOC Verification Using Process Automation and IntegrationSeonghee Yim, Hanna Jang, Sunchang Choi, and Seonil Brian Choi2020Paper2020paper
Accelerating the IP Design Cycle with Formal Techniques Beyond Everyday FPVBhushan Parikh, Shaman Narayana, Buck Lem, David Cassetti2021Paper2021paper
Acceleration of Coreless SoC Design-Verification using PSS on Configurable Testbench in Multi-Link PCIe SubsystemsThanu Ganapathy, Pravin Kumar, Garima Srivastava, Seonil Brian Choi, Harish Peta2021Paper2021paper
Accellera UVM-AMS Standard UpdateTom Fitzpatrick and Tim Pylant2022Presentation2022presentation
Ace’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power ConsumptionMehul Kumar, Tushar Mattu, and Amir Nilipour2016Paper2016paper
ACE’ing the Verification of a Coherent System Using UVMRomondy Luo, Ray Varghese, Parag Goel, Amit Sharma, Satyapriya Acharya, and Peer Mohammed2012Paper2012paper
ACE’ing the Verification of a Coherent System Using UVMParag Goel; Amit Sharma, Ray Varghese, Romondy Luo, Satyapriya Acharya, Peer Mohammed2012Presentation2012presentation
ACE’ing the Verification of SOCs with Cache Coherent Heterogeneous Multiprocessors Targeted for Optimized Power ConsumptionMehul Kumar, Shawn Honess, Amir Nilipour, and Tushar Mattu2016Poster2016poster
Achieving First-Time Success with a UPF-based Low Power Verification FlowKjeld Svendsen, Chuck Seeley, and Erich Marschner2011Paper2011paper
Activity Trend Guided Efficient Approach to Peak Power Estimation Using EmulationGaurav Saharawat, Saurabh Jain, and Madhur Bhatia2016Presentation2016presentation
Activity Trend Guided Efficient Approach to Peak Power Estimation Using EmulationGaurav Saharawat, Saurabh Jain, and Madhur Bhatia2016Paper2016paper
Adapting the UVM Register Abstraction Layer for Burst AccessMark Villalpando2016Presentation2016presentation
Adapting the UVM Register Layer for Burst AccessM. P. Villalpando2016Paper2016paper
Adaptive Test Generation for Fast Functional Coverage ClosureAzade Nazi, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhoseini, Richard Ho2022Presentation2022presentation
Adaptive Test Generation for Fast Functional Coverage ClosureAzade Naziz, Qijing Huang, Hamid Shojaei, Hodjat Asghari Esfeden, Azalia Mirhosseiniz, and Richard Ho2022Paper2022paper
Addressing Challenges in Verification of DSP based Audio IPs using a Novel Hybrid-TestBench ArchitectureSuvadeep Bose, Kanak Singh Rajput, Parag S Lonkar, Somasunder K Sreenath2021Paper2021paper
Addressing HW/SW Interface Quality through StandardsDavid Murray and Sean Boyan2012Paper2012paper
Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail MacrosBrandon S. Skaggs2020Paper2020paper
Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail MacrosBrandon Skaggs2020Poster2020poster
Addressing the Challenges of Reset Verification in SoC DesignsChris Kwok, Priya Viswanathan, and Ping Yeung2015Paper2015paper
Addressing the Challenges of Reset Verification in SoC DesignsChris Kwok, Priya Viswanathan, and Ping Yeung2015Presentation2015presentation
Addressing the verification challenge of SERDES-based FPGAs: The performance/accuracy/efficiency trade-offChris Schalick2011Paper2011paper
Adopting Accellera’s Portable Stimulus Standard: Early Development and Validation using Virtual PrototypingSimranjit Singh, Ashwani Aggarwal, Harshita Prabha, Vishnu Ramadas, Seonil Brian Choi, Woojoo Space Kim2021Paper2021paper
Advanced Digital-Centric Mixed-Signal MethodologyMichael Kontz, David Lacey, and Peter Maroni2015Presentation2015presentation
Advanced Digital-Centric Mixed-Signal MethodologyMichael Kontz, David Lacey, and Peter Maroni2015Paper2015paper
Advanced Functional Verification for Automotive System on a ChipJaein Hong, Jieun Jeong , Namyoung Kim, Hongkyu Kim, Sungcheol Park,2022Presentation2022presentation
Advanced Functional Verification for Automotive System on a ChipJaein Hong, Jieun Jeong, Namyoung Kim, Hongkyu Kim, and Sungcheol Park2022Paper2022paper
Advanced Functional Verification Methodology Using UVM for complex DSP Algorithms in Mixed Signal RF SoCsSrinivas Aluri and Jaimin Mehta2014Paper2014paper
Advanced Functional Verification Methodology Using UVM For Complex DSP Algorithms In Mixed Signal RF SoCsSrinivas Aluri and Jaimin Mehta2014Presentation2014presentation
Advanced SOC Randomization Tool for Complex SOC Level VerificationMarvin Mei, Chris Weller, Michael Sedmak, and Zhiqiang Ren2020Paper2020paper
Advanced Techniques for ARM L2 Cache Verification in an Accelerated Hardware and Software environmentRob Pelt and Jay O’Donnell2012Paper2012paper
Advanced Techniques for AXI Fabric Verification in a Software/Hardware OVM EnvironmentGalen Blake and Steve Chappell2012Paper2012paper
Advanced Testbench Configuration with ResourcesMark Glasser2011Paper2011paper
Advanced Usage Models for Continuous Integration in Verification EnvironmentsJohn Dickol2015Paper2015paper
Advanced Usage Models for Continuous Integration in Verification EnvironmentsJohn Dickol2015Presentation2015presentation
Advanced UVM Command Line ProcessorSiddharth Krishna Kumar2022Presentation2022presentation
Advanced UVM Command Line Processor for Central Maintenance and Randomization of Control KnobsSiddharth Krishna Kumar2022Paper2022paper
Advanced UVM Register ModelingMark Litterick and Marcus Harnisch2014Paper2014paper
Advanced UVM Register ModelingMark Litterick2014Presentation2014presentation
Advanced UVM, Multi-Interface, Reactive Stimulus TechniquesClifford E. Cummings, Stephen DOnofrio, Jeff Wilcox, Heath Chambers2021Paper2021paper
Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification CycleCharul Agrawal, Ashwin Vijayan, and Jakub Dudek2017Paper2017paper
Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification CycleCharul Agrawal, Ashwin Vijayan, and Jakub Dudek2017Presentation2017presentation
Advancing system-level verification using UVM in SystemCMartin Barnasconi, François Pêcheux, and Thilo Vörtler2014Presentation2014presentation
Advancing system-level verification using UVM in SystemCMartin Barnasconi, François Pêcheux, and Thilo Vörtler2014Paper2014paper
Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC.Nipun Bhatt2020Paper2020paper
Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC.Nipun Bhatt2020Poster2020poster
An Analytical View of Test Results Using CityScapesMarkus Borg, Andreas Brytting, and Daniel Hansson2018Paper2018paper
An Analytical View of Test Results Using CityScapesMarkus Borg, Andreas Brytting, and Daniel Hansson2018Poster2018poster
An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 ExperienceMahesha Shankarathota, Vybhava S, and Indrajit Dutta2013Poster2013poster
An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 ExperienceMahesha Shankarathota, Vybhava S, and Indrajit Dutta2013Paper2013paper
An Assertion Based Approach to Implement VHDL Functional CoverageSusan Eickhoff, Michael DeBole, and Tagbo Ekwueme-Okoli2014Paper2014paper
An Assertion Based Approach to Implement VHDL Functional CoverageMichael Wazlowski, Susan Eickhoff, Michael Debole, and Tagbo Ekwueme-Okoli2014Presentation2014presentation
An Automated Validation Framework for Power Management and Data Retention Logic Kits of Standard Cell LibraryAkshay Kamath, Bharath Kumar, Sunil Aggarwal, Subramanian Parameswaran, Parag Lonkar, Debi Prasanna, Somasunder Sreenath2021Paper2021paper
An Automatic Visual System Performance Stress Test for TLM DesignsGeorge F. Frazier, Neeti Bhatnagar, and Woody Larue2011Paper2011paper
An Easy VE/DUV Integration ApproachUwe Simm2015Presentation2015presentation
An efficient analog fault-injection flow harnessing the power of abstractionRenaud Gillon, Enrico Fraccaroliy, and Franco Fummi2019Poster2019poster
An Efficient and Modular Approach for Formally Verifying Cache ImplementationsM, Achutha KiranKumar V and Abhijith A Bharadwaj2018Paper2018paper
An Efficient and Modular Approach for Formally Verifying Cache implementationsM Achutha KiranKumar V, Abhijith A Bharadwaj, and Bindumadhava S S2018Presentation2018presentation
An Efficient Method to Verify Dynamic IP Clock Frequency on SOC Level by Using Auto-generated Active Clock MonitorJaecheon Kim, Gyuhong Lee, Yeonho Jeong, Hyunsun Ahn, Daewoo Kim, Seonil Brian Choi2021Paper2021paper
An Enhanced Stimulus and Checking Mechanism on Cache VerificationChenghuan Li, Xiaohui Zhao, and Yunyang Song2019Poster2019poster
An Equivalent Modeling Approach for High-Density DRAM Array System-Level Design-Space Exploration in SystemVerilogSeyoung Kim, Jaeha Kim2021Paper2021paper
An Experience of Complex Design Validation: How to Make Semiformal Verification WorkSabih Agbaria, Dan Carmi, Orly Cohen, Dmitry Korchemny, Michael Lifshits, and Alexander Nadel2010Paper2010paper
An experience to finish code refinement earlier at behavioral levelDae-Han Youn, Sik Kim, Byeong Min, and Kyu-Myung Choi2011Paper2011paper
An Expert System Based Tool for Pre-design Chip Power EstimationBhanu Singh, Arunprasath Shankar, Francis Wolff, and Christos Papachristou2014Paper2014paper
An Expert System Based Tool for Pre-design Chip Power EstimationBhanu Singh, Arunprasath Shankar, Francis Wolff, and Christos Papachristou2014Presentation2014presentation
An Innovative Methodology for RTL and Verification IP Sharing Between Two ProjectsAlbert Xu and Joonyoung Kim2013Poster2013poster
An Innovative Methodology for RTL and Verification IP Sharing Between Two ProjectsAlbert Xu and Joonyoung Kim2013Paper2013paper
An Innovative Methodology for Verifying Mixed-Signal ComponentsFabian Delguste and Graeme Nunn2011Paper2011paper
An Integrated Framework for Power Aware VerificationHarsh Chilwal, Manish Jain, and Bhaskar Pal2012Paper2012paper
An Overview of Security Annotation for Electronic Design Integration (SA-EDI) StandardSohrab Aftabjahani2022Presentation2022presentation
Analog Transaction Level Modeling for Verification of Mixed-Signal-BlocksAlexander W. Rath, Volkan Esen, and Wolfgang Ecker2012Paper2012paper
Analog Transaction Level Modeling for Verification of Mixed-Signal-BlocksAlexander W. Rath2012Presentation2012presentation
Analysis of TLM-2.0 and it’s Applicability to Non Memory Mapped InterfacesDelbergue Guillaume2016Presentation2016presentation
Analysis of TLM-2.0 and it’s Applicability to Non Memory Mapped InterfacesGuillaume Delbergue, Mark Burton, and Bertrand Le Gal and Christophe Jego2016Paper2016paper
Apples versus Apples HVL Comparison Finally Arrives Comparing OVM SystemVerilog to OVM eBrett Lammers and Riccardo Oddone2010Paper2010paper
Application Abstraction Layer: The Carpool Lane on the SoC Verification FreewayAbhisek Verma, Varun S, and Subramanian Kuppusamy2015Paper2015paper
Application Abstraction Layer: The Carpool Lane on the SoC Verification FreewayAbhisek Verma, Varun S, and Subramanian Kuppusamy2015Presentation2015presentation
Application of SystemC/SystemC-AMS in 3G Virtual PrototypingTao Huang and Stefan Heinen2011Paper2011paper
Application Optimized HW/SW Design & Verification of a Machine Learning SoCLauro Rizzatti, Russell Klein, Stephen Bailey, and Andrew Meier2020Presentation2020presentation
Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical PropertiesKonstantin Selyunin, Thang Nguyen, Andrei-Daniel Basa, Ezio Bartocci, Dejan Nickovic, and Radu Grosu2016Presentation2016presentation
Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical PropertiesK. Selyunin, T. Nguyen, A.D. Basa, E. Bartocci, D. Nickovic, and R. Grosu2016Paper2016paper
Applying Test-Driven Development Methods to Design Verification SoftwareDoug Gibson and Mike Kontz2014Presentation2014presentation
Applying Test-Driven Development Methods to Design Verification Software in UVM-eDoug Gibson and Mike Kontz2014Paper2014paper
Applying Transaction-level Debug and Analysis Techniques to DUT Simulated Activity Using Data- Mining TechniquesLeo Chai, Bindesh Patel, and Jun Zhao2014Paper2014paper
Applying Transaction-level Debug and Analysis Techniques to DUT Simulated Activity Using Data-Mining TechniquesLeo Chai, Jun Zhao, and Bindesh Patel2014Poster2014poster
Architecting “Checker IP” for AMBA protocolsSrinivasan Venkataramanan and Ajeetha Kumari2017Paper2017paper
Architecting “Checker IP” for AMBA protocolsAjeetha Kumari and Srinivasan Venkataramanan2017Presentation2017presentation
Architectural Evaluation of a Programmable Accelerator for Baseband, Phy and Video Applications using High Level SynthesisAndy Fox, Tigran Sargsyan, and Steven Anderson2014Paper2014paper
Architectural Evaluation Of a Programmable Accelerator For Baseband, Phy and Video Applications Using High Level SynthesisAndy Fox, Tigran Sargsyan, and Steven Anderson2014Poster2014poster
Architectural Formal Verification of System-Level DeadlocksMandar Munishwar1, Naveed Zaman, Anshul Jain, HarGovind Singh, and Vigyan Singhal2018Paper2018paper
Architectural Formal Verification of System-Level DeadlocksMandar Munishwar and Vigyan Singhal2018Presentation2018presentation
Are OVM & UVM Macros Evil? A Cost-Benefit AnalysisAdam Erickson2011Paper2011paper
Are you really confident that you are getting the very best from your verification resources?Darron May and Fritz Ferstl2014Paper2014paper
Are you really confident that you are getting the very best from your verification resources?Darron May and Fritz Ferstl2014Poster2014poster
Are You Safe Yet? Safety Mechanism Insertion and ValidationPing Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen2020Paper2020paper
Are You Safe Yet? Safety Mechanism Insertion and ValidationPing Yeung, Jin Hou, Vinayak Desai, and Jacob Wiltgen2020Poster2020poster
Are You Smarter Than Your Testbench? With a little work you can be.Rich Edelman and Raghu Ardeishar2015Paper2015paper
Are You Smarter Than Your Testbench? With a little work you could beRich Edelman and Raghu Ardeishar2015Poster2015poster
ASIC-Strength Verification in a Fast-Moving FPGA WorldBryan Murdock2013Poster2013poster
ASIC-Strength Verification in a Fast-Moving FPGA WorldBryan Murdock2013Paper2013paper
Assertion Based Self-checking of Analog Circuits for Circuit Verification and Model Validation in SPICE and Co-simulation EnvironmentsLakshmanan Balasubramanian, Pooja Sundar, and Timothy W Fischer2011Paper2011paper
Assertion-based Verification for Analog and Mixed Signal DesignsSrinivas Aluri2017Paper2017paper
Assertion-based Verification for Analog andMixed Signal DesignsSrinivas Aluri2017Poster2017poster
Asynchronous Behaviors Meet Their Match with SystemVerilog AssertionsDoug Smith2010Paper2010paper
Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor CoreWei Foong Thoo and David A. Burgoon2012Presentation2012presentation
Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor CoreWei Foong Thoo and David A. Burgoon2012Paper2012paper
Automated approach to Register Design and Verification of complex SOCBallori Banerjee, Subashini Rajan, and Silpa Naidu2011Paper2011paper
Automated Comparison of Analog Behavior in a UVM EnvironmentSebastian Simon, Alexander W. Rath, Volkan Esen, and Wolfgang Ecker2014Paper2014paper
Automated Comparison of Analog Behavior in a UVM EnvironmentSebastian Simon2014Presentation2014presentation
Automated Generation of RAL-based UVM SequencesVijayakrishnan Rousseau, Satyajit Sinari, Benjamin Applequist, Timothy McLean, and Geddy Lallathin2020Paper2020paper
Automated Generation of RAL-based UVM SequencesSatyajit Sinari, Timothy McLean, Benjamin Applequist, Vijayakrishnan Rousseau, and Geddy Lallathin2020Presentation2020presentation
Automated Performance Verification to Maximize your ARMv8 pulling powerNick Heaton and Simon Rance2015Paper2015paper
Automated Performance Verification to Maximize your ARMv8 pulling powerNick Heaton and Simon Rance2015Presentation2015presentation
Automated Physical Hierarchy Generation: Tools and MethodologyAli El-Zein, Alvan Ng, Benedikt Geukes, Maya H. Safieddine, and Wolfgang Roesner2018Paper2018paper
Automated Physical Hierarchy Generation: Tools and MethodologyAli El-Zein, Alvan Ng, Benedikt Geukes, Maya H. Safieddine, and Wolfgang Roesner2018Presentation2018presentation
Automated RTL Update for Abutted DesignWonkyung Lee, Ayoung Kwon, Soyeong Kwon, Youngsik Kim, and Seonil Brian Choi2020Paper2020paper
Automated RTL Update for Abutted DesignWonkyung Lee, Ayoung Kwon, Soyeong Kwon, Youngsik Kim, and Seonil Brian Choi2020Poster2020poster
Automated Safety Verification for Automotive MicrocontrollersHolger Busch2016Presentation2016presentation
Automated Safety Verification for Automotive MicrocontrollersH. Busch2016Paper2016paper
Automated Seed Selection Algorithm for an Arbitrary Test SuiteDavid Crutchfield, Brian Craw, Jim Sharpe, and Brandon Skaggs2018Paper2018paper
Automated Seed Selection Algorithm for an Arbitrary Test SuiteDavid Crutchfield, Brian Craw, Jim Sharpe, and Brandon Skaggs2018Presentation2018presentation
Automated Specification Driven Verification by Generation of SystemVerilog AssertionsFerdinando Pace2016Poster2016poster
Automated Specification Driven Verification by Generation of SystemVerilog AssertionsFerdinando Pace2016Paper2016paper
Automated Test Generation to Verify IP Modified for System Level Power ManagementChristophe Lamard and Frederic Dupuis2015Presentation2015presentation
Automated Test Generation to Verify IP Modified for System Level Power ManagementChristophe Lamard2015Paper2015paper
Automated traceability of requirements in the design and verification process of safety-critical mixed-signal systemsGabriel Pachiana, Maximilian Grunwald, Thomas Markwirth, Christoph Sohrmann2021Paper2021paper
Automatic Debug Down to the LineDaniel Hansson and Patrik Granath2017Poster2017poster
Automatic Debug Down to the Line of CodeDaniel Hansson and Patrik Granath2017Paper2017paper
Automatic Exploration of Hardware/Software PartitioningSyed Abbas Ali Shah, Sven Alexander Horsinka, Basitan Farkas, Rolf Meyer, and Malden Berekovic2017Paper2017paper
Automatic Exploration of Hardware/Software PartitioningSyed Abbas Ali Shah, Sven Alexander Horsinka, Basitan Farkas, Rolf Meyer, and Malden Berekovic2017Presentation2017presentation
Automatic Generation of Formal Properties for Logic Related to Clock GatingShuqing Zhao and Shan Yan2015Presentation2015presentation
Automatic Generation of Formal Properties for Logic Related to Clock GatingShuqing Zhao and Shan Yan2015Paper2015paper
Automatic Investigation of Power InefficienciesKuo Kai Hsieh, Li C. Wang, Wen Chen, Monica Farkash, and Jayanta Bhadra2017Presentation2017presentation
Automatic Investigation of Power InefficiencyKuo-Kai Hsieh, Wen Chen, Monica Farkash, Jayanta Bhadra, and Li-C. Wang2017Paper2017paper
Automatic Partitioning for Multi-core HDL SimulationGaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra2015Paper2015paper
Automatic Partitioning for Multi-core HDL SimulationGaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra2015Poster2015poster
Automatic SOC Test Bench CreationDavid Crutchfield, Mark Glasser, and Stephen Roe2015Paper2015paper
Automatic SOC Test Bench CreationDavid Crutchfield, Mark Glasser, and Stephen Roe2015Presentation2015presentation
Automatic Translation of Natural Language to SystemVerilog AssertionsAbhishek Chauhan2022Presentation2022presentation
Automatic Translation of Natural Language to SystemVerilog AssertionsAbhishek Chauhan2022Paper2022paper
Automatic verification for Assertion Based Verification: How can a SPIRIT IP-XACT extension help?Sofiene Mejri and Mirella Negro Marcigaglia2010Paper2010paper
Automating sequence creation from a microarchitecture specificationSubramoni Parameswaran and Ravi Ram2016Poster2016poster
Automating sequence creation from a Microarchitecture specificationSubramoni Parameswaran and Ravi Ram2016Paper2016paper
Automating the formal verification sign-off flow of configurable digital IP’sGiovanni Auditore and Giuseppe Falconeri2019Paper2019paper
Automation of Power On Reset AssertionShang-Wei Tu, Penny Yang, Joydeep Gangopadhyay, and Amol Herlekar2015Paper2015paper
Automation of Reusable Protocol-Agnostic Performance Analysis in UVM EnvironmentsD. P. Carrington, A. J. Pippin, and T. Pertuit2019Paper2019paper
Automation of Reusable Protocol-Agnostic Performance Analysis in UVM EnvironmentsDaniel Carrington, Alan Pippin, and Timothy Pertuit2019Presentation2019presentation
Avoiding Confounding Configurations an RDC Methodology for Configurable DesignsEamonn Quigley, Jonathan Niven, and Kurt Takara2022Poster2022poster
Avoiding Confounding Configurations An RDC Methodology for Configurable DesignsEamonn Quigley, Jonathan Niven, and Kurt Takara2022Paper2022paper
BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering ProblemDebarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, Siddhanth Dhodhi, Spandan Kachhadiya2022Presentation2022presentation
BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering ProblemDebarshi Chatterjee, Ismet Bayraktaroglu, Nikhil Sathe, Kavya Shagrithaya, and Siddhanth Dhodhi2022Paper2022paper
Be a Sequence Pro to Avoid Bad Con SequencesJeff Vance, Jeff Montesano, Mark Litterick, and Jason Sprott2019Presentation2019presentation
Best Practices in Verification PlanningBenjamin Ehlers, Carmen Vargas, and Paul Carzola2013Paper2013paper
Best Practices in Verification PlanningBenjamin Ehlers and Paul Carzola2013Presentation2013presentation
Better Living Through Better Class-Based SystemVerilog DebugRich Edelman, Raghu Ardeishar, and John Amouroux2012Paper2012paper
Better Living Through Better Class-Based SystemVerilog DebugRich Edelman, Raghu Ardeishar, and John Amouroux2012Presentation2012presentation
Beyond UVM: Creating Truly Reusable Protocol LayeringJanick Bergeron, Fabian Delguste, Steve Knoeck, Steve McMaster, Aron Pratt, and Amit Sharma2013Paper2013paper
Beyond UVM: Creating Truly Reusable Protocol LayeringJanick Bergeron2013Presentation2013presentation
Bi-Directional UVM Agents and Complex Stimulus Generation for UDN and UPF PinsChuck McClish2021Paper2021paper
Big Data in Verification: Making Your Engineers SmarterDavid Lacey, Mike McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson2019Paper2019paper
Big Data in Verification: Making Your Engineers SmarterDavid Lacey, Michael McGrath, Alan Pippin, Ed Powell, Ron Thurgood, and Alex Wilson2019Presentation2019presentation
Blending multiple metrics from multiple verification engines for improved productivityDarron May and Darren Galpin2012Paper2012paper
Boost Verification Results by Bridging the Hardware/Software Testbench GapMatthew Ballance2013Paper2013paper
Boost Verification Results by Bridging the Hw/Sw Testbench GapMatthew Ballance2013Presentation2013presentation
BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMSAhmed Yehia2013Poster2013poster
BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMSAhmed Yehia2013Paper2013paper
Bridge the Portable Test and Stimulus to UVM Simulation EnvironmentTheta Yang and Evean Qin2018Paper2018paper
Bridge the Portable Test and Stimulus to UVM Simulation EnvironmentTheta Yang and Evean Qin2018Presentation2018presentation
Bridging the gap between TLM-2.0 AT models and RTL – Experiments and OpportunitiesZhu Zhou, Atul Kwatra, Rajesh Gadiyar, and Paul Heraty2010Paper2010paper
Bringing Constrained Random into SoC SW-driven VerificationAlberto Allara and Fabio Brognara2013Paper2013paper
Bringing Constrained Random into SoC SW-driven VerificationAlberto Allara and Fabio Brognara2013Presentation2013presentation
BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPSPrabal K Bhattacharya, Swapnajit Chakraborti, Scott Little, Donald O’Riordan, and Vaibhav Bhutani2012Paper2012paper
BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPSPrabal K Bhattacharya, Swapnajit Chakraborti, Donald O’Riordan, Vaibhav Bhutani, and Scott Little2012Presentation2012presentation
Bringing Regression Systems into the 21st CenturyDavid Crutchfield and Thom Ellis2014Paper2014paper
Bringing Regression Systems into the 21st CenturyDavid Crutchfield2014Poster2014poster
Bringing Reset Domains and Power Domains together – Confronting issues due to UPF InstrumentationInayat Ali, Abdul Moyeen, Manish Bhati, Manjunatha Srinivas2021Paper2021paper
Bringing UVM to VHDLUVVM2022Presentation2022presentation
Building a Comprehensive Hardware Security MethodologyAnders Nordstrom and Jagadish Nayak2022Presentation2022presentation
Building Portable Stimulus Into Your IP-XACT FlowPetri Karppa, Lauri Matilainen, and Matthew Balance2018Paper2018paper
Building Portable Stimulus Into your IP-XACT FlowPetri Karppa, Lauri Matilainen, and Matthew Ballance2018Presentation2018presentation
C through UVM: Effectively using C based models with UVM based Verification IPAdiel Khan, Chris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile2013Presentation2013presentation
C through UVM: Effectively using C based models with UVM based Verification IPChris Spear, Kevork Dikramanjian, Abhisek Verma, and Senay Haile2013Paper2013paper
Caching Tool Run Results in Large Scale RTL Development ProjectsAshfaq Khan2022Presentation2022presentation
Caching Tool Run Results in Large-Scale RTL Development ProjectsAshfaq Khan2022Paper2022paper
Calling All Checkers: Collaboratively Utilizing SVA In UVM Based SimulationHui K. Zhang2016Paper2016paper
Calling All Checkers: Collaboratively Utilizing SVA in UVM Based SimulationHui C. K. Zhang2016Poster2016poster
CAMEL – A Flexible Cache Model for Cache VerificationYue Liu, Fang Liu, Yunyang Song2022Presentation2022presentation
CAMEL: A Flexible Cache Model for Cache VerificationYue Liu, Fang Liu, and Yunyang Song2022Paper2022paper
Can Formal Outsmart Synthesis: Improving Synthesis Quality of Results through Formal MethodsEldon Nelson2021Paper2021paper
Can My Synthesis Compiler Do That?Stuart Sutherland and Don Mills2014Presentation2014presentation
Can My Synthesis Compiler Do That?Stuart Sutherland and Don Mills2014Paper2014paper
Can You Even Debug a 200M+ Gate Design?Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss2013Poster2013poster
Can You Even Debug a 200M+ Gate Design?Horace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss2013Paper2013paper
Case Study: Low-Power Verification Success Depends on Positive PessimismJohn Decker2011Paper2011paper
Case Study: Power-aware IP and Mixed-Signal VeriLuke Lang2011Paper2011paper
Case Study: Successes and Challenges of Validation Content ReuseMike Chin, Jonathan Edwards, Josh Pfrimmer, and Hooi Jing Tan2022Paper2022paper
Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation)Vikas Billa and Sundar Haran2018Paper2018paper
Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation)Vikas Billa and Sundar Haran2018Presentation2018presentation
Challenges in UVM + Python Random Verification Environment for Digital Signal Processing Datapath DesignShabbar Vejlani and Ashok Chandran2016Presentation2016presentation
Challenges in UVM + Python random verification environment for Digital Signal Processing datapath design.Shabbar Vejlani and Ashok Chandran2016Paper2016paper
Checking Security Path with Formal Verification Tool: New Application DevelopmentJulia Dushina and Joerg Mueller2014Poster2014poster
Checking security path with formal verification tool: new application developmentJulia Dushina, Saumil Shah, Joerg Mueller, and Vincent Reynolds2014Paper2014paper
Chef’s Special – an Efficient Verification Recipe for Maximizing Productivity While Using a Third Party Verification IPVarun S and Bhavik Vyas2012Paper2012paper
Cleaning Out Your Pipes – Pipeline Debug in UVM TestbenchesRich Edelman and Neil Bulman2018Paper2018paper
Cleaning Out Your Pipes – Pipeline Debug in UVM TestbenchesRich Edelman and Neil Bulman2018Poster2018poster
CLOCK DOMAIN CROSSING CHALLENGES IN LATCH BASED DESIGNSMadan Das, PhD, Chris Kwok, and Kurt Takara2018Paper2018paper
Clock Domain Crossing Challenges in Latch Based DesignsMadan Das, Chris Kwok, and Kurt Takara2018Presentation2018presentation
Clock Domain Crossing Verification in Transistor-level DesignHyungjung Seo, KwangSun Kim, YoungRok Choi, Jihwan Kim, and Jong-Bae Lee2019Poster2019poster
Closing Functional and Structural Coverage on RTL Generated by High-Level SynthesisBryan Bowyer2015Poster2015poster
Closing Functional and Structural Coverage on RTL Generated by High-Level SynthesisB. Bowyer2015Paper2015paper
Co-Developing Firmware and IP with PSSM. Ballance2022Paper2022paper
Co-Developing IP and SoC Bring-Up Firmware with PSSMatthew Ballance, Siemens EDA2022Presentation2022presentation
Co-Simulating Matlab/Simulink Models in a UVM EnvironmentNeal Okumura and Glenn Richards2015Paper2015paper
Co-Simulating Matlab/Simulink Models in a UVM EnvironmentNeal Okumura, Paul Yue, and Glenn Richards2015Presentation2015presentation
Coding Guidelines and Code GenerationJohn Aynsley and Dr. Christoph Sühnel2014Poster2014poster
Coherency Verification & Deadlock Detection Using Perspec/Portable StimulusMoonki Jang and Phu Huynh2019Presentation2019presentation
Coherency Verification & Deadlock Detection Using Perspec/Portable StimulusMoonki Jang, Jiwoong Kim, Hyerim Chung, Phu L. Huynh, and Shai Fuss2019Paper2019paper
Combining Simulation with Formal Techniques to Reduce the Overall Verification CycleAneet Agarwal and Gaurav Gupta2010Paper2010paper
Command Line Debug Using UVM SequencesMark Peryer2011Paper2011paper
Common Challenges and Solutions to Integrating a UVM TestbenchFrank Verhoorn and Mike Baird2018Presentation2018presentation
Common Challenges and Solutions to Integrating a UVM Testbench in Place of a Legacy Monolithic Testing EnvironmentFrank Verhoorn and Michael Baird2018Paper2018paper
Comparison of TLM2-Quantum Keeping and TLM+-Resource Modeling with regard to Timing in Virtual PrototypesWolfgang Ecker, Volkan Esen, Rainer Findenigy, Thomas Leitnerz and Michael Velten2011Paper2011paper
Complementing EDA with Meta-Modeling and Code GenerationWolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal2014Paper2014paper
Complementing EDA with Meta-Modelling & Code GenerationWolfgang Ecker, Michael Velten, Leily Zafari, and Ajay Goyal2014Poster2014poster
Complementing EDA with Meta-Modelling and Code GenerationEcker Wolfgang, Michael Velten, Ajay Goyal, and Leily Zafari2014Presentation2014presentation
CompMon: Ensuring Rigorous Protocol Specification and IP ComplianceRobert Adler, Sava Krstic and Erik Seligman2011Paper2011paper
Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain CrossingsYossi Mirsky2017Presentation2017presentation
Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain CrossingsYossi Mirsky B.Sc, M.Sc, MBA2017Paper2017paper
Comprehensive IP to SoC CDC Verification Using Hybrid Data ModelAnwesha Choudhury and Ashish Hari2018Poster2018poster
Comprehensive IP to SoC Clock Domain Crossing Verification Using Hybrid Data ModeAnwesha Choudhury and Ashish Hari2018Paper2018paper
Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-ChipsEllie Burns, Gabriel Chidolue, and Guillaume Boillet2018Presentation2018presentation
Comprehensive Register Description Languages: The case for standardization of RDLs across design domainsDavid C Black and Doug Smith2012Paper2012paper
Comprehensive Systemverilog-Systemc-Vhdl Mixed-Language Design MethodologyRudra Mukherjee, Gaurav Kumar Verma, and Sachin Kakkar2010Paper2010paper
Conditional Delays for Negative Limit Timing Checks in Event Driven SimulationNadeem Kalil and David Roberts2015Paper2015paper
Conditional Delays for Negative Limit Timing Checks in Event Driven SimulationN. Kalil and D. Roberts2015Poster2015poster
Confidently Sign-off Any low-Power Designs without ConsequencesMadhur Bhargava, Jitesh Bansal, and Progyna Khondkar2022Poster2022poster
Confidently Sign-Off Any Low-Power Designs Without ConsequencesMadhur Bharga, Jitesh Bansal and Progyna Khondkar2022Paper2022paper
Configuration Conundrum: Managing Test Configuration with a Bite Sized SolutionKevin Vasconcellos, Jeff McNeal2021Paper2021paper
Configuring Your Resources the UVM Way!Parag Goel, Amit Sharma, and Rajiv Hasija2012Paper2012paper
Configuring Your Resources the UVM Way!Parag Goel, Amit Sharma, and Rajiv Hasija2012Presentation2012presentation
CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITYBin Ju2014Paper2014paper
CONNECTING THE DOTS: APPLICATION OF FORMAL VERIFICATION FOR SOC CONNECTIVITYBin Ju2014Poster2014poster
Connecting UVM with Mixed-Signal DesignIvica Ignjić2017Presentation2017presentation
CONNECTING UVM WITH MIXED-SIGNAL DESIGNIvica Ignjić2017Paper2017paper
Connectivity and BeyondShahid Ikram, Joseph DErrico, Yasmin Farhan, Jim Ellis, and Tushar Parikh2019Presentation2019presentation
Connectivity and BeyondShahid Ikram, Joseph DErrico, Yasmin Farhan, Jim Ellis, and Tushar Parikh2019Paper2019paper
Conquer the Graphics Legacy: Develop the Customized UVM VIP Embedded a Cycle-based C++ Reference ModelRoman Wang2019Poster2019poster
Conscious of Streams Managing Parallel StimulusJeff Wilcox2012Presentation2012presentation
Conscious of Streams: Managing Parallel StimulusJeffrey Wilcox and Stephen D’Onofrio2012Paper2012paper
Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL SynthesisRainer Findenig, Thomas Leitner, and Wolfgang Ecker2011Paper2011paper
CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTIONMartin Fröjd, Adiel Khan, and Jussi Mäkelä2014Paper2014paper
CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTIONJussi Mäkelä, Martin Fröjd, and Adiel Khan2014Presentation2014presentation
CONSTRAINING THE REAL PROBLEM OF FLOATING POINT NUMBER DISTRIBUTIONJussi Mäkelä, Martin Fröjd, and Adiel Khan2014Presentation2014presentation
Context-Aware DFM Rule Analysis and Scoring Using Machine LearningVikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, and Jonathan Ong2018Paper2018paper
Context-Aware DFM Rule Analysis and Scoring Using Machine LearningVikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, and Jonathan Ong2018Poster2018poster
Conversion of Performance Model to Functional ModelH G Pavan Kumar, Sumail Singh Brar, Ashwani Aggarwal, Seonil Brian Choi, Woojoo Space Kim2021Paper2021paper
Coverage Data Exchange is no robbery…or is it?Darron May and Samiran Laha2015Paper2015paper
Coverage Data Exchange is no robbery…or is it?Darron May and Samiran Laha2015Poster2015poster
Coverage Driven Distribution of Constrained Random StimuliRaz Azaria, Amit Metodi, and Marat Teplitsky2015Presentation2015presentation
Coverage Driven Distribution of Constrained Random StimuliMarat Teplitsky, Amit Metodi, and Raz Azaria2015Paper2015paper
Coverage Driven Signoff with Formal Verification on Power Management IPsBaosheng Wang and Xiaolin Chen2016Paper2016paper
Coverage Driven Signoff with Formal Verification on Power Management IPsBaosheng Wang and Xiaolin Chen2016Poster2016poster
Coverage Driven Verification of an Unmodified DUT within an OVM TestbenchMichael Baird2010Paper2010paper
Coverage Models for Formal VerificationXiushan Feng, Xiaolin Chen, and Abhishek Muchandikar2017Paper2017paper
Coverage Models for Formal VerificationXiushan Feng, Xiaolin Chen, and Abhishek Muchandikar2017Poster2017poster
COVERGATE: Coverage ExposedRich Edelman2020Paper2020paper
COVERGATE: Coverage ExposedRich Edelman2020Poster2020poster
Creating a Complete Low Power Verification Strategy using the Common Power Format and UVMRobert Meyer and Joel Artmann2012Paper2012paper
Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation RequirementsDavid Lacey and Ed Powell2018Paper2018paper
Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation RequirementsDavid Lacey and Ed Powell2018Poster2018poster
Cross Coverage of Power StatesVeeresh Vikram Singh and Awashesh Kumar2016Paper2016paper
Data-Driven Verification: Driving the next wave of productivity improvementsLarry Melling, Chris Komar, Sharon Rosenberg, Michael Young, and Hanan Moller2019Presentation2019presentation
De-mystifying synchronization between various verification components by employing novel UVM classesPushpal Nautiyal and Gaurav Chugh2016Poster2016poster
De-mystifying synchronization between various verification components by employing novel UVM classesPushpal Nautiyal and Gaurav Chugh2016Paper2016paper
Deadlock Verification For Dummies – The Easy Way of Using SVA and FormalMark Eslinger, Jeremy Levitt, and Joe Hupcey III2020Poster2020poster
Deadlock Verification For Dummies – The Easy Way Using SVA and FormalMark Eslinger, Jeremy Levitt, and Joe Hupcey III2020Paper2020paper
Dealing with Programmable IP: Where the Rubber Meets the PSS Deployment RoadKarthick Gururaj2020Presentation2020presentation
Debug APIs – next wave of innovation in DV spaceSrinivasan Venkataramanan and Ajeetha Kumari2017Poster2017poster
Debug APIs – next wave of innovation in DV spaceSrinivasan Venkataramanan and Ajeetha Kumari2017Paper2017paper
Debug Challenges in Low-Power Design and VerificationDurgesh Prasad, Madhur Bhargava, Jitesh Bansal, and Chuck Seeley2015Paper2015paper
Debug Challenges in Low-Power Design and VerificationDurgesh Prasad, Madhur Bhargava, Jitesh Bansal, and Chuck Seeley2015Poster2015poster
Debugging Communicating Systems: The Blame Game – Blurring the Line Between Performance Analysis and DebugRich Edelman and Raghu Ardeishar2014Paper2014paper
Debugging Functional Coverage Models Get The Most Out of Your Cover CrossesMennatallah Amer and Amr Hany2018Paper2018paper
Debugging Functional Coverage Models Get The Most Out of Your Cover CrossesMennatallah Amer and Amr Hany2018Presentation2018presentation
Deep Learning for Design and Verification EngineersJohn Aynsley2018Presentation2018presentation
Deep Learning for EngineersJohn Aynsley2019Presentation2019presentation
Deep Predictive Coverage CollectionRajarshi Roy, Chinmay Duvedi, Saad Godil, and Mark Williams2018Paper2018paper
Deep Predictive Coverage CollectionRajarshi Roy, Chinmay Duvedi, Saad Godil, and Mark Williams2018Presentation2018presentation
Defining TLM+Wolfgang Ecker, Volkan Esen, Robert Schwencker, and Michael Velten2010Paper2010paper
DeltaCov: Automated Stimulus Quality Monitoring SystemNimish Girdhar, Srinivas Badam2021Paper2021paper
Demystifying the UVM Configuration DatabaseVanessa R. Cooper and Paul Marriott2014Paper2014paper
Demystifying the UVM Configuration DatabaseVanessa R. Cooper and Paul Marriott2014Poster2014poster
Deploying Customized Solution for Graphics Registers with UVM1.2 RALRoman Wang, Nigel Wang, Lunping Guo, Robert Liu, and Jia Zhu2018Paper2018paper
Deploying Customized Solution for Graphics Registers with UVM1.2 RALRoman Wang, Nigel Wang, Lunping Guo, Robert Liu, and Jia Zhu2018Presentation2018presentation
DEPLOYING PARAMETERIZED INTERFACE WITH UVMWayne Yun and Shihua Zhang2013Poster2013poster
Deploying Parameterized Interface with UVMWayne Yun and Shihua Zhang2013Paper2013paper
Design and Verification of a Multichip Coherence ProtocolShahid Ikram, Isam Akkawi, Richard Kessler, Jim Ellis, and David Asher2015Poster2015poster
Design and Verification of a Multichip Coherence ProtocolShahid Ikram, Isam Akkawi, Richard Kessler, Jim Ellis, and David Asher2015Paper2015paper
Design and Verification of an Image Processing CPU using UVMMilos Becvar and Greg Tumbush2013Paper2013paper
Design and Verification of an Image Processing CPU Using UVMGreg Tumbush and Milos Becvar2013Presentation2013presentation
Design Guidelines for Formal VerificationAnamaya Sullerey2015Presentation2015presentation
Design Guidelines for Formal VerificationAnamaya Sullerey2015Paper2015paper
Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012Eldon Nelson2016Presentation2016presentation
Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012Eldon Nelson M.S. P.E.2016Paper2016paper
Designers Work Less with Quality Formal Equivalence CheckingOrly Cohen, Moran Gordon, Michael Lifshits, Alexander Nadel, and Vadim Ryvchin2010Paper2010paper
Designing Portable UVM Test Benches for Reusable IPsXiaoning Zhang, Baosheng Wang, and Terry Li2015Paper2015paper
Designing Portable UVM Test Benches for Reusable IPsXIAONING ZHANG and BAOSHENG WANG2015Poster2015poster
Designing PSS Environment Integration for Maximum ReuseMatthew Ballance2020Paper2020paper
Designing PSS Environment Integration for Maximum ReuseMatthew Ballance2020Presentation2020presentation
Designing, Verifying and Building an Advanced L2 Cache Sub-System using SystemCThomas Tessier, Dr. Hai Lin, Daniel Ringoen, Eileen Hickey, and Steven Anderson2012Paper2012paper
Designing, Verifying and Building an Advanced L2 Cache Subsystem using SystemCSteve Frank, Thomas Tessier, Dr. Hai Lin, Daniel Ringoen, Eileen Hickey, and Steven Anderson2012Presentation2012presentation
Detecting Circular Dependencies in Forward Progress CheckersSaurabh Chaurdia, Arun Khurana, Naveen Kumar, Aditya Chaurasiya, Yogesh Mahajan, Prasenjit Biswas2021Paper2021paper
Detecting Harmful Race Conditions in SystemC Models Using Formal TechniquesSven Beyer and Dominik Strasser2015Presentation2015presentation
Detecting Harmful Race Conditions in SystemC Models Using Formal TechniquesSven Beyer and Dominik Strasser2015Paper2015paper
Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog AssertionsKelly D. Larson2014Paper2014paper
Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog AssertionsKelly D. Larson2014Presentation2014presentation
Detoxify Your Schedule With A Low-Fat UVM EnvironmentNihar Shah2016Paper2016paper
Detoxify Your Schedule With A Low-Fat UVM Environment A success story on using self-checking stimulus instead of a scoreboard to reduce development time2016Poster2016poster
Developing a Portable Block Testbench and Reusable SOC Verification Scenarios Using IP XACT Based AutomationTaejin Kim, Minjae Kim, Yonghyun Yang, Hyundon Kim, Daewoo Kim, Tae Hee Han, and Seonil Brian Choi2020Presentation2020presentation
Did Power Management Break My CDC Logic? An Integrated Approach to Power Domain and Clock Domain Crossing VerificationAshish Amonkar, Kurt Takara, and Avinash Agrawal2020Presentation2020presentation
Digitizing Mixed Signal VerificationDavid Brownell and Courtney Schmitt2014Paper2014paper
Digitizing Mixed Signal Verification: Digital Verification Techniques Applied to Mixed Signal and Analog Blocks on the LMA ProjectDavid Brownell and Courtney Schmitt2014Presentation2014presentation
Distributed Simulation of UVM TestbenchTheta Yang2016Poster2016poster
Distributed Simulation of UVM TestbenchTheta Yang2016Paper2016paper
Do You Know What Your Assertions Are up To? A New Approach to Safety Critical VerificationLee C. Smith2016Presentation2016presentation
Do You Know What Your Assertions Are Up To? A New Approach to Safety Critical VerificationLee C. Smith2016Paper2016paper
Do You Verify Your Verification Components?Josh Rensch and Neil Johnson2016Poster2016poster
Doing Funny Stuff with the UVM Register Layer: Experiences Using Front Door Sequences, Predictors, and CallbacksJohn Aynsley2017Presentation2017presentation
Doing Funny Stuff with the UVM Register Layer: Experiences Using Front Door Sequences, Predictors, and CallbacksJohn Aynsley2017Paper2017paper
Don’t delay catching bugs: Using UVM based architecture to model external board delaysAmit Paunikar, Saurabh Arya, Vikas Makhija, and Shaily Khare2018Poster2018poster
Don’t delay catching bugs: Using UVM based architecture to model external board delaysAmit Paunikar, Saurabh Arya, Vikas Makhija, and Shaily Khare2018Paper2018paper
Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to SimulationJonathan Bromley2015Presentation2015presentation
Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to SimulationJonathan Bromley2015Paper2015paper
DPI Redux. Functionality. Speed. Optimization.Rich Edelman, Rohit Jain, and Hui Yin2017Paper2017paper
DPI Redux. Functionality. Speed. Optimization.Rich Edelman, Rohit Jain, and Hui Yin2017Presentation2017presentation
DVCon U.S 2021 Proceedings2021Program2021program
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DVS Interface Element – A Novel Approach in Multi-Power Domain, Mixed-Signal Design VerificationVijay Kumar Sankaran, Ji Du, Qingyu Lin, Arumugan A, and Badrinarayan Zanwar2016Paper2016paper
DVS Interface Element—A Novel Approach in Multi-Power Domain, Mixed-Signal Design VerificationShekar Chetput2016Poster2016poster
Dynamic and Scalable OVM Stimulus for Accelerated Functional CoverageMichael J Castle2012Paper2012paper
Dynamic Control Over UVM Register Backdoor HierarchyRoy Vincent, Unnikrishnan Nath, and Ashok Chandran2019Poster2019poster
Dynamic Regression Suite Generation Using Coverage-Based ClusteringShahid Ikram and Jim Ellis2017Presentation2017presentation
Dynamic Regression Suite Generation Using Coverage-Based ClusteringShahid Ikram and Jim Ellis2017Paper2017paper
Dynamically Optimized Test Generation Using Machine LearningRajarshi Roy, Mukhdeep Singh Benipal, Saad Godil2021Paper2021paper
e/eRM to SystemVerilog/UVM: Mind the Gap, But Don’t Miss the TrainAvidan Efody and Michael Horn2012Paper2012paper
e/eRM to SystemVerilog/UVM: Mind the Gap, But Don’t Miss the TrainMichael Horn2012Presentation2012presentation
EARLY SOFTWARE DEVELOPMENT AND VERIFICATION METHODOLOGY USING HYBRID EMULATION PLATFORMWoojoo Kim, Haemin Park, Hyundon Kim, Seonil Brian Choi, and SukWon Kim2017Paper2017paper
EASI2L: A Specification Format for Automated Block Interface Generation and VerificationChintan Kaur, Ravi Narayanaswami, and Richard Ho2016Paper2016paper
Easier SystemVerilog with UVM: Taming the BeastJohn Aynsley2012Paper2012paper
Easier SystemVerilog with UVM: Taming the BeastJohn Aynsley2012Presentation2012presentation
Easier UVM – Coding Guidelines and Code GenerationJohn Aynsley and Dr. Christoph Sühnel2014Paper2014paper
Easier UVM for Functional Verification by Mainstream UsersJohn Aynsley2011Paper2011paper
Easy Steps Towards Virtual Prototyping using the SystemVerilog DPIDave Rich2013Paper2013paper
Easy uvm_config_db use: A simplified and reusable uvm_config_db methodology for environment developers and test writersBob Oden2015Paper2015paper
Easy uvm_config_db use: A simplified and reusable uvm_config_db methodology for environment developers and test writersBob Oden2015Poster2015poster
Effects of Abstraction in Stimulus Generation of Layered Protocols within OVMJosh Rensch and Jesse Prusi2010Paper2010paper
Efficient and Exhaustive Floating Point Verification Using Sequential Equivalence CheckingTravis W. Pouarz and Vaibhav Agrawal2017Paper2017paper
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Efficient Bug-Hunting Techniques Using Graph-Based Stimulus ModelsNguyen Le and Mike Andrews2016Presentation2016presentation
Efficient Bug-Hunting Techniques Using Graph-Based Stimulus ModelsNguyen Le and Mike Andrews2016Paper2016paper
Efficient distribution of video frames to achieve better throughputBhavik Vyas and Suruchi Jain2012Paper2012paper
Efficient hierarchical low power verification of custom designs using static and dynamic techniquesHimanshu Bhatt, Archanna Srinivasan, and Chong Lee Kuay2019Poster2019poster
Efficient Methods for Display Power Estimation & VisualizationSrikanth Reddy Rolla and Aakash Modi2020Poster2020poster
Efficient Methods for Display Power Estimation and VisualizationSrikanth Reddy Rolla and Aakash Modi2020Paper2020paper
Efficient SCE-MI Usage to Accelerate TBA PerformancePonnambalam Lakshmanan, Prashantkumar Ravindra, and Rajarathinam Susaimanickam2017Paper2017paper
Efficient Simulation Based Verification by ReorderingChao Ya and Kevin Jones2010Paper2010paper
Efficient SoC Level Mixed Signal Frontend Verification using Wreal ModelsAnu Marisha, Nayana Prakash, Udit Kumar, Rajesh Tiwari, and Vijay Kumar Birange2014Paper2014paper
Efficient SoC Level Mixed Signal Frontend Verification using Wreal ModelsAnu Marisha, Nayana Prakash, Udit Kumar, and Rajesh Tiwari2014Presentation2014presentation
Efficient Standard Co-Emulation Modeling Interface (SCE-MI) Usage to Accelerate TBA PerformancePonnambalam Lakshmanan2017Presentation2017presentation
EMULATION BASED FULL CHIP LEVEL LOW POWER VALIDATION AT PRE-SILICON STAGEKyoungmin Park, Jaegeun Song, Hyundon Kim, Seonil Brian Choi, and Suk Won Kim2017Paper2017paper
Emulation Based Power and Performance Workloads on ML NPUsPragati Mishra, Ritu Suresh, Issac Zacharia, and Jitendra Aggarwal2022Poster2022poster
Emulation Based Power and Performance Workloads on ML NPUsPragati Mishra, Ritu Suresh, Issac Zacharia, and Jitendra Aggarwal2022Paper2022paper
Emulation Testbench Optimizations for better Hardware Software Co-ValidationVijayakrishnan Rousseau, Suresh Balasubramanian, Srikanth Reddy Rolla, and Mohamed Saheel Nandikotkur Hussainsaheb2019Poster2019poster
End to End Formal Verification Strategies for IP VerificationJacob Ryan Maas, Nirabh Regmi, Ashish Kulkarni, and Krishnan Palaniswami2017Paper2017paper
End to End Formal Verification Strategies for IP VerificationJacob Ryan Maas, Nirabh Regmi, Krishnan Palaniswami, and Ashish Kulkarni2017Poster2017poster
Engineered SystemVerilog ConstraintsJeremy Ridgeway2015Presentation2015presentation
Engineered SystemVerilog ConstraintsJeremy Ridgeway2015Paper2015paper
Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software VerificationVictor Besyakov2022Poster2022poster
Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software VerificationVictor Besyakov2022Paper2022paper
Environment for efficient and reusable SystemC module level verificationFlavia Gontia2014Paper2014paper
Environment for efficient and reusable SystemC module level verificationFlavia Gonția2014Presentation2014presentation
Equivalence Validation of Analog Behavioral ModelsHardik Parekh, Manish Kumar Karna, Mohit Jain, Atul Pandey, and Sandeep Mittal2014Paper2014paper
Equivalence Validation of Analog Behavioral ModelsHardik Parekh, Manish Kumar Karna, Mohit Jain, Atul Pandey, and Sandeep Mittal2014Poster2014poster
Equivalence Validation of Analog Behavioral ModelsManish Kumar Karna, Hardik Parekh, Mohit Jain, Atul Pandey, and Sandeep Mittal2014Poster2014poster
Eradicating X-bugs and Achieving Higher Design Quality Using Static X-propagation Sign-offSanjay Thatte, Andrew Guyler, Nikhil Rahagude, and Savitha Raghunath2020Presentation2020presentation
Error Injection in a Subsystem Level Constrained Random UVM TestbenchJ. Ridgeway and H. Nguyen2018Paper2018paper
Error Injection in a Subsystem Level Constrained Random UVM TestbenchJeremy Ridgeway and Hoe Nguyen2018Presentation2018presentation
Error Injection: When Good Input Goes BadKurt Schwartz and Tim Corcoran2017Paper2017paper
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Estimating Power Dissipation of End-User Application on RTLMagdy El-Moursy2022Presentation2022presentation
Evaluating the Feasibility of a RISC V Core for Real Time Applications Using a Virtual PrototypeJ. Santana , G. Pachiana, T. Markwirth, C. Sohrmann, B. Fischer, M. Matschnig 2022Presentation2022presentation
Evaluating the Feasibility of a RISCV Core for Real-Time Applications Using a Virtual PrototypeJuan Santana, Gabriel Pachiana, Thomas Markwirth, Christoph Sohrmann, Bernhard Fischer, and Martin Matschnig2022Paper2022paper
Every Cloud – Post-Silicon Bug Spurs Formal Verification AdoptionBlaine Hsieh, Stewart Li, and Mark Eslinger2015Presentation2015presentation
Every Cloud – Post-Silicon Bug Spurs Formal Verification AdoptionBlaine Hsieh, Stewart Li, and Mark Eslinger2015Paper2015paper
Evolution of CDC recipe: Learning through real case studies and methodology improvementsAmit Kulkarni, Suhas DS, Deepmala Sachan2021Paper2021paper
Evolution of Triage: Real-time Improvements in Debug ProductivityGordon Allan2016Paper2016paper
Exhaustive Equivalence Checking on AMD’s Next-generation Microprocessor CoreBaosheng Wang, Brian McMinn, Borhan Roohipour, Ashok Venkatachar, Arun Chandra, Richard Bartolotti, and Lerzan Celikkanat2011Paper2011paper
Exhaustive Latch Flow – Through Verification with Formal MethodsBaosheng Wang, Sean Ater, Baris Piyade, Brian McMinn, and Borhan Roohipour2012Presentation2012presentation
Exhaustive Latch Flow-through Verification with Formal MethodsBaosheng Wang, Sean Ater, Baris Piyade, Brian McMinn, and Borhan Roohipour2012Paper2012paper
Experience with OVM-Based Mixed-Signal Verification of the Impedance Calibration Block for a DDR InterfaceHarry Wang, Wessam El-Naji, and Kenneth Bakalar2012Paper2012paper
Experience with OVM-Based Mixed-Signal Verification of the Impedance Calibration Block for a DDR InterfaceHarry Wang, Wessam El-Naji, and Kenneth Bakalar2012Presentation2012presentation
Experiences in Migrating a Chip-Level Verification Environment from UVM EA to UVM 1.1Ashish Kumar, Dave Stang, Dudyala Sasidhar, S, Manikandan, and Thirumalai Srishan2012Paper2012paper
Experiences in Migrating a Chip-Level Verification Environment from UVM-EA to UVM-1.xAshish Kumar, S Manikandan, Sasidhar Dudyala, Srishan Thirumalai, and Dave Stang2012Presentation2012presentation
Experiencing Checkers for a Cache Controller DesignBen Cohen, Srinivasan Venkataramanan, Ajeetha Kumari, and Lisa Piper2010Paper2010paper
Exquisite modeling of verification IP: Challenges and RecommendationsAnuradha Tambad, Subashini Rajan, Shivani Upasani, Prashanth Srinivasa, Imran Ali, and Adiel Khan2012Paper2012paper
Exquisite Modeling of VIPAdiel Khan, Anuradha Tambad, Imran Ali, Prashanth Srinivasa, Shivani Upasani, and Subashini Rajan2012Presentation2012presentation
Extendable Messaging Techniques for Debugging and Analyzing UVM Testbench Structure and Transaction FlowJun Zhao, Bindesh Patel, and Rex Chen2013Presentation2013presentation
Extendable Messaging Techniques for Debugging and Analyzing UVM Testbench Structure and Transaction FlowJun Zhao, Bindesh Patel, and Rex Chen2013Paper2013paper
Extension of the Power-Aware IP Reuse Approach to ESLAntonio Genov, Loic Leconte, Fran ç ois Verdier2022Presentation2022presentation
Fabric VerificationGalen Blake and Steve Chappell2012Presentation2012presentation
Failure Triage: The Neglected Debugging ProblemSean Safarpour, Evean Qin, Yu-Shen Yang, and Brian Keng2012Paper2012paper
Failure Triage: The Neglected Debugging ProblemSean Safarpour, Evean Qin, Yu-Sheng Yang, and Brian Keng2012Presentation2012presentation
Fast Track Formal Verification SignoffMandar Munishwar, Xiaolin Chen, Arunava Saha, and Sandeep Jana2018Poster2018poster
Fast Track Formal Verification SignoffMandar Munishwar, Xiaolin Chen, Arunava Saha, and Sandeep Jana2018Paper2018paper
Fault-Effect Analysis on Multiple Abstraction Levels in Hardware ModelingB-A. Tabacaru, M. Chaari, W. Ecker, T. Kruse, and C. Novello2016Presentation2016presentation
Fault-Effect Analysis on Multiple Abstraction Levels in Hardware ModelingBogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, and Cristiano Novello2016Paper2016paper
Finding a Needle in a Haystack: A Novel Log Analysis Method with Test Clustering in Distributed SystemJin Choi2022Presentation2022presentation
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Finding Hidden Bugs In Deep Cycles: Advanced Debug Methodologies for Software-first System ValidationYoucef Qassid and Andy Jolley2022Presentation2022presentation
Finding the Last Bug in a CNN DMA UnitBruno Lavigueur, Dean Ke, Eric Rao, Fergus Casey, Achin Mittal, Pallavi Kumari, Michael Thompson, and Roger Sabbagh2020Paper2020paper
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First Reports from the UVM Trenches: User-friendly, Versatile and Malleable, or just the Emperor’s New Methodology?Jonathan Bromley2011Paper2011paper
Flattening the UVM Learning Curve Automated Solutions for DSP Filter VerificationAvinash Lakshminarayana, Eric Jackowski, Eric Cigan, and Mark Lin2022Paper2022paper
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Flexible Checker: A one-stop shop for all your checkers and a methodology for elastic scoreboardingSaad Zahid, Chandra Veedhi, and Sumit Dhamanwala2019Poster2019poster
Flexible Indirect Registers with UVMUwe Simm2017Presentation2017presentation
Fnob: Command Line-Dynamic Random GeneratorHaoxiang Hu, Tuo Wang2022Presentation2022presentation
Fnob: Command Line-Dynamic Random GeneratorHaoxiang Hu and Tuo Wang2022Paper2022paper
Formal Architectural Specification and Verification of A Complex SOCShahid Ikram, Isam Akkawi, David Asher, and Jim Ellis2018Presentation2018presentation
FORMAL ARCHITECUTRAL SPECIFICATION AND VERIFICATION OF A COMPLEX SOCShahid Ikram, Isam Akkawi, David Asher, and Jim Ellis2018Paper2018paper
Formal Bug Hunting with “River Fishing” TechniquesMark Eslinger and Ping Yeung2019Presentation2019presentation
Formal Bug Hunting with “River Fishing” TechniquesMark Eslinger and Ping Yeung2019Paper2019paper
Formal Methods to Verify the Power Manager for an Embedded Multiprocessor ClusterKesava R. Talu2010Paper2010paper
Formal Proof for GPU Resource ManagementJia Zhu, Chuanqin Yan, and Nigel Wang2017Presentation2017presentation
Formal Proof for GPU Resource ManagementJia Zhu, Chuanqin Yan, and Nigel Wang2017Paper2017paper
Formal Verification BootcampMike Bartley2019Presentation2019presentation
Formal Verification by The Book: Error Detection and Correction CodesK. Devarajegowda, V. Hiltl, T. Rabenalt, D. Stoffel, W. Kunz, and W. Ecker2020Presentation2020presentation
Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug HuntPing Yeung, Mark Eslinger, Jin Hou2021Paper2021paper
Formal Verification in the Real WorldJonathan Bromley and Jason Sprott2018Presentation2018presentation
Formal Verification of Connections at SoC-levelPenny Yang, Prasun Das, Yuya Kao, and Mingchu Kuo2018Paper2018paper
Formal Verification of Connections at SoC-levelPenny Yang, Prasun Das, Yuya Kao, and Mingchu Kuo2018Presentation2018presentation
FORMAL VERIFICATION OF FLOATING-POINT HARDWARE WITH ASSERTION-BASED VIPRavi Ram, Adam Elkins, Adnan Pratama, Sasa Stamenkovic, Sven Beyer, and Sergio Marchese2018Paper2018paper
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Formal verification of Macro-op cache for Arm Cortex-A77, and its successor CPUVaibhav Agrawal2020Paper2020paper
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Formal Verification of Silicon for Software Defined NetworkingSaurabh Shrivastava, Keqin Han, Anh Tran, Chirag Agarwal, Ankit Saxena, Achin Mittal, Anshul Jain, and Roger Sabbagh2018Paper2018paper
Formal Verification on Deep Learning Instructions of GPUJian (Jeffrey) Wang and Jia Zhu2018Paper2018paper
Formal Verification Tutorial Breaking Through the Knowledge BarrierSean Safarpour, Iain Singleton, Shaun Feng, Syed Suhaib, and Mandar Munishwar2018Presentation2018presentation
FPGA-based Clock Domain Crossing Validation for Safety-Critical DesignsAlexander Gnusin2019Paper2019paper
FPGA-based Clock Domain Crossing Validation for Safety-Critical DesignsAlexander Gnusin2019Presentation2019presentation
Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPFProgyna Khondkar, Ping Yeung, Gabriel Chidolue, Joe Hupcey, Rick Koster, and Madhur Bhargava2017Paper2017paper
Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPFProgyna Khondkar, Ping Yeung, Gabriel Chidolue, Joe Hupcey, Rick Koster, and Madhur Bhargava2017Poster2017poster
From Spec to Verification Closure: a case study of applying UVM-MS for first pass success to a complex Mixed-Signal SoC designNeyaz Khan and Yaron Kashai2012Paper2012paper
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From the Magician’s Hat: Developing a Multi-Methodology PCIe Gen2 VIPAmit Sharma, Abhisek Verma, Varun S., and Anoop Kumar2011Paper2011paper
fsim_logic – A VHDL type for testing of FLYTRAPJoanne E. DeGroat, Ph.D.2013Paper2013paper
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Full Flow Clock Domain Crossing – From Source To SiMark Litterick2016Presentation2016presentation
Full Flow Clock Domain Crossing – From Source to SiM. Litterick2016Paper2016paper
Fully Automated Functional Coverage ClosureManohar Kodi, Sagar Sudam Patil, and Ranjith Nair2019Paper2019paper
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Fully Hierarchical CDC Analysis Using Comprehensive CDC Meta DatabaseYoungchan Lee, Youngsik Kim, Soenil Brian Choi, and Vikas Sachdeva2019Paper2019paper
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Fun with UVM Sequences – Coding and DebuggingRich Edelman2019Paper2019paper
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Functional Coverage – without SystemVerilog!Alan Fitch and Doug Smith2010Paper2010paper
Functional Coverage Collection for Analog Circuits – Enabling Seamless Collaboration between Design and VerificationZ. Ye, H. Lin and A. M. Khan2016Paper2016paper
Functional Coverage Collection for Analog Circuits –Enabling Seamless Collaboration between Design and VerificationZhipeng Ye, Honghuang Lin and Asad Khan2016Presentation2016presentation
FUNCTIONAL COVERAGE OF REGISTER ACCESS VIA SERIAL BUS INTERFACE USING UVMDarko M. Tomušilovic2017Poster2017poster
Functional Coverage of Register Access via Serial Bus Interface using UVMD. M. Tomušilović2017Paper2017paper
Functional coverage-driven verification with SystemC on multiple level of abstractionChristoph Kuznik and Wolfgang M¨uller2011Paper2011paper
Functional Safety Verification For ISO 26262Kevin Rich, Shekhar Mahatme, and Meirav Nitzan2018Presentation2018presentation
Generation of Constraint Random Transactions for Verification of Mixed-Signal BlocksAlexander W. Rath, Sebastian Simon, Volkan Esen, and Wolfgang Ecker2014Paper2014paper
Generic Programming in SystemVerilogMark Glasser2016Paper2016paper
Generic SCSI-Based Host Controller Verification Framework Using SystemVerilogMohamed Rayan, Mohamed Samy, Haytham Ashour, Ashraf Salem2021Paper2021paper
Getting Rid of False Errors when Verifying LSI Designs Including Non-DeterminismMatthieu Parizy and Hiroaki Iwashita2011Paper2011paper
Git for Hardware DesignersJeffery Scott and Sanjeev Singh2015Paper2015paper
GIT for Hardware DesignersJeffery Scott and Sanjeev Singh2015Poster2015poster
Goldilocks and System Performance ModelingRich Edelman and Shashi Bhutada2015Paper2015paper
Goldilocks and System Performance Modelling A SystemVerilog Adaptive Rate Control (ARC) Stimulus Generation MethodologyRich Edelman and Shashi Bhutada2015Poster2015poster
GoldMine: Automatic Assertion Generation and Coverage Closure in Design ValidationDavid Sheridan, Lingyi Liu, and Shobha Vasudevan2011Paper2011paper
Graph-IC VerificationDennis Ramaekers and Grégory Faux2012Paper2012paper
Graph-IC VerificationGregory Faux and Dennis Ramaekers2012Presentation2012presentation
Graphical Topology Info Structure for Constrained Random Verification in SoC/Subsystem TestsEvean Qin, Richard Bell, and David Chen2019Presentation2019presentation
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Guaranteed Vertical Reuse – C Execution In A UVM EnvironmentRachida El Idrissi and Alain Gonier2013Presentation2013presentation
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Hardware Acceleration for UVM Based CLTsMohamed Saheel, Rohith M. S., and Andrew Tan2020Presentation2020presentation
Hardware Emulation: ICE vs VirtualLauro Rizzatti2016Presentation2016presentation
Hardware Trojan Design and Detection with Formal Verification to Deep Neural NetworkSi-Han Chen, Yu-Ting Huang, Yi-Chun Kao, Yean-Ru Chen, Shang-Wei Lin, Chia-I Chen2021Paper2021paper
Hardware/Software co-verification using Specman and SystemC with TLM portsHorace Chan and Brian Vandegriend2012Paper2012paper
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Hierarchical UPF: Uniform UPF across FE & BEDipankar Narendra Arya, Balaji Vishwanath Krishnamurthy, Aditi Nigam, Tahir Ali2022Presentation2022presentation
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High-Level Synthesis Walks the Talk: Synthesizing a Complete Graphics Processing ApplicationThomas Bollaert2011Paper2011paper
High-Speed Interface IP Validation based on Virtual Emulation PlatformJaehun Lee, DaeSeo Cha, and Sungwook Moon2019Paper2019paper
High-Speed Interface IP Validation based on Virtual Emulation PlatformJaehun Lee, Daeseo Cha, and Sungwook Moon2019Presentation2019presentation
Highly Configurable UVM Environment for Parameterized IP VerificationHongLiang Liu and Karl Whiting2015Paper2015paper
Highly Configurable UVM Environment for Parameterized IP VerificationHongLiang Liu and Karl Whiting2015Poster2015poster
Holistic Approach to IO Timing Verification Using Portable Stimulus and AssertionsAmitesh Khandelwal and Praveen Kumar2018Poster2018poster
Holistic Approach to IO Timing Verification Using Portable Stimulus and AssertionsAmitesh Khandelwal and Praveen Kumar2018Paper2018paper
Holistic Automated Code Generation: No Headache with Last-Minute ChangesKlaus Strohmayer and Norbert Pramstaller2012Paper2012paper
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Hopscotch: A Scalable Flow-Graph Based Approach to Formally Specify and Verify Memory-Tagged Store Execution in Arm CPUsAbhinav Sethi, Madhu Iyer, Sai Komaravelli, and Vikram Khosa2022Paper2022paper
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How Do You Verify Your Verification Components?Josh Rensch and Neil Johnson2016Paper2016paper
How Far Can You Take UVM Code Generation and Why Would You Want To?John Aynsley2016Presentation2016presentation
How Far Can You Take UVM Code Generation and Why Would You Want To?John Aynsley2016Paper2016paper
How HLS and SystemC is Delivering on its Promise of Design and Verification ProductivityStuart Swan, Mike Meredith, Matthew Bone, and Rangharajan Venkatesan2020Presentation2020presentation
How I Learned to Stop Worrying and Love Benchmarking Functional Verification!Mike Bartley2012Presentation2012presentation
How I Learned to Stop Worrying and Love Benchmarking Functional Verification!Mike Bartley and Mike Benjamin2012Paper2012paper
How to Avoid the Pitfalls of Mixing Formal and Simulation CoverageMark Eslinger, Joseph V Hupcey III, and Nicolae Tusinschi2022Paper2022paper
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How to Create Reusable Portable Testing and Stimulus Standard (PSS) Verification IPSharon Rosenberg2019Poster2019poster
How to Kill 4 Birds with 1 Stone: Using Formal Verification to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software SpecificationsSaurabh Shrivastava, Kavita Dangi, Darrow Chu, and Mukesh Sharma2013Presentation2013presentation
How to Kill 4 Birds with 1 Stone: Using Formal Verification to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software SpecificationsSaurabh Shrivastava, Kavita Dangi, Darrow Chu, and Mukesh Sharma2013Paper2013paper
How to Overcome Editor Envy: Why Can’t My Editor Do That?Dillan Mills, Chuck McClish2021Paper2021paper
How to Stay Out of the News with ISO26262-Compliant VerificationCharles Battikha and Doug Smith2018Presentation2018presentation
How to Succeed Against Increasing Pressure: Automated Techniques for Unburdening Verification EngineersJames Pascoe and Steve Hobbs2013Presentation2013presentation
How to Succeed Against Increasing Pressure: Automated Techniques for Unburdening Verification EngineersJames Pascoe, Pierre Kuhn, and Steve Hobbs2013Paper2013paper
How to test the whole firmware/software when the RTL can’t fit the emulatorHorace Chan and Byron Watt2019Paper2019paper
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How UPF 3.1 Reduces the Complexities of Reusing PA MacrosMadhusudhana Reddy Lebaka, Abraham Guizer, and Progyna Khondkar2020Poster2020poster
How UPF 3.1 Reduces the Complexities of Reusing Power Aware MacrosMadhusudhana Reddy Lebaka, Abraham Guizer, and Progyna Khondkar2020Paper2020paper
HSI Issues – Fake News or Not? How Hardware/Software Interface Impacts Tape-OutsGary Stringham, Rich Weber, and Jamsheed Agahi2020Presentation2020presentation
Hybrid Approach to Testbench and Software Driven Verification on EmulationDebdutta Bhattacharya and Ayub Khan2018Paper2018paper
Hybrid Approach to Testbench and Software Driven Verification on EmulationDebdutta Bhattacharya and Ayub Khan2018Poster2018poster
Hybrid Emulation: Accelerating Software Driven Verification and DebugIssac P Zacharia and Jitendra Aggarwal2022Poster2022poster
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I created the Verification GapRam Narayan and Tom Symons2015Paper2015paper
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I’m Still In Love With My X! (but, do I want my X to be an optimist, a pessimist, or eliminated?)Stuart Sutherland2013Paper2013paper
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IDEs Should be Available to Hardware Engineers Too!Syed Daniyal Khurram and Horace Chan2018Paper2018paper
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IEEE-Compatible UVM Reference Implementation and Verification ComponentsJustin Refice, Mark Strickland, Mark Peryer, Uwe Simm, and Srivatsa Vasudevan2018Presentation2018presentation
Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed ManipulationEldon Nelson M.S. P.E.2017Paper2017paper
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Improving Software Testing Speed by 100X with SystemC Virtualization in IoT DevicesDavid Barahona, Motaz Thiab, Isael Díaz, Joakim Urdahl, and Milica Orlandic2021Paper2021paper
Improving the UVM Register Model: Adding Product Feature based API for Easier Test ProgrammingKrishnan Balakrishnan, Courtney Fricano, and Kaushal Modi2016Poster2016poster
Improving the UVM Register Model: Adding Product Feature based API for Easier Test ProgrammingKrishnan Balakrishnan, Courtney Fricano, and Kaushal Modi2016Paper2016paper
Improving Verification Predictability and Efficiency Using Big DataDarron May2018Poster2018poster
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Incomplete Low-Power Verification Flow & the oncoming Internet of Things (IoT) Tsunami!Neyaz Khan and Kamran Haqqani2016Paper2016paper
Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning CoffeeThomas Ellis2017Paper2017paper
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Innovative Uses of SystemVerilog Bind Statements within Formal VerificationXiushan Feng and Christopher Starr2022Paper2022paper
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Integration of HDL Logic inside SystemVerilog UVM based Verification IPAleksandra Panajotu2020Paper2020paper
Integration of HDL Logic inside SystemVerilog UVM based Verification IPAleksandra Panajotu2020Poster2020poster
Interface Centric UVM Acceleration for Rapid SOC VerificationJiwoong Kim, Yoona Lhim, Hyungjin Park, Hyunsun Ahn, and Seonil Brian Choi2020Presentation2020presentation
Interfacing Python with a Systemverilog Test BenchLakshay Grover and Kaushal Modi2019Poster2019poster
INTERPRETING UPF FOR A MIXED-SIGNAL DESIGN UNDER TESTKenneth Bakalar and Eric Jeandeau2014Paper2014paper
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Introducing your team to an IDES. Dawson and M. Ballance2019Poster2019poster
Introduction to the 5 Levels of RISC-V Processor VerificationSimon Davidmann and Lee Moore2022Presentation2022presentation
Introspection Into Systemverilog Without Turning It Inside OutDave Rich2016Poster2016poster
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IP-XACT based SoC Interconnect Verification AutomationYoungRae Cho, YoungSik Kim, and Seonil Brian Choi2018Paper2018paper
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IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 90 minutes!Nikita Gulliya, Neena Chandawale, and Anupam Bakshi2022Presentation2022presentation
Ironic But Effective: How Formal Analysis Can Perfect Your Simulation ConstraintsPenny Yang, Jin Hou, Yuya Kao, Nan-Sheng Huang, Ping Yeung, and Joe Hupcey2017Presentation2017presentation
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Is It a Software Bug? Is It a Hardware Bug?Horace Chan, Mame Maria Mbaye, and Sim Ang2022Paper2022paper
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Is Power State Table (PST) Golden?Ankush Bagotra, Neha Bajaj, and Harsha Vardhan2012Presentation2012presentation
Is Power State Table Golden?Harsha Vardhan, Ankush Bagotra, and Neha Bajaj2012Paper2012paper
Is Specman Still Relevant? Using UVM-ML to Take Advantage of Multiple Verification LanguagesTimothy Pertuit, David Lacey, and Doug Gibson2018Poster2018poster
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Is the simulator behavior wrong for my SystemVerilog code?Weihua Han2017Paper2017paper
Is The Simulator Behavior Wrong With My SystemVerilog CodeWeihua Han2017Presentation2017presentation
Is Your Hardware Dependable?DARPA, AMD, Arm Research, and Synopsys2022Presentation2022presentation
Is your Power Aware design really x-aware?Durgesh Prasad and Jitesh Bansal2014Paper2014paper
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ISO 26262 Dependent Failure Analysis using PSSMoonki Jang, Jiwoong Kim, and Dongjoo Kim2020Paper2020paper
ISO 26262 Dependent Failure Analysis Using PSSMoonki Jang2020Presentation2020presentation
It Should Just Work! Tips and Tricks for Creating Flexible, Vendor Agnostic Analog Behavioral ModelsChuck McClish2020Presentation2020presentation
It’s Been 24 Hours –Should I Kill My Formal Run?Mark Eslinger, Jin Hou, Joe Hupcey III, and Jeremy Levitt2019Presentation2019presentation
JESD204B Deterministic Latency Verification with UVM Constrained Random ApproachesGirish Nadiger and Ashok Chandran2016Poster2016poster
JESD204B Deterministic Latency Verification with UVM Constrained Random ApproachesGirish Nadiger and Ashok Chandran2016Paper2016paper
Jump start your RISCV project with OpenHWMike Thompson, Jingliang (Leo) Wang, Steve Richmond, Lee Moore, David McConnell, Greg Tumbush2021Paper2021paper
Jump-Start Portable Stimulus Test Creation with SystemVerilog ReuseMatthew Ballance2016Poster2016poster
Jump-Start Portable Stimulus Test Creation with SystemVerilog ReuseMatthew Ballance2016Paper2016paper
Jump-Start Software-Driven Hardware Verification with a Verification FrameworkMatthew Ballance2015Poster2015poster
Jump-Start Software-Driven Hardware Verification with a Verification FrameworkMatthew Ballance2015Paper2015paper
Just do it! Who cares if a Structural Analysis tool is using Formal VerificationScott Aron Bloom2018Presentation2018presentation
Keeping Score, Part 1 of 2 – Architectural Considerations for Scoreboard DesignGordon Allan2012Paper2012paper
Keeping Up with Chip — the Proposed SystemVerilog 2012 Standard Makes Verifying Ever-increasing Design Complexity More EfficientStuart Sutherland and Tom Fitzpatrick2012Paper2012paper
Keeping Up with Chip — the Proposed SystemVerilog 2012 Standard Makes Verifying Ever-increasing Design Complexity More EfficientStuart Sutherland2012Presentation2012presentation
Keeping Your Sequences RelevantNicholas Zicha and Eric Combes2017Paper2017paper
Key Gochas in implementing CDC for various Bus ProtocolsNikita Gulliya, Mukesh Kumar Singh, and Abhishek Bora2020Paper2020paper
Key Gochas in implementing CDC for various Bus ProtocolsNikita Gulliya, Mukesh Kumar Singh, and Abhishek Bora2020Poster2020poster
Lay it On Me: Creating Layered ConstraintsBryan Morris2021Paper2021paper
Leaping Left: Seamless IP to SoC Hand offSwetha Thiagarajan, Rashika Madan, Hiran Morar, and Sangeivi Sivagnanasundaram2022Presentation2022presentation
Leaping Left: Seamless IP to SoC Hand-offSwetha Thiagarajan, Rashika Madan, Hiran Morar, and Sangeivi Sivagnanasundaram2022Paper2022paper
Learning From Advanced Hardware Verification for Hardware Dependent SoftwareSimond Davidmann and Duncan Graham2014Paper2014paper
Left Shift Mechanism to Mitigate Gate Level Asynchronous Design ChallengesKotha Kavya and Sinha Rohit Kumar2022Poster2022poster
Left Shift Mechanism to Mitigate Gate Level Asynchronous Design ChallengesRohit Kumar Sinha and Kavya Kotha2022Paper2022paper
Lessons from the field – IP/SoC integration techniques that workDavid Murray and Sean Boylan2013Paper2013paper
Lessons from the field IP/SoC integration techniques that workDavid Murray2013Presentation2013presentation
Let’s be Formal While Talking About Verification Quality: A Novel Approach to Qualify Assertion Based VIPsSachin Scaria, Surinder Sood, and Erik Seligman2018Paper2018paper
Let’s DisCOVER Power StatesPankaj Kumar Dwivedi, Amit Srivastava, and Veeresh Vikram Singh2015Paper2015paper
Lets be Formal While Talking About Verification Quality: A Novel Approach Of Qualifying Assertion Based IPsSurinder Sood, Sachin Scaria, and Erik Seligman2018Presentation2018presentation
Lets disCOVER Power StatesPankaj Kumar Dwivedi, Amit Srivastava, and Veeresh Vikram Singh2015Poster2015poster
Leveraging Formal to Verify SoC Register MapAbdul Elaydi and Jose Barandiaran2014Paper2014paper
Leveraging Formal to Verify SoC Register MapAbdul Elaydi and Jose Barandiaran2014Presentation2014presentation
Leveraging IP-XACT standardized IP interfaces for rapid IP integrationDavid Murray and Simon Rance2014Paper2014paper
Leveraging IP-XACT Standardized IP Interfaces for Rapid IP IntegrationDavid Murray2014Presentation2014presentation
Leveraging more from GLS: Using metric driven GLS stimuli to boost Timing VerificationSowmya Ega, Richardson Jeyapaul, and Kunal Jani2018Paper2018paper
Leveraging more from GLS: Using metric driven GLS stimuli to boost timing verificationSowmya Ega, Richardson Jeyapaul, and Kunal Jani2018Presentation2018presentation
Leveraging Virtual Platform ESL and TLM SystemVerification in RTL using UVMAshok Mehta, Albert Chiang, and Wei-Hua Han2012Paper2012paper
Lies, Damned Lies, and CoverageMark Litterick2015Paper2015paper
Lies, Damned Lies, and CoverageMark Litterick2015Presentation2015presentation
Low Power Apps (Shaping the Future of Low Power Verification)Awashesh Kumar, Madhur Bhargava, Vinay Kumar Singh, and Pankaj Gairola2018Presentation2018presentation
Low Power Apps: Shaping the Future of Low Power VerificationAwashesh Kumar, Madhur Bhargava, Vinay Singh, and Pankaj Gairola2018Paper2018paper
Low Power Coverage: The Missing Piece in Dynamic SimulationProgyna Khondkar, Gabriel Chidolue, and Ping Yeung2018Paper2018paper
Low Power Coverage: The Missing Piece in Dynamic SimulationProgyna Khondkar2018Presentation2018presentation
Low Power SoC Verification: IP Reuse and Hierarchical Composition using UPFAmit Srivastava, Rudra Mukherjee, Erich Marschner, and Chuck Seeley2012Presentation2012presentation
Low Power SoC Verification: IP Reuse and Hierarchical Composition using UPFAmit Srivastava, Rudra Mukherjee, Erich Marschner, and Chuck Seeley2012Paper2012paper
Low Power Static Verification- Beyond Linting and Corruption SemanticsKaustav Guha , Ankush Bagotra, and Neha Bajaj2011Paper2011paper
Low Power Verification With LDOShang-Wei Tu, Amol Herlekar, and Yu-Juei Chen2016Paper2016paper
Low Power Verification with LDOShang-Wei Tu and Amol Herlekar2016Poster2016poster
Low Power Verification with UPF: Principle and PracticeJianfeng Liu, Mi-Sook Hong, Bong Hyun Lee JungYun Choi, HyoSig Won, Kyu-Myung Choi, Harsha Vardhan, and Aditya Kher2010Paper2010paper
Low-Power Verification at Gate Level for Zen Microprocessor CoreBaosheng Wang, Keerthi Mullangi, Raluca Stan, and Diana Irimia2020Presentation2020presentation
Low-Power Verification Automation – A Practical ApproachShaji Kunjumohamed and Hendy Kosasih2013Paper2013paper
LOW-POWER VERIFICATION AUTOMATION: A PRACTICAL APPROACHShaji K. Kunjumohamed and Hendy Kosasih2013Poster2013poster
Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design VerificationHonghuang Lin, Zhipeng Ye, and Asad Khan2017Presentation2017presentation
Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design VerificationH. Lin, Z. Ye, and A. M. Khan2017Paper2017paper
Machine Learning Based Verification Planning Methodology Using Design and Verification DataHanna Jang, Seonghee Yim, Sunchang Choi, and Seonil Brian Choi2022Paper2022paper
Machine Learning Based Verification Planning Methodology Using Design and Verification Data2022Presentation2022presentation
Machine Learning Driven Verification A Step Function in Productivity and ThroughputDaniel Hansson, John Rose, and Matt Graham2022Presentation2022presentation
Machine Learning-Guided Stimulus Generation for Functional VerificationSaumil Gogri, Jiang Hu, Aakash Tyagi, Mike Quinn, Swati Ramachandran, Fazia Batool, and Amrutha Jagadeesh2020Paper2020paper
Machine Learning-Guided Stimulus Generation for Functional VerificationS. Gogri, J. Hu, A. Tyagi, M. Quinn S. Ramachandran, F. Batool, and A. Jagadeesh2020Presentation2020presentation
Making Autonomous Cars Safer – One chip at a timeApurva Kalia and Ann Keffer2018Presentation2018presentation
Making Formal Property Verification Mainstream: An Intel Graphics ExperienceM Achutha KiranKumar V, Erik Seligman, Aarti Gupta, Ss Bindumadhava, and Abhijith Bharadwaj2017Paper2017paper
Making Formal Property Verification Mainstream: An Intel® Graphics ExperienceM Achutha Kiran, Kumar V., Erik Seligman, Aarti Gupta, Bindumadhava S. S., and Abhijith A. Bharadwaj2017Presentation2017presentation
Making Legacy Portable with the Portable Stimulus SpecificationMatthew Ballance2017Presentation2017presentation
Making Legacy Portable with the Portable Stimulus SpecificationMatthew Ballance2017Paper2017paper
Making RAL Jump, an IntrospectionJeremy Ridgeway, Karishma Dhruv, and Manmohan Singh2014Paper2014paper
Making RAL Jump, an IntrospectionJeremy Ridgeway, Karishma Dhruv, and Manmohan Singh2014Poster2014poster
Making Security Verification “SECURE”NAGESH RANGANATH and SUBIN THYKKOOTTATHIL2018Poster2018poster
Making Security Verification “SECURE”Subin Thykkoottathil and Nagesh Ranganath2018Paper2018paper
Making Your DPI-C Interface a Fast River of DataRich Edelman2021Paper2021paper
Managing and Automating Hw/Sw Tests from IP to SoCMatthew Ballance2018Poster2018poster
MANAGING AND AUTOMATING HW/SW TESTS FROM IP TO SOCMatthew Ballance2018Paper2018paper
Managing Highly Configurable Design and VerificationJ. Ridgeway2018Paper2018paper
Managing Highly Configurable Design and VerificationJeremy Ridgeway2018Presentation2018presentation
Marrying Simulation and Formal Made Easier!Lun Li, Durga Rangarajan, Christopher Starr, and James Greene2016Paper2016paper
Matrix Math package for VHDLDavid W. Bishop2015Poster2015poster
Matrix Math package for VHDLDavid W. Bishop2015Paper2015paper
Maximize Vertical Reuse, Building Module to System Verification Environments with UVM eHorace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss2013Paper2013paper
Maximize Vertical Reuse, Building Module to System Verification Environments with UVMeHorace Chan, Brian Vandegriend, Deepali Joshi, and Corey Goss2013Poster2013poster
Maximizing Formal ROI through Accelerated IP Verification Sign-offScott Peverelle, Hao Chen, Kamakshi Sarat Vallabhapurapu, Rosanna Yee, Hee Chul Kim, Johann Te, and Jacob Hotz2022Presentation2022presentation
Maximizing Formal ROI through Accelerated IP Verification Sign-offHao Chen, Kamakshi Sarat Vallabhapurapu, Scott Peverelle, Rosanna Yee, Hee Chul Kim, Johann Te, and Jacob Hotz2022Paper2022paper
May the powers be with you! – Unleashing powerful new features in UPF IEEE 1801Srinivasan Venkataramanan and Ajeetha Kumari2020Presentation2020presentation
Mechanism to Generate FIFO VC Dependency Graph and Its Application to System Level Deadlock VerificationDebarshi Chatterjee, Chad Parsons, Siddhanth Dhodhi2021Paper2021paper
Media Performance Validation in Emulation and Post Silicon Using Portable Stimulus StandardSuresh Vasu, Nithin Venkatesh, Joydeep Maitra2021Paper2021paper
Melioration of Enhanced Low Power Memory Retention and Low Power Feature Validation Using API’sNithin Venkatesh, Akula Hareesh2021Paper2021paper
Melting Verification Pot: Integrating RVM/VMM and UVM, a Practical Guide and Lessons Learned.Mark A. Azadpour2012Paper2012paper
Melting Verification Pot: Integrating RVM/VMM and UVM, a Practical Guide and Lessons Learned.Mark Azadpour2012Presentation2012presentation
Memory Debugging of Virtual PlatformsGeorge F. Frazier, Neeti Bhatnagar, Qizhang Chao, and Kathy Lang2012Presentation2012presentation
Memory Debugging of Virtual Prototypes with TLM 2.0George F. Frazier, Qizhang Chao, Neeti Bhatnagar, and Kathy Lang2012Paper2012paper
Memory Subsystem Verification – Can it be taken for granted?Shivani Upasani2013Presentation2013presentation
Memory Subsystem Verification: Can it be taken for granted?Shivani Upasani and Prashanth Srinivasa2013Paper2013paper
Meta Design FrameworkSanjeev Singh and Jonathan Sadowsky2015Poster2015poster
Meta Design Framework: Building Designs ProgrammaticallySanjeev Singh and Jonathan Sadowsky2015Paper2015paper
Metadata Based Testbench GenerationDaeseo Cha, Soonoh Kwon, and Ahhyung Shin2022Presentation2022presentation
Metadata Based Testbench Generation AutomationDaeseo Cha, Soonoh Kwon, Ahhyung Shin, Youngnam Youn, Youngsik Kim, and Seonil Brian Choi2022Paper2022paper
Method for Generating Unique Coverage Classes to Enable Meaningful Covergroup Merges Across TestbenchesEldon Nelson, MS, PE2015Paper2015paper
Method for Generating Unique Coverage Classes to Enable Meaningful Covergroup Merges Across TestbenchesEldon Nelson, M.S., P.E.2015Presentation2015presentation
Methodology for automating coverage-driven interrupt testing of instruction setsDavid McConnell, Greg Tumbush2021Paper2021paper
Methodology for Separation of Design Concerns Using Conservative RTL Flipflop InferenceMaya H. Safieddine, Fadi A. Zaraket, and Rouwaida Kanj2015Presentation2015presentation
Methodology for Separation of Design Concerns Using Conservative RTL Flipflop InferenceMaya H. Safieddine, Fadi A. Zaraket, and Rouwaida Kanj2015Paper2015paper
Metric Driven Mixed-Signal Verification Methodology and Practices for Complex Mixed-signal ASSPsFrank Yang, Andy Sha, Morton Zhao, and Yanping Sha2014Paper2014paper
Metric Driven Mixed-Signal Verification Methodology and Practices for Complex Mixed-signal ASSPsFrank Yang, Andy Sha, Morton Zhao, and Yanping Sha2014Poster2014poster
Metric Driven Verification of Mixed-Signal DesignsNeyaz Khan, Yaron Kashai, and Hao Fang2011Paper2011paper
Metrics Driven Sign-off for SoC Specific Logic (SSL) Using Formal TechniquesAbhinav Gaur, Gaurav Jain, Ruchi Singh2021Paper2021paper
Metrics in SoC VerificationAndreas Meyer and Harry Foster2012Paper2012paper
Micro-processor verification using a C++11 sequence-based stimulus engine.Stephan Bourduas and Chris Mikulis2017Paper2017paper
Micro-processor verification using a C++11 sequence-based stimulus engine.Stephan Bourduas and Chris Mikulis2017Presentation2017presentation
Migrating from OVM to UVM The Definitive GuideAdiel Khan2013Presentation2013presentation
Migrating to UVM : Conquering LegacySantosh Sarma, Amit Sharma, and Adiel Khan2013Paper2013paper
Mind the Gap(s): Creating & Closing Gaps Between Design and VerificationChris Giles and Kurt Takara2020Presentation2020presentation
Mining Coverage Data for Test Set Coverage EfficiencyMonica Farkash, Bryan Hickerson, Mike Behm, and Balavinayagam Samynathan2015Paper2015paper
Mining Coverage Data for Test Set Coverage EfficiencyBryan Hickerson, Mike Behm, Balavinayagam Samynathan, and Monica Farkash2015Presentation2015presentation
Mixed Signal Assertion-Based VerificationPrabal Bhattacharya, Don O’Riordan, and Walter Hartong2011Paper2011paper
Mixed Signal Design Verification: Leveraging the Best of AMS and DMSRock Z. Shi, Padmashree Bhinge, Preston Birdsong, Geeta Chaitanya, and Kunal Jani2022Presentation2022presentation
Mixed Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP SimulationS. Do, J. Park, D. Kim, and J. Jang2022Presentation2022presentation
Mixed Signal Verification of a Voltage Regulator using a State Space Approach and the SV-DC extensionsRajat Mitra2016Paper2016paper
Mixed Signal Verification of Dynamic Adaptive Power Management in Low Power SoCNeyaz Khan2010Paper2010paper
Mixed Signal Verification of UPF based designs A Practical ExampleAndrew Milne and Damian Roberts2015Presentation2015presentation
Mixed Signal Verification of UPF based designs A Practical ExampleAndrew Milne and Damian Roberts2015Paper2015paper
Mixed-abstraction Modeling Approach with Fault Injection for Hardware-Firmware Co-design and Functional Co-verification of an Automotive Airbag System on Chip ProductDipl.-Ing. Dr.-techn. Thang Nguyen, Dipl.-Ing. and Dieter Haerle2013Paper2013paper
Mixed-abstraction Modeling Approach with Fault Injection for Hardware-Firmware Co-design and Functional Co-verification of an Automotive Airbag System on Chip ProductThang Nguyen, Dipl.-Ing.-Dr. and Dieter Haerle, Dipl.-Ing.2013Presentation2013presentation
Mixed-Signal Design Verification: Leveraging the Best of AMS and DMSRock Z. Shi, Padmashree Bhinge, Preston Birdsong, Geeta Chaitanya, and Kunal Jani2022Paper2022paper
Mixed-Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP SimulationS. Do, J. Park, D. Kim, and J. Jang2022Paper2022paper
Mixed-Signal Systems-on-Chip Design Verification With Automatic Real-Number AbstractionNancy Qiu, Frank Yang, and Himadri De2016Paper2016paper
Mixed-Signal Verification Methodology to Verify Type-C USBVarun R, Vinayak Hegde, and Somasunder Kattepura Sreenath2017Paper2017paper
Mixed-Signal Verification Methodology to Verify USB Type-CVarun R, Vinayak Hegde ans Somasunder Kattepura Sreenath2017Poster2017poster
ML-Based Verification and Regression AutomationAbhishek Chauhan, Asif Ahmad2021Paper2021paper
Modeling a Hierarchical Register Scheme with UVMJoshua Hardy2017Presentation2017presentation
Modeling a Hierarchical Register Scheme with UVMJoshua Hardy2017Paper2017paper
Modeling Analog Devices Using SV-RNMMariam Maurice2022Poster2022poster
Modeling Analog Devices using SV-RNMMariam Maurice2022Paper2022paper
Modeling Analog Systems Using Full Digital Simulations (A State Space Approach)Rajat K Mitra 2016Presentation2016presentation
Modeling Memory Coherency During Concurrent/Simultaneous AccessesSubramoni Parameswaran2022Paper2022paper
Modeling Memory Coherency for concurrent/parallel accessesSubramoni Parameswaran2022Presentation2022presentation
Modeling Memory Coherency for Concurrent/Parallel AccessesSubramoni Parameswaran2022Presentation2022presentation
Molding Functional Coverage for Highly Configurable IPJ. Ridgeway, K. Chaturvedula, and K. Dhruv2016Paper2016paper
Molding Functional Coverage for Highly Configurable IPJeremy Ridgeway, Kavitha Chaturvedula, and Karishma Dhruv2016Poster2016poster
Monitors, Monitors Everywhere – Who Is Monitoring the MonitorsRich Edelman and Raghu Ardeishar2013Paper2013paper
Monitors, Monitors Everywhere …Rich Edelman and Raghu Ardeishar2013Poster2013poster
Moving beyond Assertions: An Innovative approach to Low-Power Checking using UPF Tcl AppsMadhur Bhargava2019Poster2019poster
MS-SoC Best Practices – Advanced Modeling & Verification Techniques for first-pass successNeyaz Khan, Greg Glennon, and Dan Romaine2013Paper2013paper
Multi-Domain Verification: When Clock, Power and Reset Domains CollidePing Yeung, Erich Marschner, and Kaowen Liu2015Paper2015paper
Multi-Domain Verification: When Clock, Power and Reset Domains CollidePing Yeung, Erich Marschner, and Kaowen Liu2015Presentation2015presentation
Multi-Language Verification: Solutions for Real World ProblemsBryan Sniderman and Vitaly Yankelevich2014Paper2014paper
Multi-Language Verification: Solutions for Real World ProblemsBryan Sniderman and Vitaly Yankelevich2014Presentation2014presentation
Multimedia IP DMA verification platformSuhyung Kim, Sangkyu Park, Myungwoo Seo, Sangjin Lee, and Jiyeon Park2020Paper2020paper
Multimedia IP DMA verification platformSuhyung Kim, Sangkyu Park, Myungwoo Seo, Sangjin Lee, and Jiyeon Park2020Poster2020poster
Multiplier-Adder-Converter Linear Piecewise Approximation for Low Power Graphics ApplicationsDina M. Ellaithy, Magdy A. El-Moursy, Amal Zaki, and Abdelhalim Zekry2019Poster2019poster
Multithreading a UVM Testbench for Faster SimulationBenjamin Applequist, Vijayakrishnan Rousseau, Andrew Tan, and Jayasrinivas Sesham2020Presentation2020presentation
My Testbench Used to Break! Now it Bends (Adapting to Changing Design Configurations)Jeff Vance, Jeff Montesano, Kevin Vasconcellos, and Kevin Johnston2018Presentation2018presentation
My Testbench Used to Break! Now it Bends: Adapting to Changing Design ConfigurationsJeff Vance, Jeff Montesano, Kevin Vasconcellos, and Kevin Johnston2018Paper2018paper
Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage ModelingJason Sprott, Paul Marriott, and Matt Graham2015Paper2015paper
Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage ModelingJason Sprott, Paul Marriott, and Matt Graham2015Presentation2015presentation
Never Too Late With Formal: Stepwise Guide for Applying Formal Verification in Post-Silicon Phase to Avoid Re-SpinsAnshul Jain, Aarti Gupta, Achutha KiranKumar V M, Bindumadhava Ss, Shivakumar S Kolar, and Siva Gadey NV2022Paper2022paper
Never Too Late with Formal: Stepwise Guide for Applying FV in Post Si Phase to Avoid Re-SpinsAnshul Jain, Aarti Gupta, Achutha KiranKumar V M, Bindumadhava Ss, Shivakumar S Kolar, Siva Gadey NV2022Presentation2022presentation
New and active ways to bind to your designKaiming Ho2013Presentation2013presentation
New and Active Ways to Bind to Your DesignsKaiming Ho2013Paper2013paper
New Challenges in Verification of Mixed-Signal IP and SoC DesignLuke Lang and Christina Chu2012Paper2012paper
New Constrained Random and Metric-Driven Verification Methodology using PythonMarek Ciepłucha and Witold Pleskacz2017Presentation2017presentation
New Constrained Random and Metric-Driven Verification Methodology using PythonMarek Cieplucha and Witold A. Pleskacz2017Paper2017paper
Next Gen System Design and Verification for TransportationDavid Aerne, Jacob Wiltgen, and Richard Pugh2019Presentation2019presentation
Next Generation Verification for the Era of AI/ML and 5GFrank Schirrmeister, Pete Hardee, Larry Melling, Amit Dua, and Moshik Rubin2020Presentation2020presentation
Next-generation Power Aware CDC Verification – What have we learned?Kurt Takara, Chris Kwok, Naman Jain, and Ashish Hari2015Paper2015paper
Next-generation Power Aware CDC Verification What have we learned?Kurt Takara, Chris Kwok, Naman Jain, and Ashish Hari2015Poster2015poster
No RTL Yet? No Problem UVM Testing a SystemVerilog Fabric ModelRich Edelman2016Presentation2016presentation
No RTL Yet? No Problem UVM Testing a SystemVerilog Fabric ModelRich Edelman2016Paper2016paper
NOT JUST FOR HARDWARE DEBUG: PROTOTYPE DEBUGGERS FOR SYSTEM VALIDATION AND OPTIMIZATIONMichael Sachtjen and Joe Gaubatz2015Poster2015poster
Not Just for Hardware Debug: Prototype Debuggers for System Validation and OptimizationMichael Sachtjen and Joe Gaubatz2015Paper2015paper
Novel Approach to ASIC PrototypingMohamed Saheel, Suresh Balasubramanian, and Vijayakrishnan Rousseau2019Poster2019poster
Novel Approaches for C vs. RTL Formal Verification of Vertex Attribute Address Generator UnitNianchen Wu, Christopher Starr, and Xiushan Feng2020Presentation2020presentation
Novel GUI Based UVM Test Bench Template BuilderVignesh Manoharan2022Poster2022poster
Novel GUI Based UVM Test Bench Template BuilderVignesh Manoharan2022Paper2022paper
Novel Mixed Signal Verification Methodology using complex UDNsRakesh Dama, Ravi Reddy, and Andy Vitek2019Paper2019paper
Novel Mixed Signal Verification Methodology Using Complex UDNsRakesh Dama, Ravi Reddy, and Andy Vitek2019Presentation2019presentation
Novel Paradigm in Formally Verifying Complex AlgorithmsM Achutha KiranKumar V, Disha Puri, Mohit Choradia, Paras Gupta2021Paper2021paper
Novel Test Case Design Techniques for Logical Specifications of Safety Critical Systems Software in Aerial VehicleLakshmi KVNS and Sanjeev Kumar2017Paper2017paper
Novel Verification Techniques for ARM A15 Multi-core Subsystem Using IEEE 1647Vaibhav Mahimkar, Akshit Dayal, Tomas Huynh, Van Huynh, and Erwin Hermanto2014Poster2014poster
Novel Verification Techniques for ARM A15 Multi-core Subsystem Using IEEE 1647Vaibhav Mahimkar, Akshit Dayal, Tomas Huynh, Van Huynh, and Erwin Hermanto.2014Paper2014paper
Novelty-Driven Verification: Using Machine Learning to Identify Novel Stimuli and Close CoverageTim Blackmore, Rhys Hodson, Sebastian Schaal2021Paper2021paper
NVMe Development and Debug for a 16 x Multicore SystemSoummya Mallick, Raj Mathur, Arindam Guha, and Frank Schirrmeister2019Paper2019paper
Of Camels and CommitteesTom Fitzpatrick and Dave Rich2014Paper2014paper
Of Camels and Committees: Standardization Should Enable Innovation, Not Strangle ItTom Fitzpatrick and Dave Rich2014Presentation2014presentation
Off To The Races With Your Accelerated SystemVerilog Testbench (A Methodology for Hardware-Assisted Acceleration of SystemVerilog Testbenches)Hans van der Schoot, Anoop Saha, Ankit Garg, and Krishnamurthy Suresh2011Paper2011paper
On Verification Coverage Metrics in Formal Verification and Speeding Verification Closure with UCIS Coverage Interoperability StandardRajeev Ranjan, PhD, Ross Weber, and Ziyad Hanna, PhD2013Paper2013paper
One Compile to Rule them All: An elegant solution for OVM/UVM Testbench TopologiesGalen Blake and Steve Chappell2013Presentation2013presentation
One Compile to Rule Them All: An Elegant Solution for OVM/UVM Testbench TopologiesGalen Blake and Steve Chappell2013Paper2013paper
One Stop Solution for DFT Register Modelling in UVMRui Huang2017Paper2017paper
One Stop Solution of DFT Register Modelling in UVMRui Huang2017Presentation2017presentation
Open-source Framework for Co-emulation using PYNQIoana-Cătălina Cristea, Dragoș Dospinescu2021Paper2021paper
Optimal Usage of the Computer Farm for Regression TestingDaniel Hansson and Patrik Granath2016Presentation2016presentation
Optimal Usage of the Computer Farm for Regression TestingDaniel Hansson and Patrik Granath2016Paper2016paper
Optimizing Area and Power Using Formal MethodAlan Carlin, Chris Komar Cadence, and Anuj Singhania2011Paper2011paper
Optimizing Random Test Constraints Using Machine Learning AlgorithmsStan Sokorac2017Presentation2017presentation
Optimizing Random Test Constraints Using Machine Learning AlgorithmsStan Sokorac2017Paper2017paper
Optimizing Turnaround Times In A CI Flow Using a Scheduler ImplementationRobert Strong2022Presentation2022presentation
Optimizing Turnaround Times in a Continuous Integration Flow Using a Scheduler Based ImplementationRobert Strong2022Paper2022paper
OS aware IP Development MethodologyHyunjae Woo, Woojoo Kim, Youngsik Kim, and Seonil Brian Choi2019Presentation2019presentation
OS-aware IP Development MethodologyHyunjae Woo, Woojoo Kim, Youngsik Kim, and Seonil Brian Choi2019Paper2019paper
OS-aware Performance and Power Analysis MethodologyHyunjae Woo, HojinJo, Woojoo Kim, and Seonil Brian Choi2020Presentation2020presentation
Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath ScoreboardsBochra El-Meray and Jörg Müller2013Presentation2013presentation
Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath ScoreboardsBochra Elmaray and Joerg Mueller2013Paper2013paper
OVM & UVM Techniques for On-the-fly ResetMuralidhara Ramalingaiah and Boobalan Anantharaman2012Paper2012paper
OVM & UVM Techniques for On-the-fly ResetMuralidhara Ramalingaiah and Boobalan Anantharaman2012Presentation2012presentation
OVM & UVM Techniques for Terminating TestsClifford E. Cummings and Tom Fitzpatrick2011Paper2011paper
OVM TO UVM DEFINITIVE GUIDE PART 1Adiel Khan, Justin Refice, and Warren Stapleton2013Paper2013paper
PA-APIs: Looking beyond power intent specification formatsAmit Srivastava and Awashesh Kumar2015Paper2015paper
PA-APIs: Looking beyond power intent specification formatsAmit Srivastava and Awashesh Kumar2015Poster2015poster
Panning for Gold in RTL Using TransactionsRich Edelman, Raghu Ardeishar, Akshay Sarup, and Suman Kasam2011Paper2011paper
Parallel Computing for Functional Verification and Compute Farms: The Holy MatrimonyAmit Sharma, Shekhar Basavanna, and Srinivasan Venkataramanan2011Paper2011paper
Parameter Passing From SystemVerilog to SystemCBishnupriya Bhattacharya, Samik Das, Zhiting Duan, Chandra Sekhar Katuri, and Pradipta Laha2015Presentation2015presentation
Parameter Passing from SystemVerilog to SystemC for Highly Configurable Mixed-Language DesignsBishnupriya Bhattacharya, Samik Das, Zhiting Duan, Chandra Sekhar Katuri, and Pradipta Laha2015Paper2015paper
Parameterize Like a Pro: Handling Parameterized RTL in your UVM TestbenchJeff Montesano2020Presentation2020presentation
Parameterized and Re-usable Jitter Model for Serial and Parallel InterfacesAmlan Chakrabarti and Malathi Chikkanna2015Paper2015paper
Parameterized and Re-usable Jitter Model for Serial and Parallel InterfacesMalathi Chikkanna and Amlan Chakrabarti2015Presentation2015presentation
Parameters and OVM — Can’t They Just Get Along?Bryan Ramirez and Michael Horn2011Paper2011paper
Parameters, UVM, Coverage & Emulation – Take Two and Call Me in the MorningMichael Horn, Bryan Ramirez, and Hans van der Schoot2016Paper2016paper
Path-based UPF Strategies: Optimally Manage Power on your DesignsProgyna Khondkar2022Presentation2022presentation
Path-Based UPF Strategies: Optimally Manage Power on Your DesignsProgyna Khondkar2022Paper2022paper
Pay Me Now or Pay Me Later Exploring the Implementation and Analysis Cost Trade-Offs of Coverage Model DesignPaul Graykowski and Andrew Piziali2011Paper2011paper
Plan & Metric Driven Mixed-Signal Verification for Medical DevicesGregg Sarkinen2011Paper2011paper
Plugging the Holes: SystemC and VHDL Functional Coverage MethodologyPankaj Singh and Gaurav Kumar Verma2011Paper2011paper
Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication bridgeAndrei Vintila and Ionut Tolea2019Presentation2019presentation
Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication bridgeAndrei Vintila and Ionut Tolea2019Paper2019paper
Portable Stimulus Models for C/SystemC, UVM and EmulationMike Andrews and Boris Hristov2015Paper2015paper
Portable Stimulus Models for C/SystemC, UVM and EmulationMike Andrews and Boris Hristov2015Presentation2015presentation
Portable Stimulus Standard Update: PSS in the Real WorldAccellera Portable Stimulus Working Group2022Presentation2022presentation
Portable Stimulus Standard: The Promises and Pitfalls of Early AdoptionMike Bartley2019Presentation2019presentation
Portable Stimulus Standard’s Hardware Software Interface (HSI) to validate 4G 5G Forward Error Correction Encoder/Decoder IP in Emulation SiliconJoydeep Maitra, Suresh Vasu, Nithin Venkatesh, Suhas Reddy, Luis Campos, Vinit Shenoy2022Presentation2022presentation
Portable Stimulus vs Formal vs UVM: A Comparative Analysis of Verification Methodologies Throughout the Life of an IP BlockGaurav Bhatnagar and David Brownell2018Paper2018paper
Portable Stimulus vs Formal vs UVM: A Comparative Analysis of Verification Methodologies Throughout the Life of an IP BlockGaurav Bhatnagar2018Presentation2018presentation
Portable Stimulus: What’s Coming in 1.1 and What it Means For YouPortable Stimulus Working Group2020Presentation2020presentation
Portable Test and Stimulus: The Next Level of Verification Productivity is HereAccellera Portable Stimulus Working Group2018Presentation2018presentation
Post Silicon Performance Validation Using PSSDayoung Kim, Jaehun Lee, Daeseo Cha, Phu L. Huynh, and Jake Kim2020Presentation2020presentation
Post-Silicon Performance Validation Using PSSDayoung Kim, Jaehun Lee, and Daeseo Cha2020Paper2020paper
Power Aware CDC Analysis at Top Level Using SOC Abstract FlowVenkatesh Ranga and Pramod Rajan K S2017Paper2017paper
Power Aware CDC Analysis at Top Level Using SOC Abstract FlowVenkatesh Ranga and Pramod Rajan K S2017Poster2017poster
Power Aware Verification Strategy for SoCsBoobalan Anantharaman and Arunkumar Narayanamurthy2013Presentation2013presentation
Power Aware Verification Strategy for SoCsBoobalan Anantharaman and Arunkumar Narayanamurthy2013Paper2013paper
Power estimation – what to expect what not to expectPrakash Parikh2014Presentation2014presentation
Power Estimation Techniques – what to expect, what not to expectPrakash Parikh2014Paper2014paper
Power Management Verification for SoC ICsDavid Akselrod, Alex Miretsky, Sergey Golubkov, Pearl Liu, Afshin Parvaresh, Shu Wang, and Feng Yan2016Poster2016poster
Power Management Verification for SOC ICsDavid Akselrod, Alex Miretsky, Sergey Golubkov, Pearl Liu, Afshin Parvaresh, Shu Wang, and Feng Yan2016Paper2016paper
Power State to PST Conversion: Simplifying static analysis and debugging of power aware designsMadhur Bhargava and Pankaj Gairola2016Poster2016poster
Power State to PST Conversion: Simplifying static analysis and debugging of power aware designsMadhur Bhargava and Pankaj Gairola2016Paper2016paper
Practical Applications of the Portable Testing and Stimulus Standard (PSS)Sharon Rosenberg2019Presentation2019presentation
Practical Approach Using a Formal App to Detect X-Optimism-Related RTL BugsShuqing Zhao, Shan Yan, and Yafang Feng2014Paper2014paper
Practical Approach Using a Formal App to Detect X-Optimism-Related RTL BugsShuqing Zhao, Shan Yan, and Yafang Feng2014Presentation2014presentation
Practical Considerations for Real Valued Modeling of High Performance Analog SystemsDushyant Juneja, Siddharth Prabhu, and Syam Veluri2016Presentation2016presentation
Practical Considerations for Real Valued Modeling of High Performance Analog SystemsDushyant Juneja, Siddharth Prabhu, and Syam Veluri2016Poster2016poster
Practical Considerations for Real Valued Modeling of High Performance Analog SystemsDushyant Juneja, Siddharth Prabhu, and Syam Veluri2016Paper2016paper
Practical Considerations for Real Valued Modeling of High Performance Analog SystemsDushyant Juneja, Siddharth Prabhu, and Syam Veluri2016Paper2016paper
Practical Issues in Implementing Fast and Accurate SystemC-Constructed Virtual Platform SimulationYu-Fu Yeh and Chung-Yang (Ric) Huang2013Paper2013paper
Practical Issues in Implementing Fast and Accurate SystemC-Constructed Virtual Platform SimulationYu-Fu Yeh and Chung-Yang (Ric) Huang2013Presentation2013presentation
Practical Scheme to Enhance Verification Turn-Around-Time by Using Reusable Harness Interface (RHI)Jongpil Jung, Hyunju Lee, Jaejin Ha, and Yonghee Im2018Paper2018paper
Practical Scheme to Enhance Verification Turn-Around-Time by Using Reusable Harness Interface (RHI)Jong pil Jung, Hyunju Lee, Jaejin Ha, and Yonghee Im2018Presentation2018presentation
Practical Schemes to Enhance Vertical, Horizontal and Platform Reusability of Verification Components in AMBA Based SoC DesignIeryung Park, Nara Cho and Yonghee Im2017Presentation2017presentation
PRACTICAL SCHEMES TO ENHANCE VERTICAL, HORIZONTAL AND PLATFORM REUSABILITY OF VERIFICATION COMPONENTS IN AMBA BASED SOC DESIGNIeryung Park, Nara Cho, and Yonghee Im2017Paper2017paper
Pragmatic Verification Reuse in a Vertical WorldMark Litterick2013Poster2013poster
Pragmatic Verification Reuse in a Vertical WorldMark Litterick2013Paper2013paper
Pre-Silicon Power Management Verification of Complex SOCs: Experiences with Intel MoorefieldRajeev Muralidhar, Nivedha Krishnakumar, Bryan Morgan, Robert Karas, Billy Dennie, and Neil Rosenberg2016Paper2016paper
Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads using Hybrid System Level Emulation SoC PlatformNeeraj Gupta, Reddaiah Yedoti, Dixit Sethi, and Sarvesh Kumar Pandey2022Poster2022poster
Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads Using Hybrid System Level Emulation SoC PlatformNeeraj Gupta, Reddaiah Yedoti, Dixit Sethi, and Sarvesh Kumar Pandey2022Paper2022paper
Predicting Bad CommitsChristian Graber, Daniel Hansson, and Adam Tornhill2019Poster2019poster
Preventing Chip-Killing Glitches on CDC Paths with Automated Formal AnalysisJackie Hsiung, Ashish Hari, and Sulabh Kumar Khare2018Paper2018paper
Preventing Chip-Killing Glitches on CDC Paths with Automated Formal AnalysisJackie Hsiung, Sulabh Kumar Khare, and Ashish Hari2018Poster2018poster
Preventing Glitch Nightmares on CDC Paths: The Three WitchesJian-Hua Yan, Ping Yeung, Stewart Li, Sulabh-Kumar Khare2021Paper2021paper
Primary, Anonymous, or What? The Destiny of Ports from Design Top that Ultimately are Driven from Off-Chip…Brandon Skaggs, Progyna Khondkar2021Paper2021paper
Problematic Bi-Directional Port Connections: How Well is Your Simulator Filling the UPF LRM Void?Brandon Skaggs2022Presentation2022presentation
Problematic Bi-Directional Port Connections: How Well Is Your Simulator Filling the UPF LRM Void?Brandon Skaggs2022Paper2022paper
Product Life Cycle of an Interconnect Bus: A Portable Stimulus Methodology for Performance Modeling, Design Verification, and Post-Silicon ValidationGaurav Bhatnagar and Courtney Fricano2019Paper2019paper
Product Life Cycle of Interconnect Bus:A Portable Stimulus Methodology for Performance Modeling, Design Verification, and Post-Silicon ValidationGaurav Bhatnagar and Courtney Fricano2019Presentation2019presentation
Programming Model Inheritance and Sequence ReuseAji Varghese2016Paper2016paper
Proper probing: Flexibility on the TLM levelGergő V kony2018Paper2018paper
Proper Probing: Flexibility on the TLM LevelGergö Vékony2018Poster2018poster
Property-Driven Development of a RISC-V CPUTobias Ludwig, Michael Schwarz, Joakim Urdahl, Lucas Deutschmann, Salaheddin Hetalani, Dominik Stoffel, and Wolfgang Kunz2019Paper2019paper
Property-Driven Development of a RISC-V CPUTobias Ludwig2019Presentation2019presentation
Proven Strategies for Better Verification Planning: DVCon 2022 WorkshopPaul Marriott, Jeff Vance, and Jeff McNeal 2022Presentation2022presentation
PSL/SVA Assertions in SPICEDonald O’Riordan and Prabal Bhattacharya2012Paper2012paper
PSS Action Sequence Modeling Using Machine LearningMoonki Jang2022Presentation2022presentation
PSS Action Sequence Modeling Using Machine LearningMoonki Jang, Myeongwhan Hyun, Hyunkyu Ahn, Jiwoong Kim, Yunwhan Kim, and Dongjoo Kim2022Paper2022paper
PSS: The Promises and Pitfalls of Early AdoptionMike Bartley2019Paper2019paper
Qualification of Formal Properties for Productive Automotive Microcontroller VerificationHolger Busch2013Paper2013paper
Quantification of Formal Properties for Productive Automotive Microcontroller VerificationHolger Busch2013Presentation2013presentation
Raising the level of Formal Signoff with End to End Checking MethodologyPing Yeung, Arun Khurana, Dhruv Gupta, Ashutosh Prasad, Achin Mittal2022Presentation2022presentation
Raising the Level of Formal Signoff with End-to-End Checking MethodologyPing Yeung, Arun Khurana, Dhruv Gupta, Ashutosh Prasad, and Achin Mittal2022Paper2022paper
Random Directed Low Power Coverage Methodology: A Smart Approach to Power Aware Verification ClosureAwashesh Kumar and Madhur Bhargava2017Paper2017paper
Random Directed Low Power Coverage Methodology:(A Smart Approach to Power Aware Verification Closure)Awashesh Kumar and Madhur Bhargava2017Presentation2017presentation
Randomizing UVM Config DB ParametersJeremy Ridgeway2015Paper2015paper
Randomizing UVM Config DB ParametersJeremy Ridgeway2015Poster2015poster
Real Number ModelingTom Cole, Wes Queen, Mark Kautzman, and Dan Romaine2013Paper2013paper
Real Number Modeling Enables Fast, Accurate Functional VerificationWes Queen, Tom Cole, and Dan Romaine2013Poster2013poster
Real Number Modeling for RF CircuitsJakub Dudek, Joshua Nekl and Keith O’Donoghue2017Presentation2017presentation
Real Number Modeling of RF CircuitsJakub Dudek, Joshua Nekl, and Keith O’Donoghue2017Paper2017paper
Recipe for bug hunting: Tips & Tricks for Low power silicon sign-offMonika Rawat, Dipankar Narendra Arya, Anuroop R, Deepmala Sachan2021Paper2021paper
RegAnalyzer – A tool for programming analysis and debug for verification and validationSuresh Vasu2020Poster2020poster
RegAnalyzer -A tool for programming analysis and debug for verification and validationSuresh Vasu2020Paper2020paper
Register This! Experiences Applying UVM RegistersSharon Rosenberg2012Paper2012paper
Register This! Experiences Applying UVM RegistersKathleen Meade2012Presentation2012presentation
Register Verification: Do We Have Reliable Specification?NamDo Kim, Junhyuk Park, Byeong Min, and Wesley Park2013Poster2013poster
Register Verification: Do We Have Reliable Specification?NamDo Kim, Junhyuk Park, Byeong Min, and Wesley Park2013Paper2013paper
Registering the standard: Migrating to the UVM_REG code baseSachin Patel, Amit Sharma, and Adiel Khan2012Paper2012paper
Regressions in the 21st Century – Tools for Global SurveillanceDavid Crutchfield, Tushar Grupta, Frank Roberts, and Venkataramanan Srinivasan2016Presentation2016presentation
Regressions in the 21st Century – Tools for Global SurveillanceDavid Crutchfield, Tushar Grupta, Frank Roberts, and Venkataramanan Srinivasan2016Paper2016paper
Relieving the Parameterized Coverage HeadacheChristine Lovett, Bryan Ramirez, Stacey Secatch, and Michael Horn2012Paper2012paper
Relieving the Parameterized Coverage HeadacheChristine Lovett2012Presentation2012presentation
Reset and Initialization, the Good, the Bad and the UglyPing Yeung and Kaowen Liu2016Paper2016paper
Reset and Initialization, the Good, the Bad and the UglyPing Yeung and Kaowen Liu2016Poster2016poster
Reset and Initialization: the Good, the Bad and the UglyPing Yeung and Kaowen Liu2016Presentation2016presentation
Reset Domain Crossing for designs with set-reset flopsAbdul Moyeen, Inayat Ali2021Paper2021paper
Resetting Anytime with the Cadence UVM Reset PackageCourtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm2014Poster2014poster
Resetting Anytime with the Cadence UVM Reset PackageCourtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm2014Paper2014paper
Results Checking Strategies with Portable StimulusTom Fitzpatrick and Matthew Balance2019Presentation2019presentation
Results Checking Strategies with Portable StimulusTom Fitzpatrick and Matthew Ballance2019Paper2019paper
Reusable System-Level Power-Aware IP Modeling ApproachAntonio Genov, Francois Verdier, and Loic Leconte2022Paper2022paper
REUSABLE UPF: Transitioning from RTL to Gate Level VerificationDurgesh Prasad, Jitesh Bansal, and Madhur Bhargava2018Poster2018poster
REUSABLE UPF: Transitioning from RTL to Gate Level VerificationDurgesh Prasad, Jitesh Bansal, and Madhur Bhargava2018Paper2018paper
Reuse C test and UVM sequence utilizing TLM2, register model and interrupt handlerHongLiang Liu and Teng-Fei Gao2015Presentation2015presentation
Reuse C test and UVM sequence utilizing TLM2, register model and interrupt handlerLiu HongLiang and Gao Teng-Fei2015Paper2015paper
Reusing Testbench Components in a Hybrid Simulation-Formal EnvironmentRitero Chi and Xiaolin Chen2010Paper2010paper
Reusing UVM Test Benches in a Cycle SimulatorKristina Hager, Carter Alvord, Andrew Lynch, and Umer Yousafzai2014Presentation2014presentation
Reusing UVM Testbenches in a Cycle SimulatorKristina Hager, Andrew Lynch, Umer Yousafzai, and Carter Alvord2014Paper2014paper
RISC-V Processor Verification: Case StudyAdi Maymon, Shay Harari, Lee Moore, Larry Lapides2021Paper2021paper
Robust Physical Layer IP Verification for DDR4-3DS Memory by Channel ModellingAditya S Kumar, Gowdra Bomanna Chethan, Shivani Maurya, Kumar Rajeev Ranjan, Anil Deshpande, Somasunder Kattepura Sreenath2021Paper2021paper
Rockin’ the Polymorphism for an Elegant UVM Testbench ArchitectureMike Baird and Frank Verhoorn2018Poster