DVCon: Europe

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TitleAuthor(s)YearTypeLinkhf:tax:event_yearhf:tax:document_type
1,2,3,…8 simple steps towards a single digital signal processing testbench supporting heterogeneous interfaces and datatypesNico Lugil2016Presentationy2016presentation
1,2,3,…8 simple steps towards a single digital signal processing testbench supporting heterogeneous interfaces and datatypesNico Lugil2016Papery2016paper
400G IPU Case Study: Demonstrating Shift-left of Soft Logic RTL Development on Real World Design using Intel Agilex FPGA SystemC ModelPravat K Nayak, Vikrant Kapila, Pushpa Naik & Niketkumar Sharma2023Papery2023paper
5G – Chances and Challenges from Test & Measurement PerspectiveMeik Kottkamp2017Presentationy2017presentation
5G / NR Explained From 3GPP 5G Standard Fundamentals To 5G Enabled VerticalsMichael Faerber and Kilian Roth2019Presentationy2019presentation
5G for people and things Spectrum Opportunities and Challenges of 5G 2017Presentationy2017presentation
A comparison of methodologies to simulate mixed-signal ICSimone Fontanesi, Karsten Einwich, Paul Ehrlich, Gaetano Formato, Andrea Possemato2021Papery2021paper
A Compositional Simulation Framework for Testing Adversarial Robustness of Deep Neural NetworksYoussef Maher Nader; Mostafa Lotfy Hatab; Mazen Mostafa Ghaleb; Safia Medhat Bakr; Tasneem A. Awaad; Ahmed AlGanzouri; Mohamed Abdelsalam; M. Watheq El-Kharashi2023Papery2023paper
A Compositional Simulation Framework for Testing Adversarial Robustness of Deep Neural NetworksYoussef Maher Nader, Mostafa Lotfy Hatab, Mazen Mostafa Ghaleb, Safia Medhat Bakr, Tasneem A. Awaad, Ahmed AlGanzouri, Mohamed Abdelsalam, and M. Watheq El-Kharashi2023Papery2023paper
A Comprehensive Verification Platform for RISC-V based ProcessorsEmre Karabulut, Berk Kisinbay, Abdullah Yildiz and Rifat Demircioglu2020Papery2020paper
A Comprehensive Verification Platform for RISC-V based ProcessorsEmre Karabulut, Berk Kisinbay, Abdullah Yildiz, and Rifat Demircioglu 2020Presentationy2020presentation
A concept for expanding a UVM testbench to the analog-centric toplevelFelix Assmann, Axel Strobel and Hans Zander2015Papery2015paper
A concept for expanding a UVM testbenchto the analog-centric toplevelFelix Assmann, Axel Strobel and Hans Zander2015Postery2015poster
A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMSMuhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, Daniel Große2022Papery2022paper
A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMSMuhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, Daniel Große2022Presentationy2022presentation
A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog-AMSMike Bartley and Jeganath Gandhi R2014Papery2014paper
A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog-AMSMike Bartley, Jeganath Gandhi R2014Papery2014paper
A Framework for the Execution of Python Tests in SystemC and Specman TestbenchesChristoph Tietz, Sebastian Stieber , Najdet Charaf, Diana Göhringer2022Papery2022paper
A Framework for the Execution of Python Tests in SystemC and Specman TestbenchesChristoph Tietz, Sebastian Stieber, Najdet Charaf, Diana Göhringer2022Presentationy2022presentation
A Generic Approach to Handling Sideband SignalsMarkus Brosch and Salman Tanvir2019Presentationy2019presentation
A Generic Configurable Error Injection Agent for On-Chip MemoriesNiharika Sachdeva, Arjun Suresh Kumar, Damandeep Saini, Anil Deshpande, Ravi Teja Gopagiri, Somasunder KS, Jaechul Park2022Papery2022paper
A Generic Configurable Error Injection Agent for All On-Chip MemoriesAnil Deshpande, Jaechul Park, Niharika Sachdeva, Arjun Suresh Kumar, Raviteja Gopagiri, Somasund Kattepura Sreenath, Damandeep Saini2022Presentationy2022presentation
A Guide To Using Continuous Integration Within The Verification EnvironmentJason Sprott, André Winkelmann, and Gordon McGregor2014Papery2014paper
A Guide To Using Continuous Integration Within The Verification EnvironmentAndré Winkelmann, Jason Sprott, and Gordon McGregor2014Postery2014poster
A Hybrid Approach For Interrupts VerificationGiovanni Auditore, Francesco Rua’, Qibo Peng2023Presentationy2023presentation
A Hybrid Approach To Interrupt VerificationGiovanni Auditore, Francesco Rua’, Qibo Peng2023Papery2023paper
A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGAAntonis Papagrigoriou, Miltos D. Grammatikakis and Voula Piperaki2018Presentationy2018presentation
A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGA*Antonis Papagrigoriou, Antonis Papagrigoriou and Voula Piperaki2018Papery2018paper
A Meta-Model-Based Approach for Semantic Fault Modeling on Multiple Abstraction LevelsMichael Schwarz and Moomen Chaari, Bogdan-Andrei Tabacaru2015Papery2015paper
A Meta-Model-Based Approach for Semantic Fault Modeling on Multiple Abstraction LevelsM. Schwarz M. Chaari, B.-A. Tabacaru, and W. Ecker2015Presentationy2015presentation
A Meta-Modeling-Based Approach for Automatic Generation of Fault-Injection ProcessesBogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, and Thomas Kruse2014Papery2014paper
A Meta-Modeling-Based Approach for Automatic Generation of Fault-Injection ProcessesB.-A. Tabacaru, M. Chaari, W. Ecker, and T. Kruse2014Presentationy2014presentation
A Methodology for Evaluating SI Artefacts in DDR4-3DS PHY using Channel ModellingAditya S Kumar, Gowdra Bomanna Chethan, Shivani Maurya, Anil Deshpande, Somasunder Kattepura Sreenath2021Papery2021paper
A Methodology to Verify Functionality, Security, and Trust for RISC-V CoresW. W. Chen, N. Tusinschi and T. L. Anderson2020Papery2020paper
A Methodology to Verify Functionality, Security, and Trust for RISC-V CoresW. W. Chen, N. Tusinschi, and T. L. Anderson2020Presentationy2020presentation
A Metric-driven Methodology For Firmware Verification In Simulation/Emulation EnvironmentsGoran Savić2016Papery2016paper
A Mixed Signal System Design Methodology in SystemC AMS for Automotive Audio Power AmplifiersSkule Pramm, Joen Westendorp, and Quino Sandifort2019Papery2019paper
A Model-Based Reusable Framework to Parallelize Hardware and Software DevelopmentJouni Sillanpää, Håkan Pettersson & Tom Richter2023Papery2023paper
A Mutually-Exclusive Deployment of Formal and Simulation Techniques Using Proof-Core AnalysisKeerthikumara Devarajegowda, Jeroen Vliegen, Goran Petrovity, and Kawe Fotouhi2017Presentationy2017presentation
A Mutually-Exclusive Deployment of Formal and Simulation Techniques Using Proof-Core AnalysisKeerthikumara Devarajegowda, Jeroen Vliegen, Goran Petrovity, and Kawe Fotouhi2017Papery2017paper
A New Approach to Low-Power Verification: Low Power AppsMadhur Bhargava and Awashesh Kumar2018Papery2018paper
A NOVEL AND EFFICIENT METHODOLOGY TO EXPEDITE COMPLEX SOC DV CLOSURE BY LEVERAGING MODULARLY ARCHITECTURED SCALABLE ENVIRONMENTVinay Swargam, Guttapalem Yatisha, Ayush Agrawal, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Papery2022paper
A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoCHarshal Kothari, Manishadevi Satyanarayana Cheernam, Vignesh Adiththan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath2022Papery2022paper
A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoCHarshal Kothari, Manishadevi Satyanarayana Cheernam, Vignesh Adiththan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath2022Postery2022poster
A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoCHarshal Kothari, Manishadevi Satyanarayana Cheernam, Vignesh Adiththan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath2022Presentationy2022presentation
A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform DevelopmentHarshal Kothari, Vinay Swargam, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Papery2022paper
A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform DevelopmentHarshal Kothari, Vinay Swargam, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Postery2022poster
A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform DevelopmentHarshal Kothari, Vinay Swargam, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Presentationy2022presentation
A Novel Approach to Functional Test Development and Execution using High-Speed IOMarcus Schulze Westenhorst, Jörg Simon, Markus Bücker, Klaus Dieter Hilliges, Michael Braun2021Papery2021paper
A NOVEL APPROACH TO HARDWARE CONTROLLED POWER AWARE VERIFICATION WITH OPTIMISED POWER CONSUMPTION TECHNIQUES AT SOCEldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Presentationy2022presentation
A NOVEL APPROACH TO HARDWARE CONTROLLED POWER AWARE VERIFICATION WITH OPTIMISED POWER CONSUMPTION TECHNIQUES AT SOCEldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Papery2022paper
A Novel Approach To In-System SRAM Repair Verification in Embedded SoC to Bridge Gap between Test and Functional ModeHarshal Kothari, Eldin Ben Jacob, Ajay Vamshi Krishna, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath2021Papery2021paper
A Novel Approach to Reuse Firmware for Verification of Controller based Sub-Systems using PSSVishnu Ramadas, Simranjit Singh, Ashwani Aggarwal, Woojoo Space Kim , Seonil Brian Choi2021Papery2021paper
A novel approach to standardize reusable Modular Plug and Play Skeleton Structure (MPPSS) to expedite verification closureHimanshu Dixit, Chandrachud Murali, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Papery2022paper
A novel approach to standardize reusable Modular Plug and Play Skeleton Structure (MPPSS) to expedite verification closureChandrachud Murali, Himanshu Dixit, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Postery2022poster
A Novel Approach to Standardize Verification Configurations using YAMLNikhil Tambekar2023Papery2023paper
A Novel Approach to Standardize Verification Configurations using YAMLNikhil Tambekar2023Presentationy2023presentation
A Novel Framework to Accelerate System Validation on EmulationManoj Sharma Khandelwal, Rinkesh Yadav, Sarang Kalbande & Garima Srivastav2023Papery2023paper
A Novel Performance Evaluation Methodology using Virtual Prototyping and EmulationWoojooSpace Kim2019Presentationy2019presentation
A Novel Performance Evaluation Methodology using Virtual Prototyping and EmulationWoojoo Space Kim2018Presentationy2018presentation
A Novel Processor Verification Methodology based on UVMAbhineet Bhojak, Tejbal Prasad, and Stephan Herrmann2015Papery2015paper
A perfect blend of verification techniques, platforms, and AI-empowered debugging in Ethernet Subsystem VerificationOlivera Stojanovic & Tijana Misic2023Papery2023paper
A Pragmatic Approach to Metastability-Aware SimulationJoseph Bulone, Roger Sabbagh2014Papery2014paper
A Pragmatic Approach to Metastability-Aware SimulationJoseph Bulone, Roger Sabbagh2014Presentationy2014presentation
A real world application of IP-XACT for IP packaging Bridging the usability gapPhilip Todd2014Papery2014paper
A real world application of IP-XACT for IP packaging Bridging the usability gapPhilip Todd2014Presentationy2014presentation
A Reconfigurable Interface Architecture to Protect System IPArshad Riazuddin, Shoab A. Khan2022Papery2022paper
A Reconfigurable Interface Architecture to Protect System IPArshad Riazuddin, Shoab A. Khan2022Presentationy2022presentation
A scalable VIP component to increase robustness of co-verification within an ASICMario de Matteis, Matteo Barbati2023Presentationy2023presentation
A scalableVIP component to increase robustness of co-verification within an ASICMario de Matteis & Matteo Barbati2023Papery2023paper
A Shift-left Methodology for an Early Power Closure Using EDCs and Power AnalysisMohammed Fahad2022Presentationy2022presentation
A shift-left Methodology for an early power closure using PowerProMohammed Fahad2022Papery2022paper
A Step Towards Zero Silicon Bugs Using Assertion Based Assumption ValidationRohit Kumar Sinha and Babu Christie2020Papery2020paper
A Step towards Zero Silicon Bugs: SVA Protocol Based Assumption ValidationRohit Kumar Sinha and Babu Christie2020Poster, Presentationy2020poster presentation
A Structured Approach to verify Ties, Unconnected Signals and ParametersSaurabh Singh, Peter Limmer, and Thomas Luedeke2016Presentationy2016presentation
A Structured Approach to verify Ties, Unconnected Signals and ParametersSaurabh Singh, Peter Limmer, and Thomas Luedeke2016Papery2016paper
A SystemC-based UVM verification infrastructureMike Bartley and Harshavardhan Narla2015Papery2015paper
A SystemC-based UVM verification infrastructureMike Bartley and Harshavardhan Narla2015Postery2015poster
A Tool for Investigating Cyber-Physical Systems via SystemC AMS Virtual Prototypes Derived from SysML ModelsDaniela Genius; Ludovic Apvrille2023Papery2023paper
A UVM Based Methodology for Processor VerificationAbhineet Bhojak, Stephan Herrmann, and TejbalPrasad2015Presentationy2015presentation
A UVM SystemVerilog Testbench for 5G/LTE Multi-Standard RF TransceiverByeong Kyu Kim, Jaeha Kim2022Papery2022paper
A UVM SystemVerilog Testbench for 5G/LTE Multi-Standard RF TransceiverByeongKyu Kim, Jaeha Kim2022Presentationy2022presentation
A UVM Test-bench Skeleton Leveraging the Event Pool and Sequence LayeringMarcela Zachariasova, Jiri Bartak, Tomas Pehnelt & Jan Riha2023Papery2023paper
Accelerate Functional Coverage Closure Using Machine-Learning-Based Test SelectionJakub Pluciński, Łukasz Bielecki, Robert Synoczek, Emelie Andersson, Antii Löytynoja, Cristian Macario2023Presentationy2023presentation
Accelerate Functional Coverage Closure Using Machine-Learning-Based Test SelectionJakub Pluciński, Łukasz Bielecki, Robert Synoczek, Emelie Andersson, Antii Löytynoja & Cristian Macario2023Papery2023paper
Accelerated Coverage Closure by Utilizing Local Structure in the RTL CodeRhys Buggy, Gokce Sarar, Guillaume Shippee, Han Nuou, Vishal Karna, Tushit Jain2021Papery2021paper
Accelerated SOC verification Using UVM Methodology for a Mix-signal Low Power DesignGiuseppe Scata, Ashwini Padoor, Vladimir Milosevic2014Papery2014paper
Accelerated SOC Verification Using UVM Methodology for a Mixed-Signal Low Power DesignGiuseppe Scata, Ashwini Padoor, Vladimir Milosevic2014Presentationy2014presentation
Accelerating and Improving FPGA Design Reviews Using Analysis ToolsAnna Tseng, Kurt Takara and Abdelouahab Ayari2020Papery2020paper
Accelerating and Improving FPGA Design Reviews Using Analysis ToolsAbdelouahab Ayari, Anna Tseng, and Kurt Takara2020Presentationy2020presentation
Accelerating Automotive Ethernet validation by leveraging Synopsys Virtualizer with TraceCompassAshish Gandhi, Praveen Kumar Kondugari and Sam Tennent2020Papery2020paper
Accelerating Automotive Ethernet validation by leveraging Synopsys Virtualizer with TraceCompassAshish Gandhi, Praveen Kumar Kondugari, and Sam Tennent2020Presentationy2020presentation
Accelerating Complex System Simulation using Parallel SystemC and FPGAsStanislaw Kaushanski, Johannes Wirth, Eyck Jentzsch, Andreas Koch2023Presentationy2023presentation
Accelerating Complex System Simulation using Parallel SystemC and FPGAsStanislaw Kaushanski, Johannes Wirth, Eyck Jentzsch & Andreas Koch2023Papery2023paper
Accelerating Functional Verification Coverage Data Manipulation Using Map ReduceEman El Mandouh, A. Gamal, A. Khaled, B. Amr G. Wassal, and Elsayed Hemayed2017Presentationy2017presentation
Accelerating Functional Verification Coverage Data Manipulation Using Map ReduceEman El Mandouh, A. Gamal, A. Khaled, T. Ibrahim, Amr G. Wassal, Elsayed Hemayed2017Papery2017paper
Accelerating RTL Simulation TechniquesLior Grinzaig2015Papery2015paper
Accelerating RTL Simulation TechniquesLior Grinzaig2015Presentationy2015presentation
Acceleration of product and test environment development using SystemC-TLMFlorian Barrau, Alexandre Piccini, Alexandre Nabais Moreno, Mark Burton, Luc Michel, Clement Descha2018Papery2018paper
Acceleration of product and test environment using SystemC TLMFlorian Barrau, Alexandre Piccini, Alexandre Nabais Mark Burton, Luc Michel, and Clement Deschamps2018Presentationy2018presentation
Accellera FS WG UpdateAlessandra Nardi, Ghani Kanawati2022Presentationy2022presentation
Accellera Functional Safety Working Group Update and Next StepsAlessandra Nardi, Ghani Kanawati2023Presentationy2023presentation
Accellera Systems InitiativeSystemC Standards UpdateMartin Barnasconi, Philipp A. Hartmann, Trevor Wieman2014Presentationy2014presentation
Accellera Systems InitiativeSystemC Standards UpdateMartin Barnasconi, Philipp A. Hartmann, and Stephan Schulz 2015Presentationy2015presentation
Achieve Complete SoC Memory Map Verification Through Efficient Combination of Formal and Simulation TechniquesClemens Roettgermann, Peter Limmer, and Michael Rohleder2015Papery2015paper
Achieve Complete SoC Memory Map Verification through Efficient Combination of Formal and Simulation TechniquesClemens Roettgermann, Peter Limmer, and Michael Rohleder2015Presentationy2015presentation
Achieving Faster Code Coverage Closure using High-Level SynthesisSurendhar Thudukuchi Chandrapandiyan, Preetham Lakshmikanthan, Ashwani Aggarwal, Youngchan Lee, Youngsik Kim, Seonil Brian Choi2021Papery2021paper
Achieving Faster Reset Verification Closure with Intelligent Reset Domain Crossings DetectionMilanpreet Kaur and Sulabh Kumar Khare2020Papery2020paper
Achieving Faster Reset Verification Closure with Intelligent Reset Domain Crossings DetectionMilanpreet Kaur and Sulabh Kumar Khare2020Poster, Presentationy2020poster presentation
Achieving Portable Stimulus with Graph-Based Verification – TutorialJosef Derner, Holger Horbach, Frederic Krampac, Staffan Berg2014Presentationy2014presentation
Achieving system dependability: the role of automation and scalabilityAlessandra Nardi2022Papery2022paper
Achieving system dependability: the role of automation and scalabilityTeo Cupaiuolo, Paul Baron, Ghani Kanawati2022Presentationy2022presentation
Addressing Asynchronous FIFO Verification ChallengeAnchal Gupta, Ashish Hari and Sulabh Kumar Khare2019Presentationy2019presentation
Addressing Asynchronous FIFO Verification ChallengeAnchal Gupta, Ashish Hari, Sulabh Kumar Khare2018Presentationy2018presentation
Addressing Renewed Gate Level Simulation Needs for 10nm-28nm and BelowGagandeep Singh2016Papery2016paper
Addressing the Complex Challenges in Low-Power Design and VerificationMadhur Bhargava, Durgesh Prasad, Jitesh Bansal, and Gabriel Chidolue2016Presentationy2016presentation
Addressing the Complex Challenges in Low-Power Design and VerificationMadhur Bhargava, Durgesh Prasad, and Jitesh Bansal2016Papery2016paper
Adopting UVM for safety Verification requirementsSrinivasan Venkatarmanan, Hemakiran Kolli, Gurubasappa Kinagi, and Satinder Paul Singh2017Presentationy2017presentation
Adopting UVM for safety Verification requirementsSrinivasan Venkatarmanan, Hema Kiran, and Satinder Paul Singh2017Papery2017paper
Advance Approach for Formal Verification of Configurable Pulse Width Modulation ControllerSumit K. Kulshreshtha, Raghavendra J N2021Papery2021paper
Advance your Design and Verification Flow Using IP XACTEdwin Dankert, Maximilian Albrecht and Vincent Thibaut2019Presentationy2019presentation
Advanced Techniques to Accomplish Power Aware CDC VerificationRohit K Sinha, Ashish Hari and Sulabh Kumar Khare2018Papery2018paper
Advanced UVM in the real world ‐ TutorialMark Litterick, Jason Sprott, Jonathan Bromley, and Vanessa Cooper2014Presentationy2014presentation
Advanced UVM Tutorial Taking Reuse to the Next LevelMark Litterick, Jason Sprott, and Jonathan Bromley2015Presentationy2015presentation
Advanced, High Throughput Debug From Design to SiliconGordon Allan & Michael Horn2015Presentationy2015presentation
Advancing the SystemC EcosystemPhilipp A Hartmann, Jerome Cornet, Martin Scnierginger, and Frederic Doucet2017Presentationy2017presentation
Advancing traceability and consistency in Verification and ValidationWalter Tibboel and Martin Barnasconi2014Papery2014paper
Advancing traceability and consistency in Verification and ValidationWalter Tibboel and Martin Barnasconi2014Postery2014poster
Agile and dynamic functional coverage using SQL on the cloudFilip Dojcinovic and Mihailo Ivanovic2019Presentationy2019presentation
Agile and dynamic functional coverage using SQL on the cloudFilip Dojcinovic and Mihailo Ivanovic2018Presentationy2018presentation
Agile Approaches to ASIC Verification (A3V) – A Novel Agile Flow in Functional VerificationAdithya Rangan, Vidyasagar Kantamneni, Vishal Dalal2022Papery2022paper
Agile Approaches to ASIC Verification (A3V) – A Novel Agile Flow in Functional VerificationAdithya Rangan CK, Vidyasagar Kantamneni, Vishal Dalal2022Presentationy2022presentation
Agnostic UVM-XX Testbench GenerationJacob Andersen, Stephan Gerth, and Filippo Dughetti2016Presentationy2016presentation
Agnostic UVM-XX Testbench Generation Replace XX (almost) as you see fit!Jacob Andersen, Stephan Gerth, and Filippo Dughetti2016Papery2016paper
Algorithm Verification with Open Source and System VerilogAndra Socianu and Daniel Ciupitu2014Presentationy2014presentation
AMS Verification in a UVM EnvironmentSilvia Strähle2016Presentationy2016presentation
AMS Verification in a UVM EnvironmentSilvia Strähle2016Papery2016paper
An Accelerated System Level CPU Verification through Simulation-Emulation Co-ExistenceRuchi Misra, Samridh Deva, Sai Krishna Pallekonda, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi2022Papery2022paper
An Accelerated System Level CPU Verification through Simulation-Emulation Co-ExistenceRuchi Misra, Samridh Deva, P Sai Krishna, Alok Kumar, Garima Srivastava YoungSik Kim, Seonil Brian Choi2022Presentationy2022presentation
An Analysis of Stimulus Techniques for Efficient Functional Coverage ClosureCaglayan Yalein, Aileen McCabe2021Papery2021paper
An Automated Formal Verification Flow for Safety RegistersHolger Busch2015Papery2015paper
An Automated Formal Verification Flow for Safety RegistersHolger Busch2015Presentationy2015presentation
An Automated Pre-silicon IP Trustworthiness Assessment for Hardware AssuranceJohn Hallman, David Landoll, Sergio Marchese, Sven Beyer, Garrett Chan, Salam Zantout and Vikram Rao2020Papery2020paper
An Automated Pre-silicon IP Trustworthiness Assessment for Hardware AssuranceJ. Hallman, D. Landoll, S. Marchese, S. Beyer, G. Chan, S. Zantout, and V. Rao2020Poster, Presentationy2020poster presentation
An Easy VE/DUV Integration ApproachUwe Simm2015Papery2015paper
An Easy VE/DUV Integration ApproachUwe Simm2015Presentationy2015presentation
An Effective Design and Verification Methodology for Digital PLLBiju Viswanathan, Rajagopal P.C, Ramya Nair S. R, Joseph J Vettickatt, and Jobin Cyriac2014Papery2014paper
An Effective Design and Verification Methodology for Digital PLLBiju Viswanathan, Rajagopal P.C, Ramya Nair S. R, Joseph J Vettickatt, and Jobin Cyriac2014Postery2014poster
An Efficient Methodology for Mutation-Coverage-Collection of Formal-Property-CheckingHolger Busch2022Papery2022paper
An Efficient Methodology for Mutation-Coverage-Collection of Formal-Property-CheckingHolger Busch2022Presentationy2022presentation
An efficient requirements-driven and scenario-driven verification flowHeino van Orsouw 2017Presentationy2017presentation
An efficient requirements-driven and scenario-driven verification flowWalter Tibboel, Heino van Orsouw, and Shuang Han2017Papery2017paper
An Efficient Verification Framework for Audio/Video Interface ProtocolsNoha Shaarawy, Mustafa Khairallah, Khaled Khalifa, Hany Salah, Amr Salah and Maged Ghoneima2015Papery2015paper
An Elegant scoreboard eco-system deploying UVM Callbacks, Parameterization for Multimedia designs from Imaging perspectiveChakravarthi Devakinanda Vurukutla, Sahana Ranganathan, Devendra Satish Bilaye, Vivek Kumar & Karthik Majeti2023Papery2023paper
An Elegant scoreboard eco-system deploying UVM Callbacks, Parameterization for Multimedia designs from Imaging perspectiveChakravarthi Devakinanda, Sahana Ranganathan, Devendra Satish Bilaye, Vivek Kumar & Karthik Majeti2023Presentationy2023presentation
An end-to-end approach to Design and Verify Battery Management Systems: from Requirements to Virtual Field TestingIrina Costachescu, Marius-Lucian Andrei, Manuel Fedou, Conrado Ramirez Garcia, 2022Papery2022paper
An end-to-end approach to Design and Verify BMS: from Requirements to Virtual Field TestingConrado Ramirez, Irina Costachescu, Marius Andrei, Carlos Villegas2022Presentationy2022presentation
An Improved Methodology for Debugging UPF Issues at SoC level Power Aware SimulationsRuchi Misra, S Shrinidhi Rao, Alok Kumar, Garima Srivastava & Sarang Kalbande2023Papery2023paper
An Introduction to using Event-B for Cyber-Physical System Specification and DesignJohn Colley and Michael Butler2014Presentationy2014presentation
An Open and Fast Virtual Platform for TriCore™-based SoCs Using QEMUBastian Koppelmann, Bernd Messidat, Markus Becker, and Christoph Kuznik2014Papery2014paper
An Open and Fast Virtual Platform for TriCore™-based SoCs Using QEMUBastian Koppelmann2014Postery2014poster
An open and flexible SystemC to VHDL workflow for rapid prototypingBastian Farkas2016Presentationy2016presentation
An open and flexible SystemC to VHDL workflow for rapid prototypingBastian Farkas, Syed Abbas Ali Shah, Jan Wagner, Rolf Meyer, Rainer Buchty, and Mladen Berekovic2016Papery2016paper
Analog Modelling to Suit Emulation for Hardware-Software Co-VerificationSaranya Das2020Papery2020paper
Analog Modelling to Suit Emulation for Hardware-Software Co-VerificationSaranya Das2020Poster, Presentationy2020poster presentation
Applying Design Patterns to accelerate development of reusable, configurable and portable UVCs. 2015Presentationy2015presentation
Applying Design Patterns to Maximize Verification Reuse at Block, Subsystem and System on Chip LevelPaul Kaunds, Revati Bothe and Jesvin Johnson2019Presentationy2019presentation
Attack Your SoCPowerChallenges with Virtual PrototypingStefan Thiel and Gunnar Braun2014Presentationy2014presentation
Automate and Accelerate RISC-V Verification by Compositional Formal MethodsYean-Ru Chen, Cheng-Ting Kao, Yi-Chun Kao, Tien-Yin Cheng, Chun-Sheng Ke and Chia-Hao Hsu2019Presentationy2019presentation
Automate and Accelerate RISC-V Verification by Compositional Formal MethodsYean-Ru Chen, Cheng-Ting Kao, Yi-Chun Kao, Tien-Yin Cheng, Chun-Sheng Ke and Chia-HaoHsu2018Presentationy2018presentation
Automate Interrupt Checking with UVM Macros and PythonAleksandra Dimanic, Nemanja Stevanovic, Yoav Furman, Itay Henigsberg2022Papery2022paper
Automate Interrupt Checking with UVM Macros and PythonAleksandra Dimanic, Nemanja Stevanovic, Yoav Furman, Itay Henigsberg2022Presentationy2022presentation
Automated Configuration of System Level C-Based CPU Testbench in Modern SoCs : A Novel FrameworkRuchi Misra, Chetan Kulkarni, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi2022Papery2022paper
Automated Configuration of System Level C-Based CPU Testbench in Modern SoCs : A Novel FrameworkRuchi Misra, Chetan Kulkarni, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi2022Presentationy2022presentation
Automated Configuration of Verification Environments using Specman Macros DVcon Europe 2018 – Paper number 260-OH22Milos Mirosavljevic, Ron Sela, Dejan Janjic and Efrat Shneydor2018Papery2018paper
Automated Configuration of Verification Environments using SpecmanMacrosMilos Mirosavljevic, Ron Sela, Dejan Janjic and Efrat Shneydor2018Presentationy2018presentation
Automated Creation of Reusable Generators for Analog IC Design with the Intelligent IP MethodUwe Eichler, Benjamin Prautsch, Torsten Reich2022Papery2022paper
Automated Creation of Reusable Generators for Analog IC Design with the Intelligent IP MethodUwe Eichler, Benjamin Prautsch, Torsten Reich2022Presentationy2022presentation
Automated SystemC Model Instantiation with modern C++ Features and sc_vectorRalph Görgen and Philipp A. Hartmann2015Papery2015paper
Automated SystemC Model Instantiation with modern C++ Features and sc_vectorRalph Görgen, Philipp A. Hartmann, and Wolfgang Nebel2015Presentationy2015presentation
Automatic Diagram Creation for Design and TestbenchesPaul O’Keeffe, Jamie Beattie and Gian Lorenzo2020Papery2020paper
Automatic Diagram Creation for Design and TestbenchesPaul O’Keeffe, Jamie Beattie, and Gian Lorenzo2020Poster, Presentationy2020poster presentation
Automatic Firmware Design for Application-specific Electronic Systems: Opportunities, Challenges and SolutionsDaniel Große, Joscha Benz, Vladimir Herdt, and Martin Dittrich2017Presentationy2017presentation
Automatic Firmware Verification for Automotive ApplicationsTorsten Andre and Daniel Valtiner2017Presentationy2017presentation
Automatic Firmware Verification for Automotive ApplicationsTorsten Andre and Daniel Valtiner2017Papery2017paper
Automatic Netlist Modifications required by Functional SafetyHarald Lüpken, Dirk Hönicke, and Michael Rohleder2014Papery2014paper
Automatic Netlist Modifications required by Functional SafetyHarald Lüpken, Dirk Hönicke, and Michael Rohleder2014Postery2014poster
Automatic Testbench Build to Reduce Cycle Time and Forster ReuseJoachim Geishauser and Alexander Schilling2017Papery2017paper
Automatic Testbench Build to Reduce Cycle Time and Foster ReuseJoachim Geishauser and Alexander Schilling2017Presentationy2017presentation
Be a Sequence Pro to Avoid Bad Con SequencesMark Litterick2019Presentationy2019presentation
Between the Dialog and the Algorithm or Innovative Technological Narratives Leveraging the Idea of Authenticity in a Human Being Visualizing log files enables intuitive comprehension of complex test scenariosAnna M. Ravitzki and Uri Feigin2017Papery2017paper
Bit density based pre characterization of RAM cells for area critical SOC designDilip Kumar Ajay ([email protected])2020Presentationy2020presentation
Bit Density-Based Pre-Characterization of RAM Cells for Area Critical SOC DesignDilip Kumar Ajay2020Papery2020paper
Boost your productivity in FPGA & ASIC design and verificationBart Brosens2022Papery2022paper
Boost your productivity in FPGA & ASIC design and verificationBart Brosens2022Presentationy2022presentation
Boosting Debug Productivity Practical Applications of Debug Innovations in a UVM WorldJoerg Richter2017Presentationy2017presentation
Boosting Mixed-Signal Design Productivity with FPGA-Based Methods Throughout the Chip Design ProcessGabriel Rutsch, Simone Fontanesi, Steven G. Herbst, Steven Tan Hee Yeng, Andrea Possemato, Gaetano Formato, Mark Horowitz, and Wolfgang Ecker2020Papery2020paper
Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven GenerationHoang M. Le and Rolf Drechsler2015Papery2015paper
Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven GenerationHoang M. Le and Rolf Drechsler2015Presentationy2015presentation
Break the SoC with UVM Dynamically Generated Program CodeBogdan Todea, Madhukar Mahadevappa & Pravin Wilfred2023Papery2023paper
Bridging the gap between system-level and chip-level performance optimizationSoniya Gupta, Vikrant Kapila & Holger Keding2023Papery2023paper
Bringing Reset Domains and Power Domains Together – Set/Reset Flops Augmenting Complexities in Power-Aware RDC Verification.Manish Bhati, Manjunatha Srinivas, Abdul Moyeen, Inayat Ali2021Papery2021paper
Build Reliable and Efficient Reset Networks with a Comprehensive Reset Domain Crossing Verification SolutionWanggen Shi, Yuxin You, and Kurt Takara2020Papery2020paper
Build Reliable and Efficient Reset Networks with a Comprehensive Reset Domain Crossing Verification SolutionWanggen Shi, Yuxin You, and Kurt Takara2020Presentationy2020presentation
Building a coherent ESL design and verification eco-system with SystemC, TLM, UVM-SystemC, and CCIMartin Barnasconi2016Papery2016paper
Building Code Generators for Reuse – Demonstrated by a SystemC GeneratorSaad Siddiqui and Ulrich Nageldinger2017Papery2017paper
Building Code Generators for Reuse – Demonstrated by a SystemC GeneratorUlrich Nageldinger and Saad Siddiqui2017Presentationy2017presentation
Building Confidence in System level CPU Cache Coherency Verification for Complex SoC’s through a Configurable, Flexible and Portable TestbenchRuchi Misra, Shrinidhi Rao, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi2022Papery2022paper
Building Confidence in System Level CPU Cache Coherency Verification for Complex SoCs through a Configurable Flexible and Portable Test BenchS Shrinidhi Rao, Ruchi Misra, Alok Kumar, Garima Srivastava, YoungSik Kim, Seonil Brian Choi2022Presentationy2022presentation
Building Smart SoCs Using Virtual Prototyping for the Design and SoC Integration of Deep Learning AcceleratorsHolger Keding2019Presentationy2019presentation
Cadence vManager Platform and Virtuoso ADE Verifier Leading-edge technologies provide methodology for mixedsignal verification closureKawe Fotouhi and Walter Hartong2019Presentationy2019presentation
Case Study of Verification Planning to Coverage Closure @Block, Subsystem and System on Chip LevelPaul Kaunds, Revati Bothe, and Jesvin Johnson2018Presentationy2018presentation
Catching the low hanging fruits on intel® Graphics DesignsM, Achutha KiranKumar V, Aarti Gupta, Bindumadhava S S, Savitha Manojna, and Abhijith A Bharadwaj2016Papery2016paper
Centralized Regression Optimisation Toolkit (CROT) for expediting Regression Closure With Simulator Performance OptimisationHarshal Kothari, Pavan M, Ajay Vamshi Krishna, Eldin Ben Jacob, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath2021Papery2021paper
Challenges and Solutions for Creating Virtual Platforms of FPGA and SASIC DesignsKalen Brunham, Jakob Engblom2022Presentationy2022presentation
Challenges and Solutions for Creating Virtual Platforms of FPGA and SASIC DesignsKalen Brunham, Jakob Engblom2022Papery2022paper
Challenges of VHDL X-propagation SimulationsKarthik Baddam and Piyush Sukhija2015Papery2015paper
Challenges of VHDL X-propagation SimulationsKarthik Baddam and Piyush Sukhija2015Presentationy2015presentation
Characterizing RF Wireless Receivers Performance in UVM EnvironmentSalwa Elqassas, Salwa Elqassas and Mohammed T. Abdel-Hafe2018Papery2018paper
Chiplevel Analog Regressions in ProductionYi Wang2021Papery2021paper
Clock Controller Unit Design Metrics: Area, Power, Software Flexibility and Congestion Impacts at System LevelMichele Chilla and Leonardo Gobbi2020Papery2020paper
Clock Tree Design Considerations in The Presence of Asymmetric Transistor AgingFreddy Gabbay; Firas Ramadan; Majd Ganaiem2023Papery2023paper
Closed-Loop Model-First SoC Development With the Intel® Simics® SimulatorKalen Brunham, Anthony Moore, Tobias Rozario, Wei Jun Yeap, and Jakob Engblom2023Presentationy2023presentation
Closed-Loop Model-First SoC Development With the Intel® Simics® SimulatorKalen Brunham, Anthony Moore, Tobias Rozario, Wei Jun Yeap, and Jakob Engblom2023Papery2023paper
Closing and AwardsAccellera Systems Initiative2022Videoy2022video
Closing Ceremony – DVCon Europe 20232023Videoy2023video
Closing the gap between requirement management and system design by requirement tracingHayri Verner Hasou, Guillermo Conde, Adrian Rolufs, Dominic Scharfe2022Papery2022paper
Closing the loop from requirements management to verification execution for automotive applicationsWalter Tibboel and Jan Vink2015Papery2015paper
Closing the loop from requirements management to verification execution for automotive applicationsWalter Tibboel and Jan Vink2015Presentationy2015presentation
Closing with AwardsAccellera Systems Initiative2022Videoy2022video
Clustering and Classification of UVM Test Failures Using Machine Learning TechniquesAndy Truong, Daniel Hellström, Harry Duque, and Lars Viklund2018Papery2018paper
Clustering and Classification of UVM Test Failures Using Machine Learning TechniquesAndy Troung, Daniel Hellström, Harry Duque, and Lars Viklund2018Presentationy2018presentation
Co-Design of Automotive Boardnet Topology and ArchitectureSebastian Post, Christoph Grimm2023Presentationy2023presentation
Co-Design of Automotive Boardnet Topology and ArchitectureSebastian Post; Christoph Grimm2023Papery2023paper
Combining Static and Dynamic Low Power Verification for the Power-Aware SoC Sign-offHimanshu Bhatt and Prashanth M2014Papery2014paper
Combining Static and Dynamic Low Power Verification for the Power-Aware SoC Sign-offHimanshu Bhatt, Prashanth M, and Adiel Khan2014Presentationy2014presentation
Complete Formal Verification of a Family of Automotive DSPsRafal Baranowski and Marco Trunzer2016Presentationy2016presentation
Complete Formal Verification of a Family of Automotive DSPsRafal Baranowski and Marco Trunzer2016Papery2016paper
Complex Low Power Verification Challenges in NextGen SoCs : Taming the Beast!Abhinav Nawal, Gaurav Jain, and Joachim Geishauser2014Presentationy2014presentation
Complex Low Power Verification Challenges in NextGen SoCs: Taming the Beast!Abhinav Nawal and Gaurav Jain2014Papery2014paper
Comprehensive AMS Verification using Octave, Real Number Modelling and UVMJohn McGrath, Patrick Lynch, and Ali Boumaalif2015Papery2015paper
Comprehensive AMS Verification using Octave, Real Number Modelling and UVMJohn McGrath, Patrick Lynch, and Ali Boumaalif2015Presentationy2015presentation
Connecting a Company’s Verification Methodology to Standard Concepts of UVMFrank Poppen, Marco Trunzer, and Jan‐Hendrik Oetjens2014Papery2014paper
Connecting a Company’s Verification Methodology to Standard Concepts of UVMFrank Poppen, Marco Trunzer, and Jan‐Hendrik Oetjens2014Presentationy2014presentation
Connecting Enterprise Applications to Metric Driven VerificationMatt Graham2014Papery2014paper
Connecting Enterprise Applications to Metric Driven VerificationMatt Graham2014Presentationy2014presentation
Control Flow Analysis for Bottom-up Portable Models CreationPetr Bardonek; Marcela Zachariasova2023Papery2023paper
Covering the Last Mile in SoC-Level Deadlock VerificationJef Verdonck, Khaled Nsaibia, Sagar Dewangan, HarGovind Singh and Roger Sabbagh2019Presentationy2019presentation
Covering the Last Mile in SoC-Level Deadlock VerificationJef Verdonck, Dhruv Gupta, and HarGovind Singh2018Presentationy2018presentation
CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemCHoang M. Le and Rolf Drechsler2014Papery2014paper
CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemCHoang M. Le and Rolf Drechsler2014Presentationy2014presentation
Customizing UVM Agent Supporting Multi-Layered & TDM ProtocolsAmit Pessach2019Presentationy2019presentation
Customizing UVM Agent Supporting Multi-Layered & TDM ProtocolsAmit Pessach2018Presentationy2018presentation
Data path verification on cross domain with formal scoreboardLiu Jun2014Papery2014paper
Data path verification on cross domain with formal scoreboardLiu Jun2014Postery2014poster
Day 1 OpeningAccellera Systems Initiative2022Videoy2022video
Day 2 OpeningAccellera Systems Initiative2022Videoy2022video
Democratizing Formal VerificationTobias Ludwig, Michael Schwarz, Paulius Morkunas, Silvio Santana, Dominik Stoffel, Wolfgang Kunz2021Papery2021paper
Deploying HLS in a DO-254/ED-80 WorkflowTammy Reeve, Jacob Wiltgen, Byron Brinson, and David Aerne2020Papery2020paper
Deploying HLS in a DO-254/ED-80 WorkflowByron Brinson Jacob Wiltgen, David Aerne and Tammy Reeve2020Poster, Presentationy2020poster presentation
Design and verification in ARMHobson Bullman2016Presentationy2016presentation
Design Verification of the Quantum Control StackSeyed Amir Alavi, Samin Ishtiaq, Nick Johnson, Rojalin Mishra, Dwaraka O N, Asher Pearl and Jan Snoeijs2023Papery2023paper
Designing a PSS Reuse StrategyMatthew Ballance2019Presentationy2019presentation
Designing a PSS Reuse StrategyMatthew Ballance2018Presentationy2018presentation
Designing the Future with Efficiency Guidance to Adopting SystemVerilog for Design!Axel Scherer and Junette Tan2015Papery2015paper
Detection of glitch-prone clock and reset propagation with automated formal analysisKaushal Shah, Sulabh Kumar Khare2021Papery2021paper
Developing & Testing Automotive Software on Multi SoC ECU Architectures using Virtual PrototypingSam Tennent2018Presentationy2018presentation
Developing Dynamic Resource Management System in SoCEmulationSeonchang Choi, Sangwoo Noh, Seonghee Yim and Seonil Brian Choi2019Presentationy2019presentation
Developing Dynamic Resource Management System in SoCEmulationSeonchang Choi and Seonghee Yim2018Presentationy2018presentation
Development and Verification of RISC-V Based DSP Subsystem IP: Case StudyPascal Gouedo, Damien Le Bars, Olivier Montfort, Lee Moore, Aimee Sutton, Larry Lapides2022Papery2022paper
Development of a Core-Monitor for HW/SW Co-Debugging targetting Emulation PlatformShreya Morgansgate, Johannes Grinschgl, Djones Lettnin2022Presentationy2022presentation
Development of Flexi Performance Analysis Platform for Multi–SoC Networking SystemsSrinivasan Reddy Devarajan, Anant Raj Gupta, IngoVolkening, Franz Josef Schaefer and Vijay Raj Franklin Paul Rajan William2019Presentationy2019presentation
Discovering Deadlocks in a Memory Controller IPJef Verdonck, Emrah Armagan, Khaled Nsaibia, Slava Bulach, Pranay Gupta, Anshul Jain, Chirag Agarwal and Roger Sabbagh2020Papery2020paper
Discovering Deadlocks in a Memory Controller IPJef Verdonck, Emrah Armagan, Khaled Nsaibia, Slava Bulach, Pranay Gupta, Anshul Jain, Chirag Agarwal, and Roger Sabbagh2020Presentationy2020presentation
Does It Pay Off To Add Portable Stimulus Layer On Top Of UVM IP Block Test Bench?Xia Wu, Jacob Sander Andersen and Ole Kristoffersen2020Papery2020paper
Does It Pay Off To Add Portable Stimulus Layer On Top Of UVM IP Block Test Bench?Xia Wu, Jacob Sander Andersen, and Ole Kristoffersen2020Presentationy2020presentation
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in SiliconAbdelouahab Ayari, Sukriti Bisht, Sulabh Kumar Khare and Kurt Takara2019Presentationy2019presentation
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in SiliconAbdelouahab Ayari, Sukriti Bisht, Sulabh Kumar Khare, and Kurt Takara2018Presentationy2018presentation
DSA Monitoring Framework for HW/SW Partitioning of Application Kernels leveraging VPChristoph Hazott, Daniel Große2023Presentationy2023presentation
DSA Monitoring Framework for HW/SW Partitioning of Application Kernels leveraging VPsChristoph Hazott; Daniel Grosse2023Papery2023paper
DVCon EU 2014 ProceedingsAccellera Systems Initiative2014Programy2014program
DVCon EU 2015 ProceedingsAccellera Systems Initiative2015Programy2015program
DVCon EU 2016 ProceedingsAccellera Systems Initiative2016Programy2016program
DVCon EU 2017 ProceedingsAccellera Systems Initiative2017Programy2017program
DVCon EU 2018 ProceedingsAccellera Systems Initiative2018Programy2018program
DVCon EU 2019 ProceedingsAccellera Systems Initiative2019Programy2019program
DVCon EU 2020 ProceedingsAccellera Systems Initiative2020Videoy2020video
DVCon EU 2020 ProceedingsAccellera Systems Initiative2020Programy2020program
DVCon EU 2021 ProceedingsAccellera Systems Initiative2021Programy2021program
DVCon Europe 2015 Road to self driving cars: View of a semiconductor companyHans Adlkofer2015Presentationy2015presentation
DVCon Europe 2022 Proceedings Showcase LinkAccellera Systems Initiative2022Videoy2022video
Dynamic Fault Injection Library Approach for SystemC AMSThomas Markwirth, Paul Ehrlich, and Dominik Matter2016Presentationy2016presentation
Dynamic Fault Injection Library Approach for SystemC AMSThomas Markwirth, Paul Ehrlich, and Dominik Matter2016Papery2016paper
Early Performance Verification of Embedded Inferencing Systems using open source SystemC NVIDIA MatchLibHerbert Taucher and Russell Klein2019Presentationy2019presentation
Easier UVM – Making Verification Methodology More ProductiveJohn Aynsley and David Long2014Presentationy2014presentation
Easier UVM: Learning and Using UVM with a Code GeneratorJohn Aynsley, Doulos2015Presentationy2015presentation
Effective Design Verification – Constrained Random with Python and CocotbDeepak Narayan Gadde, Suruchi Kumari & Aman Kumar2023Papery2023paper
Efficient Clock Monitoring System for SoC Clock VerificationNam Pham Van2016Presentationy2016presentation
Efficient Clock Monitoring System for SoC Clock VerificationNam Pham Van, Bernhard Braun, Dirk Moeller, and Clemens Roettgermann2016Papery2016paper
Efficient Constrained Random Generation of Address Blocks: A comparative study of simulation speedsMeenakshy Ramachandran2015Papery2015paper
Efficient Constrained Random Generation of Address Blocks: A comparative study of simulation speedsMeenakshy Ramachandran2015Postery2015poster
Efficient Debugging on Virtual Prototype using Reverse Engineering MethodSandeep Puttappa, Dineshkumar Selvaraj & Ankit Kumar2023Papery2023paper
Efficient Debugging on Virtual Prototype using Reverse Engineering MethodSandeep Puttappa, Dineshkumar Selvaraj & Ankit Kumar2023Presentationy2023presentation
Efficient Exploration of Safety-Relevant Systems Through a Link Between Analysis and SimulationMoomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello, and Bogdan-Andrei Tabacaru2016Presentationy2016presentation
Efficient Exploration of Safety-Relevant Systems Through a Link Between Analysis and SimulationMoomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello, and Bogdan-Andrei Tabacaru2016Papery2016paper
Efficient Fault Injection Methods for Safety Software Testing Based on Virtual Prototypes: Application to Powertrain ECUOns Mbarek, Dineshkumar Selvaraj, and Romero Chica Jose Miguel2018Papery2018paper
Efficient Loosely-Timed SystemC TLM-2.0 Modeling: A Hands-On TutorialNils Bosbach, Lukas Junger, Rainer Leupers2022Papery2022paper
Efficient Loosely-Timed SystemC TLM-2.0 Modeling: A Hands-On TutorialNils Bosbach, Lukas Jünger, Rainer Leupers2022Presentationy2022presentation
Efficient use of Virtual Prototypes in HW/SW Development and VerificationRocco Jonack and Eyck Jentzsch2018Presentationy2018presentation
Efficient Verification Framework for Audio/Video InterfacesNoha Shaarawy2015Presentationy2015presentation
Efficient Verification of a RADAR SoC Using Formal and Simulation-Based MethodsAman Kumar, Mark Litterick & Samuele Candido2023Papery2023paper
Emulation based Power and Performance Workloads on ML NPUsPragati Mishra, Ritu Suresh, Issac P Zacharia, Jitendra Aggarwal2021Papery2021paper
Enabling Digital Mixed-Signal Verification of Loading Effects in Power Regulation using SystemVerilog User-Defined NettypeAlvaro Caicedo and Sebastian Fritz2019Presentationy2019presentation
Enabling Digital Mixed-Signal Verification of Loading Effects in Power Regulation using SystemVerilog User-Defined NettypeAlvaro Caicedo and Sebastian Fritz2018Presentationy2018presentation
Enabling Energy Aware System Level Design with UPF-Based System Level Power ModelsT4A and T4B2014Presentationy2014presentation
Enabling Visual Design Verification Analytics – From Prototype Visualizations to an Analytics Tool using the Unity Game EngineMarkus Borg, Andreas Brytting, and Daniel Hansson2018Papery2018paper
Energy-efficient High Performance Compute, at the heart of Europe2023Presentationy2023presentation
Enhancements of metric driven verification for the ISO26262: Recent advancements better supporting specific verification requirements including functional safetyMichael Rohleder, Clemens Röttgermann, Stephan Rüttiger, John Brennan, Matt Graham, and Riccardo Oddone2016Papery2016paper
Enhancing Quality and Coverage of CDC Closure in Intel’s SoC DesignRohit Kumar Sinha2020Papery2020paper
Enhancing Quality and Coverage of CDC Closure in Intel’s SoC DesignRohit Kumar Sinha2020Presentationy2020presentation
Enriching UVM in SystemC with AMS extensions for randomization and functional coverage*Thilo Vörtler, Thomas Klotz, Karsten Einwich, Yao Li, Zhi Wang, Marie-Minerve Louërat, Jean-Paul Chaput, François Pêcheux, Ramy Iskander, and Martin Barnasconi2014Papery2014paper
Enriching UVM in SystemC with AMS extensions for randomization and functional coverage*Thilo Vörtler, Thomas Klotz, Karsten Einwich, Yao Li, Zhi Wang, Marie-Minerve Louërat, Jean-Paul Chaput, François Pêcheux, Ramy Iskander, and Martin Barnasconi2014Presentationy2014presentation
ESL Design and Modeling with SystemCAMS for Mixed-Signal IoTand Automotive ApplicationsKarsten Einwich, Martin Barnasconi, Christoph Grimm, and Torsten Mähne2017Presentationy2017presentation
Evaluation of the RISC-V Floating Point ExtensionsNiko Zurstrassen; Lennart M. Reimann; Nils Bosbach; Lukas Juenger; Rainer Leupers2023Papery2023paper
Experience of Using Formal Verification for a Complex Memory Subsystem DesignSujeet Kumar, Vandana Goel, Hrushikesh Vaidya and Ronak Sarikhada2020Papery2020paper
Experience of using Formal Verification for a Complex Memory Subsystem DesignSujeet Kumar,Vandana Goel,Hrushikesh Vaidya, and Ronak Sarikhada2020Poster, Presentationy2020poster presentation
Exploring New Frontiers of High-Performance Verification with UVM-AMSTim Pylant2023Presentationy2023presentation
Extending functionality of UVM components by using Visitor design patternDarko M. Tomušilović2018Papery2018paper
Extending functionality of UVM components by using Visitor design patternDarko M. Tomušilović2018Presentationy2018presentation
Extending Proven Digital Verification Techniques for Mixed-Signal SoCswith VCS AMSHelene Thibieroz, Adiel Khan, Pierluigi Daglio, and Gernot Koch2014Presentationy2014presentation
Extending the UVM register model generation and integration flow to support user-defined scenarios and register mask valuesShuang Han, Kees van Kaam, and Martin Barnasconi2017Presentationy2017presentation
Extending the UVM register model generation and integration flow to support user-defined scenarios and register mask valuesShuang Han, Kees van Kaam, and Martin Barnasconi2017Papery2017paper
Extending UVM Register Abstraction Layer for Verification of Register Access via Serial Bus InterfaceDarko M. Tomušilović2016Presentationy2016presentation
Extending UVM Register Abstraction Layer for Verification of Register Access via Serial Bus InterfaceDarko Tomušilović2016Papery2016paper
Facilitating Transactions in System Verilog and VHDLRich Edelman2020Presentationy2020presentation
Facilitating Transactions in VHDL and SystemVerilogRich Edelman2020Papery2020paper
Fast and Furious Quick Innovation from Idea to Real PrototypeSimone Fontanesi, Gaetano Formato, Thomas Arndt, and Andrea Monterastelli2018Papery2018paper
Fast and FuriousQuick Innovation from Idea to Real PrototySimone Fontanesi, Gaetano Formato, Thomas Arndt, and Andrea Monterastelli2018Presentationy2018presentation
Fast, Parallel RISC-V Simulation for Rapid Software VerificationLukas Jünger, Jan Henrik Weinstock, Rainer Leupers2022Presentationy2022presentation
Fault Effect Propagation using Verilog A for Analog Test CoverageAishwarya Prabhakaran, Ahmed Sokar, and Jaafar Mejri2018Presentationy2018presentation
Fault Effect Propagation using Verilog-A for Analog Test CoverageAishwarya Prabhakaran, Ahmed Sokar and Jaafar Mejri2018Papery2018paper
Fault Injection Analysis for Automotive Safety and SecuritySesha Sai Kumar C V, Ayman Mouallem, Jamil Mazzawi2022Presentationy2022presentation
Fault Injection Analysis for Automotive Safety and SecuritySesha Sai Kumar C.V., Jamil Mazzawi, Ayman Mouallem 2022Papery2022paper
Fault Proof: Using Formal Techniques for Safety Verification and Fault AnalysisAdrian Traskov, Thorsten Ehrenberg, Sacha Loitz, Abdelouahab Ayari, Avidan Efody, and Joseph Hupcey III2016Presentationy2016presentation
Fault Proof: Using Formal Techniques for Safety Verification and Fault AnalysisAdrian Traskov,Thorsten Ehrenberg, Sacha Loitz, Abdelouahab Ayari, Avidan Efody, and Joseph Hupcey III2016Papery2016paper
Fault-injection-Enhanced Virtual Prototypes Enable Early SW Development for Automotive ApplicationsMohammad Badawi, Javier Castillo, Andreas Mauderer & Jan-Hendrik Oetjens2023Papery2023paper
Fault-injection-Enhanced Virtual Prototypes Enable Early SW Development for Automotive ApplicationsMohammad Badawi, Javier Castillo, Andreas Mauderer & Jan-Hendrik Oetjens2023Presentationy2023presentation
Firmware Firmly under Control: New Optimization and Verification Techniques for Application Specific Electronic SystemDaniel Große, Manuel Strobel, Daniel Mueller-Gritschneder, Vladimir Herdt, and Tobias Ludwig2018Presentationy2018presentation
Five Ways to Make Your Specman Environment More Reusable and ConfigurableStefan Sljukic, Nikola Knezevic, Filip Dojcinovic2021Papery2021paper
Flexible Indirect Registers With UVMUwe Simm2017Presentationy2017presentation
Flexible Indirect Registers With UVMUwe Simm2017Papery2017paper
Formal Fault Propagation Analysis that Scales to Modern Automotive SoCsSergio Marchese2017Presentationy2017presentation
Formal Fault Propagation Analysis that Scales to Modern Automotive SoCsSergio Marchese and Jörg Grosse2017Papery2017paper
Formal Property Verification of the Digital Section of an Ultra-Low Current Digitizer ASICKatharina Ceesay-Seitz, Sarath Kundumattathil Mohanan, Hamza Boukabache, Daniel Perrin2021Papery2021paper
Formal Verification Experiences: Silicon Bug Hunt with “Deep Sea Fishing”Mark Handover, Abdelouahab Ayari and Ping Yeung2020Papery2020paper
Formal Verification Experiences: Silicon Bug Hunt with “Deep Sea Fishing”Ping Yeung, Mark Handover, and Abdelouahab Ayari2020Poster, Presentationy2020poster presentation
Formal Verification of a Highly Configurable DDR Controller IPSumit Neb, Chirag Agarwal, Deepak K. Gupta, and Roger Sabbagh2018Papery2018paper
Formal Verificationin the Real WorldJonathan Bromley and Jason Sprott2017Presentationy2017presentation
FPGA Debug Using Configuration ReadbackMike Dini 2015Presentationy2015presentation
Functional Safety Verification for ISO 26262 – Compliant Automotive DesignsJM Forey and Werner Kerscher2018Presentationy2018presentation
Functional Safety WG UpdateAlessandra Nardi2022Papery2022paper
Fuzzing Firmware Running on Intel® Simics® Virtual PlatformsJakob Engblom, Robert Guenzel2023Presentationy2023presentation
Fuzzing Firmware Running on Intel® Simics® Virtual PlatformsJakob Engblom & Robert Guenzel2023Papery2023paper
Gathering Memory Hierarchy Statistics in QEMUClément Deschamps, Mark Burton, Eric Jenn and Frédéric Pétrot2019Presentationy2019presentation
Gathering Memory Hierarchy Statistics in QEMUClément Deschamps, Mark Burton, Eric Jenn, and Frédéric Pétrot2018Presentationy2018presentation
Generating Bus Traffic PatternsJacob Sander Andersen, Lars Viklund and Kenneth Branth2018Papery2018paper
Generation of (at least) UVM Register Models from IP Xact Using Model Driven SW TechniquesJacob Sander Andersen2017Presentationy2017presentation
Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS*Ronan Lucas, Marie-Minerve Louërat, Yao Li, Zhi Wang, Jean-Paul Chaput, François Pêcheux, Ramy Iskander, Martin Barnasconi, and Thilo Vörtler2014Papery2014paper
Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS*Ronan Lucas and Philippe Cuenot2014Presentationy2014presentation
Generic Core-Monitor for Hardware/Software Co-Debugging targeting Emulation PlatformShreya Morgansgate, Johannes Grinschgl, Djones Lettnin2022Papery2022paper
Generic Testbench/Portable Stimulus/PromotabilityRevati Bothe and Jesvin Johnson2019Presentationy2019presentation
Go Figure – UVM Configure The Good, The Bad, The DebugRich Edelman and Dirk Hansen2016Presentationy2016presentation
Go Figure – UVM Configure The Good, The Bad, The DebugRich Edelman and Dirk Hansen2016Papery2016paper
Golden UPF: Preserving Power Intent From RTL to ImplementationHimanshu Bhatt and Harsh Chilwal2015Presentationy2015presentation
Grid-based Mapping and Analysis of a GoogLeNet CNN using MapGL EditorClaudio Raccomandato, Emad M. Arasteh & Rainer Dömer2023Presentationy2023presentation
Grid-based Mapping and Analysis of a GoogLeNet CNN using MapGL EditorClaudio Raccomandato, Emad M. Arasteh & Rainer Dömer2023Papery2023paper
Guiding Functional Verification Regression Analysis Using Machine Learning and Big Data MethodsEman El Mandouh, Laila Maher, Moutaz Ahmed and Amr G. Wassal2018Papery2018paper
Handling Asynchronous Reset(s) Testing by building reset-awareness into UVM testbench componentsWei Wei Cheong, Katherine Garden, Ana Sanz Carretero2021Papery2021paper
Hardware construction with SystemCRoman Popov and Roman Popov2018Papery2018paper
Hardware Software Co-verification in Hybrid QEMU/HDL EnvironmentRadoslaw Nawrot and Krzysztof Szczur2018Presentationy2018presentation
Hardware/Software Co-Simulation of SPI enabled ASICs and Software Drivers for Fault Injection and Regression TestsElias Kyrlies-Chrysoulidis, Andreas Plange, Thomas Gürtler, Matthias Auerswald, and Josef Schmid2014Papery2014paper
Hardware/Software Co-Simulation of SPI enabled ASICs and Software Drivers for Fault Injection and Regression TestsElias Kyrlies-Chrysoulidis, Andreas Plange, Thomas Guertler, Matthias Auerswald, and Josef Schmid2014Postery2014poster
Heterogeneous Virtual Prototyping for IoTApplicationsPaul Ehrilich, Karsten Einwich, Mark Burton, and Luc Michel2017Presentationy2017presentation
Heterogenous Virtual Prototyping for IoT ApplicationsMark Burton, Luc Michel, Paul Ehrlich, and Karsten Einwich2017Papery2017paper
High-Performance Mixed-Signal ESL Design of a Magneto Resistive Sensor ApplicationMartin Barnasconi and Sumit Adhikari2016Presentationy2016presentation
High-Performance Mixed-Signal ESL Design of a Magneto Resistive Sensor ApplicationMartin Barnasconi and Sumit Adhikari2016Papery2016paper
How creativity kills reuse – A modern take on UVM/SV TB architectureAndrei Vintila, Sergiu Duda2022Papery2022paper
How creativity kills reuse – A modern take on UVM/SV TB architecturesAndrei Vintila, Sergiu Duda2022Presentationy2022presentation
How Far Can You Take UVM Code Generation and Why Would You Want To?John Aynsley2016Presentationy2016presentation
How Far Can You Take UVM Code Generation and Why Would You Want To?John Aynsley2016Papery2016paper
How rich descriptions enable early detection of hookup issuesPeter Birch, Thomas Brown2022Presentationy2022presentation
How the Right Mindset Increases Quality in RISC-V VerificationPhilippe Luc, Salaheddin Hetalani, Nicolae Tusinschi2022Papery2022paper
How the Right Mindset Increases Quality in RISC-V VerificationPhilippe Luc, Salaheddin Hetalani2022Presentationy2022presentation
How to achieve verification closure of configurable code by combining static analysis and dynamic testingAntonello Celano, Alexandre Langenieux2022Presentationy2022presentation
How to achieve verification closure of configurable code by combining static analysis and dynamic testingAntonello Celano, Alexandre Langenieux2022Papery2022paper
How to Create a Complex Testbench in a Couple of HoursTom Fitzpatrick and Graeme Jessiman2017Presentationy2017presentation
How to leverage the power of MATLAB from Functional Verification Test BenchesTom Richter2023Presentationy2023presentation
How to Use Formal Analysis to Prevent DeadlocksAbdelouahab Ayari, Mark Eslinger and Joe Hupcey III2020Presentationy2020presentation
How to Verify Complex FPGA Designs for FreeSebastian Dreßler, Nikos Anastasiadis, and Thomas Richter2016Presentationy2016presentation
How to Verify Complex FPGA Designs for FreeSebastian Dreßler, Nikos Anastasiadis, and Thomas Richter2016Papery2016paper
How To Verify Encoder And Decoder Designs Using Formal VerificationJin Hou2020Papery2020paper
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HW-SW-Coverification as part of CI/CDAlexander Hoffmann, Ganesh Nair, Nan Ni & Johannes Grischgl2023Papery2023paper
Hybrid Emulation for faster Android Home screen bring up and Software DevelopmentRinkesh Yadav, Manoj Khandelwal, Sarang Kalbande & Garima Srivastava2023Papery2023paper
Hybrid Flow: A smart methodolgy to migrate from traditional Low Power MethodologyRohit Kumar Sinha and N. Prashanth2018Papery2018paper
Hybrid Flow: A smart methodology to migrate from traditional Low Power MethodologyRohit Kumar Sinha and Prashanth N2018Presentationy2018presentation
IEEE 1801 Assisted Custom IP Development and Low Power Checks Using Cadence Virtuoso Power ManagerDr. Matthias Steffen, Amit Chopra and Amit Chopra2018Papery2018paper
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Implementation of a closed loop CDC verification methodologyAndrew Cunningham, Ireneusz Sobanski2014Papery2014paper
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Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design VerificationDeepak Narayan Gadde, Sebastian Simon, Djones Lettnin, Thomas Ziller2022Papery2022paper
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Improving the Confidence Level in Functional Safety Simulation Tools for ISO 26262Ahmet Cagri Bagbaba, Felipe Augusto Da Silva, and Christian Sauer2018Papery2018paper
Increased Regression Efficiency with Jenkins Continuous IntegrationThomas Ellis2016Papery2016paper
Increasing Efficiency and Reuse in Modeling SystemC/TLM IPs Targeting Virtual Prototypes for Software DevelopmentDavid Spieker, Thomas Schuster, Rafael Zuralski, and Christian Sauer2020Papery2020paper
Initialization Techniques for D-Flip-Flop Based Scan Chain with Scan Flush Architecture in Gate-Level SimulationWei Jun Yeap, Rahul Chauhan & Wonyoung Choi2023Papery2023paper
Innovative Technological Narratives Leveraging the Idea of Authenticity in a Human BeingAnna M. Ravitzki, Uri Feigin, and Hagai Arbel2017Presentationy2017presentation
Institutionalize a certified ISO26262 safety processM. Rohleder, C. Röttgermann, amd M. Müller2016Presentationy2016presentation
Institutionalizing a certified ISO26262 safety process: Experiences and lessons learnedMichael Rohleder, Clemens Röttgermann, and Marcus Müller2016Papery2016paper
Integrating a Virtual Platform Framework for Smart DevicesV. Guarnieri, F. Stefanni, F. Fummi, M. Grosso, D. Lena, A. Ciccazzo, G. Gangemi, and S. Rinaudo2015Presentationy2015presentation
Integrating Different Types of Models into a Complete Virtual SystemJakob Engblom, Andreas Hedström, Xiuliang Wang, and Håkan Zeffer2016Presentationy2016presentation
Integrating Different Types of Models into a Complete Virtual System: The Simics SystemC* LibraryJakob Engblom, Andreas Hedström, Xiuliang Wang, and Håkan Zeffer2016Papery2016paper
Integrating Parallel SystemC Simulationinto Simics® Virtual PlatformDaniel Mendoza, Ajit Dingankar, ZhongqiCheng and Rainer Doemer2019Presentationy2019presentation
Integrating Parallel SystemC Simulationinto Simics® Virtual PlatformDaniel Mendoza, Ajit Dingankar, Zhongqi Cheng and Rainer Doemer2018Presentationy2018presentation
Integration of modern verification methodologies in a TCL test frameworkMatteo De Luigi and Alessandro Ogheri2015Papery2015paper
Integration Verification of Safety Components in Automotive Chip ModulesHolger Busch2023Papery2023paper
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Introduction to Next Generation Verification Language – VlangPuneet Goel and Sumit Adhikari2014Papery2014paper
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IP-Coding Style Variants in a Multi-layer Generator FrameworkZhao Han, Keerthikumara Devarajegowda, Andreas Neumeier and Wolfgang Ecker2020Papery2020paper
IP-Coding Style Variants in a Multi-layer Generator FrameworkZhao Han, Keerthikumara Devarajegowda, Andreas Neumeier, and Wolfgang Ecker2020Poster, Presentationy2020poster presentation
Is Your Testing N wise or Unwise? Pairwise and N wise Patterns in SystemVerilog for Efficient Test Configuration and StimulusJonathan Bromley and Kevin Johnston2015Presentationy2015presentation
Is Your Testing N-wise or Unwise? Pairwise and N-wise Patterns in SystemVerilog for Efficient Test Configuration and StimulusJonathan Bromley and Kevin Johnston2015Papery2015paper
ISO 26262 Fault Analysis in Safety Mechanisms Considering the impact of residual and latent faults in hardware safety mechanismsJörg Grosse, Mark Hampton, Sergio Marchese, Jörg Koch, Neil Rattray and Alin Zagardan2019Presentationy2019presentation
ISO 26262: Better be safe with modelling and simulation on system-levelJoachim Hößler, Sven Johr, Thang Nguyen, Stephan Schulz, and Gert-Jan Tromp2014Papery2014paper
ISO 26262: Better be safe with modelling and simulation on system-levelJoachim Hößler, Sven Johr, Thang Nguyen, Stephan Schulz, and Gert-Jan Tromp2014Postery2014poster
Keynote: Challenges in Soc Verification for 5G and BeyondAxel Jahnke2022Videoy2022video
Keynote: Developing the Chip-to-Cloud Architecture for the Most Desirable CarsMagnus Östberg2022Videoy2022video
Keynote: Energy-efficient High Performance Compute, at the heart of Europe2023Videoy2023video
Keynote: Pervasive and Sustainable AI with Adaptive Computing2023Videoy2023video
Language Agnostic Communication for SystemC TLM Compliant Virtual PrototypesSmurti Khire, Kunal Sharma, Vishal Chovatiya2021Papery2021paper
Large-scale Gatelevel Optimization Leveraging Property CheckingLucas Klemmer; Dominik Bonora; Daniel Grosse2023Papery2023paper
Lean Verification Techniques: Executable SystemVerilog UVM Defect Table For SimulationsSteve Burchfiel, Kevin Schott, Kamel Belhous and Paul Ulrich2020Papery2020paper
Lean Verification Techniques: Executable SystemVerilog UVM Defect Table For SimulationsKamel Belhous and Steve Bu2020Presentationy2020presentation
Leveraging hardware emulation to accelerate SoCverification in multi-physics automotive simulation environment via the Functional Mock-up InterfacePierre-Guillaume Le Guay, Henrique Vicente De Souza, Caaliph Andriamisaina, Emmanuel Molina Gonzalez and Tanguy Sassolas2019Presentationy2019presentation
Leveraging hardware emulation to accelerate SoCverification in multi-physics automotive simulation environment via the Functional Mock-up InterfacePierre-Guillaume Le Guay, Henrique Vicente De Souza, Caaliph Andriamisaina, Emmanuel Molina Gonzalez, and Tanguy Sassolas2018Presentationy2018presentation
Leveraging the UVM RAL for Memory Sub-System VerificationTudor Timisescu and Uwe Simm2015Presentationy2015presentation
Leveraging the UVM Register Abstraction Layer for Memory Sub-System VerificationTudor Timisescu and Uwe Simm2015Papery2015paper
Leveraging virtual prototypes from concept to siliconRob Kaye2017Presentationy2017presentation
Low-Power Validation Framework for Standard Cell Library Including Front-End and Back-End ImplementationJ. Lee, H. Bak, S. Do, T. Yoo, Hwaseong-si, Gowrishankar Srinivasan & Vishw Mitra Singh Bhadouria2023Papery2023paper
Low-Power Verification Methodology using UPF Query functions and Bind checkersMadhur Bhargava and Durgesh Prasad2014Papery2014paper
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Machine Learning based Structure Recognition in Analog Schematics for Constraints GenerationRituj Patel, Husni Habal, Konda Reddy Venkata2021Papery2021paper
Machine Learning for Coverage Analysis in Design VerificationV Jayasree2021Papery2021paper
Machine Learning Introduction and Exemplary Application in Embedded Wireless PlatformsJonathan Ah Sue2018Presentationy2018presentation
Make Your Testbenches Run Like Clockwork!Markus Brosch, Salman Tanvir and Martin Ruhwandl2020Papery2020paper
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Making Autonomous Cars SafeJoern Stohmann and Frederico Ferlini2017Presentationy2017presentation
Making ISO26262 Functional Safety Verification a Natural Extension of Functional VerificationAndrew Betts and Ann Keffer2018Presentationy2018presentation
MapGL: Interactive Application Mapping and Profiling on a Grid of Processing CellsClaudio Raccomandato, Emad M. Arasteh & Rainer Dömer2023Presentationy2023presentation
MapGL: Interactive Application Mapping and Profiling on a Grid of Processing CellsClaudio Raccomandato; Emad M. Arasteh; Rainer Doemer2023Papery2023paper
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Mechanical mounting variation effects on magnetic speed sensor applicationsSimone Fontanesi, Se Hwan Kim, Gernot Binder and Andrea Monterastelli2017Presentationy2017presentation
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Method for early performance verification of hardware-accelerated embedded processor systems in RTL simulationLuca Sasselli, Mehmet Tukel, David Guthrie2021Papery2021paper
Methodology for Automated Generation and Validation of Analog Behavioral Models for Mixed-Signal VerificationNan Ni, Chunya Xu, and Sebastian Simon2018Papery2018paper
Methodology for checking UVM VIPsMilan Vlahovic and Ilija Dimitrijevic2019Presentationy2019presentation
Methodology for checking UVM VIPsMilan Vlahovic and Ilija Dimitrijevic2018Presentationy2018presentation
Methodology of Communication Protocols Development: from Requirements to ImplementationIrina Lavrovskaya and Valentin Olenev2015Presentationy2015presentation
MicroTESK: Automated Architecture Validation Suite Generator for MicroprocessorsMikhail Chupilko, Alexander Kamkin, Alexander Protsenko, Sergey Smolov, and Andrei Tatarnikov2018Papery2018paper
Migrating from UVM to UVM-MSTim Pylant2023Presentationy2023presentation
Mixed Electronic System Level Power/Performance EstimationAntonio Genov, Loic Leconte and François Verdier2020Papery2020paper
Mixed ESL Power/Performance Estimation using SystemC/TLM2.0 Modeling and PwClkARCHLibraryAntonio Genov, Loic Leconte, and François Verdier2020Presentationy2020presentation
Model based Automation of Verification Development for automotive SOCsAljoscha Kirchner, Jan Hendrik Oetjens, and Oliver Bringmann,2020Presentationy2020presentation
Model Validation for Mixed-Signal VerificationCarsten Wegener2016Presentationy2016presentation
Model Validation for Mixed-Signal Verification The Importance of Being Earnest about ModelingCarsten Wegener2016Papery2016paper
Model-Based Approach for Developing Optimal HW/SW Architectures for AI systemsPetri Solanti, Russell Klein2023Presentationy2023presentation
Model-Based Automation of Verification Development for Automotive SOCsAljoscha Kirchner, Jan-Hendrik Oetjens and Oliver Bringmann2020Papery2020paper
Modeling of Generic Transfer Functions in SystemVerilogElvis Shera2016Presentationy2016presentation
Modeling of Generic Transfer Functions in SystemVerilog. Demystifying the Analytic ModelElvis Shera2016Papery2016paper
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Modelling Finite-State Machines in the Verification Environment using Software Design PatternsDarko M. Tomušilović and Mihajlo Z. Minović2017Papery2017paper
Modelling of UVC Monitor Class as a Finite State Machine for a Packet-Based InterfaceDjordje Velickovic, Milos Mitic2022Papery2022paper
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Modern methodologies in a TCL test environmentMatteo De Luigi and Alessandro Ogheri2015Presentationy2015presentation
Moving SystemC to a New C++ StandardRalph Görgen and Philipp A. Hartmann2016Papery2016paper
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Multi-Variant Coverage: Effective Planning and ModellingVikas Sharma and Manoj Manu2018Presentationy2018presentation
Mutable Verification Environments Through Visitor and Dynamic Register Map ConfigurationMatteo Barbati, Alberto Allara2020Papery2020paper
Mutable Verification Environments through Visitor and Dynamic Register Map ConfigurationMatteo Barbati and Alberto Allara2020Presentationy2020presentation
Netlist PathsJamie Hanlon, Samuel Kong2021Papery2021paper
New Trends in RTL Verification: Bug Localization, Scan- Chain-Based Methodology, GA-Based Test GenerationKhaled Salah 2015Postery2015poster
New Trends in RTL Verification: Bug Localization, Scan-Chain-Based Methodology, GA-Based Test GenerationKhaled Salah2015Papery2015paper
Next Gen System Design and Verification for TransportationBryan Ramirez, Petri Solanti and Richard Pugh2019Presentationy2019presentation
Next Generation ISO 26262-basedDesign Reliability FlowsJörg Große and Sanjay Pillay2017Presentationy2017presentation
No Country For Old Men – A Modern Take on Metrics Driven VerificationSvetlomir Hristozkov, James Pallister, Richard Porter2021Papery2021paper
NVVM: A Netlist-based Verilog Verification Methodology for Mixed-Signal DesignJiping Qiu, Kurt Schwartz2014Papery2014paper
NVVM: A Netlist-based Verilog Verification Methodology for Mixed-Signal DesignJiping Qiu, Kurt Schwartz2014Presentationy2014presentation
On the Performance Differences of SystemC and SystemC AMS: A Guideline for Real Number Modeling and BeyondAlexandra Kuester; Rainer Dorsch; Christian Haubelt2023Papery2023paper
One Testbench to Rule them all!Salman Tanvir, Markus Brosch, Amer Siddiqi2021Papery2021paper
Open Source Solution for RISC-V VerificationMikhail Chupilko, Alexander Kamkin and Alexander Protsenko2019Presentationy2019presentation
Open Source Solution for RISC-V VerificationMikhail Chupilko, Alexander Kamkin, and Alexander Protsenko 2018Presentationy2018presentation
Open-Source Virtual Platforms for Industry and ResearchNils Bosbach, Lukas Jünger & Rainer Leupers2023Presentationy2023presentation
Opening Session – Day 1 – DVCon Europe 20232023Videoy2023video
Opening Session – Day 2 – DVCon Europe 20232023Videoy2023video
Optimizing Design Verification using Machine LearningWilliam Hughes, Sandeep Srinivasan, Rohit Suvarna, Maithilee Kulkarni2021Papery2021paper
OSVVM and Error ReportingJim Lewis2015Papery2015paper
OSVVM and Error ReportingJim Lewis2015Presentationy2015presentation
OSVVM: Advanced Verification for VHDLJim Lewis2014Papery2014paper
OSVVM: Advanced Verification for VHDLJim Lewis2014Postery2014poster
Overcoming Challenges in SoC RTL Verification of USB SubsystemTijana Mišić and Marko Mišić,2019Presentationy2019presentation
Overcoming System Verilog Assertions limitations through temporal decoupling and automationMattia De Pascalis, Xia Wu, Matteo Vottero, Jacob Sander Andersen2022Presentationy2022presentation
Overcoming SystemVerilog Assertions limitations through temporal decoupling and automationMattia De Pascalis, Xia Wu, Matteo Vottero, Jacob Sander Andersen2022Papery2022paper
Panel: “All AI All the Time” Poses New Challenges for Traditional Verification2023Videoy2023video
Panel: 5G Chip Design Challenges and their Impact on VerificationAccellera Systems Initiative2022Videoy2022video
Panel: Are Processor/SoC Discontinuities Turning Verification on its Head?Accellera Systems Initiative2022Videoy2022video
Panel: The Great Verification Chiplet Challenge2023Videoy2023video
Paving a Path to Hardware-Based Acceleration in a Single UVM Environment (Because there can be only one UVM environment!)Axel Scherer and Mark Azadpour2015Papery2015paper
Pedal Faster! Or Make Your Verification Environment More Efficient. You Choose.Rich Edelman, Raghu Ardeishar, and Rohit Jain2014Papery2014paper
Pedal Faster! Or Make Your Verification Environment More Efficient. You Choose.Rich Edelman, Raghu Ardeishar, and Rohit Jain2014Postery2014poster
Performance modeling and timing verification for DRAM memory subsystemsThomas Schuster, Peter Prüller, and Christian Sauer2018Papery2018paper
Performance modeling and timing verification for DRAM memory subsystemsThomas Schuster, Peter Prüller, and Christian Sauer2018Presentationy2018presentation
Pervasive and Sustainable AI with Adaptive Computing ArchitecturesMichaela Blott2023Presentationy2023presentation
Planning for RISC-V SuccessPascal Gouedo, Xavier Aubert, Yoann Pruvost2023Papery2023paper
Planning for RISC-V Success Verification Planning and Functional CoverageDuncan Graham, Aimee Sutton, Simon Davidmann, Pascal Gouedo, Xavier Aubert, & Yoann Pruvost2023Presentationy2023presentation
Plug and Play Verification: Leveraging Block-Level Components for Seamless Top-Level IntegrationTchiya Dayan2023Presentationy2023presentation
Plug and Play Verification: Leveraging Block-Level Components for Seamless Top-Level IntegrationTchiya Dayan2023Papery2023paper
Portable Stimuli over UVM using portable stimuli in HW verification flowEfrat Shneydor, Slava Salnikov, Liran Kosovizer and Dr’ Shlomo Greenberg2019Presentationy2019presentation
Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication endpointAndrei Vintila and Ionut Tolea2018Papery2018paper
Portable Test and Stimulus: The Next Level of Verification Productivity is HereTom Fitzpatrick and Sharon Rosenberg2018Presentationy2018presentation
Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) ArtifactsMark Handover, Jonathan Lovett, and Kurt Takara2015Papery2015paper
Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) ArtifactsMark Handover, Jonathan Lovett, and Kurt Takara2015Presentationy2015presentation
Power Aware Models: Overcoming barriers in Power Aware SimulationMohit Jain, Amit Singh, J.S.S.S. Bharath, Amit Srivastava, and Bharti Jain2014Papery2014paper
Power Aware Models: Overcoming barriers in Power Aware SimulationMohit Jain, Amit Singh, J.S.S.S. Bharath, Amit Srivastava, and Bharti Jain2014Presentationy2014presentation
Power-Aware Verification in Mixed-Signal SimulationAtul Pandey, Mattias Welponer, and Gregor Kowalczyk2014Papery2014paper
Power-Aware Verification in Mixed-Signal SimulationAtul Pandey, Mattias Welponer, and Gregor Kowalczyk2014Presentationy2014presentation
Practical Experience in Automatic Functional Coverage Convergence and Reusable Collection Infrastructure in UVMRoman Wang, Suresh Babu Pusphaparaj, Mike Bartley2014Presentationy2014presentation
Practical experience in automatic functional coverage convergence and reusable collection infrastructure in UVM verificationRoman Wang, Suresh Babu Pusphaparaj2014Papery2014paper
Practical experience in automatic functional coverage convergence and reusable collection infrastructure in UVM verificationRoman Wang and Suresh Babu Pusphaparaj2014Presentationy2014presentation
Pragmatic Formal Verification Methodology for Clock Domain CrossingAman Kumar, Muhammad U.H. Khan & Bijitendra Mittra2023Presentationy2023presentation
Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)Aman Kumar, Muhammad U.H. Khan & Bijitendra Mittra2023Papery2023paper
Probing UPF Dynamic Objects: Methodologies to Build Your Custom Low-Power VerificationProgyna Khondkar2020Poster, Presentationy2020poster presentation
Probing UPF Dynamic Objects: Methodologies to Build Your Custom Low-Power Verification PlatformProgyna Khondkar2020Papery2020paper
Processing deliberate verification errors during regressionAlastair Lefley, Roger Witlox, Clemens Süßmuth, Thomas Ziller and Kawe Fotouhi2019Presentationy2019presentation
Processing deliberate verification errors during regressionAlastair Lefley, Roger Witlox, Clemens Süßmuth, Thomas Ziller, and Kawe Fotouhi2018Presentationy2018presentation
Programmable Analysis of RISC-V Processor Simulations using WALLucas Klemmer, Eyck Jentzsch, Daniel Große2022Papery2022paper
Protocol verification of an IEEE 802.3bw PHY Application of mixed signal extensions to an UVM verification environmentJoen Westendorp and Marcel Oosterhuis2018Papery2018paper
Pythonized SystemC A non-intrusive scripting approachEyck Jentzsch and Rocco Jonack2019Presentationy2019presentation
QED & Symbolic QED Pre-silicon Verification, Post-silicon Validation, Industrial ResultsSubhasish Mitra, Eshan Singh and K. Devarajegowda2019Presentationy2019presentation
Qualification of a Verification IP under Requirement Based Verification standards An approach to the verification of the verificationFrancois Cerisier, Adrien Carmagnat, Alessandro Basili, and Gilles Curchod2018Papery2018paper
Random Stimuli Models for UVM RegistersJacob Sander Andersen, Lars Viklund and Laura Montero2019Presentationy2019presentation
Reboot your Reset Methodology: Resetting Anytime with the UVM Reset PackageCourtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm2014Papery2014paper
Reboot your Reset Methodology: Resetting Anytime with the UVM Reset PackageCourtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm2014Presentationy2014presentation
Refining Successive Refinement: Improving a Methodology for Incremental Specification of Power IntentDesinghu PS, Adnan Khan, Erich Marschner, and Gabriel Chidolue2015Papery2015paper
Refining Successive Refinement: Improving a Methodology for Incremental Specification of Power IntentErich Marschner and Gabriel Chidolue2015Presentationy2015presentation
Register Testing – Exploring Tests, Register Model Libraries, Sequences and Backdoor AccessRich Edelman2022Presentationy2022presentation
Register Testing – Exploring Tests, Register Model Libraries, Sequences and Backdoor AccessRich Edelman2022Papery2022paper
Requirement Driven Safety VerificationRanga Kadambi, Vladimir Litovtchenko, Jens Rosenbusch, and Antonio Vilela2016Presentationy2016presentation
Requirement Driven Safety VerificationRanga Kadambi, Vladimir Litovtchenko, Jens Rosenbusch, and Antonio Vilela2016Papery2016paper
Requirements Driven Design Verification Flow TutorialAteş Berna and Ahmet Jorghanxhi 2018Presentationy2018presentation
Requirements driven Verification methodology (for standards compliance)Serrie-Justine Chapman, Darren Galpin, and Mike Bart2014Papery2014paper
Requirements driven Verification methodology (for standards compliance)Serrie-justine Chapman, Mike Bartley, and Darren Galpin 2014Presentationy2014presentation
Requirements-driven Verification Methodology for Standards ComplianceSerrie-justine Chapman and Mike Bartley2014Presentationy2014presentation
Reset Your Reset Domain Crossing (RDC) Verification with Machine LearningMark Handover2022Papery2022paper
Reset Your Reset Domain Crossing (RDC) Verification with Machine LearningMark Handover2022Postery2022poster
Reset Your Reset Domain Crossing (RDC) Verification with Machine LearningMark Handover2022Presentationy2022presentation
Resetting RDC ExpectationsEamonn Quigley, Jonathan Niven, Mark Handover2021Papery2021paper
Results Checking Strategies with Portable StimulusTom Fitzpatrick and Matthew Ballance2019Presentationy2019presentation
Retrascope: Open-Source Model Checkerfor HDL DescriptionsAlexander Kamkin, Mikhail Lebedev and Sergey Smolov2019Presentationy2019presentation
Retrascope: Open-Source Model Checkerfor HDL DescriptionsAlexander Kamkin, Mikhail Lebedev, and Sergey Smolov2018Presentationy2018presentation
Reusable Processor Verification Methodology Based on UVMMustafa Khairallah and Maged Ghoneima2014Papery2014paper
Reusable Processor Verification Methodology Based on UVMMustafa Khairallah and Maged Ghoneima2014Postery2014poster
Reusable Verification Environment for a RISC-V Vector AcceleratorR. Ignacio Genovese, Josue Quiroga, Ivan Diaz, Henrique Yano, Asif Ali, Nehir Sonmez, Oscar Palomar, Victor Jimenez, Mario Rodriguez, Marc Dominguez2022Presentationy2022presentation
Reusable Verification Environment for a RISC-V Vector AcceleratorJosue Quiroga, Roberto Ignacio Genovese, Ivan Diaz, Henrique Yano, Asif Ali, Nehir Sonmez, Oscar Palomar, Victor Jimenez, Mario Rodriguez, Marc Dominguez2022Papery2022paper
Reuse doesn’t come for free – learnings from a UVM deploymentSumeet Gulati, Srinivasan Venkataramanan, Ketki Gosavi, Saumya Anvekar, and Azhar Ahammad2016Presentationy2016presentation
Reuse doesn’t come for free – learnings from a UVM deploymentSumeet Gulati, Srinivasan Venkataramanan, Azhar Ahammad, Ketki Gosavi, and Saumya Anvekar2016Papery2016paper
Reuse of System-Level Verification Components within Chip-Level UVM EnvironmentsDiego Alagna, Marzia Annovazzi, Alessandro Cannone, Marcello Raimondi, Simone Saracino, Mukesh Chugh, Marc Erickson, Cristian Macario, Giuseppe Ridinò2021Papery2021paper
Reverse Hypervisor – Hypervisor as fast SoC simulator.François-Frédéric Ozog & Mark Burton2023Papery2023paper
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Revitalizing Automotive Safety Hard and Soft Error ApproachesNael Qudsi and Ayman Mouallem2019Presentationy2019presentation
Revolutionary Debug Techniques to Improve Verification ProductivityNadav Chazan2014Presentationy2014presentation
RISC-V Compliance & Verification Techniques Processor Cores and Custom ExtensionsSimon Davidmann, Lee Moore, Richard Ho, Doug Letcher and Kevin McDermott2019Presentationy2019presentation
RISC-V Integrity: A Guide for Developers and IntegratorsNicolae Tusinschi2019Presentationy2019presentation
RTL2RTL Formal Equivalence: Boosting the Design ConfidenceM. Achutha KiranKumar V, Aarti Gupta, and Ss. Bindumadhava2014Papery2014paper
RTL2RTL Formal Equivalence: Boosting the Design ConfidenceM. Achutha KiranKumar V, Aarti Gupta, and Ss. Bindumadhava2014Postery2014poster
Safety and Security Aware Pre-Silicon Hardware / Software Co-DevelopmentNikola Velinov and Frank Schirrmeister2019Presentationy2019presentation
Safety-Verification Flow Sporting Gate-Level Accuracy and Near Virtual-Prototype SpeedB.-A. Tabacaru, M. Chaari, W. Ecker, T. Kruse, and C. Novello2016Presentationy2016presentation
Safety-Verification Flow Sporting Gate-Level Accuracy and Near Virtual-Prototype SpeedBogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, and Cristiano Novello2016Papery2016paper
Same bits, different meaning – when direct execution based simulation becomes complicatedEvgeny Yulyugin2018Papery2018paper
SAWD: Systemverilog Assertions Waveform-based Development ToolAhmed Alsawi2022Papery2022paper
SAWD: Systemverilog Assertions Waveform-based Development toolAhmed Alsawi2022Presentationy2022presentation
Scalable agile processor verification using SystemC UVM and friendsEyck Jentzsch2023Presentationy2023presentation
Self-Triggering Mechanism for Modeling a Low-Dropout Regulator with Load CapacitorMariska van der Struijk & Yi Wang2023Papery2023paper
Semi-formal Reformulation of Requirements for Formal Property VerificationKatharina Ceesay-Seitz, Hamza Boukabache and Daniel Perrin2019Presentationy2019presentation
SIM-V Fast, Parallel RISC-V Simulation for Rapid Software VerificationLukas Jünger, Jan Henrik Weinstock, Rainer Leupers2022Papery2022paper
SimpleLink™ MCU Platform: IP-XACT to UVM Register Model – Standardizing IP and SoC Register VerificationJasminka Pasagic and Frank Donner2017Presentationy2017presentation
SimpleLink™ MCU Platform: IP-XACT to UVM Register Model – Standardizing IP and SoC Register Verification “UVM is a perfect start”Jasminka Pasagic and Frank Donner2017Papery2017paper
Simplifying UVM in SystemCThilo Vörtler, Thomas Klotz, Karsten Einwich, and Felix Assma2015Papery2015paper
Simplifying UVM in SystemCThilo Vörtler, Thomas Klotz, Karsten Einwich, and Felix Assma2015Postery2015poster
SimPy for ChipsHachem Tassine, Daniel Wilkinson, Graham Cunnigham, Iason Myttas2021Papery2021paper
Simulation and Debug of Mixed Signal Virtual Platforms for Hardware-Software co-developmentVincent Motel, Alexandre Roybier, and Serge Imbert2014Papery2014paper
Simulation and Debug of Mixed Signal Virtual Platforms for Hardware-Software co-developmentVincent Motel, Alexandre Roybier, and Serge Imbert2014Presentationy2014presentation
Single Source System to Register-Transfer Level Design Methodology Using High-Level SynthesisPetri Solanti and Thomas Arndt2020Papery2020paper
Single Source System to Register-Transfer Level Design Methodology Using High-Level SynthesisPetri Solanti and Thomas Arndt2020Presentationy2020presentation
Slicing Through the UVM’s Red TapeA Frustrated User’s Survival GuideJonathan Bromley © Accellera2016Presentationy2016presentation
Slicing Through the UVM’s Red Tape: A Frustrated User’s Survival GuideJonathan Bromley2016Papery2016paper
Smart TSV (Through Silicon Via) Repair Automation in 3DIC DesignsSubramanian R, Naveen Srivastava, Jyoti Verma & Sekhar Dangudubiyyam2023Papery2023paper
Smart TSV Repair Automation in 3DIC DesignsSubramanian R, Naveen Srivastava, Jyoti Verma & Sekhar Dangudubiyyam2023Presentationy2023presentation
SOBEL FILTER: Software Implementation to RTL using High Level SynthesisBhavna Aggarwal, Umesh Sisodia and Snigdha Tyagi2020Papery2020paper
SOBEL FILTER: Software Implementation to RTL using High Level SynthesisBhavna Aggarwal, Umesh Sisodia, and Snigdha Tyagi2020Presentationy2020presentation
Software Driven Test of FPGA PrototypeMethods & Use casesKrzysztof Szczur and Radosław Nawrot2017Presentationy2017presentation
Soumak – How rich descriptions enable early detection of hookup issuesPeter Birch, Thomas Brown2022Papery2022paper
Specification by Example for Hardware Design and VerificationJussi Mäkelä2017Presentationy2017presentation
Specification by Example for Hardware Design and VerificationJussi Mäkelä2017Papery2017paper
State-Space “Switching” Model of DC-DC Converters in SystemVerilogElvis Shera2017Presentationy2017presentation
State-Space “Switching” Model of DC-DC Converters in SystemVerilog.Elvis Shera2017Papery2017paper
Static Analysis of SystemC/SystemC-AMS System and Architectural Level ModelsKarsten Einwich and Thilo Vörtler2020Papery2020paper
Static Analysis of SystemC/SystemC-AMS System and Architectural Level ModelsKarsten Einwich and Thilo Vörtler2020Presentationy2020presentation
Static Checking for Correctness of Functional Coverage ModelsWael Mahmoud2017Presentationy2017presentation
Static Checking for Correctness of Functional Coverage ModelsWael Mahmoud2017Papery2017paper
Static Sign-Off Best Practices Learnings and Experiences from Industry Use CasesVikas Sachdeva2022Presentationy2022presentation
Static Signoff Best Practices – Learnings and experiences from industry use casesVikas Sachdeva2022Papery2022paper
Successive Refinement – An approach to decouple Front-End and Back-end Power IntentRohit Kumar Sinha2021Papery2021paper
SV VQC UDN for Modeling Switch-Capacitor-based CircuitsYi Wang2023Papery2023paper
SysML based Architecture Definition and Platform Generation FlowRalph Görgen and Erwin de Kock2019Presentationy2019presentation
SysML v2 – An overview with SysMD demonstrationChristoph Grimm, Axel Ratzke, Sebastian Post, Hagen Heermann, Johannes Koch2023Presentationy2023presentation
System Verilog Assertions VerificationIonuț Ciocîrlan and Andra Radu2015Presentationy2015presentation
System-Level Register Verification and DebugUtkarsh Bhiogade, Kautilya Joshi, Puneet Goel2021Papery2021paper
System-Level Simulation of a SPAD-Based Time-of-Flight Sensor in SystemVerilogSeungah Park, Hyeongseok Seo, Canxing Piao, Jaemin Park, Jaehyuk Choi, Jung-Hoon Chun2023Presentationy2023presentation
System-Level Simulation of a SPAD-Based Time-of-Flight Sensor in SystemVerilogSeungah Park, Hyeongseok Seo, Canxing Piao, Jaemin Park, Jaehyuk Choi & Jung-Hoon Chun2023Papery2023paper
SystemC extension for power specification, simulation and verificationMikhail Moiseev, Ilya Klotchkov, and Kirill Gagarski2016Papery2016paper
SystemC extension for power specification,simulation and verificationMikhail Moiseev, Ilya Klotchkov, Maxim Petrov, and Kirill Gagarski2016Presentationy2016presentation
SystemC gaps encountered in Virtual Platform developmentEyck Jentzsch2016Papery2016paper
SystemC-to-Verilog Compiler: a productivity-focused tool for hardware design in cycle-accurate SystemCMikhail Moiseev, Roman Popov and Ilya Klotchkov2019Presentationy2019presentation
SystemC-to-Verilog Compiler: a productivity-focused tool for hardware design in cycle-accurate SystemCMikhail Moiseev, Roman Popov, and Ilya Klotchkov2018Presentationy2018presentation
Taking Design Automation to the next level with User Experience DesignJamie Lai, Bodo Hoppe2022Presentationy2022presentation
Temporal Assertions in SystemCMikhail Moiseev, Leonid Azarenkov and Ilya Klotchkov2020Papery2020paper
Temporal assertions in SystemCMikhail Moiseev, Leonid Azarenkov, and Ilya Klotchkov2020Presentationy2020presentation
Temporal Decoupling – Are “Fast” and “Correct” Mutually Exclusive?Jakob Engblom2018Papery2018paper
Temporal Decoupling – Are “Fast” and “Correct” Mutually Exclusive?Jakob Engblom2018Presentationy2018presentation
Test document linkTest2023Papery2023paper
Testbench Flexiblity as a Foundation for SuccessAna Sanz Carretero, Katherine Garden, Wei Wei Cheong2021Papery2021paper
Testbench Linting – open-source waySrinivasan Venkataramanan, Deepa Palaniappan & Satinder Paul Singh2023Papery2023paper
The Application of Formal Technology on Fixed Point Arithmetic SystemC DesignsSven Beyer, Dominik Straßer, and Dave Kelf2015Presentationy2015presentation
The Application of Formal Technology on Fixed-Point Arithmetic SystemC DesignsSven Beyer, Dominik Straßer, and David Kelf2015Papery2015paper
The Cost of Standard Verification Methodology ImplementationsAbigail Williams, Svetlomir Hristozkov, Adam Hizzey2022Papery2022paper
The Cost Of Standard Verification Methodology ImplementationsAdam Hizzey, Abigail Williams, Svetlomir Hristozkov2022Presentationy2022presentation
The How To’s of Advanced Mixed-Signal VerificationJohn Brennan, Thomas Ziller, Kawe Fotouhi, and Ahmed Osman2015Presentationy2015presentation
The How To’s of Metric Driven Verification to Maximize ProductivityMatt Graham and John Brennan2014Presentationy2014presentation
The missing SystemC and TLM asynchronous features enabling inter-simulation synchronization.Guillaume Delbergue, Mark Burton, Bertrand Le Gal and Christophe Jego2016Papery2016paper
The Open Source DRAM Simulator DRAMSys4.0Matthias Jung2022Presentationy2022presentation
The Open-Source DRAM Simulator DRAMSys4.0Matthias Jung2022Papery2022paper
The Road to Robustness: Addressing LPDDR5X PHY Verification Challenges with DFEMuhammed Asif, Gowdra Bomanna Chethan, Anil Deshpande & Somasunder Kattepura Sreenath2023Papery2023paper
The Three Body ProblemPeter Birch & Ben Marshall2023Papery2023paper
The Three Body Problem There’s more to building Silicon than EDA currently helpsPeter Birch & Ben Marshall2023Presentationy2023presentation
The Top Most Common SystemVerilog Constrained Random GotchasAhmed Yehia2014Papery2014paper
The Top Most Common SystemVerilog Constrained Random GotchasAhmed Yehia2014Presentationy2014presentation
The Universal TranslatorDavid Cornfield2014Presentationy2014presentation
The Universal Translator – A Fundamental UVM Component for Networking ProtocolsDavid Cornfield2014Papery2014paper
The Universal Translator – A Fundamental UVM Component for Networking ProtocolsDavid Cornfield2014Presentationy2014presentation
Timing-Aware High Level Power Estimation of Industrial Interconnect ModuleAmal Ben Ameur, Antonio Genov, François Verdier and Loic Leconte2020Papery2020paper
Timing-Aware high level power estimation of industrial interconnect moduleAmal Ben Ameur, Antonio Genov, François Verdier, and Loic Leconte2020Presentationy2020presentation
TLM based Virtual Platforms at Ericsson Challenges and ExperiencesOla Dahl, Michael Lebert, and Eric Frejd2016Presentationy2016presentation
TLM Beyond Memory Mapped BussesBart Vanthournout and Mark Burton2016Papery2016paper
TLM modeling and simulation for NAND Flash and Solid State Drive systemsTim Kogel and Victor Reyes2017Presentationy2017presentation
TLM-based Virtual Platforms at Ericsson: Challenges and ExperiencesOla Dahl, Michael Lebert, and Eric Frejd2016Papery2016paper
Towards 5G Internet of ThingsSabine Roessel2017Presentationy2017presentation
Towards a Hybrid Verification Environment for Signal Processing SoCsJan Hahlbeck, Steffen Löbel & Chandana G P2023Presentationy2023presentation
Towards a Hybrid Verification Environment for Signal Processing SoCsJan Hahlbeck & Steffen Löbel2023Papery2023paper
Towards a UVM-based Solution for Mixed-signal VerificationAlexander W. Rath, Sebastian Simon, Volkan Esen, and Wolfgang Ecker2016Presentationy2016presentation
Towards a UVM-based Solution for Mixed-signal VerificationAlexander W. Rath, Sebastian Simon, Volkan Esen, and Wolfgang Ecker2016Papery2016paper
Transaction‐Based Testing with OSVVM and the OSVVM Model LibraryJim Lewis and Patrick Lehmann2019Presentationy2019presentation
Tutorial 7 Tutorial on RISC-V Design and VerificationKevin McDermott, Zdenek Prikryl, and Peter Shields2018Presentationy2018presentation
TwIRTee design exploration with Capella and IP-XACTPhilippe Cuenot, Bassem Ouni, and Pierre Gaufillet2016Presentationy2016presentation
TwIRTee: design exploration with Capella and IP-XACTBassem Ouni, Philippe Cuenot, and Pierre Gaufillet2016Papery2016paper
Types of Robustness Test According to DO-254 Guideline for Avionic SystemsGözde Asena KILINÇ, Yavuz AKSU, Fatih BAYSAL2022Papery2022paper
Types of Robustness Test According to DO-254 Guideline for Avionic SystemsGözde Asena KILINÇ, Yavuz AKSU, Fatih BAYSAL2022Postery2022poster
Types of Robustness Test According to DO-254 Guideline for Avionic SystemsGözde Asena KILINÇ, Yavuz AKSU, Fatih BAYSAL2022Presentationy2022presentation
Understanding the effectiveness of your system-level SoC stimulus suiteRobert Fredieu, Alan Hunter, and Andreas Meyer2014Papery2014paper
Understanding the effectiveness of your system-level SoC stimulus suiteAlan Hunter , Robert Fredieu, and Andreas Meyer2014Postery2014poster
Unified Architecture of L1 and L2 Cache with Low Power Extensions for Multi-Core UVM-based Library PackageAvnita Pal, Priyanka Gharat, Sastry Puranapanda & Darshan Sarode2023Papery2023paper
Unified Architecture of L1 L2 Cache with Low Power Extensions for MultiCore UVM-based Library PackageAvnita Pal, Priyanka Gharat, Puranapanda Sastry, & Darshan Sarode2023Presentationy2023presentation
Unified Firmware Debug throughout SoC Development LifecycleDimitri Ciaglia, Thomas Winkler, Jurica Kundrata2022Papery2022paper
Unified firmware debug throughout SoC development lifecycleD. Ciaglia, T. Winkler, J. Kundrata2022Presentationy2022presentation
Unified Functional Safety Verification Platform for ISO 26262 Compliant AutomotiveJoerg Richter2019Presentationy2019presentation
Unified Model/Hardware-in-the-Loop Methodology for Mixed-Signal System Design and Hardware PrototypingMartin Barnasconi, Wil Kitzen, Thieu Lammers, Paul Ehrlich, Karsten Einwich2021Papery2021paper
Unified Test Writing Framework for Pre and Post Silicon VerificationRahulkumar Patel, Pablo Cholbi, Sivasubrahmanya Evani and Raman K2019Presentationy2019presentation
Unifying Mixed-Signal and Low-Power VerificationAdam Sherer, Andre Baguenier, Kawe Fotouhi, Abhijit Madhu Kumar, Qingyu Lin, Raj Mitra, and William Winkeler2018Presentationy2018presentation
Universal Scripting Interface for SystemCRolf Meyer, Jan Wagner, Rainer Buchty, and Mladen Berekovic2015Papery2015paper
Universal Scripting Interface for SystemCRolf Meyer2015Presentationy2015presentation
UPF Power Models: Empowering the power intent specificationAmit Srivastava and Harsh Chilwal2018Papery2018paper
UPF: How to avoid traps in a Hierarchical Implementation Low Power flow?Frederic Saint-Preux,2017Presentationy2017presentation
UPF: How to avoid traps in a Hierarchical Implementation Low Power flow?Frederic Saint-Preux2017Papery2017paper
Use of CDC-jitter-modeling in clock-domaincrossing- circuits in RTL design phaseJan Hayek, Jochen Neidhardt, and Robert Richter2017Papery2017paper
Use of CDC-Jitter-Modeling inClock-Domain-Crossing-Circuits in RTL Design PhaseJan Hayek, JochenNeidhardt, and Robert Richter2017Presentationy2017presentation
Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Said Hamdioui, and Christian Sauer2018Papery2018paper
Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262Felipe A. da Silva, Ahmet C. Bagbaba, Said Hamdioui and Christian Sauer2018Presentationy2018presentation
Use Stimulus Domain for Systematic Exploration of Time Dimension and Automatic Testcase ConstructNing Chen and Martin Ruhwandl2018Papery2018paper
Using an Enhanced Verification Methodology for Back-to-Back RTL/TLM SimulationFrank Poppen, Ralph Görgen, Kai Schulz, Andreas Mauderer, Jan-Hendrik Oetjens, Robert Bosch, Joachim Gerlach, and Hochschule, Albstadt-Sigmaringen2017Presentationy2017presentation
Using an Enhanced Verification Methodology for Back-to-Back RTL/TLM SimulationFrank Poppen, Ralph Görgen, Kai Schulz, Andreas Mauderer, Jan-Hendrik Oetjens, Robert Bosch, Joachim Gerlach, and Hochschule Albstadt-Sigmaringen2017Papery2017paper
Using Cadence and MathWorksTools Together for Mixed-Signal Design and VerificationGraham Reith and Andrew Beckett2017Presentationy2017presentation
Using Constraints for SystemC AMS Design and VerificationThilo Vörtler, Karsten Einwich, Muhammad Hassan, and Daniel Große2018Papery2018paper
Using Constraints for SystemC AMS Design and VerificationThilo Vörtler, Karsten Einwich, Muhammad Hassan, and Daniel Große2018Presentationy2018presentation
Using Dependency Injection Design Pattern in Power Aware TestsMehmet Tukel, Luca Sasselli, David Guthrie2021Papery2021paper
Using Formal to Prevent DeadlocksAbdelouahab Ayari, Mark Eslinger and Joe Hupcey III2020Papery2020paper
Using High-level Synthesis and Emulation to Rapidly Develop AI Algorithms in HardwareJohn Stickley and Petri Solanti2018Presentationy2018presentation
Using HLS to improve Design-for-Verification of multi-pipeline designs with resource sharingSarmad Dahir, Nils Luetke-Steinhorst, Christian Sauer2021Papery2021paper
Using Mutation Coverage for Advanced Bug Hunting and Verification SignoffNicolae Tusinschi2018Presentationy2018presentation
Using Open-Source EDA Tools in an Industrial Design FlowDaniela Sánchez Lopera, Sven Wenzek, Wolfgang Ecker2022Papery2022paper
Using Open-Source EDA Tools in an Industrial Design FlowDaniela Sánchez Lopera, Prajwal Kashyap, Nicolas Gerlin, Sven Wenzek, Wolfgang Ecker2022Presentationy2022presentation
Using UVM-ML library to enable reuse of TLM2.0 models in UVM test benchesSarmad Dahir, Hans-Martin Bluethgen, Rafael Zuralski, Nils Luetke-Steinhorst, and Christian Sauer2018Papery2018paper
Using UVM-ML library to enable reuse of TLM2.0 models in UVM test benchesSamah Dahir2018Presentationy2018presentation
UVM & Emulation Architecting SystemVerilog UVM Testbenches for Simulation-Emulation Portability to Boost Block-to-System Verification Productivity – TutorialHans van der Schoot and Ellie Burns-Brookens2014Presentationy2014presentation
UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-upHans van der Schoot and Ahmed Yehia2015Papery2015paper
UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-upHans van der Schoot and Ahmed Yehia2015Postery2015poster
UVM Audit Tutorial Assessing UVM Testbenches to Expose Coding Errors & Improve QualityMark Litterick 2018Presentationy2018presentation
UVM based Hardware/Software Co- Verification of a HW Coprocessor using Host Execution TechniquesFrançois Cerisier, Christian Rivier, Andrea Battistella, and Arnaud Grasset2018Presentationy2018presentation
UVM based Hardware/Software Co-Verification of a HW Coprocessor using Host Execution TechniquesFrançois Cerisier, Christian Rivier, Andrea Battistella and Arnaud Grasset2019Presentationy2019presentation
UVM goesUniversal -IntroducingUVM in SystemCStephan Schulz, Thilo Vörtler, and Martin Barnasconi2015Presentationy2015presentation
UVM hardware assisted acceleration with FPGA co-emulationAlex Grove2015Presentationy2015presentation
UVM Made Language Agnostic – Introducing UVM For SystemC Application of UVM-SystemCAkhila M2017Papery2017paper
UVM Made Language Agnostic: Introducing UVM For SystemCAkhila M2017Presentationy2017presentation
UVM mixed signal extensionsSharing Best Practice and Standardization IdeasJoen Westendorp, Sebastian Simon, and Joachim Geishauser2018Presentationy2018presentation
UVM Rapid Adoption: A Practical Subset of UVMStuart Sutherland and Tom Fitzpatrick2015Presentationy2015presentation
UVM Ready: Transitioning Mixed-Signal Verification Environments to Universal Verification MethodologyArthur Freitas, Régis Santonja2014Papery2014paper
UVM Ready: Transitioning Mixed-Signal Verification Environments to Universal Verification MethodologyArthur Freitas, Régis Santonja2014Presentationy2014presentation
UVM Register Map Dynamic ConfigurationMatteo Barbati and Alberto Allara2018Papery2018paper
UVM Register Map Dynamic ConfigurationMatteo Barbati and Alberto Allara2018Presentationy2018presentation
UVM SystemC Functional coverage & constrained randomizationStephan Gerth, Dragos Dospinescu, Muhammad Hassan, Thilo Vörtler and Manuel Soto 2019Presentationy2019presentation
uvm_mem – challenges of using UVM infrastructure in a hierarchical verificationJoachim Geishauser, Aditya Chopra, Stephan Ruettiger, Luca Rossi, Sanjay Kakasaniya, L.N. Zhang2022Papery2022paper
uvm_mem – challenges of using UVM infrastructure in a hierarchical verificationJoachim Geishauser, Aditya Chopra, Stephan Ruettiger, Luca Rossi, Sanjay Kakasaniya, L.N. Zhang2022Presentationy2022presentation
UVM-Light A Subset of UVM for Rapid AdoptionStuart Sutherland and Tom Fitzpatrick2015Papery2015paper
UVM-Multi-Language Hands-OnThorsten Dworzak and Angel Hidalga2017Presentationy2017presentation
UVM-Multi-Language Hands-On Integrating a System-C model into a SV-UVM testbenchThorsten Dworzak and Angel Hidalga2017Papery2017paper
UVM-SystemC Applications in the real worldStephan Schulz, Thilo Vörtler, and Martin Barnasconi2014Presentationy2014presentation
UVM-SystemC based hardware in the loop simulations for accelerated Co-VerificationPaul Ehrlich, Thang Nguyen, and Thilo Vörtler2014Papery2014paper
UVM-SystemC based hardware in the loop simulations for accelerated Co-VerificationPaul Ehrlich, Thang Nguyen, and Thilo Vörtler2014Presentationy2014presentation
UVM-SystemC: Migrating complex verification environmentsStephan Gerth and Akhila Madhukumar2017Presentationy2017presentation
UX Design & EDA – Enable Collaboration on Functional Coverage using Opens Source SoftwareBodo Hoppe, Jamie Lai2022Papery2022paper
Validation of Timing Constraints on RTL Reducing Risk and Effort on Gate-LevelPeter Limmer, Dirk Moeller, Marcus Mueller and Clemens Roettgermann2016Presentationy2016presentation
Validation of Timing Constraints on RTL Reducing Risk and Effort on Gate-LevelPeter Limmer, Dirk Moeller, Marcus Mueller, and Clemens Roettgermann2016Papery2016paper
Variation-Aware Performance Verification of Analog Mixed-Signal SystemsCarna Zivkovic; Jan Roedel; Neha Chavan; Frank Rethmeier; Christoph Grimm2023Papery2023paper
Verification 2.0 – Multi Engine, Multi-Run – AI-Driven VerificationMatt Graham2022Papery2022paper
Verification 2.0 – Multi Engine, Multi-Run AI-Driven VerificationMatt Graham2022Presentationy2022presentation
Verification Challenges For Deep Color Mode In HDMISnigdha Arora and Apoorva Mathur2016Presentationy2016presentation
Verification Challenges for Deep Color Mode in HDMISnigdha Arora and Apoorva Mathur2016Papery2016paper
Verification IP for Complex Analog and Mixed-Signal BehaviorThilo Vörtler and Karsten Einwich2017Presentationy2017presentation
Verification IP for Complex Analog and Mixed-Signal BehaviorThilo Vörtler and Karsten Einwich2017Papery2017paper
Verification of a Multi-language Components A case Study: Specman E Env with SV UVM VIPEran Lahav2020Poster, Presentationy2020poster presentation
Verification of a Multi-language Components A Case Study: Specman E Environment with SystemVerilog UVMEran Lahav2020Papery2020paper
Verification of an AXI cache controller using multi-thread approach based on OOP design patternFrancesco Rua’ & Péter Sági2023Presentationy2023presentation
Verification of an AXI cache controller with a multi-thread approach based on OOP design patternsFrancesco Rua’ & Péter Sági2023Papery2023paper
Verification of High-Speed Links through IBIS-AMI ModelsGanesh Rathinavel2022Presentationy2022presentation
Verification of High-Speed Links through IBIS-AMI ModelsGanesh Rathinavel2022Papery2022paper
Verification of Inferencing Algorithm AcceleratorsRussell Klein, Petri Solanti2022Papery2022paper
Verification of Inferencing Algorithm AcceleratorsRussell Klein, Petri Solanti2022Presentationy2022presentation
Verification of Virtual Platform Models – What do we Mean with Good Enough?Jakob Engblom, Ola Dahl2022Papery2022paper
Verification of Virtual Platform Models – What do we Mean with Good Enough?Ola Dahl, Jakob Engblom2022Presentationy2022presentation
Verifying Functional, Safety and Security Requirements (for Standards Compliance)Mike Bartley2015Presentationy2015presentation
Verilator + UVM-SystemC: a match made in heavenLuca Sasselli2023Papery2023paper
Versatile UVM ScoreboardingJacob Andersen, Peter Jensen, and Kevin Steffensen2014Papery2014paper
Versatile UVM ScoreboardingJacob Andersen, Peter Jensen, and Kevin Steffensen2014Presentationy2014presentation
Vertical Reuse of functional verification from subsystem to SoC level (with seamless SoC emulation)Pranav Kumar, Digvijaya Pratap SINGH, and Ankur Jain2014Presentationy2014presentation
Virtual ECUs with QEMU and SystemC TLM-2.0Lukas Jünger, Jan Henrik Weinstock, Munish Jassi, Megumi Yoshinaga, Hitoshi Hamio, Koichi Sato2023Presentationy2023presentation
Virtual ECUs with QEMU and SystemC TLM-2.0Lukas Jünger, Jan Henrik Weinstock, Munish Jassi, Megumi Yoshinaga, Hitoshi Hamio & Koichi Sato2023Papery2023paper
Virtual Platforms for Automotive: Use Cases, Benefits and ChallengesAngela Kramer and Martin Vaupel 2014Presentationy2014presentation
Virtual Platforms for complex IP within system contextRocco Jonack2015Presentationy2015presentation
Virtual Prototypes and PlatformsA PrimerEyck Jentzsch, Rocco Jonack, and Josef Eckmüller2017Presentationy2017presentation
Virtual Prototyping in SpaceFibre System-on-Chip DesignIlya Korobkov2015Presentationy2015presentation
Virtual Prototyping in SpaceFibre System-on-Chip Design System-level designElena Suvorova2015Papery2015paper
Virtual Prototyping of Power Converter Systems based on AURIX™ using SystemC AMSRadovan Vuletic, Dineshkumar Selvaraj, Thomas Arndt2021Papery2021paper
Virtual Prototyping using SystemC and TLM-2.0John Aynsley2014Presentationy2014presentation
Virtual Testing of Overtemperature Protection Algorithms in Automotive Smart FusesThomas Markwirth, Gabriel Pachiana, Christoph Sohrmann, Mehdi Meddeb, Gunnar Bublitz & Heinz Wagensonner2023Presentationy2023presentation
Virtual testing of overtemperature protection algorithms in automotive smart fusesThomas Markwirth, Gabriel Pachiana, Christoph Sohrmann, Mehdi Meddeb, Gunnar Bublitz & Heinz Wagensonner2023Papery2023paper
VP Performance Optimization – How to analyze and optimize the speed of SystemC TLM models?Rocco Jonack and Juan Lara Ambel2014Papery2014paper
VP Performance Optimization – How to analyze and optimize the speed of SystemC TLM models?Rocco Jonack and Juan Lara Ambel2014Presentationy2014presentation
VPSim: Virtual Prototyping Simulator with best accuracy & execution time trade-off for High Performance Computing systems evaluation and benchmarkingMohamed Benazouz, Ayoub Mouhagir & Lilia Zaourar2023Papery2023paper
Wave Digital Filter Modeling for Complex Automotive Sensor Load Case VerificationAndrei-Daniel Basa, Thang Nguyen, and Dirk Hammerschmidt2015Papery2015paper
Wave Digital Filter Modeling for Complex Automotive Sensor Load Case VerificationA. Basa, T. Nguyen, and D. Hammerschmidt2015Presentationy2015presentation
Web Template Mechanisms in SOC VerificationAlberto Allara, Via Tolomeo, Rinaldo Franco, and Via Remo2015Papery2015paper
Web Template Mechanisms in SOC VerificationRinaldo Franco and Alberto Allara2015Presentationy2015presentation
What is needed on top of TLM-2 for bigger Systems?Jerome Cornet and Martin Schnieringer2015Presentationy2015presentation
What is new in IP-XACT IEEE Std. 1685-2022?Erwin de Kock, Jean-Michel Fernandez, Devender Khari2022Papery2022paper
What is new in IP-XACT Std. IEEE 1685-2022?Erwin de Kock, Jean-Michel Fernandez, Devender Khari2022Presentationy2022presentation
What is next for SystemC Synthesizable Subset?Peter Frey2016Papery2016paper
Who takes the driver seat for ISO 26262 and DO 254 verification?Avidan Efody2015Papery2015paper
Who takes the driver seat for ISO 26262 and DO 254 verification?Avidan Efody2015Presentationy2015presentation
YAMMYet Another Memory ManagerAndrei Vintila and Ionut Tolea2016Presentationy2016presentation
Yet Another Memory Manager (YAMM)Ionut Tolea and Andrei Vintila2016Papery2016paper