| 1,2,3,…8 simple steps towards a single digital signal processing testbench supporting heterogeneous interfaces and datatypes | Nico Lugil | | | | | |
| 1,2,3,…8 simple steps towards a single digital signal processing testbench supporting heterogeneous interfaces and datatypes | Nico Lugil | | | | | |
| 400G IPU Case Study: Demonstrating Shift-left of Soft Logic RTL Development on Real World Design using Intel Agilex FPGA SystemC Model | Pravat K Nayak, Vikrant Kapila, Pushpa Naik & Niketkumar Sharma | | | | | |
| 5G – Chances and Challenges from Test & Measurement Perspective | Meik Kottkamp | | | | | |
| 5G / NR Explained From 3GPP 5G Standard Fundamentals To 5G Enabled Verticals | Michael Faerber and Kilian Roth | | | | | |
| 5G for people and things Spectrum Opportunities and Challenges of 5G | | | Presentation | | | presentation |
| A comparison of methodologies to simulate mixed-signal IC | Simone Fontanesi, Karsten Einwich, Paul Ehrlich, Gaetano Formato, Andrea Possemato | | | | | |
| A Compositional Simulation Framework for Testing Adversarial Robustness of Deep Neural Networks | Youssef Maher Nader; Mostafa Lotfy Hatab; Mazen Mostafa Ghaleb; Safia Medhat Bakr; Tasneem A. Awaad; Ahmed AlGanzouri; Mohamed Abdelsalam; M. Watheq El-Kharashi | | Paper | | | paper |
| A Compositional Simulation Framework for Testing Adversarial Robustness of Deep Neural Networks | Youssef Maher Nader, Mostafa Lotfy Hatab, Mazen Mostafa Ghaleb, Safia Medhat Bakr, Tasneem A. Awaad, Ahmed AlGanzouri, Mohamed Abdelsalam, and M. Watheq El-Kharashi | | | | | |
| A Comprehensive Verification Platform for RISC-V based Processors | Emre Karabulut, Berk Kisinbay, Abdullah Yildiz and Rifat Demircioglu | | | | | |
| A Comprehensive Verification Platform for RISC-V based Processors | Emre Karabulut, Berk Kisinbay, Abdullah Yildiz, and Rifat Demircioglu | | | | | |
| A concept for expanding a UVM testbench to the analog-centric toplevel | Felix Assmann, Axel Strobel and Hans Zander | | | | | |
| A concept for expanding a UVM testbenchto the analog-centric toplevel | Felix Assmann, Axel Strobel and Hans Zander | | | | | |
| A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMS | Muhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, Daniel Große | | Paper | | | paper |
| A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMS | Muhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, Daniel Große | | | | | |
| A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog-AMS | Mike Bartley and Jeganath Gandhi R | | | | | |
| A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog-AMS | Mike Bartley, Jeganath Gandhi R | | | | | |
| A Framework for the Execution of Python Tests in SystemC and Specman Testbenches | Christoph Tietz, Sebastian Stieber , Najdet Charaf, Diana Göhringer | | Paper | | | paper |
| A Framework for the Execution of Python Tests in SystemC and Specman Testbenches | Christoph Tietz, Sebastian Stieber, Najdet Charaf, Diana Göhringer | | Presentation | | | presentation |
| A Generic Approach to Handling Sideband Signals | Markus Brosch and Salman Tanvir | | | | | |
| A Generic Configurable Error Injection Agent for On-Chip Memories | Niharika Sachdeva, Arjun Suresh Kumar, Damandeep Saini, Anil Deshpande, Ravi Teja Gopagiri, Somasunder KS, Jaechul Park | | | | | |
| A Generic Configurable Error Injection Agent for All On-Chip Memories | Anil Deshpande, Jaechul Park, Niharika Sachdeva, Arjun Suresh Kumar, Raviteja Gopagiri, Somasund Kattepura Sreenath, Damandeep Saini | | | | | |
| A Guide To Using Continuous Integration Within The Verification Environment | Jason Sprott, André Winkelmann, and Gordon McGregor | | Paper | | | paper |
| A Guide To Using Continuous Integration Within The Verification Environment | André Winkelmann, Jason Sprott, and Gordon McGregor | | | | | |
| A Hybrid Approach For Interrupts Verification | Giovanni Auditore, Francesco Rua’, Qibo Peng | | | | | |
| A Hybrid Approach To Interrupt Verification | Giovanni Auditore, Francesco Rua’, Qibo Peng | | | | | |
| A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGA | Antonis Papagrigoriou, Miltos D. Grammatikakis and Voula Piperaki | | Presentation | | | presentation |
| A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGA* | Antonis Papagrigoriou, Antonis Papagrigoriou and Voula Piperaki | | Paper | | | paper |
| A Meta-Model-Based Approach for Semantic Fault Modeling on Multiple Abstraction Levels | Michael Schwarz and Moomen Chaari, Bogdan-Andrei Tabacaru | | Paper | | | paper |
| A Meta-Model-Based Approach for Semantic Fault Modeling on Multiple Abstraction Levels | M. Schwarz M. Chaari, B.-A. Tabacaru, and W. Ecker | | | | | |
| A Meta-Modeling-Based Approach for Automatic Generation of Fault-Injection Processes | Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, and Thomas Kruse | | Paper | | | paper |
| A Meta-Modeling-Based Approach for Automatic Generation of Fault-Injection Processes | B.-A. Tabacaru, M. Chaari, W. Ecker, and T. Kruse | | Presentation | | | presentation |
| A Methodology for Evaluating SI Artefacts in DDR4-3DS PHY using Channel Modelling | Aditya S Kumar, Gowdra Bomanna Chethan, Shivani Maurya, Anil Deshpande, Somasunder Kattepura Sreenath | | Paper | | | paper |
| A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores | W. W. Chen, N. Tusinschi and T. L. Anderson | | Paper | | | paper |
| A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores | W. W. Chen, N. Tusinschi, and T. L. Anderson | | Presentation | | | presentation |
| A Metric-driven Methodology For Firmware Verification In Simulation/Emulation Environments | Goran Savić | | Paper | | | paper |
| A Mixed Signal System Design Methodology in SystemC AMS for Automotive Audio Power Amplifiers | Skule Pramm, Joen Westendorp, and Quino Sandifort | | | | | |
| A Model-Based Reusable Framework to Parallelize Hardware and Software Development | Jouni Sillanpää, Håkan Pettersson & Tom Richter | | | | | |
| A Mutually-Exclusive Deployment of Formal and Simulation Techniques Using Proof-Core Analysis | Keerthikumara Devarajegowda, Jeroen Vliegen, Goran Petrovity, and Kawe Fotouhi | | Presentation | | | presentation |
| A Mutually-Exclusive Deployment of Formal and Simulation Techniques Using Proof-Core Analysis | Keerthikumara Devarajegowda, Jeroen Vliegen, Goran Petrovity, and Kawe Fotouhi | | | | | |
| A New Approach to Low-Power Verification: Low Power Apps | Madhur Bhargava and Awashesh Kumar | | | | | |
| A NOVEL AND EFFICIENT METHODOLOGY TO EXPEDITE COMPLEX SOC DV CLOSURE BY LEVERAGING MODULARLY ARCHITECTURED SCALABLE ENVIRONMENT | Vinay Swargam, Guttapalem Yatisha, Ayush Agrawal, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | Paper | | | paper |
| A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoC | Harshal Kothari, Manishadevi Satyanarayana Cheernam, Vignesh Adiththan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | Paper | | | paper |
| A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoC | Harshal Kothari, Manishadevi Satyanarayana Cheernam, Vignesh Adiththan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | Poster | | | poster |
| A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoC | Harshal Kothari, Manishadevi Satyanarayana Cheernam, Vignesh Adiththan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | Presentation | | | presentation |
| A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development | Harshal Kothari, Vinay Swargam, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | Paper | | | paper |
| A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development | Harshal Kothari, Vinay Swargam, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development | Harshal Kothari, Vinay Swargam, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A Novel Approach to Functional Test Development and Execution using High-Speed IO | Marcus Schulze Westenhorst, Jörg Simon, Markus Bücker, Klaus Dieter Hilliges, Michael Braun | | | | | |
| A NOVEL APPROACH TO HARDWARE CONTROLLED POWER AWARE VERIFICATION WITH OPTIMISED POWER CONSUMPTION TECHNIQUES AT SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A NOVEL APPROACH TO HARDWARE CONTROLLED POWER AWARE VERIFICATION WITH OPTIMISED POWER CONSUMPTION TECHNIQUES AT SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A Novel Approach To In-System SRAM Repair Verification in Embedded SoC to Bridge Gap between Test and Functional Mode | Harshal Kothari, Eldin Ben Jacob, Ajay Vamshi Krishna, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | |
| A Novel Approach to Reuse Firmware for Verification of Controller based Sub-Systems using PSS | Vishnu Ramadas, Simranjit Singh, Ashwani Aggarwal, Woojoo Space Kim , Seonil Brian Choi | | Paper | | | paper |
| A novel approach to standardize reusable Modular Plug and Play Skeleton Structure (MPPSS) to expedite verification closure | Himanshu Dixit, Chandrachud Murali, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | Paper | | | paper |
| A novel approach to standardize reusable Modular Plug and Play Skeleton Structure (MPPSS) to expedite verification closure | Chandrachud Murali, Himanshu Dixit, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | Poster | | | poster |
| A Novel Approach to Standardize Verification Configurations using YAML | Nikhil Tambekar | | Paper | | | paper |
| A Novel Approach to Standardize Verification Configurations using YAML | Nikhil Tambekar | | Presentation | | | presentation |
| A Novel Framework to Accelerate System Validation on Emulation | Manoj Sharma Khandelwal, Rinkesh Yadav, Sarang Kalbande & Garima Srivastav | | Paper | | | paper |
| A Novel Performance Evaluation Methodology using Virtual Prototyping and Emulation | WoojooSpace Kim | | Presentation | | | presentation |
| A Novel Performance Evaluation Methodology using Virtual Prototyping and Emulation | Woojoo Space Kim | | Presentation | | | presentation |
| A Novel Processor Verification Methodology based on UVM | Abhineet Bhojak, Tejbal Prasad, and Stephan Herrmann | | Paper | | | paper |
| A perfect blend of verification techniques, platforms, and AI-empowered debugging in Ethernet Subsystem Verification | Olivera Stojanovic & Tijana Misic | | Paper | | | paper |
| A Pragmatic Approach to Metastability-Aware Simulation | Joseph Bulone, Roger Sabbagh | | Paper | | | paper |
| A Pragmatic Approach to Metastability-Aware Simulation | Joseph Bulone, Roger Sabbagh | | Presentation | | | presentation |
| A real world application of IP-XACT for IP packaging Bridging the usability gap | Philip Todd | | Paper | | | paper |
| A real world application of IP-XACT for IP packaging Bridging the usability gap | Philip Todd | | Presentation | | | presentation |
| A Reconfigurable Interface Architecture to Protect System IP | Arshad Riazuddin, Shoab A. Khan | | Paper | | | paper |
| A Reconfigurable Interface Architecture to Protect System IP | Arshad Riazuddin, Shoab A. Khan | | Presentation | | | presentation |
| A scalable VIP component to increase robustness of co-verification within an ASIC | Mario de Matteis, Matteo Barbati | | | | | |
| A scalableVIP component to increase robustness of co-verification within an ASIC | Mario de Matteis & Matteo Barbati | | Paper | | | paper |
| A Shift-left Methodology for an Early Power Closure Using EDCs and Power Analysis | Mohammed Fahad | | Presentation | | | presentation |
| A shift-left Methodology for an early power closure using PowerPro | Mohammed Fahad | | | | | |
| A Step Towards Zero Silicon Bugs Using Assertion Based Assumption Validation | Rohit Kumar Sinha and Babu Christie | | Paper | | | paper |
| A Step towards Zero Silicon Bugs: SVA Protocol Based Assumption Validation | Rohit Kumar Sinha and Babu Christie | | | | | |
| A Structured Approach to verify Ties, Unconnected Signals and Parameters | Saurabh Singh, Peter Limmer, and Thomas Luedeke | | | | | |
| A Structured Approach to verify Ties, Unconnected Signals and Parameters | Saurabh Singh, Peter Limmer, and Thomas Luedeke | | Paper | | | paper |
| A SystemC-based UVM verification infrastructure | Mike Bartley and Harshavardhan Narla | | | | | |
| A SystemC-based UVM verification infrastructure | Mike Bartley and Harshavardhan Narla | | Poster | | | poster |
| A Tool for Investigating Cyber-Physical Systems via SystemC AMS Virtual Prototypes Derived from SysML Models | Daniela Genius; Ludovic Apvrille | | Paper | | | paper |
| A UVM Based Methodology for Processor Verification | Abhineet Bhojak, Stephan Herrmann, and TejbalPrasad | | | | | |
| A UVM SystemVerilog Testbench for 5G/LTE Multi-Standard RF Transceiver | Byeong Kyu Kim, Jaeha Kim | | | | | |
| A UVM SystemVerilog Testbench for 5G/LTE Multi-Standard RF Transceiver | ByeongKyu Kim, Jaeha Kim | | | | | |
| A UVM Test-bench Skeleton Leveraging the Event Pool and Sequence Layering | Marcela Zachariasova, Jiri Bartak, Tomas Pehnelt & Jan Riha | | | | | |
| Accelerate Functional Coverage Closure Using Machine-Learning-Based Test Selection | Jakub Pluciński, Łukasz Bielecki, Robert Synoczek, Emelie Andersson, Antii Löytynoja, Cristian Macario | | Presentation | | | presentation |
| Accelerate Functional Coverage Closure Using Machine-Learning-Based Test Selection | Jakub Pluciński, Łukasz Bielecki, Robert Synoczek, Emelie Andersson, Antii Löytynoja & Cristian Macario | | | | | |
| Accelerated Coverage Closure by Utilizing Local Structure in the RTL Code | Rhys Buggy, Gokce Sarar, Guillaume Shippee, Han Nuou, Vishal Karna, Tushit Jain | | | | | |
| Accelerated SOC verification Using UVM Methodology for a Mix-signal Low Power Design | Giuseppe Scata, Ashwini Padoor, Vladimir Milosevic | | | | | |
| Accelerated SOC Verification Using UVM Methodology for a Mixed-Signal Low Power Design | Giuseppe Scata, Ashwini Padoor, Vladimir Milosevic | | Presentation | | | presentation |
| Accelerating and Improving FPGA Design Reviews Using Analysis Tools | Anna Tseng, Kurt Takara and Abdelouahab Ayari | | | | | |
| Accelerating and Improving FPGA Design Reviews Using Analysis Tools | Abdelouahab Ayari, Anna Tseng, and Kurt Takara | | | | | |
| Accelerating Automotive Ethernet validation by leveraging Synopsys Virtualizer with TraceCompass | Ashish Gandhi, Praveen Kumar Kondugari and Sam Tennent | | | | | |
| Accelerating Automotive Ethernet validation by leveraging Synopsys Virtualizer with TraceCompass | Ashish Gandhi, Praveen Kumar Kondugari, and Sam Tennent | | | | | |
| Accelerating Complex System Simulation using Parallel SystemC and FPGAs | Stanislaw Kaushanski, Johannes Wirth, Eyck Jentzsch, Andreas Koch | | | | | |
| Accelerating Complex System Simulation using Parallel SystemC and FPGAs | Stanislaw Kaushanski, Johannes Wirth, Eyck Jentzsch & Andreas Koch | | | | | |
| Accelerating Functional Verification Coverage Data Manipulation Using Map Reduce | Eman El Mandouh, A. Gamal, A. Khaled, B. Amr G. Wassal, and Elsayed Hemayed | | Presentation | | | presentation |
| Accelerating Functional Verification Coverage Data Manipulation Using Map Reduce | Eman El Mandouh, A. Gamal, A. Khaled, T. Ibrahim, Amr G. Wassal, Elsayed Hemayed | | Paper | | | paper |
| Accelerating RTL Simulation Techniques | Lior Grinzaig | | | | | |
| Accelerating RTL Simulation Techniques | Lior Grinzaig | | | | | |
| Acceleration of product and test environment development using SystemC-TLM | Florian Barrau, Alexandre Piccini, Alexandre Nabais Moreno, Mark Burton, Luc Michel, Clement Descha | | Paper | | | paper |
| Acceleration of product and test environment using SystemC TLM | Florian Barrau, Alexandre Piccini, Alexandre Nabais Mark Burton, Luc Michel, and Clement Deschamps | | Presentation | | | presentation |
| Accellera FS WG Update | Alessandra Nardi, Ghani Kanawati | | | | | |
| Accellera Functional Safety Working Group Update and Next Steps | Alessandra Nardi, Ghani Kanawati | | | | | |
| Accellera Systems InitiativeSystemC Standards Update | Martin Barnasconi, Philipp A. Hartmann, Trevor Wieman | | | | | |
| Accellera Systems InitiativeSystemC Standards Update | Martin Barnasconi, Philipp A. Hartmann, and Stephan Schulz | | | | | |
| Achieve Complete SoC Memory Map Verification Through Efficient Combination of Formal and Simulation Techniques | Clemens Roettgermann, Peter Limmer, and Michael Rohleder | | | | | |
| Achieve Complete SoC Memory Map Verification through Efficient Combination of Formal and Simulation Techniques | Clemens Roettgermann, Peter Limmer, and Michael Rohleder | | Presentation | | | presentation |
| Achieving Faster Code Coverage Closure using High-Level Synthesis | Surendhar Thudukuchi Chandrapandiyan, Preetham Lakshmikanthan, Ashwani Aggarwal, Youngchan Lee, Youngsik Kim, Seonil Brian Choi | | Paper | | | paper |
| Achieving Faster Reset Verification Closure with Intelligent Reset Domain Crossings Detection | Milanpreet Kaur and Sulabh Kumar Khare | | | | | |
| Achieving Faster Reset Verification Closure with Intelligent Reset Domain Crossings Detection | Milanpreet Kaur and Sulabh Kumar Khare | | | | | |
| Achieving Portable Stimulus with Graph-Based Verification – Tutorial | Josef Derner, Holger Horbach, Frederic Krampac, Staffan Berg | | | | | |
| Achieving system dependability: the role of automation and scalability | Alessandra Nardi | | Paper | | | paper |
| Achieving system dependability: the role of automation and scalability | Teo Cupaiuolo, Paul Baron, Ghani Kanawati | | | | | |
| Addressing Asynchronous FIFO Verification Challenge | Anchal Gupta, Ashish Hari and Sulabh Kumar Khare | | | | | |
| Addressing Asynchronous FIFO Verification Challenge | Anchal Gupta, Ashish Hari, Sulabh Kumar Khare | | | | | |
| Addressing Renewed Gate Level Simulation Needs for 10nm-28nm and Below | Gagandeep Singh | | | | | |
| Addressing the Complex Challenges in Low-Power Design and Verification | Madhur Bhargava, Durgesh Prasad, Jitesh Bansal, and Gabriel Chidolue | | | | | |
| Addressing the Complex Challenges in Low-Power Design and Verification | Madhur Bhargava, Durgesh Prasad, and Jitesh Bansal | | | | | |
| Adopting UVM for safety Verification requirements | Srinivasan Venkatarmanan, Hemakiran Kolli, Gurubasappa Kinagi, and Satinder Paul Singh | | | | | |
| Adopting UVM for safety Verification requirements | Srinivasan Venkatarmanan, Hema Kiran, and Satinder Paul Singh | | Paper | | | paper |
| Advance Approach for Formal Verification of Configurable Pulse Width Modulation Controller | Sumit K. Kulshreshtha, Raghavendra J N | | | | | |
| Advance your Design and Verification Flow Using IP XACT | Edwin Dankert, Maximilian Albrecht and Vincent Thibaut | | | | | |
| Advanced Techniques to Accomplish Power Aware CDC Verification | Rohit K Sinha, Ashish Hari and Sulabh Kumar Khare | | Paper | | | paper |
| Advanced UVM in the real world ‐ Tutorial | Mark Litterick, Jason Sprott, Jonathan Bromley, and Vanessa Cooper | | Presentation | | | presentation |
| Advanced UVM Tutorial Taking Reuse to the Next Level | Mark Litterick, Jason Sprott, and Jonathan Bromley | | Presentation | | | presentation |
| Advanced, High Throughput Debug From Design to Silicon | Gordon Allan & Michael Horn | | | | | |
| Advancing the SystemC Ecosystem | Philipp A Hartmann, Jerome Cornet, Martin Scnierginger, and Frederic Doucet | | Presentation | | | presentation |
| Advancing traceability and consistency in Verification and Validation | Walter Tibboel and Martin Barnasconi | | | | | |
| Advancing traceability and consistency in Verification and Validation | Walter Tibboel and Martin Barnasconi | | | | | |
| Agile and dynamic functional coverage using SQL on the cloud | Filip Dojcinovic and Mihailo Ivanovic | 2019 | Presentation | | y2019 | presentation |
| Agile and dynamic functional coverage using SQL on the cloud | Filip Dojcinovic and Mihailo Ivanovic | | | | | |
| Agile Approaches to ASIC Verification (A3V) – A Novel Agile Flow in Functional Verification | Adithya Rangan, Vidyasagar Kantamneni, Vishal Dalal | | | | | |
| Agile Approaches to ASIC Verification (A3V) – A Novel Agile Flow in Functional Verification | Adithya Rangan CK, Vidyasagar Kantamneni, Vishal Dalal | | | | | |
| Agnostic UVM-XX Testbench Generation | Jacob Andersen, Stephan Gerth, and Filippo Dughetti | | | | | |
| Agnostic UVM-XX Testbench Generation Replace XX (almost) as you see fit! | Jacob Andersen, Stephan Gerth, and Filippo Dughetti | | | | | |
| Algorithm Verification with Open Source and System Verilog | Andra Socianu and Daniel Ciupitu | | | | | |
| AMS Verification in a UVM Environment | Silvia Strähle | | | | | |
| AMS Verification in a UVM Environment | Silvia Strähle | | | | | |
| An Accelerated System Level CPU Verification through Simulation-Emulation Co-Existence | Ruchi Misra, Samridh Deva, Sai Krishna Pallekonda, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi | | Paper | | | paper |
| An Accelerated System Level CPU Verification through Simulation-Emulation Co-Existence | Ruchi Misra, Samridh Deva, P Sai Krishna, Alok Kumar, Garima Srivastava YoungSik Kim, Seonil Brian Choi | | | | | |
| An Analysis of Stimulus Techniques for Efficient Functional Coverage Closure | Caglayan Yalein, Aileen McCabe | | | | | |
| An Automated Formal Verification Flow for Safety Registers | Holger Busch | | | | | |
| An Automated Formal Verification Flow for Safety Registers | Holger Busch | | | | | |
| An Automated Pre-silicon IP Trustworthiness Assessment for Hardware Assurance | John Hallman, David Landoll, Sergio Marchese, Sven Beyer, Garrett Chan, Salam Zantout and Vikram Rao | | Paper | | | paper |
| An Automated Pre-silicon IP Trustworthiness Assessment for Hardware Assurance | J. Hallman, D. Landoll, S. Marchese, S. Beyer, G. Chan, S. Zantout, and V. Rao | | | | | |
| An Easy VE/DUV Integration Approach | Uwe Simm | | | | | |
| An Easy VE/DUV Integration Approach | Uwe Simm | | | | | |
| An Effective Design and Verification Methodology for Digital PLL | Biju Viswanathan, Rajagopal P.C, Ramya Nair S. R, Joseph J Vettickatt, and Jobin Cyriac | | | | | |
| An Effective Design and Verification Methodology for Digital PLL | Biju Viswanathan, Rajagopal P.C, Ramya Nair S. R, Joseph J Vettickatt, and Jobin Cyriac | | | | | |
| An Efficient Methodology for Mutation-Coverage-Collection of Formal-Property-Checking | Holger Busch | | Paper | | | paper |
| An Efficient Methodology for Mutation-Coverage-Collection of Formal-Property-Checking | Holger Busch | | Presentation | | | presentation |
| An efficient requirements-driven and scenario-driven verification flow | Heino van Orsouw | | Presentation | | | presentation |
| An efficient requirements-driven and scenario-driven verification flow | Walter Tibboel, Heino van Orsouw, and Shuang Han | | | | | |
| An Efficient Verification Framework for Audio/Video Interface Protocols | Noha Shaarawy, Mustafa Khairallah, Khaled Khalifa, Hany Salah, Amr Salah and Maged Ghoneima | | | | | |
| An Elegant scoreboard eco-system deploying UVM Callbacks, Parameterization for Multimedia designs from Imaging perspective | Chakravarthi Devakinanda Vurukutla, Sahana Ranganathan, Devendra Satish Bilaye, Vivek Kumar & Karthik Majeti | | | | | |
| An Elegant scoreboard eco-system deploying UVM Callbacks, Parameterization for Multimedia designs from Imaging perspective | Chakravarthi Devakinanda, Sahana Ranganathan, Devendra Satish Bilaye, Vivek Kumar & Karthik Majeti | | | | | |
| An end-to-end approach to Design and Verify Battery Management Systems: from Requirements to Virtual Field Testing | Irina Costachescu, Marius-Lucian Andrei, Manuel Fedou, Conrado Ramirez Garcia, | | Paper | | | paper |
| An end-to-end approach to Design and Verify BMS: from Requirements to Virtual Field Testing | Conrado Ramirez, Irina Costachescu, Marius Andrei, Carlos Villegas | | | | | |
| An Improved Methodology for Debugging UPF Issues at SoC level Power Aware Simulations | Ruchi Misra, S Shrinidhi Rao, Alok Kumar, Garima Srivastava & Sarang Kalbande | | | | | |
| An Introduction to using Event-B for Cyber-Physical System Specification and Design | John Colley and Michael Butler | | Presentation | | | presentation |
| An Open and Fast Virtual Platform for TriCore™-based SoCs Using QEMU | Bastian Koppelmann, Bernd Messidat, Markus Becker, and Christoph Kuznik | | | | | |
| An Open and Fast Virtual Platform for TriCore™-based SoCs Using QEMU | Bastian Koppelmann | | | | | |
| An open and flexible SystemC to VHDL workflow for rapid prototyping | Bastian Farkas | | | | | |
| An open and flexible SystemC to VHDL workflow for rapid prototyping | Bastian Farkas, Syed Abbas Ali Shah, Jan Wagner, Rolf Meyer, Rainer Buchty, and Mladen Berekovic | | Paper | | | paper |
| Analog Modelling to Suit Emulation for Hardware-Software Co-Verification | Saranya Das | | | | | |
| Analog Modelling to Suit Emulation for Hardware-Software Co-Verification | Saranya Das | | | | | |
| Applying Design Patterns to accelerate development of reusable, configurable and portable UVCs. | | | Presentation | | | presentation |
| Applying Design Patterns to Maximize Verification Reuse at Block, Subsystem and System on Chip Level | Paul Kaunds, Revati Bothe and Jesvin Johnson | | | | | |
| Attack Your SoCPowerChallenges with Virtual Prototyping | Stefan Thiel and Gunnar Braun | | | | | |
| Automate and Accelerate RISC-V Verification by Compositional Formal Methods | Yean-Ru Chen, Cheng-Ting Kao, Yi-Chun Kao, Tien-Yin Cheng, Chun-Sheng Ke and Chia-Hao Hsu | | Presentation | | | presentation |
| Automate and Accelerate RISC-V Verification by Compositional Formal Methods | Yean-Ru Chen, Cheng-Ting Kao, Yi-Chun Kao, Tien-Yin Cheng, Chun-Sheng Ke and Chia-HaoHsu | | | | | |
| Automate Interrupt Checking with UVM Macros and Python | Aleksandra Dimanic, Nemanja Stevanovic, Yoav Furman, Itay Henigsberg | | Paper | | | paper |
| Automate Interrupt Checking with UVM Macros and Python | Aleksandra Dimanic, Nemanja Stevanovic, Yoav Furman, Itay Henigsberg | | | | | |
| Automated Configuration of System Level C-Based CPU Testbench in Modern SoCs : A Novel Framework | Ruchi Misra, Chetan Kulkarni, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi | | | | | |
| Automated Configuration of System Level C-Based CPU Testbench in Modern SoCs : A Novel Framework | Ruchi Misra, Chetan Kulkarni, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi | | | | | |
| Automated Configuration of Verification Environments using Specman Macros DVcon Europe 2018 – Paper number 260-OH22 | Milos Mirosavljevic, Ron Sela, Dejan Janjic and Efrat Shneydor | | | | | |
| Automated Configuration of Verification Environments using SpecmanMacros | Milos Mirosavljevic, Ron Sela, Dejan Janjic and Efrat Shneydor | | | | | |
| Automated Creation of Reusable Generators for Analog IC Design with the Intelligent IP Method | Uwe Eichler, Benjamin Prautsch, Torsten Reich | | | | | |
| Automated Creation of Reusable Generators for Analog IC Design with the Intelligent IP Method | Uwe Eichler, Benjamin Prautsch, Torsten Reich | | Presentation | | | presentation |
| Automated SystemC Model Instantiation with modern C++ Features and sc_vector | Ralph Görgen and Philipp A. Hartmann | | | | | |
| Automated SystemC Model Instantiation with modern C++ Features and sc_vector | Ralph Görgen, Philipp A. Hartmann, and Wolfgang Nebel | | | | | |
| Automatic Diagram Creation for Design and Testbenches | Paul O’Keeffe, Jamie Beattie and Gian Lorenzo | | Paper | | | paper |
| Automatic Diagram Creation for Design and Testbenches | Paul O’Keeffe, Jamie Beattie, and Gian Lorenzo | | | | | |
| Automatic Firmware Design for Application-specific Electronic Systems: Opportunities, Challenges and Solutions | Daniel Große, Joscha Benz, Vladimir Herdt, and Martin Dittrich | | Presentation | | | presentation |
| Automatic Firmware Verification for Automotive Applications | Torsten Andre and Daniel Valtiner | | | | | |
| Automatic Firmware Verification for Automotive Applications | Torsten Andre and Daniel Valtiner | | | | | |
| Automatic Netlist Modifications required by Functional Safety | Harald Lüpken, Dirk Hönicke, and Michael Rohleder | | | | | |
| Automatic Netlist Modifications required by Functional Safety | Harald Lüpken, Dirk Hönicke, and Michael Rohleder | | | | | |
| Automatic Testbench Build to Reduce Cycle Time and Forster Reuse | Joachim Geishauser and Alexander Schilling | | | | | |
| Automatic Testbench Build to Reduce Cycle Time and Foster Reuse | Joachim Geishauser and Alexander Schilling | | Presentation | | | presentation |
| Be a Sequence Pro to Avoid Bad Con Sequences | Mark Litterick | | | | | |
| Between the Dialog and the Algorithm or Innovative Technological Narratives Leveraging the Idea of Authenticity in a Human Being Visualizing log files enables intuitive comprehension of complex test scenarios | Anna M. Ravitzki and Uri Feigin | | | | | |
| Bit density based pre characterization of RAM cells for area critical SOC design | Dilip Kumar Ajay ([email protected]) | | | | | |
| Bit Density-Based Pre-Characterization of RAM Cells for Area Critical SOC Design | Dilip Kumar Ajay | | | | | |
| Boost your productivity in FPGA & ASIC design and verification | Bart Brosens | | | | | |
| Boost your productivity in FPGA & ASIC design and verification | Bart Brosens | | | | | |
| Boosting Debug Productivity Practical Applications of Debug Innovations in a UVM World | Joerg Richter | | | | | |
| Boosting Mixed-Signal Design Productivity with FPGA-Based Methods Throughout the Chip Design Process | Gabriel Rutsch, Simone Fontanesi, Steven G. Herbst, Steven Tan Hee Yeng, Andrea Possemato, Gaetano Formato, Mark Horowitz, and Wolfgang Ecker | | Paper | | | paper |
| Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven Generation | Hoang M. Le and Rolf Drechsler | | | | | |
| Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven Generation | Hoang M. Le and Rolf Drechsler | | | | | |
| Break the SoC with UVM Dynamically Generated Program Code | Bogdan Todea, Madhukar Mahadevappa & Pravin Wilfred | | | | | |
| Bridging the gap between system-level and chip-level performance optimization | Soniya Gupta, Vikrant Kapila & Holger Keding | | | | | |
| Bringing Reset Domains and Power Domains Together – Set/Reset Flops Augmenting Complexities in Power-Aware RDC Verification. | Manish Bhati, Manjunatha Srinivas, Abdul Moyeen, Inayat Ali | | | | | |
| Build Reliable and Efficient Reset Networks with a Comprehensive Reset Domain Crossing Verification Solution | Wanggen Shi, Yuxin You, and Kurt Takara | | | | | |
| Build Reliable and Efficient Reset Networks with a Comprehensive Reset Domain Crossing Verification Solution | Wanggen Shi, Yuxin You, and Kurt Takara | | | | | |
| Building a coherent ESL design and verification eco-system with SystemC, TLM, UVM-SystemC, and CCI | Martin Barnasconi | | | | | |
| Building Code Generators for Reuse – Demonstrated by a SystemC Generator | Saad Siddiqui and Ulrich Nageldinger | | | | | |
| Building Code Generators for Reuse – Demonstrated by a SystemC Generator | Ulrich Nageldinger and Saad Siddiqui | | | | | |
| Building Confidence in System level CPU Cache Coherency Verification for Complex SoC’s through a Configurable, Flexible and Portable Testbench | Ruchi Misra, Shrinidhi Rao, Alok Kumar, Garima Srivastava, Youngsik Kim, Seonil Brian Choi | | | | | |
| Building Confidence in System Level CPU Cache Coherency Verification for Complex SoCs through a Configurable Flexible and Portable Test Bench | S Shrinidhi Rao, Ruchi Misra, Alok Kumar, Garima Srivastava, YoungSik Kim, Seonil Brian Choi | | | | | |
| Building Smart SoCs Using Virtual Prototyping for the Design and SoC Integration of Deep Learning Accelerators | Holger Keding | | | | | |
| Cadence vManager Platform and Virtuoso ADE Verifier Leading-edge technologies provide methodology for mixedsignal verification closure | Kawe Fotouhi and Walter Hartong | 2019 | Presentation | | y2019 | presentation |
| Case Study of Verification Planning to Coverage Closure @Block, Subsystem and System on Chip Level | Paul Kaunds, Revati Bothe, and Jesvin Johnson | | | | | |
| Catching the low hanging fruits on intel® Graphics Designs | M, Achutha KiranKumar V, Aarti Gupta, Bindumadhava S S, Savitha Manojna, and Abhijith A Bharadwaj | | | | | |
| Centralized Regression Optimisation Toolkit (CROT) for expediting Regression Closure With Simulator Performance Optimisation | Harshal Kothari, Pavan M, Ajay Vamshi Krishna, Eldin Ben Jacob, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | |
| Challenges and Solutions for Creating Virtual Platforms of FPGA and SASIC Designs | Kalen Brunham, Jakob Engblom | | | | | |
| Challenges and Solutions for Creating Virtual Platforms of FPGA and SASIC Designs | Kalen Brunham, Jakob Engblom | | | | | |
| Challenges of VHDL X-propagation Simulations | Karthik Baddam and Piyush Sukhija | | Paper | | | paper |
| Challenges of VHDL X-propagation Simulations | Karthik Baddam and Piyush Sukhija | | | | | |
| Characterizing RF Wireless Receivers Performance in UVM Environment | Salwa Elqassas, Salwa Elqassas and Mohammed T. Abdel-Hafe | | | | | |
| Chiplevel Analog Regressions in Production | Yi Wang | | | | | |
| Clock Controller Unit Design Metrics: Area, Power, Software Flexibility and Congestion Impacts at System Level | Michele Chilla and Leonardo Gobbi | | Paper | | | paper |
| Clock Tree Design Considerations in The Presence of Asymmetric Transistor Aging | Freddy Gabbay; Firas Ramadan; Majd Ganaiem | | Paper | | | paper |
| Closed-Loop Model-First SoC Development With the Intel® Simics® Simulator | Kalen Brunham, Anthony Moore, Tobias Rozario, Wei Jun Yeap, and Jakob Engblom | | | | | |
| Closed-Loop Model-First SoC Development With the Intel® Simics® Simulator | Kalen Brunham, Anthony Moore, Tobias Rozario, Wei Jun Yeap, and Jakob Engblom | | | | | |
| Closing and Awards | Accellera Systems Initiative | | Video | | | video |
| Closing Ceremony – DVCon Europe 2023 | | | | | | |
| Closing the gap between requirement management and system design by requirement tracing | Hayri Verner Hasou, Guillermo Conde, Adrian Rolufs, Dominic Scharfe | | | | | |
| Closing the loop from requirements management to verification execution for automotive applications | Walter Tibboel and Jan Vink | | | | | |
| Closing the loop from requirements management to verification execution for automotive applications | Walter Tibboel and Jan Vink | | Presentation | | | presentation |
| Closing with Awards | Accellera Systems Initiative | | Video | | | video |
| Clustering and Classification of UVM Test Failures Using Machine Learning Techniques | Andy Truong, Daniel Hellström, Harry Duque, and Lars Viklund | | Paper | | | paper |
| Clustering and Classification of UVM Test Failures Using Machine Learning Techniques | Andy Troung, Daniel Hellström, Harry Duque, and Lars Viklund | | Presentation | | | presentation |
| Co-Design of Automotive Boardnet Topology and Architecture | Sebastian Post, Christoph Grimm | | | | | |
| Co-Design of Automotive Boardnet Topology and Architecture | Sebastian Post; Christoph Grimm | | Paper | | | paper |
| Combining Static and Dynamic Low Power Verification for the Power-Aware SoC Sign-off | Himanshu Bhatt and Prashanth M | | | | | |
| Combining Static and Dynamic Low Power Verification for the Power-Aware SoC Sign-off | Himanshu Bhatt, Prashanth M, and Adiel Khan | | | | | |
| Complete Formal Verification of a Family of Automotive DSPs | Rafal Baranowski and Marco Trunzer | | | | | |
| Complete Formal Verification of a Family of Automotive DSPs | Rafal Baranowski and Marco Trunzer | | | | | |
| Complex Low Power Verification Challenges in NextGen SoCs : Taming the Beast! | Abhinav Nawal, Gaurav Jain, and Joachim Geishauser | | Presentation | | | presentation |
| Complex Low Power Verification Challenges in NextGen SoCs: Taming the Beast! | Abhinav Nawal and Gaurav Jain | | Paper | | | paper |
| Comprehensive AMS Verification using Octave, Real Number Modelling and UVM | John McGrath, Patrick Lynch, and Ali Boumaalif | | Paper | | | paper |
| Comprehensive AMS Verification using Octave, Real Number Modelling and UVM | John McGrath, Patrick Lynch, and Ali Boumaalif | | Presentation | | | presentation |
| Connecting a Company’s Verification Methodology to Standard Concepts of UVM | Frank Poppen, Marco Trunzer, and Jan‐Hendrik Oetjens | | Paper | | | paper |
| Connecting a Company’s Verification Methodology to Standard Concepts of UVM | Frank Poppen, Marco Trunzer, and Jan‐Hendrik Oetjens | | Presentation | | | presentation |
| Connecting Enterprise Applications to Metric Driven Verification | Matt Graham | | Paper | | | paper |
| Connecting Enterprise Applications to Metric Driven Verification | Matt Graham | | Presentation | | | presentation |
| Control Flow Analysis for Bottom-up Portable Models Creation | Petr Bardonek; Marcela Zachariasova | | Paper | | | paper |
| Covering the Last Mile in SoC-Level Deadlock Verification | Jef Verdonck, Khaled Nsaibia, Sagar Dewangan, HarGovind Singh and Roger Sabbagh | | Presentation | | | presentation |
| Covering the Last Mile in SoC-Level Deadlock Verification | Jef Verdonck, Dhruv Gupta, and HarGovind Singh | | Presentation | | | presentation |
| CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemC | Hoang M. Le and Rolf Drechsler | | Paper | | | paper |
| CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemC | Hoang M. Le and Rolf Drechsler | | Presentation | | | presentation |
| Customizing UVM Agent Supporting Multi-Layered & TDM Protocols | Amit Pessach | | Presentation | | | presentation |
| Customizing UVM Agent Supporting Multi-Layered & TDM Protocols | Amit Pessach | | Presentation | | | presentation |
| Data path verification on cross domain with formal scoreboard | Liu Jun | | Paper | | | paper |
| Data path verification on cross domain with formal scoreboard | Liu Jun | | Poster | | | poster |
| Day 1 Opening | Accellera Systems Initiative | | Video | | | video |
| Day 2 Opening | Accellera Systems Initiative | | Video | | | video |
| Democratizing Formal Verification | Tobias Ludwig, Michael Schwarz, Paulius Morkunas, Silvio Santana, Dominik Stoffel, Wolfgang Kunz | | Paper | | | paper |
| Deploying HLS in a DO-254/ED-80 Workflow | Tammy Reeve, Jacob Wiltgen, Byron Brinson, and David Aerne | | Paper | | | paper |
| Deploying HLS in a DO-254/ED-80 Workflow | Byron Brinson Jacob Wiltgen, David Aerne and Tammy Reeve | | Poster, Presentation | | | poster presentation |
| Design and verification in ARM | Hobson Bullman | | Presentation | | | presentation |
| Design Verification of the Quantum Control Stack | Seyed Amir Alavi, Samin Ishtiaq, Nick Johnson, Rojalin Mishra, Dwaraka O N, Asher Pearl and Jan Snoeijs | | Paper | | | paper |
| Designing a PSS Reuse Strategy | Matthew Ballance | | Presentation | | | presentation |
| Designing a PSS Reuse Strategy | Matthew Ballance | | Presentation | | | presentation |
| Designing the Future with Efficiency Guidance to Adopting SystemVerilog for Design! | Axel Scherer and Junette Tan | | Paper | | | paper |
| Detection of glitch-prone clock and reset propagation with automated formal analysis | Kaushal Shah, Sulabh Kumar Khare | | Paper | | | paper |
| Developing & Testing Automotive Software on Multi SoC ECU Architectures using Virtual Prototyping | Sam Tennent | | Presentation | | | presentation |
| Developing Dynamic Resource Management System in SoCEmulation | Seonchang Choi, Sangwoo Noh, Seonghee Yim and Seonil Brian Choi | | Presentation | | | presentation |
| Developing Dynamic Resource Management System in SoCEmulation | Seonchang Choi and Seonghee Yim | | Presentation | | | presentation |
| Development and Verification of RISC-V Based DSP Subsystem IP: Case Study | Pascal Gouedo, Damien Le Bars, Olivier Montfort, Lee Moore, Aimee Sutton, Larry Lapides | | Paper | | | paper |
| Development of a Core-Monitor for HW/SW Co-Debugging targetting Emulation Platform | Shreya Morgansgate, Johannes Grinschgl, Djones Lettnin | | Presentation | | | presentation |
| Development of Flexi Performance Analysis Platform for Multi–SoC Networking Systems | Srinivasan Reddy Devarajan, Anant Raj Gupta, IngoVolkening, Franz Josef Schaefer and Vijay Raj Franklin Paul Rajan William | | Presentation | | | presentation |
| Discovering Deadlocks in a Memory Controller IP | Jef Verdonck, Emrah Armagan, Khaled Nsaibia, Slava Bulach, Pranay Gupta, Anshul Jain, Chirag Agarwal and Roger Sabbagh | | Paper | | | paper |
| Discovering Deadlocks in a Memory Controller IP | Jef Verdonck, Emrah Armagan, Khaled Nsaibia, Slava Bulach, Pranay Gupta, Anshul Jain, Chirag Agarwal, and Roger Sabbagh | | Presentation | | | presentation |
| Does It Pay Off To Add Portable Stimulus Layer On Top Of UVM IP Block Test Bench? | Xia Wu, Jacob Sander Andersen and Ole Kristoffersen | | Paper | | | paper |
| Does It Pay Off To Add Portable Stimulus Layer On Top Of UVM IP Block Test Bench? | Xia Wu, Jacob Sander Andersen, and Ole Kristoffersen | | Presentation | | | presentation |
| Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon | Abdelouahab Ayari, Sukriti Bisht, Sulabh Kumar Khare and Kurt Takara | | Presentation | | | presentation |
| Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon | Abdelouahab Ayari, Sukriti Bisht, Sulabh Kumar Khare, and Kurt Takara | | Presentation | | | presentation |
| DSA Monitoring Framework for HW/SW Partitioning of Application Kernels leveraging VP | Christoph Hazott, Daniel Große | | Presentation | | | presentation |
| DSA Monitoring Framework for HW/SW Partitioning of Application Kernels leveraging VPs | Christoph Hazott; Daniel Grosse | | Paper | | | paper |
| DVCon EU 2014 Proceedings | Accellera Systems Initiative | | Program | | | program |
| DVCon EU 2015 Proceedings | Accellera Systems Initiative | | Program | | | program |
| DVCon EU 2016 Proceedings | Accellera Systems Initiative | | Program | | | program |
| DVCon EU 2017 Proceedings | Accellera Systems Initiative | | Program | | | program |
| DVCon EU 2018 Proceedings | Accellera Systems Initiative | | Program | | | program |
| DVCon EU 2019 Proceedings | Accellera Systems Initiative | | Program | | | program |
| DVCon EU 2020 Proceedings | Accellera Systems Initiative | | Video | | | video |
| DVCon EU 2020 Proceedings | Accellera Systems Initiative | | Program | | | program |
| DVCon EU 2021 Proceedings | Accellera Systems Initiative | | Program | | | program |
| DVCon Europe 2015 Road to self driving cars: View of a semiconductor company | Hans Adlkofer | | Presentation | | | presentation |
| DVCon Europe 2022 Proceedings Showcase Link | Accellera Systems Initiative | | Video | | | video |
| Dynamic Fault Injection Library Approach for SystemC AMS | Thomas Markwirth, Paul Ehrlich, and Dominik Matter | | Presentation | | | presentation |
| Dynamic Fault Injection Library Approach for SystemC AMS | Thomas Markwirth, Paul Ehrlich, and Dominik Matter | | Paper | | | paper |
| Early Performance Verification of Embedded Inferencing Systems using open source SystemC NVIDIA MatchLib | Herbert Taucher and Russell Klein | | Presentation | | | presentation |
| Easier UVM – Making Verification Methodology More Productive | John Aynsley and David Long | | | | | |
| Easier UVM: Learning and Using UVM with a Code Generator | John Aynsley, Doulos | | Presentation | | | presentation |
| Effective Design Verification – Constrained Random with Python and Cocotb | Deepak Narayan Gadde, Suruchi Kumari & Aman Kumar | | Paper | | | paper |
| Efficient Clock Monitoring System for SoC Clock Verification | Nam Pham Van | | Presentation | | | presentation |
| Efficient Clock Monitoring System for SoC Clock Verification | Nam Pham Van, Bernhard Braun, Dirk Moeller, and Clemens Roettgermann | | | | | |
| Efficient Constrained Random Generation of Address Blocks: A comparative study of simulation speeds | Meenakshy Ramachandran | | | | | |
| Efficient Constrained Random Generation of Address Blocks: A comparative study of simulation speeds | Meenakshy Ramachandran | | Poster | | | poster |
| Efficient Debugging on Virtual Prototype using Reverse Engineering Method | Sandeep Puttappa, Dineshkumar Selvaraj & Ankit Kumar | | Paper | | | paper |
| Efficient Debugging on Virtual Prototype using Reverse Engineering Method | Sandeep Puttappa, Dineshkumar Selvaraj & Ankit Kumar | | | | | |
| Efficient Exploration of Safety-Relevant Systems Through a Link Between Analysis and Simulation | Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello, and Bogdan-Andrei Tabacaru | | | | | |
| Efficient Exploration of Safety-Relevant Systems Through a Link Between Analysis and Simulation | Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello, and Bogdan-Andrei Tabacaru | | Paper | | | paper |
| Efficient Fault Injection Methods for Safety Software Testing Based on Virtual Prototypes: Application to Powertrain ECU | Ons Mbarek, Dineshkumar Selvaraj, and Romero Chica Jose Miguel | | Paper | | | paper |
| Efficient Loosely-Timed SystemC TLM-2.0 Modeling: A Hands-On Tutorial | Nils Bosbach, Lukas Junger, Rainer Leupers | | | | | |
| Efficient Loosely-Timed SystemC TLM-2.0 Modeling: A Hands-On Tutorial | Nils Bosbach, Lukas Jünger, Rainer Leupers | | | | | |
| Efficient use of Virtual Prototypes in HW/SW Development and Verification | Rocco Jonack and Eyck Jentzsch | | Presentation | | | presentation |
| Efficient Verification Framework for Audio/Video Interfaces | Noha Shaarawy | | | | | |
| Efficient Verification of a RADAR SoC Using Formal and Simulation-Based Methods | Aman Kumar, Mark Litterick & Samuele Candido | | | | | |
| Emulation based Power and Performance Workloads on ML NPUs | Pragati Mishra, Ritu Suresh, Issac P Zacharia, Jitendra Aggarwal | | | | | |
| Enabling Digital Mixed-Signal Verification of Loading Effects in Power Regulation using SystemVerilog User-Defined Nettype | Alvaro Caicedo and Sebastian Fritz | | Presentation | | | presentation |
| Enabling Digital Mixed-Signal Verification of Loading Effects in Power Regulation using SystemVerilog User-Defined Nettype | Alvaro Caicedo and Sebastian Fritz | | | | | |
| Enabling Energy Aware System Level Design with UPF-Based System Level Power Models | T4A and T4B | | | | | |
| Enabling Visual Design Verification Analytics – From Prototype Visualizations to an Analytics Tool using the Unity Game Engine | Markus Borg, Andreas Brytting, and Daniel Hansson | | | | | |
| Energy-efficient High Performance Compute, at the heart of Europe | | | | | | |
| Enhancements of metric driven verification for the ISO26262: Recent advancements better supporting specific verification requirements including functional safety | Michael Rohleder, Clemens Röttgermann, Stephan Rüttiger, John Brennan, Matt Graham, and Riccardo Oddone | | | | | |
| Enhancing Quality and Coverage of CDC Closure in Intel’s SoC Design | Rohit Kumar Sinha | | | | | |
| Enhancing Quality and Coverage of CDC Closure in Intel’s SoC Design | Rohit Kumar Sinha | | Presentation | | | presentation |
| Enriching UVM in SystemC with AMS extensions for randomization and functional coverage* | Thilo Vörtler, Thomas Klotz, Karsten Einwich, Yao Li, Zhi Wang, Marie-Minerve Louërat, Jean-Paul Chaput, François Pêcheux, Ramy Iskander, and Martin Barnasconi | | | | | |
| Enriching UVM in SystemC with AMS extensions for randomization and functional coverage* | Thilo Vörtler, Thomas Klotz, Karsten Einwich, Yao Li, Zhi Wang, Marie-Minerve Louërat, Jean-Paul Chaput, François Pêcheux, Ramy Iskander, and Martin Barnasconi | | | | | |
| ESL Design and Modeling with SystemCAMS for Mixed-Signal IoTand Automotive Applications | Karsten Einwich, Martin Barnasconi, Christoph Grimm, and Torsten Mähne | | | | | |
| Evaluation of the RISC-V Floating Point Extensions | Niko Zurstrassen; Lennart M. Reimann; Nils Bosbach; Lukas Juenger; Rainer Leupers | | Paper | | | paper |
| Experience of Using Formal Verification for a Complex Memory Subsystem Design | Sujeet Kumar, Vandana Goel, Hrushikesh Vaidya and Ronak Sarikhada | | | | | |
| Experience of using Formal Verification for a Complex Memory Subsystem Design | Sujeet Kumar,Vandana Goel,Hrushikesh Vaidya, and Ronak Sarikhada | | Poster, Presentation | | | poster presentation |
| Exploring New Frontiers of High-Performance Verification with UVM-AMS | Tim Pylant | | Presentation | | | presentation |
| Extending functionality of UVM components by using Visitor design pattern | Darko M. Tomušilović | | Paper | | | paper |
| Extending functionality of UVM components by using Visitor design pattern | Darko M. Tomušilović | | | | | |
| Extending Proven Digital Verification Techniques for Mixed-Signal SoCswith VCS AMS | Helene Thibieroz, Adiel Khan, Pierluigi Daglio, and Gernot Koch | | | | | |
| Extending the UVM register model generation and integration flow to support user-defined scenarios and register mask values | Shuang Han, Kees van Kaam, and Martin Barnasconi | | | | | |
| Extending the UVM register model generation and integration flow to support user-defined scenarios and register mask values | Shuang Han, Kees van Kaam, and Martin Barnasconi | | | | | |
| Extending UVM Register Abstraction Layer for Verification of Register Access via Serial Bus Interface | Darko M. Tomušilović | | | | | |
| Extending UVM Register Abstraction Layer for Verification of Register Access via Serial Bus Interface | Darko Tomušilović | | Paper | | | paper |
| Facilitating Transactions in System Verilog and VHDL | Rich Edelman | | | | | |
| Facilitating Transactions in VHDL and SystemVerilog | Rich Edelman | | | | | |
| Fast and Furious Quick Innovation from Idea to Real Prototype | Simone Fontanesi, Gaetano Formato, Thomas Arndt, and Andrea Monterastelli | | Paper | | | paper |
| Fast and FuriousQuick Innovation from Idea to Real Prototy | Simone Fontanesi, Gaetano Formato, Thomas Arndt, and Andrea Monterastelli | | | | | |
| Fast, Parallel RISC-V Simulation for Rapid Software Verification | Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers | | | | | |
| Fault Effect Propagation using Verilog A for Analog Test Coverage | Aishwarya Prabhakaran, Ahmed Sokar, and Jaafar Mejri | | | | | |
| Fault Effect Propagation using Verilog-A for Analog Test Coverage | Aishwarya Prabhakaran, Ahmed Sokar and Jaafar Mejri | | | | | |
| Fault Injection Analysis for Automotive Safety and Security | Sesha Sai Kumar C V, Ayman Mouallem, Jamil Mazzawi | | | | | |
| Fault Injection Analysis for Automotive Safety and Security | Sesha Sai Kumar C.V., Jamil Mazzawi, Ayman Mouallem | | | | | |
| Fault Proof: Using Formal Techniques for Safety Verification and Fault Analysis | Adrian Traskov, Thorsten Ehrenberg, Sacha Loitz, Abdelouahab Ayari, Avidan Efody, and Joseph Hupcey III | | | | | |
| Fault Proof: Using Formal Techniques for Safety Verification and Fault Analysis | Adrian Traskov,Thorsten Ehrenberg, Sacha Loitz, Abdelouahab Ayari, Avidan Efody, and Joseph Hupcey III | | | | | |
| Fault-injection-Enhanced Virtual Prototypes Enable Early SW Development for Automotive Applications | Mohammad Badawi, Javier Castillo, Andreas Mauderer & Jan-Hendrik Oetjens | | | | | |
| Fault-injection-Enhanced Virtual Prototypes Enable Early SW Development for Automotive Applications | Mohammad Badawi, Javier Castillo, Andreas Mauderer & Jan-Hendrik Oetjens | | | | | |
| Firmware Firmly under Control: New Optimization and Verification Techniques for Application Specific Electronic System | Daniel Große, Manuel Strobel, Daniel Mueller-Gritschneder, Vladimir Herdt, and Tobias Ludwig | | | | | |
| Five Ways to Make Your Specman Environment More Reusable and Configurable | Stefan Sljukic, Nikola Knezevic, Filip Dojcinovic | | | | | |
| Flexible Indirect Registers With UVM | Uwe Simm | | | | | |
| Flexible Indirect Registers With UVM | Uwe Simm | | | | | |
| Formal Fault Propagation Analysis that Scales to Modern Automotive SoCs | Sergio Marchese | | | | | |
| Formal Fault Propagation Analysis that Scales to Modern Automotive SoCs | Sergio Marchese and Jörg Grosse | | Paper | | | paper |
| Formal Property Verification of the Digital Section of an Ultra-Low Current Digitizer ASIC | Katharina Ceesay-Seitz, Sarath Kundumattathil Mohanan, Hamza Boukabache, Daniel Perrin | | | | | |
| Formal Verification Experiences: Silicon Bug Hunt with “Deep Sea Fishing” | Mark Handover, Abdelouahab Ayari and Ping Yeung | | | | | |
| Formal Verification Experiences: Silicon Bug Hunt with “Deep Sea Fishing” | Ping Yeung, Mark Handover, and Abdelouahab Ayari | | Poster, Presentation | | | poster presentation |
| Formal Verification of a Highly Configurable DDR Controller IP | Sumit Neb, Chirag Agarwal, Deepak K. Gupta, and Roger Sabbagh | | Paper | | | paper |
| Formal Verificationin the Real World | Jonathan Bromley and Jason Sprott | | | | | |
| FPGA Debug Using Configuration Readback | Mike Dini | | Presentation | | | presentation |
| Functional Safety Verification for ISO 26262 – Compliant Automotive Designs | JM Forey and Werner Kerscher | | Presentation | | | presentation |
| Functional Safety WG Update | Alessandra Nardi | | Paper | | | paper |
| Fuzzing Firmware Running on Intel® Simics® Virtual Platforms | Jakob Engblom, Robert Guenzel | | Presentation | | | presentation |
| Fuzzing Firmware Running on Intel® Simics® Virtual Platforms | Jakob Engblom & Robert Guenzel | | Paper | | | paper |
| Gathering Memory Hierarchy Statistics in QEMU | Clément Deschamps, Mark Burton, Eric Jenn and Frédéric Pétrot | | Presentation | | | presentation |
| Gathering Memory Hierarchy Statistics in QEMU | Clément Deschamps, Mark Burton, Eric Jenn, and Frédéric Pétrot | | Presentation | | | presentation |
| Generating Bus Traffic Patterns | Jacob Sander Andersen, Lars Viklund and Kenneth Branth | | Paper | | | paper |
| Generation of (at least) UVM Register Models from IP Xact Using Model Driven SW Techniques | Jacob Sander Andersen | | Presentation | | | presentation |
| Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS* | Ronan Lucas, Marie-Minerve Louërat, Yao Li, Zhi Wang, Jean-Paul Chaput, François Pêcheux, Ramy Iskander, Martin Barnasconi, and Thilo Vörtler | | Paper | | | paper |
| Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS* | Ronan Lucas and Philippe Cuenot | | Presentation | | | presentation |
| Generic Core-Monitor for Hardware/Software Co-Debugging targeting Emulation Platform | Shreya Morgansgate, Johannes Grinschgl, Djones Lettnin | | Paper | | | paper |
| Generic Testbench/Portable Stimulus/Promotability | Revati Bothe and Jesvin Johnson | | Presentation | | | presentation |
| Go Figure – UVM Configure The Good, The Bad, The Debug | Rich Edelman and Dirk Hansen | | | | | |
| Go Figure – UVM Configure The Good, The Bad, The Debug | Rich Edelman and Dirk Hansen | | | | | |
| Golden UPF: Preserving Power Intent From RTL to Implementation | Himanshu Bhatt and Harsh Chilwal | | | | | |
| Grid-based Mapping and Analysis of a GoogLeNet CNN using MapGL Editor | Claudio Raccomandato, Emad M. Arasteh & Rainer Dömer | | Presentation | | | presentation |
| Grid-based Mapping and Analysis of a GoogLeNet CNN using MapGL Editor | Claudio Raccomandato, Emad M. Arasteh & Rainer Dömer | | | | | |
| Guiding Functional Verification Regression Analysis Using Machine Learning and Big Data Methods | Eman El Mandouh, Laila Maher, Moutaz Ahmed and Amr G. Wassal | | Paper | | | paper |
| Handling Asynchronous Reset(s) Testing by building reset-awareness into UVM testbench components | Wei Wei Cheong, Katherine Garden, Ana Sanz Carretero | | | | | |
| Hardware construction with SystemC | Roman Popov and Roman Popov | | | | | |
| Hardware Software Co-verification in Hybrid QEMU/HDL Environment | Radoslaw Nawrot and Krzysztof Szczur | | | | | |
| Hardware/Software Co-Simulation of SPI enabled ASICs and Software Drivers for Fault Injection and Regression Tests | Elias Kyrlies-Chrysoulidis, Andreas Plange, Thomas Gürtler, Matthias Auerswald, and Josef Schmid | | Paper | | | paper |
| Hardware/Software Co-Simulation of SPI enabled ASICs and Software Drivers for Fault Injection and Regression Tests | Elias Kyrlies-Chrysoulidis, Andreas Plange, Thomas Guertler, Matthias Auerswald, and Josef Schmid | | | | | |
| Heterogeneous Virtual Prototyping for IoTApplications | Paul Ehrilich, Karsten Einwich, Mark Burton, and Luc Michel | | | | | |
| Heterogenous Virtual Prototyping for IoT Applications | Mark Burton, Luc Michel, Paul Ehrlich, and Karsten Einwich | | | | | |
| High-Performance Mixed-Signal ESL Design of a Magneto Resistive Sensor Application | Martin Barnasconi and Sumit Adhikari | | | | | |
| High-Performance Mixed-Signal ESL Design of a Magneto Resistive Sensor Application | Martin Barnasconi and Sumit Adhikari | | | | | |
| How creativity kills reuse – A modern take on UVM/SV TB architecture | Andrei Vintila, Sergiu Duda | | | | | |
| How creativity kills reuse – A modern take on UVM/SV TB architectures | Andrei Vintila, Sergiu Duda | | | | | |
| How Far Can You Take UVM Code Generation and Why Would You Want To? | John Aynsley | | | | | |
| How Far Can You Take UVM Code Generation and Why Would You Want To? | John Aynsley | | | | | |
| How rich descriptions enable early detection of hookup issues | Peter Birch, Thomas Brown | | Presentation | | | presentation |
| How the Right Mindset Increases Quality in RISC-V Verification | Philippe Luc, Salaheddin Hetalani, Nicolae Tusinschi | | | | | |
| How the Right Mindset Increases Quality in RISC-V Verification | Philippe Luc, Salaheddin Hetalani | | Presentation | | | presentation |
| How to achieve verification closure of configurable code by combining static analysis and dynamic testing | Antonello Celano, Alexandre Langenieux | | | | | |
| How to achieve verification closure of configurable code by combining static analysis and dynamic testing | Antonello Celano, Alexandre Langenieux | | | | | |
| How to Create a Complex Testbench in a Couple of Hours | Tom Fitzpatrick and Graeme Jessiman | | | | | |
| How to leverage the power of MATLAB from Functional Verification Test Benches | Tom Richter | | | | | |
| How to Use Formal Analysis to Prevent Deadlocks | Abdelouahab Ayari, Mark Eslinger and Joe Hupcey III | | | | | |
| How to Verify Complex FPGA Designs for Free | Sebastian Dreßler, Nikos Anastasiadis, and Thomas Richter | | Presentation | | | presentation |
| How to Verify Complex FPGA Designs for Free | Sebastian Dreßler, Nikos Anastasiadis, and Thomas Richter | | | | | |
| How To Verify Encoder And Decoder Designs Using Formal Verification | Jin Hou | | | | | |
| How To Verify Encoder And Decoder Designs Using Formal Verification | Jin Hou | | | | | |
| HW-SW-Coverification as part of CI/CD | Alexander Hoffmann, Ganesh Nair, Nan Ni & Johannes Grischgl | | | | | |
| Hybrid Emulation for faster Android Home screen bring up and Software Development | Rinkesh Yadav, Manoj Khandelwal, Sarang Kalbande & Garima Srivastava | | | | | |
| Hybrid Flow: A smart methodolgy to migrate from traditional Low Power Methodology | Rohit Kumar Sinha and N. Prashanth | | | | | |
| Hybrid Flow: A smart methodology to migrate from traditional Low Power Methodology | Rohit Kumar Sinha and Prashanth N | | | | | |
| IEEE 1801 Assisted Custom IP Development and Low Power Checks Using Cadence Virtuoso Power Manager | Dr. Matthias Steffen, Amit Chopra and Amit Chopra | | | | | |
| IEEE 1801 Assisted Custom IP Development and Low Power Checks Using Cadence Virtuoso Power Manager | Matthias Steffen, Amit Chopra, and Sonal Singh | | | | | |
| Implementation of a closed loop CDC verification methodology | Andrew Cunningham, Ireneusz Sobanski | | | | | |
| Implementation of a closed loop CDC verification methodology | Andrew Cunningham | | | | | |
| Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification | Deepak Narayan Gadde, Sebastian Simon, Djones Lettnin, Thomas Ziller | | | | | |
| Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification | Deepak Narayan Gadde, Sebastian Simon, Djones Lettnin, Thomas Ziller | | | | | |
| Improving the Confidence Level in Functional Safety Simulation Tools for ISO 26262 | Ahmet Cagri Bagbaba, Felipe Augusto Da Silva, and Christian Sauer | | | | | |
| Increased Regression Efficiency with Jenkins Continuous Integration | Thomas Ellis | | | | | |
| Increasing Efficiency and Reuse in Modeling SystemC/TLM IPs Targeting Virtual Prototypes for Software Development | David Spieker, Thomas Schuster, Rafael Zuralski, and Christian Sauer | | | | | |
| Initialization Techniques for D-Flip-Flop Based Scan Chain with Scan Flush Architecture in Gate-Level Simulation | Wei Jun Yeap, Rahul Chauhan & Wonyoung Choi | | | | | |
| Innovative Technological Narratives Leveraging the Idea of Authenticity in a Human Being | Anna M. Ravitzki, Uri Feigin, and Hagai Arbel | | | | | |
| Institutionalize a certified ISO26262 safety process | M. Rohleder, C. Röttgermann, amd M. Müller | | | | | |
| Institutionalizing a certified ISO26262 safety process: Experiences and lessons learned | Michael Rohleder, Clemens Röttgermann, and Marcus Müller | | | | | |
| Integrating a Virtual Platform Framework for Smart Devices | V. Guarnieri, F. Stefanni, F. Fummi, M. Grosso, D. Lena, A. Ciccazzo, G. Gangemi, and S. Rinaudo | | | | | |
| Integrating Different Types of Models into a Complete Virtual System | Jakob Engblom, Andreas Hedström, Xiuliang Wang, and Håkan Zeffer | | | | | |
| Integrating Different Types of Models into a Complete Virtual System: The Simics SystemC* Library | Jakob Engblom, Andreas Hedström, Xiuliang Wang, and Håkan Zeffer | | | | | |
| Integrating Parallel SystemC Simulationinto Simics® Virtual Platform | Daniel Mendoza, Ajit Dingankar, ZhongqiCheng and Rainer Doemer | | | | | |
| Integrating Parallel SystemC Simulationinto Simics® Virtual Platform | Daniel Mendoza, Ajit Dingankar, Zhongqi Cheng and Rainer Doemer | | Presentation | | | presentation |
| Integration of modern verification methodologies in a TCL test framework | Matteo De Luigi and Alessandro Ogheri | | | | | |
| Integration Verification of Safety Components in Automotive Chip Modules | Holger Busch | | | | | |
| Integration Verification of Safety Components in Automotive Chip Modules | Holger Busch | | | | | |
| Introduction to Next Generation Verification Language – Vlang | Puneet Goel and Sumit Adhikari | | | | | |
| Introduction to Next Generation Verification Language – Vlang | Puneet Goel and Sumit Adhikari | | | | | |
| IP-Coding Style Variants in a Multi-layer Generator Framework | Zhao Han, Keerthikumara Devarajegowda, Andreas Neumeier and Wolfgang Ecker | | | | | |
| IP-Coding Style Variants in a Multi-layer Generator Framework | Zhao Han, Keerthikumara Devarajegowda, Andreas Neumeier, and Wolfgang Ecker | | | | | |
| Is Your Testing N wise or Unwise? Pairwise and N wise Patterns in SystemVerilog for Efficient Test Configuration and Stimulus | Jonathan Bromley and Kevin Johnston | | | | | |
| Is Your Testing N-wise or Unwise? Pairwise and N-wise Patterns in SystemVerilog for Efficient Test Configuration and Stimulus | Jonathan Bromley and Kevin Johnston | | | | | |
| ISO 26262 Fault Analysis in Safety Mechanisms Considering the impact of residual and latent faults in hardware safety mechanisms | Jörg Grosse, Mark Hampton, Sergio Marchese, Jörg Koch, Neil Rattray and Alin Zagardan | | | | | |
| ISO 26262: Better be safe with modelling and simulation on system-level | Joachim Hößler, Sven Johr, Thang Nguyen, Stephan Schulz, and Gert-Jan Tromp | | | | | |
| ISO 26262: Better be safe with modelling and simulation on system-level | Joachim Hößler, Sven Johr, Thang Nguyen, Stephan Schulz, and Gert-Jan Tromp | | | | | |
| Keynote: Challenges in Soc Verification for 5G and Beyond | Axel Jahnke | | | | | |
| Keynote: Developing the Chip-to-Cloud Architecture for the Most Desirable Cars | Magnus Östberg | | | | | |
| Keynote: Energy-efficient High Performance Compute, at the heart of Europe | | | | | | |
| Keynote: Pervasive and Sustainable AI with Adaptive Computing | | | | | | |
| Language Agnostic Communication for SystemC TLM Compliant Virtual Prototypes | Smurti Khire, Kunal Sharma, Vishal Chovatiya | | | | | |
| Large-scale Gatelevel Optimization Leveraging Property Checking | Lucas Klemmer; Dominik Bonora; Daniel Grosse | | | | | |
| Lean Verification Techniques: Executable SystemVerilog UVM Defect Table For Simulations | Steve Burchfiel, Kevin Schott, Kamel Belhous and Paul Ulrich | | | | | |
| Lean Verification Techniques: Executable SystemVerilog UVM Defect Table For Simulations | Kamel Belhous and Steve Bu | | | | | |
| Leveraging hardware emulation to accelerate SoCverification in multi-physics automotive simulation environment via the Functional Mock-up Interface | Pierre-Guillaume Le Guay, Henrique Vicente De Souza, Caaliph Andriamisaina, Emmanuel Molina Gonzalez and Tanguy Sassolas | | | | | |
| Leveraging hardware emulation to accelerate SoCverification in multi-physics automotive simulation environment via the Functional Mock-up Interface | Pierre-Guillaume Le Guay, Henrique Vicente De Souza, Caaliph Andriamisaina, Emmanuel Molina Gonzalez, and Tanguy Sassolas | | | | | |
| Leveraging the UVM RAL for Memory Sub-System Verification | Tudor Timisescu and Uwe Simm | | | | | |
| Leveraging the UVM Register Abstraction Layer for Memory Sub-System Verification | Tudor Timisescu and Uwe Simm | | | | | |
| Leveraging virtual prototypes from concept to silicon | Rob Kaye | | | | | |
| Low-Power Validation Framework for Standard Cell Library Including Front-End and Back-End Implementation | J. Lee, H. Bak, S. Do, T. Yoo, Hwaseong-si, Gowrishankar Srinivasan & Vishw Mitra Singh Bhadouria | | | | | |
| Low-Power Verification Methodology using UPF Query functions and Bind checkers | Madhur Bhargava and Durgesh Prasad | | | | | |
| Low-Power Verification Methodology using UPF Query functions and Bind checkers | Madhur Bhargava and Durgesh Prasad | | | | | |
| Machine Learning based Structure Recognition in Analog Schematics for Constraints Generation | Rituj Patel, Husni Habal, Konda Reddy Venkata | | | | | |
| Machine Learning for Coverage Analysis in Design Verification | V Jayasree | | | | | |
| Machine Learning Introduction and Exemplary Application in Embedded Wireless Platforms | Jonathan Ah Sue | | | | | |
| Make Your Testbenches Run Like Clockwork! | Markus Brosch, Salman Tanvir and Martin Ruhwandl | | | | | |
| Make your Testbenches Run Like Clockwork! | Markus Brosch, Salman Tanvir, and Martin Ruhwandl | | | | | |
| Making Autonomous Cars Safe | Joern Stohmann and Frederico Ferlini | | | | | |
| Making ISO26262 Functional Safety Verification a Natural Extension of Functional Verification | Andrew Betts and Ann Keffer | | | | | |
| MapGL: Interactive Application Mapping and Profiling on a Grid of Processing Cells | Claudio Raccomandato, Emad M. Arasteh & Rainer Dömer | | | | | |
| MapGL: Interactive Application Mapping and Profiling on a Grid of Processing Cells | Claudio Raccomandato; Emad M. Arasteh; Rainer Doemer | | | | | |
| Maximize PSS Reuse with Unified Test Realization Layer Across Verification Environments | Simranjit Singh, Ashwani Aggarwal, Suman Kumar Reddy Mekala, Arun K.R., Woojoo Space Kim , Seonil Brian Choi, Gnaneshwara Tatuskar | | | | | |
| Mechanical mounting variation effects on magnetic speed sensor applications | Simone Fontanesi, Se Hwan Kim, Gernot Binder and Andrea Monterastelli | | | | | |
| Mechanical mounting variation effects on magnetic speed sensor applications Combining finite element methods and SystemC simulations to study the effects of mechanical tilts and offset on magnetic speed sensor applications | Simone Fontanesi, Se Hwan Kim, Gernot Binder and Andrea Monterastelli | | | | | |
| MetaPSS: An Automation Framework for Generation of Portable Stimulus Model | Jaimini Nagar; Thorsten Dworzak; Sebastian Simon; Ulrich Heinkel; Djones Lettnin | | | | | |
| MetaPSS: An Automation Framework for Generation of Portable Stimulus Model | Jaimini Nagar, Thorsten Dworzak, Sebastian Simon, Ulrich Heinkel, Djones Lettnin | | | | | |
| Method for early performance verification of hardware-accelerated embedded processor systems in RTL simulation | Luca Sasselli, Mehmet Tukel, David Guthrie | | | | | |
| Methodology for Automated Generation and Validation of Analog Behavioral Models for Mixed-Signal Verification | Nan Ni, Chunya Xu, and Sebastian Simon | | | | | |
| Methodology for checking UVM VIPs | Milan Vlahovic and Ilija Dimitrijevic | | | | | |
| Methodology for checking UVM VIPs | Milan Vlahovic and Ilija Dimitrijevic | | | | | |
| Methodology of Communication Protocols Development: from Requirements to Implementation | Irina Lavrovskaya and Valentin Olenev | | | | | |
| MicroTESK: Automated Architecture Validation Suite Generator for Microprocessors | Mikhail Chupilko, Alexander Kamkin, Alexander Protsenko, Sergey Smolov, and Andrei Tatarnikov | | | | | |
| Migrating from UVM to UVM-MS | Tim Pylant | | | | | |
| Mixed Electronic System Level Power/Performance Estimation | Antonio Genov, Loic Leconte and François Verdier | | | | | |
| Mixed ESL Power/Performance Estimation using SystemC/TLM2.0 Modeling and PwClkARCHLibrary | Antonio Genov, Loic Leconte, and François Verdier | | | | | |
| Model based Automation of Verification Development for automotive SOCs | Aljoscha Kirchner, Jan Hendrik Oetjens, and Oliver Bringmann, | | | | | |
| Model Validation for Mixed-Signal Verification | Carsten Wegener | | | | | |
| Model Validation for Mixed-Signal Verification The Importance of Being Earnest about Modeling | Carsten Wegener | | | | | |
| Model-Based Approach for Developing Optimal HW/SW Architectures for AI systems | Petri Solanti, Russell Klein | | | | | |
| Model-Based Automation of Verification Development for Automotive SOCs | Aljoscha Kirchner, Jan-Hendrik Oetjens and Oliver Bringmann | | | | | |
| Modeling of Generic Transfer Functions in SystemVerilog | Elvis Shera | | | | | |
| Modeling of Generic Transfer Functions in SystemVerilog. Demystifying the Analytic Model | Elvis Shera | | | | | |
| Modelling Finite-State Machines in the Verification Environment using Software Design Patterns | Darko M. Tomušilović | | | | | |
| Modelling Finite-State Machines in the Verification Environment using Software Design Patterns | Darko M. Tomušilović and Mihajlo Z. Minović | | | | | |
| Modelling of UVC Monitor Class as a Finite State Machine for a Packet-Based Interface | Djordje Velickovic, Milos Mitic | | | | | |
| Modelling of UVC Monitor Class as a Finite State Machine for a Packet-Based Interface | Djordje Velickovic, Milos Mitic | | | | | |
| Modern methodologies in a TCL test environment | Matteo De Luigi and Alessandro Ogheri | | | | | |
| Moving SystemC to a New C++ Standard | Ralph Görgen and Philipp A. Hartmann | | | | | |
| Multi-Variant Coverage: Effective Planning and Modelling | Vikas Sharma and Manoj Manu | | | | | |
| Multi-Variant Coverage: Effective Planning and Modelling | Vikas Sharma and Manoj Manu | | | | | |
| Mutable Verification Environments Through Visitor and Dynamic Register Map Configuration | Matteo Barbati, Alberto Allara | | | | | |
| Mutable Verification Environments through Visitor and Dynamic Register Map Configuration | Matteo Barbati and Alberto Allara | | | | | |
| Netlist Paths | Jamie Hanlon, Samuel Kong | | | | | |
| New Trends in RTL Verification: Bug Localization, Scan- Chain-Based Methodology, GA-Based Test Generation | Khaled Salah | | | | | |
| New Trends in RTL Verification: Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation | Khaled Salah | | | | | |
| Next Gen System Design and Verification for Transportation | Bryan Ramirez, Petri Solanti and Richard Pugh | | | | | |
| Next Generation ISO 26262-basedDesign Reliability Flows | Jörg Große and Sanjay Pillay | | | | | |
| No Country For Old Men – A Modern Take on Metrics Driven Verification | Svetlomir Hristozkov, James Pallister, Richard Porter | | | | | |
| NVVM: A Netlist-based Verilog Verification Methodology for Mixed-Signal Design | Jiping Qiu, Kurt Schwartz | | | | | |
| NVVM: A Netlist-based Verilog Verification Methodology for Mixed-Signal Design | Jiping Qiu, Kurt Schwartz | | | | | |
| On the Performance Differences of SystemC and SystemC AMS: A Guideline for Real Number Modeling and Beyond | Alexandra Kuester; Rainer Dorsch; Christian Haubelt | | | | | |
| One Testbench to Rule them all! | Salman Tanvir, Markus Brosch, Amer Siddiqi | | | | | |
| Open Source Solution for RISC-V Verification | Mikhail Chupilko, Alexander Kamkin and Alexander Protsenko | | | | | |
| Open Source Solution for RISC-V Verification | Mikhail Chupilko, Alexander Kamkin, and Alexander Protsenko | | | | | |
| Open-Source Virtual Platforms for Industry and Research | Nils Bosbach, Lukas Jünger & Rainer Leupers | | Presentation | | | presentation |
| Opening Session – Day 1 – DVCon Europe 2023 | | | | | | |
| Opening Session – Day 2 – DVCon Europe 2023 | | | | | | |
| Optimizing Design Verification using Machine Learning | William Hughes, Sandeep Srinivasan, Rohit Suvarna, Maithilee Kulkarni | | | | | |
| OSVVM and Error Reporting | Jim Lewis | | | | | |
| OSVVM and Error Reporting | Jim Lewis | | | | | |
| OSVVM: Advanced Verification for VHDL | Jim Lewis | | | | | |
| OSVVM: Advanced Verification for VHDL | Jim Lewis | | | | | |
| Overcoming Challenges in SoC RTL Verification of USB Subsystem | Tijana Mišić and Marko Mišić, | | | | | |
| Overcoming System Verilog Assertions limitations through temporal decoupling and automation | Mattia De Pascalis, Xia Wu, Matteo Vottero, Jacob Sander Andersen | | | | | |
| Overcoming SystemVerilog Assertions limitations through temporal decoupling and automation | Mattia De Pascalis, Xia Wu, Matteo Vottero, Jacob Sander Andersen | | | | | |
| Panel: “All AI All the Time” Poses New Challenges for Traditional Verification | | | | | | |
| Panel: 5G Chip Design Challenges and their Impact on Verification | Accellera Systems Initiative | | | | | |
| Panel: Are Processor/SoC Discontinuities Turning Verification on its Head? | Accellera Systems Initiative | | | | | |
| Panel: The Great Verification Chiplet Challenge | | | | | | |
| Paving a Path to Hardware-Based Acceleration in a Single UVM Environment (Because there can be only one UVM environment!) | Axel Scherer and Mark Azadpour | | | | | |
| Pedal Faster! Or Make Your Verification Environment More Efficient. You Choose. | Rich Edelman, Raghu Ardeishar, and Rohit Jain | | | | | |
| Pedal Faster! Or Make Your Verification Environment More Efficient. You Choose. | Rich Edelman, Raghu Ardeishar, and Rohit Jain | | | | | |
| Performance modeling and timing verification for DRAM memory subsystems | Thomas Schuster, Peter Prüller, and Christian Sauer | | | | | |
| Performance modeling and timing verification for DRAM memory subsystems | Thomas Schuster, Peter Prüller, and Christian Sauer | | | | | |
| Pervasive and Sustainable AI with Adaptive Computing Architectures | Michaela Blott | | | | | |
| Planning for RISC-V Success | Pascal Gouedo, Xavier Aubert, Yoann Pruvost | | | | | |
| Planning for RISC-V Success Verification Planning and Functional Coverage | Duncan Graham, Aimee Sutton, Simon Davidmann, Pascal Gouedo, Xavier Aubert, & Yoann Pruvost | | | | | |
| Plug and Play Verification: Leveraging Block-Level Components for Seamless Top-Level Integration | Tchiya Dayan | | | | | |
| Plug and Play Verification: Leveraging Block-Level Components for Seamless Top-Level Integration | Tchiya Dayan | | | | | |
| Portable Stimuli over UVM using portable stimuli in HW verification flow | Efrat Shneydor, Slava Salnikov, Liran Kosovizer and Dr’ Shlomo Greenberg | | | | | |
| Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication endpoint | Andrei Vintila and Ionut Tolea | | | | | |
| Portable Test and Stimulus: The Next Level of Verification Productivity is Here | Tom Fitzpatrick and Sharon Rosenberg | | | | | |
| Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts | Mark Handover, Jonathan Lovett, and Kurt Takara | | | | | |
| Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts | Mark Handover, Jonathan Lovett, and Kurt Takara | | | | | |
| Power Aware Models: Overcoming barriers in Power Aware Simulation | Mohit Jain, Amit Singh, J.S.S.S. Bharath, Amit Srivastava, and Bharti Jain | | | | | |
| Power Aware Models: Overcoming barriers in Power Aware Simulation | Mohit Jain, Amit Singh, J.S.S.S. Bharath, Amit Srivastava, and Bharti Jain | | | | | |
| Power-Aware Verification in Mixed-Signal Simulation | Atul Pandey, Mattias Welponer, and Gregor Kowalczyk | | | | | |
| Power-Aware Verification in Mixed-Signal Simulation | Atul Pandey, Mattias Welponer, and Gregor Kowalczyk | | | | | |
| Practical Experience in Automatic Functional Coverage Convergence and Reusable Collection Infrastructure in UVM | Roman Wang, Suresh Babu Pusphaparaj, Mike Bartley | | | | | |
| Practical experience in automatic functional coverage convergence and reusable collection infrastructure in UVM verification | Roman Wang, Suresh Babu Pusphaparaj | | | | | |
| Practical experience in automatic functional coverage convergence and reusable collection infrastructure in UVM verification | Roman Wang and Suresh Babu Pusphaparaj | | | | | |
| Pragmatic Formal Verification Methodology for Clock Domain Crossing | Aman Kumar, Muhammad U.H. Khan & Bijitendra Mittra | | | | | |
| Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC) | Aman Kumar, Muhammad U.H. Khan & Bijitendra Mittra | | | | | |
| Probing UPF Dynamic Objects: Methodologies to Build Your Custom Low-Power Verification | Progyna Khondkar | | | | | |
| Probing UPF Dynamic Objects: Methodologies to Build Your Custom Low-Power Verification Platform | Progyna Khondkar | | | | | |
| Processing deliberate verification errors during regression | Alastair Lefley, Roger Witlox, Clemens Süßmuth, Thomas Ziller and Kawe Fotouhi | | | | | |
| Processing deliberate verification errors during regression | Alastair Lefley, Roger Witlox, Clemens Süßmuth, Thomas Ziller, and Kawe Fotouhi | | | | | |
| Programmable Analysis of RISC-V Processor Simulations using WAL | Lucas Klemmer, Eyck Jentzsch, Daniel Große | | | | | |
| Protocol verification of an IEEE 802.3bw PHY Application of mixed signal extensions to an UVM verification environment | Joen Westendorp and Marcel Oosterhuis | | Paper | | | paper |
| Pythonized SystemC A non-intrusive scripting approach | Eyck Jentzsch and Rocco Jonack | | | | | |
| QED & Symbolic QED Pre-silicon Verification, Post-silicon Validation, Industrial Results | Subhasish Mitra, Eshan Singh and K. Devarajegowda | | | | | |
| Qualification of a Verification IP under Requirement Based Verification standards An approach to the verification of the verification | Francois Cerisier, Adrien Carmagnat, Alessandro Basili, and Gilles Curchod | | | | | |
| Random Stimuli Models for UVM Registers | Jacob Sander Andersen, Lars Viklund and Laura Montero | | | | | |
| Reboot your Reset Methodology: Resetting Anytime with the UVM Reset Package | Courtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm | | | | | |
| Reboot your Reset Methodology: Resetting Anytime with the UVM Reset Package | Courtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm | | | | | |
| Refining Successive Refinement: Improving a Methodology for Incremental Specification of Power Intent | Desinghu PS, Adnan Khan, Erich Marschner, and Gabriel Chidolue | | | | | |
| Refining Successive Refinement: Improving a Methodology for Incremental Specification of Power Intent | Erich Marschner and Gabriel Chidolue | | | | | |
| Register Testing – Exploring Tests, Register Model Libraries, Sequences and Backdoor Access | Rich Edelman | | | | | |
| Register Testing – Exploring Tests, Register Model Libraries, Sequences and Backdoor Access | Rich Edelman | | | | | |
| Requirement Driven Safety Verification | Ranga Kadambi, Vladimir Litovtchenko, Jens Rosenbusch, and Antonio Vilela | | | | | |
| Requirement Driven Safety Verification | Ranga Kadambi, Vladimir Litovtchenko, Jens Rosenbusch, and Antonio Vilela | | | | | |
| Requirements Driven Design Verification Flow Tutorial | Ateş Berna and Ahmet Jorghanxhi | | | | | |
| Requirements driven Verification methodology (for standards compliance) | Serrie-Justine Chapman, Darren Galpin, and Mike Bart | | | | | |
| Requirements driven Verification methodology (for standards compliance) | Serrie-justine Chapman, Mike Bartley, and Darren Galpin | | | | | |
| Requirements-driven Verification Methodology for Standards Compliance | Serrie-justine Chapman and Mike Bartley | | | | | |
| Reset Your Reset Domain Crossing (RDC) Verification with Machine Learning | Mark Handover | | | | | |
| Reset Your Reset Domain Crossing (RDC) Verification with Machine Learning | Mark Handover | | | | | |
| Reset Your Reset Domain Crossing (RDC) Verification with Machine Learning | Mark Handover | | | | | |
| Resetting RDC Expectations | Eamonn Quigley, Jonathan Niven, Mark Handover | | | | | |
| Results Checking Strategies with Portable Stimulus | Tom Fitzpatrick and Matthew Ballance | | | | | |
| Retrascope: Open-Source Model Checkerfor HDL Descriptions | Alexander Kamkin, Mikhail Lebedev and Sergey Smolov | | | | | |
| Retrascope: Open-Source Model Checkerfor HDL Descriptions | Alexander Kamkin, Mikhail Lebedev, and Sergey Smolov | | | | | |
| Reusable Processor Verification Methodology Based on UVM | Mustafa Khairallah and Maged Ghoneima | | | | | |
| Reusable Processor Verification Methodology Based on UVM | Mustafa Khairallah and Maged Ghoneima | | | | | |
| Reusable Verification Environment for a RISC-V Vector Accelerator | R. Ignacio Genovese, Josue Quiroga, Ivan Diaz, Henrique Yano, Asif Ali, Nehir Sonmez, Oscar Palomar, Victor Jimenez, Mario Rodriguez, Marc Dominguez | | | | | |
| Reusable Verification Environment for a RISC-V Vector Accelerator | Josue Quiroga, Roberto Ignacio Genovese, Ivan Diaz, Henrique Yano, Asif Ali, Nehir Sonmez, Oscar Palomar, Victor Jimenez, Mario Rodriguez, Marc Dominguez | | | | | |
| Reuse doesn’t come for free – learnings from a UVM deployment | Sumeet Gulati, Srinivasan Venkataramanan, Ketki Gosavi, Saumya Anvekar, and Azhar Ahammad | | | | | |
| Reuse doesn’t come for free – learnings from a UVM deployment | Sumeet Gulati, Srinivasan Venkataramanan, Azhar Ahammad, Ketki Gosavi, and Saumya Anvekar | | | | | |
| Reuse of System-Level Verification Components within Chip-Level UVM Environments | Diego Alagna, Marzia Annovazzi, Alessandro Cannone, Marcello Raimondi, Simone Saracino, Mukesh Chugh, Marc Erickson, Cristian Macario, Giuseppe Ridinò | | Paper | | | paper |
| Reverse Hypervisor – Hypervisor as fast SoC simulator. | François-Frédéric Ozog & Mark Burton | | | | | |
| Reverse Hypervisor Hypervisor for fast SoC Simulation | François-Frédéric Ozog & Shokubai Mark Burton | | | | | |
| Revitalizing Automotive Safety Hard and Soft Error Approaches | Nael Qudsi and Ayman Mouallem | | | | | |
| Revolutionary Debug Techniques to Improve Verification Productivity | Nadav Chazan | | | | | |
| RISC-V Compliance & Verification Techniques Processor Cores and Custom Extensions | Simon Davidmann, Lee Moore, Richard Ho, Doug Letcher and Kevin McDermott | | | | | |
| RISC-V Integrity: A Guide for Developers and Integrators | Nicolae Tusinschi | | | | | |
| RTL2RTL Formal Equivalence: Boosting the Design Confidence | M. Achutha KiranKumar V, Aarti Gupta, and Ss. Bindumadhava | | | | | |
| RTL2RTL Formal Equivalence: Boosting the Design Confidence | M. Achutha KiranKumar V, Aarti Gupta, and Ss. Bindumadhava | | | | | |
| Safety and Security Aware Pre-Silicon Hardware / Software Co-Development | Nikola Velinov and Frank Schirrmeister | | | | | |
| Safety-Verification Flow Sporting Gate-Level Accuracy and Near Virtual-Prototype Speed | B.-A. Tabacaru, M. Chaari, W. Ecker, T. Kruse, and C. Novello | | | | | |
| Safety-Verification Flow Sporting Gate-Level Accuracy and Near Virtual-Prototype Speed | Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, and Cristiano Novello | | Paper | | | paper |
| Same bits, different meaning – when direct execution based simulation becomes complicated | Evgeny Yulyugin | | | | | |
| SAWD: Systemverilog Assertions Waveform-based Development Tool | Ahmed Alsawi | | | | | |
| SAWD: Systemverilog Assertions Waveform-based Development tool | Ahmed Alsawi | | | | | |
| Scalable agile processor verification using SystemC UVM and friends | Eyck Jentzsch | | | | | |
| Self-Triggering Mechanism for Modeling a Low-Dropout Regulator with Load Capacitor | Mariska van der Struijk & Yi Wang | | | | | |
| Semi-formal Reformulation of Requirements for Formal Property Verification | Katharina Ceesay-Seitz, Hamza Boukabache and Daniel Perrin | | | | | |
| SIM-V Fast, Parallel RISC-V Simulation for Rapid Software Verification | Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers | | Paper | | | paper |
| SimpleLink™ MCU Platform: IP-XACT to UVM Register Model – Standardizing IP and SoC Register Verification | Jasminka Pasagic and Frank Donner | | | | | |
| SimpleLink™ MCU Platform: IP-XACT to UVM Register Model – Standardizing IP and SoC Register Verification “UVM is a perfect start” | Jasminka Pasagic and Frank Donner | | | | | |
| Simplifying UVM in SystemC | Thilo Vörtler, Thomas Klotz, Karsten Einwich, and Felix Assma | | | | | |
| Simplifying UVM in SystemC | Thilo Vörtler, Thomas Klotz, Karsten Einwich, and Felix Assma | | | | | |
| SimPy for Chips | Hachem Tassine, Daniel Wilkinson, Graham Cunnigham, Iason Myttas | | | | | |
| Simulation and Debug of Mixed Signal Virtual Platforms for Hardware-Software co-development | Vincent Motel, Alexandre Roybier, and Serge Imbert | | | | | |
| Simulation and Debug of Mixed Signal Virtual Platforms for Hardware-Software co-development | Vincent Motel, Alexandre Roybier, and Serge Imbert | | | | | |
| Single Source System to Register-Transfer Level Design Methodology Using High-Level Synthesis | Petri Solanti and Thomas Arndt | | Paper | | | paper |
| Single Source System to Register-Transfer Level Design Methodology Using High-Level Synthesis | Petri Solanti and Thomas Arndt | | | | | |
| Slicing Through the UVM’s Red TapeA Frustrated User’s Survival Guide | Jonathan Bromley © Accellera | | | | | |
| Slicing Through the UVM’s Red Tape: A Frustrated User’s Survival Guide | Jonathan Bromley | | | | | |
| Smart TSV (Through Silicon Via) Repair Automation in 3DIC Designs | Subramanian R, Naveen Srivastava, Jyoti Verma & Sekhar Dangudubiyyam | | Paper | | | paper |
| Smart TSV Repair Automation in 3DIC Designs | Subramanian R, Naveen Srivastava, Jyoti Verma & Sekhar Dangudubiyyam | | | | | |
| SOBEL FILTER: Software Implementation to RTL using High Level Synthesis | Bhavna Aggarwal, Umesh Sisodia and Snigdha Tyagi | | | | | |
| SOBEL FILTER: Software Implementation to RTL using High Level Synthesis | Bhavna Aggarwal, Umesh Sisodia, and Snigdha Tyagi | | | | | |
| Software Driven Test of FPGA PrototypeMethods & Use cases | Krzysztof Szczur and Radosław Nawrot | | | | | |
| Soumak – How rich descriptions enable early detection of hookup issues | Peter Birch, Thomas Brown | | | | | |
| Specification by Example for Hardware Design and Verification | Jussi Mäkelä | | | | | |
| Specification by Example for Hardware Design and Verification | Jussi Mäkelä | | | | | |
| State-Space “Switching” Model of DC-DC Converters in SystemVerilog | Elvis Shera | | | | | |
| State-Space “Switching” Model of DC-DC Converters in SystemVerilog. | Elvis Shera | | | | | |
| Static Analysis of SystemC/SystemC-AMS System and Architectural Level Models | Karsten Einwich and Thilo Vörtler | | | | | |
| Static Analysis of SystemC/SystemC-AMS System and Architectural Level Models | Karsten Einwich and Thilo Vörtler | | | | | |
| Static Checking for Correctness of Functional Coverage Models | Wael Mahmoud | | | | | |
| Static Checking for Correctness of Functional Coverage Models | Wael Mahmoud | | | | | |
| Static Sign-Off Best Practices Learnings and Experiences from Industry Use Cases | Vikas Sachdeva | | | | | |
| Static Signoff Best Practices – Learnings and experiences from industry use cases | Vikas Sachdeva | | | | | |
| Successive Refinement – An approach to decouple Front-End and Back-end Power Intent | Rohit Kumar Sinha | | | | | |
| SV VQC UDN for Modeling Switch-Capacitor-based Circuits | Yi Wang | | | | | |
| SysML based Architecture Definition and Platform Generation Flow | Ralph Görgen and Erwin de Kock | | | | | |
| SysML v2 – An overview with SysMD demonstration | Christoph Grimm, Axel Ratzke, Sebastian Post, Hagen Heermann, Johannes Koch | | | | | |
| System Verilog Assertions Verification | Ionuț Ciocîrlan and Andra Radu | | Presentation | | | presentation |
| System-Level Register Verification and Debug | Utkarsh Bhiogade, Kautilya Joshi, Puneet Goel | | | | | |
| System-Level Simulation of a SPAD-Based Time-of-Flight Sensor in SystemVerilog | Seungah Park, Hyeongseok Seo, Canxing Piao, Jaemin Park, Jaehyuk Choi, Jung-Hoon Chun | | | | | |
| System-Level Simulation of a SPAD-Based Time-of-Flight Sensor in SystemVerilog | Seungah Park, Hyeongseok Seo, Canxing Piao, Jaemin Park, Jaehyuk Choi & Jung-Hoon Chun | | | | | |
| SystemC extension for power specification, simulation and verification | Mikhail Moiseev, Ilya Klotchkov, and Kirill Gagarski | | | | | |
| SystemC extension for power specification,simulation and verification | Mikhail Moiseev, Ilya Klotchkov, Maxim Petrov, and Kirill Gagarski | | | | | |
| SystemC gaps encountered in Virtual Platform development | Eyck Jentzsch | | Paper | | | paper |
| SystemC-to-Verilog Compiler: a productivity-focused tool for hardware design in cycle-accurate SystemC | Mikhail Moiseev, Roman Popov and Ilya Klotchkov | | | | | |
| SystemC-to-Verilog Compiler: a productivity-focused tool for hardware design in cycle-accurate SystemC | Mikhail Moiseev, Roman Popov, and Ilya Klotchkov | | | | | |
| Taking Design Automation to the next level with User Experience Design | Jamie Lai, Bodo Hoppe | | Presentation | | | presentation |
| Temporal Assertions in SystemC | Mikhail Moiseev, Leonid Azarenkov and Ilya Klotchkov | | | | | |
| Temporal assertions in SystemC | Mikhail Moiseev, Leonid Azarenkov, and Ilya Klotchkov | | | | | |
| Temporal Decoupling – Are “Fast” and “Correct” Mutually Exclusive? | Jakob Engblom | | | | | |
| Temporal Decoupling – Are “Fast” and “Correct” Mutually Exclusive? | Jakob Engblom | | | | | |
| Test document link | Test | | | | | |
| Testbench Flexiblity as a Foundation for Success | Ana Sanz Carretero, Katherine Garden, Wei Wei Cheong | | | | | |
| Testbench Linting – open-source way | Srinivasan Venkataramanan, Deepa Palaniappan & Satinder Paul Singh | | | | | |
| The Application of Formal Technology on Fixed Point Arithmetic SystemC Designs | Sven Beyer, Dominik Straßer, and Dave Kelf | | | | | |
| The Application of Formal Technology on Fixed-Point Arithmetic SystemC Designs | Sven Beyer, Dominik Straßer, and David Kelf | | | | | |
| The Cost of Standard Verification Methodology Implementations | Abigail Williams, Svetlomir Hristozkov, Adam Hizzey | | | | | |
| The Cost Of Standard Verification Methodology Implementations | Adam Hizzey, Abigail Williams, Svetlomir Hristozkov | | | | | |
| The How To’s of Advanced Mixed-Signal Verification | John Brennan, Thomas Ziller, Kawe Fotouhi, and Ahmed Osman | | | | | |
| The How To’s of Metric Driven Verification to Maximize Productivity | Matt Graham and John Brennan | | | | | |
| The missing SystemC and TLM asynchronous features enabling inter-simulation synchronization. | Guillaume Delbergue, Mark Burton, Bertrand Le Gal and Christophe Jego | | | | | |
| The Open Source DRAM Simulator DRAMSys4.0 | Matthias Jung | | | | | |
| The Open-Source DRAM Simulator DRAMSys4.0 | Matthias Jung | | | | | |
| The Road to Robustness: Addressing LPDDR5X PHY Verification Challenges with DFE | Muhammed Asif, Gowdra Bomanna Chethan, Anil Deshpande & Somasunder Kattepura Sreenath | | | | | |
| The Three Body Problem | Peter Birch & Ben Marshall | | | | | |
| The Three Body Problem There’s more to building Silicon than EDA currently helps | Peter Birch & Ben Marshall | | | | | |
| The Top Most Common SystemVerilog Constrained Random Gotchas | Ahmed Yehia | | | | | |
| The Top Most Common SystemVerilog Constrained Random Gotchas | Ahmed Yehia | | | | | |
| The Universal Translator | David Cornfield | | | | | |
| The Universal Translator – A Fundamental UVM Component for Networking Protocols | David Cornfield | | | | | |
| The Universal Translator – A Fundamental UVM Component for Networking Protocols | David Cornfield | | | | | |
| Timing-Aware High Level Power Estimation of Industrial Interconnect Module | Amal Ben Ameur, Antonio Genov, François Verdier and Loic Leconte | | | | | |
| Timing-Aware high level power estimation of industrial interconnect module | Amal Ben Ameur, Antonio Genov, François Verdier, and Loic Leconte | | | | | |
| TLM based Virtual Platforms at Ericsson Challenges and Experiences | Ola Dahl, Michael Lebert, and Eric Frejd | | | | | |
| TLM Beyond Memory Mapped Busses | Bart Vanthournout and Mark Burton | | | | | |
| TLM modeling and simulation for NAND Flash and Solid State Drive systems | Tim Kogel and Victor Reyes | | Presentation | | | presentation |
| TLM-based Virtual Platforms at Ericsson: Challenges and Experiences | Ola Dahl, Michael Lebert, and Eric Frejd | | | | | |
| Towards 5G Internet of Things | Sabine Roessel | | | | | |
| Towards a Hybrid Verification Environment for Signal Processing SoCs | Jan Hahlbeck, Steffen Löbel & Chandana G P | | | | | |
| Towards a Hybrid Verification Environment for Signal Processing SoCs | Jan Hahlbeck & Steffen Löbel | | | | | |
| Towards a UVM-based Solution for Mixed-signal Verification | Alexander W. Rath, Sebastian Simon, Volkan Esen, and Wolfgang Ecker | | | | | |
| Towards a UVM-based Solution for Mixed-signal Verification | Alexander W. Rath, Sebastian Simon, Volkan Esen, and Wolfgang Ecker | | | | | |
| Transaction‐Based Testing with OSVVM and the OSVVM Model Library | Jim Lewis and Patrick Lehmann | | | | | |
| Tutorial 7 Tutorial on RISC-V Design and Verification | Kevin McDermott, Zdenek Prikryl, and Peter Shields | | | | | |
| TwIRTee design exploration with Capella and IP-XACT | Philippe Cuenot, Bassem Ouni, and Pierre Gaufillet | | | | | |
| TwIRTee: design exploration with Capella and IP-XACT | Bassem Ouni, Philippe Cuenot, and Pierre Gaufillet | | | | | |
| Types of Robustness Test According to DO-254 Guideline for Avionic Systems | Gözde Asena KILINÇ, Yavuz AKSU, Fatih BAYSAL | | | | | |
| Types of Robustness Test According to DO-254 Guideline for Avionic Systems | Gözde Asena KILINÇ, Yavuz AKSU, Fatih BAYSAL | | | | | |
| Types of Robustness Test According to DO-254 Guideline for Avionic Systems | Gözde Asena KILINÇ, Yavuz AKSU, Fatih BAYSAL | | | | | |
| Understanding the effectiveness of your system-level SoC stimulus suite | Robert Fredieu, Alan Hunter, and Andreas Meyer | | | | | |
| Understanding the effectiveness of your system-level SoC stimulus suite | Alan Hunter , Robert Fredieu, and Andreas Meyer | | | | | |
| Unified Architecture of L1 and L2 Cache with Low Power Extensions for Multi-Core UVM-based Library Package | Avnita Pal, Priyanka Gharat, Sastry Puranapanda & Darshan Sarode | | | | | |
| Unified Architecture of L1 L2 Cache with Low Power Extensions for MultiCore UVM-based Library Package | Avnita Pal, Priyanka Gharat, Puranapanda Sastry, & Darshan Sarode | | | | | |
| Unified Firmware Debug throughout SoC Development Lifecycle | Dimitri Ciaglia, Thomas Winkler, Jurica Kundrata | | | | | |
| Unified firmware debug throughout SoC development lifecycle | D. Ciaglia, T. Winkler, J. Kundrata | | | | | |
| Unified Functional Safety Verification Platform for ISO 26262 Compliant Automotive | Joerg Richter | | | | | |
| Unified Model/Hardware-in-the-Loop Methodology for Mixed-Signal System Design and Hardware Prototyping | Martin Barnasconi, Wil Kitzen, Thieu Lammers, Paul Ehrlich, Karsten Einwich | | | | | |
| Unified Test Writing Framework for Pre and Post Silicon Verification | Rahulkumar Patel, Pablo Cholbi, Sivasubrahmanya Evani and Raman K | | | | | |
| Unifying Mixed-Signal and Low-Power Verification | Adam Sherer, Andre Baguenier, Kawe Fotouhi, Abhijit Madhu Kumar, Qingyu Lin, Raj Mitra, and William Winkeler | | | | | |
| Universal Scripting Interface for SystemC | Rolf Meyer, Jan Wagner, Rainer Buchty, and Mladen Berekovic | | | | | |
| Universal Scripting Interface for SystemC | Rolf Meyer | | | | | |
| UPF Power Models: Empowering the power intent specification | Amit Srivastava and Harsh Chilwal | | | | | |
| UPF: How to avoid traps in a Hierarchical Implementation Low Power flow? | Frederic Saint-Preux, | | | | | |
| UPF: How to avoid traps in a Hierarchical Implementation Low Power flow? | Frederic Saint-Preux | | | | | |
| Use of CDC-jitter-modeling in clock-domaincrossing- circuits in RTL design phase | Jan Hayek, Jochen Neidhardt, and Robert Richter | | | | | |
| Use of CDC-Jitter-Modeling inClock-Domain-Crossing-Circuits in RTL Design Phase | Jan Hayek, JochenNeidhardt, and Robert Richter | | | | | |
| Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262 | Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Said Hamdioui, and Christian Sauer | | | | | |
| Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262 | Felipe A. da Silva, Ahmet C. Bagbaba, Said Hamdioui and Christian Sauer | | | | | |
| Use Stimulus Domain for Systematic Exploration of Time Dimension and Automatic Testcase Construct | Ning Chen and Martin Ruhwandl | | | | | |
| Using an Enhanced Verification Methodology for Back-to-Back RTL/TLM Simulation | Frank Poppen, Ralph Görgen, Kai Schulz, Andreas Mauderer, Jan-Hendrik Oetjens, Robert Bosch, Joachim Gerlach, and Hochschule, Albstadt-Sigmaringen | | | | | |
| Using an Enhanced Verification Methodology for Back-to-Back RTL/TLM Simulation | Frank Poppen, Ralph Görgen, Kai Schulz, Andreas Mauderer, Jan-Hendrik Oetjens, Robert Bosch, Joachim Gerlach, and Hochschule Albstadt-Sigmaringen | | Paper | | | paper |
| Using Cadence and MathWorksTools Together for Mixed-Signal Design and Verification | Graham Reith and Andrew Beckett | | | | | |
| Using Constraints for SystemC AMS Design and Verification | Thilo Vörtler, Karsten Einwich, Muhammad Hassan, and Daniel Große | | | | | |
| Using Constraints for SystemC AMS Design and Verification | Thilo Vörtler, Karsten Einwich, Muhammad Hassan, and Daniel Große | | | | | |
| Using Dependency Injection Design Pattern in Power Aware Tests | Mehmet Tukel, Luca Sasselli, David Guthrie | | | | | |
| Using Formal to Prevent Deadlocks | Abdelouahab Ayari, Mark Eslinger and Joe Hupcey III | | | | | |
| Using High-level Synthesis and Emulation to Rapidly Develop AI Algorithms in Hardware | John Stickley and Petri Solanti | | | | | |
| Using HLS to improve Design-for-Verification of multi-pipeline designs with resource sharing | Sarmad Dahir, Nils Luetke-Steinhorst, Christian Sauer | | | | | |
| Using Mutation Coverage for Advanced Bug Hunting and Verification Signoff | Nicolae Tusinschi | | | | | |
| Using Open-Source EDA Tools in an Industrial Design Flow | Daniela Sánchez Lopera, Sven Wenzek, Wolfgang Ecker | | | | | |
| Using Open-Source EDA Tools in an Industrial Design Flow | Daniela Sánchez Lopera, Prajwal Kashyap, Nicolas Gerlin, Sven Wenzek, Wolfgang Ecker | | | | | |
| Using UVM-ML library to enable reuse of TLM2.0 models in UVM test benches | Sarmad Dahir, Hans-Martin Bluethgen, Rafael Zuralski, Nils Luetke-Steinhorst, and Christian Sauer | | | | | |
| Using UVM-ML library to enable reuse of TLM2.0 models in UVM test benches | Samah Dahir | | | | | |
| UVM & Emulation Architecting SystemVerilog UVM Testbenches for Simulation-Emulation Portability to Boost Block-to-System Verification Productivity – Tutorial | Hans van der Schoot and Ellie Burns-Brookens | | | | | |
| UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-up | Hans van der Schoot and Ahmed Yehia | | | | | |
| UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-up | Hans van der Schoot and Ahmed Yehia | | | | | |
| UVM Audit Tutorial Assessing UVM Testbenches to Expose Coding Errors & Improve Quality | Mark Litterick | | Presentation | | | presentation |
| UVM based Hardware/Software Co- Verification of a HW Coprocessor using Host Execution Techniques | François Cerisier, Christian Rivier, Andrea Battistella, and Arnaud Grasset | | | | | |
| UVM based Hardware/Software Co-Verification of a HW Coprocessor using Host Execution Techniques | François Cerisier, Christian Rivier, Andrea Battistella and Arnaud Grasset | | | | | |
| UVM goesUniversal -IntroducingUVM in SystemC | Stephan Schulz, Thilo Vörtler, and Martin Barnasconi | | | | | |
| UVM hardware assisted acceleration with FPGA co-emulation | Alex Grove | | | | | |
| UVM Made Language Agnostic – Introducing UVM For SystemC Application of UVM-SystemC | Akhila M | | | | | |
| UVM Made Language Agnostic: Introducing UVM For SystemC | Akhila M | | | | | |
| UVM mixed signal extensionsSharing Best Practice and Standardization Ideas | Joen Westendorp, Sebastian Simon, and Joachim Geishauser | | | | | |
| UVM Rapid Adoption: A Practical Subset of UVM | Stuart Sutherland and Tom Fitzpatrick | | | | | |
| UVM Ready: Transitioning Mixed-Signal Verification Environments to Universal Verification Methodology | Arthur Freitas, Régis Santonja | | | | | |
| UVM Ready: Transitioning Mixed-Signal Verification Environments to Universal Verification Methodology | Arthur Freitas, Régis Santonja | | | | | |
| UVM Register Map Dynamic Configuration | Matteo Barbati and Alberto Allara | | | | | |
| UVM Register Map Dynamic Configuration | Matteo Barbati and Alberto Allara | | | | | |
| UVM SystemC Functional coverage & constrained randomization | Stephan Gerth, Dragos Dospinescu, Muhammad Hassan, Thilo Vörtler and Manuel Soto | | Presentation | | | presentation |
| uvm_mem – challenges of using UVM infrastructure in a hierarchical verification | Joachim Geishauser, Aditya Chopra, Stephan Ruettiger, Luca Rossi, Sanjay Kakasaniya, L.N. Zhang | | | | | |
| uvm_mem – challenges of using UVM infrastructure in a hierarchical verification | Joachim Geishauser, Aditya Chopra, Stephan Ruettiger, Luca Rossi, Sanjay Kakasaniya, L.N. Zhang | | | | | |
| UVM-Light A Subset of UVM for Rapid Adoption | Stuart Sutherland and Tom Fitzpatrick | | | | | |
| UVM-Multi-Language Hands-On | Thorsten Dworzak and Angel Hidalga | | | | | |
| UVM-Multi-Language Hands-On Integrating a System-C model into a SV-UVM testbench | Thorsten Dworzak and Angel Hidalga | | | | | |
| UVM-SystemC Applications in the real world | Stephan Schulz, Thilo Vörtler, and Martin Barnasconi | | | | | |
| UVM-SystemC based hardware in the loop simulations for accelerated Co-Verification | Paul Ehrlich, Thang Nguyen, and Thilo Vörtler | | | | | |
| UVM-SystemC based hardware in the loop simulations for accelerated Co-Verification | Paul Ehrlich, Thang Nguyen, and Thilo Vörtler | | | | | |
| UVM-SystemC: Migrating complex verification environments | Stephan Gerth and Akhila Madhukumar | | | | | |
| UX Design & EDA – Enable Collaboration on Functional Coverage using Opens Source Software | Bodo Hoppe, Jamie Lai | | Paper | | | paper |
| Validation of Timing Constraints on RTL Reducing Risk and Effort on Gate-Level | Peter Limmer, Dirk Moeller, Marcus Mueller and Clemens Roettgermann | | | | | |
| Validation of Timing Constraints on RTL Reducing Risk and Effort on Gate-Level | Peter Limmer, Dirk Moeller, Marcus Mueller, and Clemens Roettgermann | | Paper | | | paper |
| Variation-Aware Performance Verification of Analog Mixed-Signal Systems | Carna Zivkovic; Jan Roedel; Neha Chavan; Frank Rethmeier; Christoph Grimm | | | | | |
| Verification 2.0 – Multi Engine, Multi-Run – AI-Driven Verification | Matt Graham | | | | | |
| Verification 2.0 – Multi Engine, Multi-Run AI-Driven Verification | Matt Graham | | | | | |
| Verification Challenges For Deep Color Mode In HDMI | Snigdha Arora and Apoorva Mathur | | | | | |
| Verification Challenges for Deep Color Mode in HDMI | Snigdha Arora and Apoorva Mathur | | | | | |
| Verification IP for Complex Analog and Mixed-Signal Behavior | Thilo Vörtler and Karsten Einwich | | | | | |
| Verification IP for Complex Analog and Mixed-Signal Behavior | Thilo Vörtler and Karsten Einwich | | Paper | | | paper |
| Verification of a Multi-language Components A case Study: Specman E Env with SV UVM VIP | Eran Lahav | | Poster, Presentation | | | poster presentation |
| Verification of a Multi-language Components A Case Study: Specman E Environment with SystemVerilog UVM | Eran Lahav | | Paper | | | paper |
| Verification of an AXI cache controller using multi-thread approach based on OOP design pattern | Francesco Rua’ & Péter Sági | | | | | |
| Verification of an AXI cache controller with a multi-thread approach based on OOP design patterns | Francesco Rua’ & Péter Sági | | | | | |
| Verification of High-Speed Links through IBIS-AMI Models | Ganesh Rathinavel | | Presentation | | | presentation |
| Verification of High-Speed Links through IBIS-AMI Models | Ganesh Rathinavel | | | | | |
| Verification of Inferencing Algorithm Accelerators | Russell Klein, Petri Solanti | | | | | |
| Verification of Inferencing Algorithm Accelerators | Russell Klein, Petri Solanti | | | | | |
| Verification of Virtual Platform Models – What do we Mean with Good Enough? | Jakob Engblom, Ola Dahl | | Paper | | | paper |
| Verification of Virtual Platform Models – What do we Mean with Good Enough? | Ola Dahl, Jakob Engblom | | Presentation | | | presentation |
| Verifying Functional, Safety and Security Requirements (for Standards Compliance) | Mike Bartley | | | | | |
| Verilator + UVM-SystemC: a match made in heaven | Luca Sasselli | | Paper | | | paper |
| Versatile UVM Scoreboarding | Jacob Andersen, Peter Jensen, and Kevin Steffensen | | | | | |
| Versatile UVM Scoreboarding | Jacob Andersen, Peter Jensen, and Kevin Steffensen | | | | | |
| Vertical Reuse of functional verification from subsystem to SoC level (with seamless SoC emulation) | Pranav Kumar, Digvijaya Pratap SINGH, and Ankur Jain | | | | | |
| Virtual ECUs with QEMU and SystemC TLM-2.0 | Lukas Jünger, Jan Henrik Weinstock, Munish Jassi, Megumi Yoshinaga, Hitoshi Hamio, Koichi Sato | | | | | |
| Virtual ECUs with QEMU and SystemC TLM-2.0 | Lukas Jünger, Jan Henrik Weinstock, Munish Jassi, Megumi Yoshinaga, Hitoshi Hamio & Koichi Sato | | | | | |
| Virtual Platforms for Automotive: Use Cases, Benefits and Challenges | Angela Kramer and Martin Vaupel | | | | | |
| Virtual Platforms for complex IP within system context | Rocco Jonack | | Presentation | | | presentation |
| Virtual Prototypes and PlatformsA Primer | Eyck Jentzsch, Rocco Jonack, and Josef Eckmüller | | | | | |
| Virtual Prototyping in SpaceFibre System-on-Chip Design | Ilya Korobkov | | | | | |
| Virtual Prototyping in SpaceFibre System-on-Chip Design System-level design | Elena Suvorova | | | | | |
| Virtual Prototyping of Power Converter Systems based on AURIX™ using SystemC AMS | Radovan Vuletic, Dineshkumar Selvaraj, Thomas Arndt | | | | | |
| Virtual Prototyping using SystemC and TLM-2.0 | John Aynsley | | | | | |
| Virtual Testing of Overtemperature Protection Algorithms in Automotive Smart Fuses | Thomas Markwirth, Gabriel Pachiana, Christoph Sohrmann, Mehdi Meddeb, Gunnar Bublitz & Heinz Wagensonner | | | | | |
| Virtual testing of overtemperature protection algorithms in automotive smart fuses | Thomas Markwirth, Gabriel Pachiana, Christoph Sohrmann, Mehdi Meddeb, Gunnar Bublitz & Heinz Wagensonner | | | | | |
| VP Performance Optimization – How to analyze and optimize the speed of SystemC TLM models? | Rocco Jonack and Juan Lara Ambel | | | | | |
| VP Performance Optimization – How to analyze and optimize the speed of SystemC TLM models? | Rocco Jonack and Juan Lara Ambel | | | | | |
| VPSim: Virtual Prototyping Simulator with best accuracy & execution time trade-off for High Performance Computing systems evaluation and benchmarking | Mohamed Benazouz, Ayoub Mouhagir & Lilia Zaourar | | | | | |
| Wave Digital Filter Modeling for Complex Automotive Sensor Load Case Verification | Andrei-Daniel Basa, Thang Nguyen, and Dirk Hammerschmidt | | | | | |
| Wave Digital Filter Modeling for Complex Automotive Sensor Load Case Verification | A. Basa, T. Nguyen, and D. Hammerschmidt | | | | | |
| Web Template Mechanisms in SOC Verification | Alberto Allara, Via Tolomeo, Rinaldo Franco, and Via Remo | | | | | |
| Web Template Mechanisms in SOC Verification | Rinaldo Franco and Alberto Allara | | | | | |
| What is needed on top of TLM-2 for bigger Systems? | Jerome Cornet and Martin Schnieringer | | Presentation | | | presentation |
| What is new in IP-XACT IEEE Std. 1685-2022? | Erwin de Kock, Jean-Michel Fernandez, Devender Khari | | | | | |
| What is new in IP-XACT Std. IEEE 1685-2022? | Erwin de Kock, Jean-Michel Fernandez, Devender Khari | | | | | |
| What is next for SystemC Synthesizable Subset? | Peter Frey | | | | | |
| Who takes the driver seat for ISO 26262 and DO 254 verification? | Avidan Efody | | | | | |
| Who takes the driver seat for ISO 26262 and DO 254 verification? | Avidan Efody | | | | | |
| YAMMYet Another Memory Manager | Andrei Vintila and Ionut Tolea | | | | | |
| Yet Another Memory Manager (YAMM) | Ionut Tolea and Andrei Vintila | | | | | |
