DVCon: Europe

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1,2,3,…8 simple steps towards a single digital signal processing testbench supporting heterogeneous interfaces and datatypesNico Lugil2016Presentation2016presentation
1,2,3,…8 simple steps towards a single digital signal processing testbench supporting heterogeneous interfaces and datatypesNico Lugil2016Paper2016paper
5G – Chances and Challenges from Test & Measurement PerspectiveMeik Kottkamp2017Presentation2017presentation
5G / NR Explained From 3GPP 5G Standard Fundamentals To 5G Enabled VerticalsMichael Faerber and Kilian Roth2019Presentation2019presentation
5G for people and things Spectrum Opportunities and Challenges of 5G2017Presentation2017presentation
A comparison of methodologies to simulate mixed-signal ICSimone Fontanesi, Karsten Einwich, Paul Ehrlich, Gaetano Formato, Andrea Possemato2021Paper2021paper
A Comprehensive Verification Platform for RISC-V based ProcessorsEmre Karabulut, Berk Kisinbay, Abdullah Yildiz, and Rifat Demircioglu 2020Presentation2020presentation
A Comprehensive Verification Platform for RISC-V based ProcessorsEmre Karabulut, Berk Kisinbay, Abdullah Yildiz and Rifat Demircioglu2020Paper2020paper
A concept for expanding a UVM testbench to the analog-centric toplevelFelix Assmann, Axel Strobel and Hans Zander2015Paper2015paper
A concept for expanding a UVM testbenchto the analog-centric toplevelFelix Assmann, Axel Strobel and Hans Zander2015Poster2015poster
A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog-AMSMike Bartley, Jeganath Gandhi R2014Paper2014paper
A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog-AMSMike Bartley and Jeganath Gandhi R2014Paper2014paper
A Generic Approach to Handling Sideband SignalsMarkus Brosch and Salman Tanvir2019Presentation2019presentation
A Guide To Using Continuous Integration Within The Verification EnvironmentJason Sprott, André Winkelmann, and Gordon McGregor2014Paper2014paper
A Guide To Using Continuous Integration Within The Verification EnvironmentAndré Winkelmann, Jason Sprott, and Gordon McGregor2014Poster2014poster
A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGAAntonis Papagrigoriou, Miltos D. Grammatikakis and Voula Piperaki2018Presentation2018presentation
A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGA*Antonis Papagrigoriou, Antonis Papagrigoriou and Voula Piperaki2018Paper2018paper
A Meta-Model-Based Approach for Semantic Fault Modeling on Multiple Abstraction LevelsMichael Schwarz and Moomen Chaari, Bogdan-Andrei Tabacaru2015Paper2015paper
A Meta-Model-Based Approach for Semantic Fault Modeling on Multiple Abstraction LevelsM. Schwarz M. Chaari, B.-A. Tabacaru, and W. Ecker2015Presentation2015presentation
A Meta-Modeling-Based Approach for Automatic Generation of Fault-Injection ProcessesBogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, and Thomas Kruse2014Paper2014paper
A Meta-Modeling-Based Approach for Automatic Generation of Fault-Injection ProcessesB.-A. Tabacaru, M. Chaari, W. Ecker, and T. Kruse2014Presentation2014presentation
A Methodology for Evaluating SI Artefacts in DDR4-3DS PHY using Channel ModellingAditya S Kumar, Gowdra Bomanna Chethan, Shivani Maurya, Anil Deshpande, Somasunder Kattepura Sreenath2021Paper2021paper
A Methodology to Verify Functionality, Security, and Trust for RISC-V CoresW. W. Chen, N. Tusinschi, and T. L. Anderson2020Presentation2020presentation
A Methodology to Verify Functionality, Security, and Trust for RISC-V CoresW. W. Chen, N. Tusinschi and T. L. Anderson2020Paper2020paper
A Metric-driven Methodology For Firmware Verification In Simulation/Emulation EnvironmentsGoran Savić2016Paper2016paper
A Mixed Signal System Design Methodology in SystemC AMS for Automotive Audio Power AmplifiersSkule Pramm, Joen Westendorp, and Quino Sandifort2019Paper2019paper
A Mutually-Exclusive Deployment of Formal and Simulation Techniques Using Proof-Core AnalysisKeerthikumara Devarajegowda, Jeroen Vliegen, Goran Petrovity, and Kawe Fotouhi2017Presentation2017presentation
A Mutually-Exclusive Deployment of Formal and Simulation Techniques Using Proof-Core AnalysisKeerthikumara Devarajegowda, Jeroen Vliegen, Goran Petrovity, and Kawe Fotouhi2017Paper2017paper
A New Approach to Low-Power Verification: Low Power AppsMadhur Bhargava and Awashesh Kumar2018Paper2018paper
A Novel Approach to Functional Test Development and Execution using High-Speed IOMarcus Schulze Westenhorst, Jörg Simon, Markus Bücker, Klaus Dieter Hilliges, Michael Braun2021Paper2021paper
A Novel Approach To In-System SRAM Repair Verification in Embedded SoC to Bridge Gap between Test and Functional ModeHarshal Kothari, Eldin Ben Jacob, Ajay Vamshi Krishna, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath2021Paper2021paper
A Novel Approach to Reuse Firmware for Verification of Controller based Sub-Systems using PSSVishnu Ramadas, Simranjit Singh, Ashwani Aggarwal, Woojoo Space Kim , Seonil Brian Choi2021Paper2021paper
A Novel Performance Evaluation Methodology using Virtual Prototyping and EmulationWoojooSpace Kim2019Presentation2019presentation
A Novel Performance Evaluation Methodology using Virtual Prototyping and EmulationWoojoo Space Kim2018Presentation2018presentation
A Novel Processor Verification Methodology based on UVMAbhineet Bhojak, Tejbal Prasad, and Stephan Herrmann2015Paper2015paper
A Pragmatic Approach to Metastability-Aware SimulationJoseph Bulone, Roger Sabbagh2014Paper2014paper
A Pragmatic Approach to Metastability-Aware SimulationJoseph Bulone, Roger Sabbagh2014Presentation2014presentation
A real world application of IP-XACT for IP packaging Bridging the usability gapPhilip Todd2014Paper2014paper
A real world application of IP-XACT for IP packaging Bridging the usability gapPhilip Todd2014Presentation2014presentation
A Step Towards Zero Silicon Bugs Using Assertion Based Assumption ValidationRohit Kumar Sinha and Babu Christie2020Paper2020paper
A Step towards Zero Silicon Bugs: SVA Protocol Based Assumption ValidationRohit Kumar Sinha and Babu Christie2020Poster, Presentation2020poster presentation
A Structured Approach to verify Ties, Unconnected Signals and ParametersSaurabh Singh, Peter Limmer, and Thomas Luedeke2016Presentation2016presentation
A Structured Approach to verify Ties, Unconnected Signals and ParametersSaurabh Singh, Peter Limmer, and Thomas Luedeke2016Paper2016paper
A SystemC-based UVM verification infrastructureMike Bartley and Harshavardhan Narla2015Paper2015paper
A SystemC-based UVM verification infrastructureMike Bartley and Harshavardhan Narla2015Poster2015poster
A UVM Based Methodology for Processor VerificationAbhineet Bhojak, Stephan Herrmann, and TejbalPrasad2015Presentation2015presentation
Accelerated Coverage Closure by Utilizing Local Structure in the RTL CodeRhys Buggy, Gokce Sarar, Guillaume Shippee, Han Nuou, Vishal Karna, Tushit Jain2021Paper2021paper
Accelerated SOC verification Using UVM Methodology for a Mix-signal Low Power DesignGiuseppe Scata, Ashwini Padoor, Vladimir Milosevic2014Paper2014paper
Accelerated SOC Verification Using UVM Methodology for a Mixed-Signal Low Power DesignGiuseppe Scata, Ashwini Padoor, Vladimir Milosevic2014Presentation2014presentation
Accelerating and Improving FPGA Design Reviews Using Analysis ToolsAnna Tseng, Kurt Takara and Abdelouahab Ayari2020Paper2020paper
Accelerating and Improving FPGA Design Reviews Using Analysis ToolsAbdelouahab Ayari, Anna Tseng, and Kurt Takara2020Presentation2020presentation
Accelerating Automotive Ethernet validation by leveraging Synopsys Virtualizer with TraceCompassAshish Gandhi, Praveen Kumar Kondugari and Sam Tennent2020Paper2020paper
Accelerating Automotive Ethernet validation by leveraging Synopsys Virtualizer with TraceCompassAshish Gandhi, Praveen Kumar Kondugari, and Sam Tennent2020Presentation2020presentation
Accelerating Functional Verification Coverage Data Manipulation Using Map ReduceEman El Mandouh, A. Gamal, A. Khaled, B. Amr G. Wassal, and Elsayed Hemayed2017Presentation2017presentation
Accelerating Functional Verification Coverage Data Manipulation Using Map ReduceEman El Mandouh, A. Gamal, A. Khaled, T. Ibrahim, Amr G. Wassal, Elsayed Hemayed2017Paper2017paper
Accelerating RTL Simulation TechniquesLior Grinzaig2015Paper2015paper
Accelerating RTL Simulation TechniquesLior Grinzaig2015Presentation2015presentation
Acceleration of product and test environment development using SystemC-TLMFlorian Barrau, Alexandre Piccini, Alexandre Nabais Moreno, Mark Burton, Luc Michel, Clement Descha2018Paper2018paper
Acceleration of product and test environment using SystemC TLMFlorian Barrau, Alexandre Piccini, Alexandre Nabais Mark Burton, Luc Michel, and Clement Deschamps2018Presentation2018presentation
Accellera Systems InitiativeSystemC Standards UpdateMartin Barnasconi, Philipp A. Hartmann, and Stephan Schulz 2015Presentation2015presentation
Accellera Systems InitiativeSystemC Standards UpdateMartin Barnasconi, Philipp A. Hartmann, Trevor Wieman2014Presentation2014presentation
Achieve Complete SoC Memory Map Verification Through Efficient Combination of Formal and Simulation TechniquesClemens Roettgermann, Peter Limmer, and Michael Rohleder2015Paper2015paper
Achieve Complete SoC Memory Map Verification through Efficient Combination of Formal and Simulation TechniquesClemens Roettgermann, Peter Limmer, and Michael Rohleder2015Presentation2015presentation
Achieving Faster Code Coverage Closure using High-Level SynthesisSurendhar Thudukuchi Chandrapandiyan, Preetham Lakshmikanthan, Ashwani Aggarwal, Youngchan Lee, Youngsik Kim, Seonil Brian Choi2021Paper2021paper
Achieving Faster Reset Verification Closure with Intelligent Reset Domain Crossings DetectionMilanpreet Kaur and Sulabh Kumar Khare2020Paper2020paper
Achieving Faster Reset Verification Closure with Intelligent Reset Domain Crossings DetectionMilanpreet Kaur and Sulabh Kumar Khare2020Poster, Presentation2020poster presentation
Achieving Portable Stimulus with Graph-Based Verification – Tutorial2014Presentation2014presentation
Addressing Asynchronous FIFO Verification ChallengeAnchal Gupta, Ashish Hari and Sulabh Kumar Khare2019Presentation2019presentation
Addressing Asynchronous FIFO Verification ChallengeAnchal Gupta, Ashish Hari, Sulabh Kumar Khare2018Presentation2018presentation
Addressing Renewed Gate Level Simulation Needs for 10nm-28nm and BelowGagandeep Singh2016Paper2016paper
Addressing the Complex Challenges in Low-Power Design and VerificationMadhur Bhargava, Durgesh Prasad, Jitesh Bansal, and Gabriel Chidolue2016Presentation2016presentation
Addressing the Complex Challenges in Low-Power Design and VerificationMadhur Bhargava, Durgesh Prasad, and Jitesh Bansal2016Paper2016paper
Adopting UVM for safety Verification requirementsSrinivasan Venkatarmanan, Hema Kiran, and Satinder Paul Singh2017Paper2017paper
Adopting UVM for safety Verification requirementsSrinivasan Venkatarmanan, Hemakiran Kolli, Gurubasappa Kinagi, and Satinder Paul Singh2017Presentation2017presentation
Advance Approach for Formal Verification of Configurable Pulse Width Modulation ControllerSumit K. Kulshreshtha, Raghavendra J N2021Paper2021paper
Advance your Design and Verification Flow Using IP XACTEdwin Dankert, Maximilian Albrecht and Vincent Thibaut2019Presentation2019presentation
Advanced Techniques to Accomplish Power Aware CDC VerificationRohit K Sinha, Ashish Hari and Sulabh Kumar Khare2018Paper2018paper
Advanced UVM in the real world ‐ TutorialMark Litterick, Jason Sprott, Jonathan Bromley, and Vanessa Cooper2014Presentation2014presentation
Advanced UVM Tutorial Taking Reuse to the Next LevelMark Litterick, Jason Sprott, and Jonathan Bromley2015Presentation2015presentation
Advanced, High Throughput Debug From Design to SiliconGordon Allan & Michael Horn2015Presentation2015presentation
Advancing the SystemC EcosystemPhilipp A Hartmann, Jerome Cornet, Martin Scnierginger, and Frederic Doucet2017Presentation2017presentation
Advancing traceability and consistency in Verification and ValidationWalter Tibboel and Martin Barnasconi2014Paper2014paper
Advancing traceability and consistency in Verification and ValidationWalter Tibboel and Martin Barnasconi2014Poster2014poster
Agile and dynamic functional coverage using SQL on the cloudFilip Dojcinovic and Mihailo Ivanovic2019Presentation2019presentation
Agile and dynamic functional coverage using SQL on the cloudFilip Dojcinovic and Mihailo Ivanovic2018Presentation2018presentation
Agnostic UVM-XX Testbench GenerationJacob Andersen, Stephan Gerth, and Filippo Dughetti2016Presentation2016presentation
Agnostic UVM-XX Testbench Generation Replace XX (almost) as you see fit!Jacob Andersen, Stephan Gerth, and Filippo Dughetti2016Paper2016paper
Algorithm Verification with Open Source and System VerilogAndra Socianu and Daniel Ciupitu2014Presentation2014presentation
AMS Verification in a UVM EnvironmentSilvia Strähle2016Presentation2016presentation
AMS Verification in a UVM EnvironmentSilvia Strähle2016Paper2016paper
An Analysis of Stimulus Techniques for Efficient Functional Coverage ClosureCaglayan Yalein, Aileen McCabe2021Paper2021paper
An Automated Formal Verification Flow for Safety RegistersHolger Busch2015Paper2015paper
An Automated Formal Verification Flow for Safety RegistersHolger Busch2015Presentation2015presentation
An Automated Pre-silicon IP Trustworthiness Assessment for Hardware AssuranceJohn Hallman, David Landoll, Sergio Marchese, Sven Beyer, Garrett Chan, Salam Zantout and Vikram Rao2020Paper2020paper
An Automated Pre-silicon IP Trustworthiness Assessment for Hardware AssuranceJ. Hallman, D. Landoll, S. Marchese, S. Beyer, G. Chan, S. Zantout, and V. Rao2020Poster, Presentation2020poster presentation
An Easy VE/DUV Integration ApproachUwe Simm2015Paper2015paper
An Easy VE/DUV Integration ApproachUwe Simm2015Presentation2015presentation
An efficient requirements-driven and scenario-driven verification flowWalter Tibboel, Heino van Orsouw, and Shuang Han2017Paper2017paper
An efficient requirements-driven and scenario-driven verification flowHeino van Orsouw 2017Presentation2017presentation
An Efficient Verification Framework for Audio/Video Interface ProtocolsNoha Shaarawy, Mustafa Khairallah, Khaled Khalifa, Hany Salah, Amr Salah and Maged Ghoneima2015Paper2015paper
An Introduction to the Accellera Portable Stimulus StandardSharon Rosenberg, Tom Fitzpatrick, David Kelf, Karthick Gururaj, and Piyush Sukhija2017Presentation2017presentation
An Introduction to using Event-B for Cyber-Physical System Specification and DesignJohn Colley and Michael Butler2014Presentation2014presentation
An Open and Fast Virtual Platform for TriCore™-based SoCs Using QEMUBastian Koppelmann, Bernd Messidat, Markus Becker, and Christoph Kuznik2014Paper2014paper
An Open and Fast Virtual Platform for TriCore™-based SoCs Using QEMUBastian Koppelmann2014Poster2014poster
An open and flexible SystemC to VHDL workflow for rapid prototypingBastian Farkas2016Presentation2016presentation
An open and flexible SystemC to VHDL workflow for rapid prototypingBastian Farkas, Syed Abbas Ali Shah, Jan Wagner, Rolf Meyer, Rainer Buchty, and Mladen Berekovic2016Paper2016paper
Analog Modelling to Suit Emulation for Hardware-Software Co-VerificationSaranya Das2020Paper2020paper
Analog Modelling to Suit Emulation for Hardware-Software Co-VerificationSaranya Das2020Poster, Presentation2020poster presentation
Applying Design Patterns to accelerate development of reusable, configurable and portable UVCs.2015Presentation2015presentation
Applying Design Patterns to Maximize Verification Reuse at Block, Subsystem and System on Chip LevelPaul Kaunds, Revati Bothe and Jesvin Johnson2019Presentation2019presentation
Attack Your SoCPowerChallenges with Virtual PrototypingStefan Thiel and Gunnar Braun2014Presentation2014presentation
Automate and Accelerate RISC-V Verification by Compositional Formal MethodsYean-Ru Chen, Cheng-Ting Kao, Yi-Chun Kao, Tien-Yin Cheng, Chun-Sheng Ke and Chia-Hao Hsu2019Presentation2019presentation
Automate and Accelerate RISC-V Verification by Compositional Formal MethodsYean-Ru Chen, Cheng-Ting Kao, Yi-Chun Kao, Tien-Yin Cheng, Chun-Sheng Ke and Chia-HaoHsu2018Presentation2018presentation
Automated Configuration of Verification Environments using Specman Macros DVcon Europe 2018 – Paper number 260-OH22Milos Mirosavljevic, Ron Sela, Dejan Janjic and Efrat Shneydor2018Paper2018paper
Automated Configuration of Verification Environments using SpecmanMacrosMilos Mirosavljevic, Ron Sela, Dejan Janjic and Efrat Shneydor2018Presentation2018presentation
Automated SystemC Model Instantiation with modern C++ Features and sc_vectorRalph Görgen and Philipp A. Hartmann2015Paper2015paper
Automated SystemC Model Instantiation with modern C++ Features and sc_vectorRalph Görgen, Philipp A. Hartmann, and Wolfgang Nebel2015Presentation2015presentation
Automatic Diagram Creation for Design and TestbenchesPaul O’Keeffe, Jamie Beattie and Gian Lorenzo2020Paper2020paper
Automatic Diagram Creation for Design and TestbenchesPaul O’Keeffe, Jamie Beattie, and Gian Lorenzo2020Poster, Presentation2020poster presentation
Automatic Firmware Design for Application-specific Electronic Systems: Opportunities, Challenges and SolutionsDaniel Große, Joscha Benz, Vladimir Herdt, and Martin Dittrich2017Presentation2017presentation
Automatic Firmware Verification for Automotive ApplicationsTorsten Andre and Daniel Valtiner2017Paper2017paper
Automatic Firmware Verification for Automotive ApplicationsTorsten Andre and Daniel Valtiner2017Presentation2017presentation
Automatic Netlist Modifications required by Functional SafetyHarald Lüpken, Dirk Hönicke, and Michael Rohleder2014Paper2014paper
Automatic Netlist Modifications required by Functional SafetyHarald Lüpken, Dirk Hönicke, and Michael Rohleder2014Poster2014poster
Automatic Testbench Build to Reduce Cycle Time and Forster ReuseJoachim Geishauser and Alexander Schilling2017Paper2017paper
Automatic Testbench Build to Reduce Cycle Time and Foster ReuseJoachim Geishauser and Alexander Schilling2017Presentation2017presentation
Be a Sequence Pro to Avoid Bad Con SequencesMark Litterick2019Presentation2019presentation
Between the Dialog and the Algorithm or Innovative Technological Narratives Leveraging the Idea of Authenticity in a Human Being Visualizing log files enables intuitive comprehension of complex test scenariosAnna M. Ravitzki and Uri Feigin2017Paper2017paper
Bit density based pre characterization of RAM cells for area critical SOC designDilip Kumar Ajay (dajay@qti.qualcomm.com)2020Presentation2020presentation
Bit Density-Based Pre-Characterization of RAM Cells for Area Critical SOC DesignDilip Kumar Ajay2020Paper2020paper
Boosting Debug Productivity Practical Applications of Debug Innovations in a UVM WorldJoerg Richter2017Presentation2017presentation
Boosting Mixed-Signal Design Productivity with FPGA-Based Methods Throughout the Chip Design ProcessGabriel Rutsch, Simone Fontanesi, Steven G. Herbst, Steven Tan Hee Yeng, Andrea Possemato, Gaetano Formato, Mark Horowitz, and Wolfgang Ecker2020Paper2020paper
Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven GenerationHoang M. Le and Rolf Drechsler2015Paper2015paper
Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven GenerationHoang M. Le and Rolf Drechsler2015Presentation2015presentation
Bringing Reset Domains and Power Domains Together – Set/Reset Flops Augmenting Complexities in Power-Aware RDC Verification.Manish Bhati, Manjunatha Srinivas, Abdul Moyeen, Inayat Ali2021Paper2021paper
Build Reliable and Efficient Reset Networks with a Comprehensive Reset Domain Crossing Verification SolutionWanggen Shi, Yuxin You, and Kurt Takara2020Paper2020paper
Build Reliable and Efficient Reset Networks with a Comprehensive Reset Domain Crossing Verification SolutionWanggen Shi, Yuxin You, and Kurt Takara2020Presentation2020presentation
Building a coherent ESL design and verification eco-system with SystemC, TLM, UVM-SystemC, and CCIMartin Barnasconi2016Paper2016paper
Building Code Generators for Reuse – Demonstrated by a SystemC GeneratorSaad Siddiqui and Ulrich Nageldinger2017Paper2017paper
Building Code Generators for Reuse – Demonstrated by a SystemC GeneratorUlrich Nageldinger and Saad Siddiqui2017Presentation2017presentation
Building Smart SoCs Using Virtual Prototyping for the Design and SoC Integration of Deep Learning AcceleratorsHolger Keding2019Presentation2019presentation
Cadence vManager Platform and Virtuoso ADE Verifier Leading-edge technologies provide methodology for mixedsignal verification closureKawe Fotouhi and Walter Hartong2019Presentation2019presentation
Case Study of Verification Planning to Coverage Closure @Block, Subsystem and System on Chip LevelPaul Kaunds, Revati Bothe, and Jesvin Johnson2018Presentation2018presentation
Catching the low hanging fruits on intel® Graphics DesignsM, Achutha KiranKumar V, Aarti Gupta, Bindumadhava S S, Savitha Manojna, and Abhijith A Bharadwaj2016Paper2016paper
Centralized Regression Optimisation Toolkit (CROT) for expediting Regression Closure With Simulator Performance OptimisationHarshal Kothari, Pavan M, Ajay Vamshi Krishna, Eldin Ben Jacob, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath2021Paper2021paper
Challenges of VHDL X-propagation SimulationsKarthik Baddam and Piyush Sukhija2015Paper2015paper
Challenges of VHDL X-propagation SimulationsKarthik Baddam and Piyush Sukhija2015Presentation2015presentation
Characterizing RF Wireless Receivers Performance in UVM EnvironmentSalwa Elqassas, Salwa Elqassas and Mohammed T. Abdel-Hafe2018Paper2018paper
Chiplevel Analog Regressions in ProductionYi Wang2021Paper2021paper
Clock Controller Unit Design Metrics: Area, Power, Software Flexibility and Congestion Impacts at System LevelMichele Chilla and Leonardo Gobbi2020Paper2020paper
Closing the loop from requirements management to verification execution for automotive applicationsWalter Tibboel and Jan Vink2015Paper2015paper
Closing the loop from requirements management to verification execution for automotive applicationsWalter Tibboel and Jan Vink2015Presentation2015presentation
Clustering and Classification of UVM Test Failures Using Machine Learning TechniquesAndy Troung, Daniel Hellström, Harry Duque, and Lars Viklund2018Presentation2018presentation
Clustering and Classification of UVM Test Failures Using Machine Learning TechniquesAndy Truong, Daniel Hellström, Harry Duque, and Lars Viklund2018Paper2018paper
Combining Static and Dynamic Low Power Verification for the Power-Aware SoC Sign-offHimanshu Bhatt and Prashanth M2014Paper2014paper
Combining Static and Dynamic Low Power Verification for the Power-Aware SoC Sign-offHimanshu Bhatt, Prashanth M, and Adiel Khan2014Presentation2014presentation
Complete Formal Verification of a Family of Automotive DSPsRafal Baranowski and Marco Trunzer2016Presentation2016presentation
Complete Formal Verification of a Family of Automotive DSPsRafal Baranowski and Marco Trunzer2016Paper2016paper
Complex Low Power Verification Challenges in NextGen SoCs : Taming the Beast!Abhinav Nawal, Gaurav Jain, and Joachim Geishauser2014Presentation2014presentation
Complex Low Power Verification Challenges in NextGen SoCs: Taming the Beast!Abhinav Nawal and Gaurav Jain2014Paper2014paper
Comprehensive AMS Verification using Octave, Real Number Modelling and UVMJohn McGrath, Patrick Lynch, and Ali Boumaalif2015Paper2015paper
Comprehensive AMS Verification using Octave, Real Number Modelling and UVMJohn McGrath, Patrick Lynch, and Ali Boumaalif2015Presentation2015presentation
Connecting a Company’s Verification Methodology to Standard Concepts of UVMFrank Poppen, Marco Trunzer, and Jan‐Hendrik Oetjens2014Paper2014paper
Connecting a Company’s Verification Methodology to Standard Concepts of UVMFrank Poppen, Marco Trunzer, and Jan‐Hendrik Oetjens2014Presentation2014presentation
Connecting Enterprise Applications to Metric Driven VerificationMatt Graham2014Paper2014paper
Connecting Enterprise Applications to Metric Driven VerificationMatt Graham2014Presentation2014presentation
Covering the Last Mile in SoC-Level Deadlock VerificationJef Verdonck, Khaled Nsaibia, Sagar Dewangan, HarGovind Singh and Roger Sabbagh2019Presentation2019presentation
Covering the Last Mile in SoC-Level Deadlock VerificationJef Verdonck, Dhruv Gupta, and HarGovind Singh2018Presentation2018presentation
CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemCHoang M. Le and Rolf Drechsler2014Paper2014paper
CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemCHoang M. Le and Rolf Drechsler2014Presentation2014presentation
Customizing UVM Agent Supporting Multi-Layered & TDM ProtocolsAmit Pessach2019Presentation2019presentation
Customizing UVM Agent Supporting Multi-Layered & TDM ProtocolsAmit Pessach2018Presentation2018presentation
Data path verification on cross domain with formal scoreboardLiu Jun2014Paper2014paper
Democratizing Formal VerificationTobias Ludwig, Michael Schwarz, Paulius Morkunas, Silvio Santana, Dominik Stoffel, Wolfgang Kunz2021Paper2021paper
Deploying HLS in a DO-254/ED-80 WorkflowTammy Reeve, Jacob Wiltgen, Byron Brinson, and David Aerne2020Paper2020paper
Deploying HLS in a DO-254/ED-80 WorkflowByron Brinson Jacob Wiltgen, David Aerne and Tammy Reeve2020Poster, Presentation2020poster presentation
Design and verification in ARMHobson Bullman2016Presentation2016presentation
Designing a PSS Reuse StrategyMatthew Balance2019Presentation2019presentation
Designing a PSS Reuse StrategyMatthew Balance2018Presentation2018presentation
Designing the Future with Efficiency Guidance to Adopting SystemVerilog for Design!Axel Scherer and Junette Tan2015Paper2015paper
Detection of glitch-prone clock and reset propagation with automated formal analysisKaushal Shah, Sulabh Kumar Khare2021Paper2021paper
Developing & Testing Automotive Software on Multi SoC ECU Architectures using Virtual PrototypingSam Tennent2018Presentation2018presentation
Developing Dynamic Resource Management System in SoCEmulationSeonchang Choi, Sangwoo Noh, Seonghee Yim and Seonil Brian Choi2019Presentation2019presentation
Developing Dynamic Resource Management System in SoCEmulationSeonchang Choi and Seonghee Yim2018Presentation2018presentation
Development of Flexi Performance Analysis Platform for Multi–SoC Networking SystemsSrinivasan Reddy Devarajan, Anant Raj Gupta, IngoVolkening, Franz Josef Schaefer and Vijay Raj Franklin Paul Rajan William2019Presentation2019presentation
Discovering Deadlocks in a Memory Controller IPJef Verdonck, Emrah Armagan, Khaled Nsaibia, Slava Bulach, Pranay Gupta, Anshul Jain, Chirag Agarwal and Roger Sabbagh2020Paper2020paper
Discovering Deadlocks in a Memory Controller IPJef Verdonck, Emrah Armagan, Khaled Nsaibia, Slava Bulach, Pranay Gupta, Anshul Jain, Chirag Agarwal, and Roger Sabbagh2020Presentation2020presentation
Does It Pay Off To Add Portable Stimulus Layer On Top Of UVM IP Block Test Bench?Xia Wu, Jacob Sander Andersen, and Ole Kristoffersen2020Presentation2020presentation
Does It Pay Off To Add Portable Stimulus Layer On Top Of UVM IP Block Test Bench?Xia Wu, Jacob Sander Andersen and Ole Kristoffersen2020Paper2020paper
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in SiliconAbdelouahab Ayari, Sukriti Bisht, Sulabh Kumar Khare and Kurt Takara2019Presentation2019presentation
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in SiliconAbdelouahab Ayari, Sukriti Bisht, Sulabh Kumar Khare, and Kurt Takara2018Presentation2018presentation
DVCon EU 2014 Proceedings2014Program2014program
DVCon EU 2015 Proceedings2015Program2015program
DVCon EU 2016 Proceedings2016Program2016program
DVCon EU 2017 Proceedings2017Program2017program
DVCon EU 2018 Proceedings2018Program2018program
DVCon EU 2019 Proceedings2019Program2019program
DVCon EU 2020 Proceedings2020Program2020program
DVCon EU 2020 ProceedingsAccellera Systems Initiative2020Video2020video
DVCon EU 2021 Proceedings2021Program2021program
DVCon Europe 2015 Road to self driving cars: View of a semiconductor companyHans Adlkofer2015Presentation2015presentation
Dynamic Fault Injection Library Approach for SystemC AMSThomas Markwirth, Paul Ehrlich, and Dominik Matter2016Presentation2016presentation
Dynamic Fault Injection Library Approach for SystemC AMSThomas Markwirth, Paul Ehrlich, and Dominik Matter2016Paper2016paper
Early Performance Verification of Embedded Inferencing Systems using open source SystemC NVIDIA MatchLibHerbert Taucher and Russell Klein2019Presentation2019presentation
Easier UVM – Making Verification Methodology More ProductiveJohn Aynsley and David Long2014Presentation2014presentation
Easier UVM: Learning and Using UVM with a Code GeneratorJohn Aynsley, Doulos2015Presentation2015presentation
Efficient Clock Monitoring System for SoC Clock VerificationNam Pham Van2016Presentation2016presentation
Efficient Clock Monitoring System for SoC Clock VerificationNam Pham Van, Bernhard Braun, Dirk Moeller, and Clemens Roettgermann2016Paper2016paper
Efficient Constrained Random Generation of Address Blocks: A comparative study of simulation speedsMeenakshy Ramachandran2015Paper2015paper
Efficient Constrained Random Generation of Address Blocks: A comparative study of simulation speedsMeenakshy Ramachandran2015Poster2015poster
Efficient Exploration of Safety-Relevant Systems Through a Link Between Analysis and SimulationMoomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello, and Bogdan-Andrei Tabacaru2016Presentation2016presentation
Efficient Exploration of Safety-Relevant Systems Through a Link Between Analysis and SimulationMoomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello, and Bogdan-Andrei Tabacaru2016Paper2016paper
Efficient Fault Injection Methods for Safety Software Testing Based on Virtual Prototypes: Application to Powertrain ECUOns Mbarek, Dineshkumar Selvaraj, and Romero Chica Jose Miguel2018Paper2018paper
Efficient use of Virtual Prototypes in HW/SW Development and VerificationRocco Jonack and Eyck Jentzsch2018Presentation2018presentation
Efficient Verification Framework for Audio/Video InterfacesNoha Shaarawy2015Presentation2015presentation
Emulation based Power and Performance Workloads on ML NPUsPragati Mishra, Ritu Suresh, Issac P Zacharia, Jitendra Aggarwal2021Paper2021paper
Enabling Digital Mixed-Signal Verification of Loading Effects in Power Regulation using SystemVerilog User-Defined NettypeAlvaro Caicedo and Sebastian Fritz2019Presentation2019presentation
Enabling Digital Mixed-Signal Verification of Loading Effects in Power Regulation using SystemVerilog User-Defined NettypeAlvaro Caicedo and Sebastian Fritz2018Presentation2018presentation
Enabling Energy Aware System Level Design with UPF-Based System Level Power ModelsT4A and T4B2014Presentation2014presentation
Enabling Visual Design Verification Analytics – From Prototype Visualizations to an Analytics Tool using the Unity Game EngineMarkus Borg, Andreas Brytting, and Daniel Hansson2018Paper2018paper
Enhancements of metric driven verification for the ISO26262: Recent advancements better supporting specific verification requirements including functional safetyMichael Rohleder, Clemens Röttgermann, Stephan Rüttiger, John Brennan, Matt Graham, and Riccardo Oddone2016Paper2016paper
Enhancing Quality and Coverage of CDC Closure in Intel’s SoC DesignRohit Kumar Sinha2020Paper2020paper
Enhancing Quality and Coverage of CDC Closure in Intel’s SoC DesignRohit Kumar Sinha2020Presentation2020presentation
Enriching UVM in SystemC with AMS extensions for randomization and functional coverage*Thilo Vörtler, Thomas Klotz, Karsten Einwich, Yao Li, Zhi Wang, Marie-Minerve Louërat, Jean-Paul Chaput, François Pêcheux, Ramy Iskander, and Martin Barnasconi2014Paper2014paper
Enriching UVM in SystemC with AMS extensions for randomization and functional coverage*Thilo Vörtler, Thomas Klotz, Karsten Einwich, Yao Li, Zhi Wang, Marie-Minerve Louërat, Jean-Paul Chaput, François Pêcheux, Ramy Iskander, and Martin Barnasconi2014Presentation2014presentation
ESL Design and Modeling with SystemCAMS for Mixed-Signal IoTand Automotive ApplicationsKarsten Einwich, Martin Barnasconi, Christoph Grimm, and Torsten Mähne2017Presentation2017presentation
Experience of Using Formal Verification for a Complex Memory Subsystem DesignSujeet Kumar, Vandana Goel, Hrushikesh Vaidya and Ronak Sarikhada2020Paper2020paper
Experience of using Formal Verification for a Complex Memory Subsystem DesignSujeet Kumar,Vandana Goel,Hrushikesh Vaidya, and Ronak Sarikhada2020Poster, Presentation2020poster presentation
Extending functionality of UVM components by using Visitor design patternDarko M. Tomušilović2018Presentation2018presentation
Extending functionality of UVM components by using Visitor design patternDarko M. Tomušilović2018Paper2018paper
Extending Proven Digital Verification Techniques for Mixed-Signal SoCswith VCS AMSHelene Thibieroz, Adiel Khan, Pierluigi Daglio, and Gernot Koch2014Presentation2014presentation
Extending the UVM register model generation and integration flow to support user-defined scenarios and register mask valuesShuang Han, Kees van Kaam, and Martin Barnasconi2017Paper2017paper
Extending the UVM register model generation and integration flow to support user-defined scenarios and register mask valuesShuang Han, Kees van Kaam, and Martin Barnasconi2017Presentation2017presentation
Extending UVM Register Abstraction Layer for Verification of Register Access via Serial Bus InterfaceDarko M. Tomušilović2016Presentation2016presentation
Extending UVM Register Abstraction Layer for Verification of Register Access via Serial Bus InterfaceDarko Tomušilović2016Paper2016paper
Facilitating Transactions in System Verilog and VHDLRich Edelman2020Presentation2020presentation
Facilitating Transactions in VHDL and SystemVerilogRich Edelman2020Paper2020paper
Fast and Furious Quick Innovation from Idea to Real PrototypeSimone Fontanesi, Gaetano Formato, Thomas Arndt, and Andrea Monterastelli2018Paper2018paper
Fast and FuriousQuick Innovation from Idea to Real PrototySimone Fontanesi, Gaetano Formato, Thomas Arndt, and Andrea Monterastelli2018Presentation2018presentation
Fault Effect Propagation using Verilog A for Analog Test CoverageAishwarya Prabhakaran, Ahmed Sokar, and Jaafar Mejri2018Presentation2018presentation
Fault Effect Propagation using Verilog-A for Analog Test CoverageAishwarya Prabhakaran, Ahmed Sokar and Jaafar Mejri2018Paper2018paper
Fault Proof: Using Formal Techniques for Safety Verification and Fault AnalysisAdrian Traskov, Thorsten Ehrenberg, Sacha Loitz, Abdelouahab Ayari, Avidan Efody, and Joseph Hupcey III2016Presentation2016presentation
Fault Proof: Using Formal Techniques for Safety Verification and Fault AnalysisAdrian Traskov,Thorsten Ehrenberg, Sacha Loitz, Abdelouahab Ayari, Avidan Efody, and Joseph Hupcey III2016Paper2016paper
Firmware Firmly under Control: New Optimization and Verification Techniques for Application Specific Electronic SystemDaniel Große, Manuel Strobel, Daniel Mueller-Gritschneder, Vladimir Herdt, and Tobias Ludwig2018Presentation2018presentation
Five Ways to Make Your Specman Environment More Reusable and ConfigurableStefan Sljukic, Nikola Knezevic, Filip Dojcinovic2021Paper2021paper
Flexible Indirect Registers With UVMUwe Simm2017Paper2017paper
Flexible Indirect Registers With UVMUwe Simm2017Presentation2017presentation
Formal Fault Propagation Analysis that Scales to Modern Automotive SoCsSergio Marchese and Jörg Grosse2017Paper2017paper
Formal Fault Propagation Analysis that Scales to Modern Automotive SoCsSergio Marchese2017Presentation2017presentation
Formal Property Verification of the Digital Section of an Ultra-Low Current Digitizer ASICKatharina Ceesay-Seitz, Sarath Kundumattathil Mohanan, Hamza Boukabache, Daniel Perrin2021Paper2021paper
Formal Verification Experiences: Silicon Bug Hunt with “Deep Sea Fishing”Mark Handover, Abdelouahab Ayari and Ping Yeung2020Paper2020paper
Formal Verification Experiences: Silicon Bug Hunt with “Deep Sea Fishing”Ping Yeung, Mark Handover, and Abdelouahab Ayari2020Poster, Presentation2020poster presentation
Formal Verification of a Highly Configurable DDR Controller IPSumit Neb, Chirag Agarwal, Deepak K. Gupta, and Roger Sabbagh2018Paper2018paper
Formal Verificationin the Real WorldJonathan Bromley and Jason Sprott2017Presentation2017presentation
FPGA Debug Using Configuration ReadbackMike Dini 2015Presentation2015presentation
Functional Safety Verification for ISO 26262 – Compliant Automotive DesignsJM Forey and Werner Kerscher2018Presentation2018presentation
Gathering Memory Hierarchy Statistics in QEMUClément Deschamps, Mark Burton, Eric Jenn and Frédéric Pétrot2019Presentation2019presentation
Gathering Memory Hierarchy Statistics in QEMUClément Deschamps, Mark Burton, Eric Jenn, and Frédéric Pétrot2018Presentation2018presentation
Generating Bus Traffic PatternsJacob Sander Andersen, Lars Viklund and Kenneth Branth2018Paper2018paper
Generation of (at least) UVM Register Models from IP Xact Using Model Driven SW TechniquesJacob Sander Andersen2017Presentation2017presentation
Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS*Ronan Lucas, Marie-Minerve Louërat, Yao Li, Zhi Wang, Jean-Paul Chaput, François Pêcheux, Ramy Iskander, Martin Barnasconi, and Thilo Vörtler2014Paper2014paper
Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS*Ronan Lucas and Philippe Cuenot2014Presentation2014presentation
Generic Testbench/Portable Stimulus/PromotabilityRevati Bothe and Jesvin Johnson2019Presentation2019presentation
Go Figure – UVM Configure The Good, The Bad, The DebugRich Edelman and Dirk Hansen2016Presentation2016presentation
Go Figure – UVM Configure The Good, The Bad, The DebugRich Edelman and Dirk Hansen2016Paper2016paper
Golden UPF: Preserving Power Intent From RTL to ImplementationHimanshu Bhatt and Harsh Chilwal2015Presentation2015presentation
Guiding Functional Verification Regression Analysis Using Machine Learning and Big Data MethodsEman El Mandouh, Laila Maher, Moutaz Ahmed and Amr G. Wassal2018Paper2018paper
Handling Asynchronous Reset(s) Testing by building reset-awareness into UVM testbench componentsWei Wei Cheong, Katherine Garden, Ana Sanz Carretero2021Paper2021paper
Hardware construction with SystemCRoman Popov and Roman Popov2018Paper2018paper
Hardware Software Co-verification in Hybrid QEMU/HDL EnvironmentRadoslaw Nawrot and Krzysztof Szczur2018Presentation2018presentation
Hardware/Software Co-Simulation of SPI enabled ASICs and Software Drivers for Fault Injection and Regression TestsElias Kyrlies-Chrysoulidis, Andreas Plange, Thomas Gürtler, Matthias Auerswald, and Josef Schmid2014Paper2014paper
Hardware/Software Co-Simulation of SPI enabled ASICs and Software Drivers for Fault Injection and Regression TestsElias Kyrlies-Chrysoulidis, Andreas Plange, Thomas Guertler, Matthias Auerswald, and Josef Schmid2014Poster2014poster
Heterogeneous Virtual Prototyping for IoTApplicationsPaul Ehrilich, Karsten Einwich, Mark Burton, and Luc Michel2017Presentation2017presentation
Heterogenous Virtual Prototyping for IoT ApplicationsMark Burton, Luc Michel, Paul Ehrlich, and Karsten Einwich2017Paper2017paper
High-Performance Mixed-Signal ESL Design of a Magneto Resistive Sensor ApplicationMartin Barnasconi and Sumit Adhikari2016Presentation2016presentation
High-Performance Mixed-Signal ESL Design of a Magneto Resistive Sensor ApplicationMartin Barnasconi and Sumit Adhikari2016Paper2016paper
How Far Can You Take UVM Code Generation and Why Would You Want To?John Aynsley2016Presentation2016presentation
How Far Can You Take UVM Code Generation and Why Would You Want To?John Aynsley2016Paper2016paper
How to Create a Complex Testbench in a Couple of HoursTom Fitzpatrick and Graeme Jessiman2017Presentation2017presentation
How to Use Formal Analysis to Prevent DeadlocksAbdelouahab Ayari, Mark Eslinger and Joe Hupcey III2020Presentation2020presentation
How to Verify Complex FPGA Designs for FreeSebastian Dreßler, Nikos Anastasiadis, and Thomas Richter2016Presentation2016presentation
How to Verify Complex FPGA Designs for FreeSebastian Dreßler, Nikos Anastasiadis, and Thomas Richter2016Paper2016paper
How To Verify Encoder And Decoder Designs Using Formal VerificationJin Hou2020Paper2020paper
How To Verify Encoder And Decoder Designs Using Formal VerificationJin Hou2020Presentation2020presentation
Hybrid Flow: A smart methodolgy to migrate from traditional Low Power MethodologyRohit Kumar Sinha and N. Prashanth2018Paper2018paper
Hybrid Flow: A smart methodology to migrate from traditional Low Power MethodologyRohit Kumar Sinha and Prashanth N2018Presentation2018presentation
IEEE 1801 Assisted Custom IP Development and Low Power Checks Using Cadence Virtuoso Power ManagerDr. Matthias Steffen, Amit Chopra and Amit Chopra2018Paper2018paper
IEEE 1801 Assisted Custom IP Development and Low Power Checks Using Cadence Virtuoso Power ManagerMatthias Steffen, Amit Chopra, and Sonal Singh2018Presentation2018presentation
Implementation of a closed loop CDC verification methodologyAndrew Cunningham, Ireneusz Sobanski2014Paper2014paper
Implementation of a closed loop CDC verification methodologyAndrew Cunningham2014Presentation2014presentation
Improving the Confidence Level in Functional Safety Simulation Tools for ISO 26262Ahmet Cagri Bagbaba, Felipe Augusto Da Silva, and Christian Sauer2018Paper2018paper
Increased Regression Efficiency with Jenkins Continuous IntegrationThomas Ellis2016Paper2016paper
Increasing Efficiency and Reuse in Modeling SystemC/TLM IPs Targeting Virtual Prototypes for Software DevelopmentDavid Spieker, Thomas Schuster, Rafael Zuralski, and Christian Sauer2020Paper2020paper
Innovative Technological Narratives Leveraging the Idea of Authenticity in a Human BeingAnna M. Ravitzki, Uri Feigin, and Hagai Arbel2017Presentation2017presentation
Institutionalize a certified ISO26262 safety processM. Rohleder, C. Röttgermann, amd M. Müller2016Presentation2016presentation
Institutionalizing a certified ISO26262 safety process: Experiences and lessons learnedMichael Rohleder, Clemens Röttgermann, and Marcus Müller2016Paper2016paper
Integrating a Virtual Platform Framework for Smart DevicesV. Guarnieri, F. Stefanni, F. Fummi, M. Grosso, D. Lena, A. Ciccazzo, G. Gangemi, and S. Rinaudo2015Presentation2015presentation
Integrating Different Types of Models into a Complete Virtual SystemJakob Engblom, Andreas Hedström, Xiuliang Wang, and Håkan Zeffer2016Presentation2016presentation
Integrating Different Types of Models into a Complete Virtual System: The Simics SystemC* LibraryJakob Engblom, Andreas Hedström, Xiuliang Wang, and Håkan Zeffer2016Paper2016paper
Integrating Parallel SystemC Simulationinto Simics® Virtual PlatformDaniel Mendoza, Ajit Dingankar, ZhongqiCheng and Rainer Doemer2019Presentation2019presentation
Integrating Parallel SystemC Simulationinto Simics® Virtual PlatformDaniel Mendoza, Ajit Dingankar, Zhongqi Cheng and Rainer Doemer2018Presentation2018presentation
Integration of modern verification methodologies in a TCL test frameworkMatteo De Luigi and Alessandro Ogheri2015Paper2015paper
Introduction to Next Generation Verification Language – VlangPuneet Goel and Sumit Adhikari2014Paper2014paper
Introduction to Next Generation Verification Language – VlangPuneet Goel and Sumit Adhikari2014Presentation2014presentation
IP-Coding Style Variants in a Multi-layer Generator FrameworkZhao Han, Keerthikumara Devarajegowda, Andreas Neumeier and Wolfgang Ecker2020Paper2020paper
IP-Coding Style Variants in a Multi-layer Generator FrameworkZhao Han, Keerthikumara Devarajegowda, Andreas Neumeier, and Wolfgang Ecker2020Poster, Presentation2020poster presentation
Is Your Testing N wise or Unwise? Pairwise and N wise Patterns in SystemVerilog for Efficient Test Configuration and StimulusJonathan Bromley and Kevin Johnston2015Presentation2015presentation
ISO 26262 Fault Analysis in Safety Mechanisms Considering the impact of residual and latent faults in hardware safety mechanismsJörg Grosse, Mark Hampton, Sergio Marchese, Jörg Koch, Neil Rattray and Alin Zagardan2019Presentation2019presentation
ISO 26262: Better be safe with modelling and simulation on system-levelJoachim Hößler, Sven Johr, Thang Nguyen, Stephan Schulz, and Gert-Jan Tromp2014Paper2014paper
ISO 26262: Better be safe with modelling and simulation on system-levelJoachim Hößler, Sven Johr, Thang Nguyen, Stephan Schulz, and Gert-Jan Tromp2014Poster2014poster
Language Agnostic Communication for SystemC TLM Compliant Virtual PrototypesSmurti Khire, Kunal Sharma, Vishal Chovatiya2021Paper2021paper
Lean Verification Techniques: Executable SystemVerilog UVM Defect Table For SimulationsSteve Burchfiel, Kevin Schott, Kamel Belhous and Paul Ulrich2020Paper2020paper
Lean Verification Techniques: Executable SystemVerilog UVM Defect Table For SimulationsKamel Belhous and Steve Bu2020Presentation2020presentation
Leveraging hardware emulation to accelerate SoCverification in multi-physics automotive simulation environment via the Functional Mock-up InterfacePierre-Guillaume Le Guay, Henrique Vicente De Souza, Caaliph Andriamisaina, Emmanuel Molina Gonzalez and Tanguy Sassolas2019Presentation2019presentation
Leveraging hardware emulation to accelerate SoCverification in multi-physics automotive simulation environment via the Functional Mock-up InterfacePierre-Guillaume Le Guay, Henrique Vicente De Souza, Caaliph Andriamisaina, Emmanuel Molina Gonzalez, and Tanguy Sassolas2018Presentation2018presentation
Leveraging the UVM RAL for Memory Sub-System VerificationTudor Timisescu and Uwe Simm2015Presentation2015presentation
Leveraging the UVM Register Abstraction Layer for Memory Sub-System VerificationTudor Timisescu and Uwe Simm2015Paper2015paper
Leveraging virtual prototypes from concept to siliconRob Kaye2017Presentation2017presentation
Low-Power Verification Methodology using UPF Query functions and Bind checkersMadhur Bhargava and Durgesh Prasad2014Paper2014paper
Low-Power Verification Methodology using UPF Query functions and Bind checkersMadhur Bhargava and Durgesh Prasad2014Poster2014poster
Machine Learning based Structure Recognition in Analog Schematics for Constraints GenerationRituj Patel, Husni Habal, Konda Reddy Venkata2021Paper2021paper
Machine Learning for Coverage Analysis in Design VerificationV Jayasree2021Paper2021paper
Machine Learning Introduction and Exemplary Application in Embedded Wireless PlatformsJonathan Ah Sue2018Presentation2018presentation
Make your Testbenches Run Like Clockwork!Markus Brosch, Salman Tanvir, and Martin Ruhwandl2020Presentation2020presentation
Make Your Testbenches Run Like Clockwork!Markus Brosch, Salman Tanvir and Martin Ruhwandl2020Paper2020paper
Making Autonomous Cars SafeJoern Stohmann and Frederico Ferlini2017Presentation2017presentation
Making ISO26262 Functional Safety Verification a Natural Extension of Functional VerificationAndrew Betts and Ann Keffer2018Presentation2018presentation
Maximize PSS Reuse with Unified Test Realization Layer Across Verification EnvironmentsSimranjit Singh, Ashwani Aggarwal, Suman Kumar Reddy Mekala, Arun K.R., Woojoo Space Kim , Seonil Brian Choi, Gnaneshwara Tatuskar2021Paper2021paper
Mechanical mounting variation effects on magnetic speed sensor applicationsSimone Fontanesi, Se Hwan Kim, Gernot Binder and Andrea Monterastelli2017Presentation2017presentation
Mechanical mounting variation effects on magnetic speed sensor applications Combining finite element methods and SystemC simulations to study the effects of mechanical tilts and offset on magnetic speed sensor applicationsSimone Fontanesi, Se Hwan Kim, Gernot Binder and Andrea Monterastelli2017Paper2017paper
Method for early performance verification of hardware-accelerated embedded processor systems in RTL simulationLuca Sasselli, Mehmet Tukel, David Guthrie2021Paper2021paper
Methodology for Automated Generation and Validation of Analog Behavioral Models for Mixed-Signal VerificationNan Ni, Chunya Xu, and Sebastian Simon2018Paper2018paper
Methodology for checking UVM VIPsMilan Vlahovic and Ilija Dimitrijevic2019Presentation2019presentation
Methodology for checking UVM VIPsMilan Vlahovic and Ilija Dimitrijevic2018Presentation2018presentation
Methodology of Communication Protocols Development: from Requirements to ImplementationIrina Lavrovskaya and Valentin Olenev2015Presentation2015presentation
MicroTESK: Automated Architecture Validation Suite Generator for MicroprocessorsMikhail Chupilko, Alexander Kamkin, Alexander Protsenko, Sergey Smolov, and Andrei Tatarnikov2018Paper2018paper
Mixed Electronic System Level Power/Performance EstimationAntonio Genov, Loic Leconte and François Verdier2020Paper2020paper
Mixed ESL Power/Performance Estimation using SystemC/TLM2.0 Modeling and PwClkARCHLibraryAntonio Genov, Loic Leconte, and François Verdier2020Presentation2020presentation
Model based Automation of Verification Development for automotive SOCsAljoscha Kirchner, Jan Hendrik Oetjens, and Oliver Bringmann,2020Presentation2020presentation
Model Validation for Mixed-Signal VerificationCarsten Wegener2016Presentation2016presentation
Model Validation for Mixed-Signal Verification The Importance of Being Earnest about ModelingCarsten Wegener2016Paper2016paper
Model-Based Automation of Verification Development for Automotive SOCsAljoscha Kirchner, Jan-Hendrik Oetjens and Oliver Bringmann2020Paper2020paper
Modeling of Generic Transfer Functions in SystemVerilogElvis Shera2016Presentation2016presentation
Modeling of Generic Transfer Functions in SystemVerilog. Demystifying the Analytic ModelElvis Shera2016Paper2016paper
Modelling Finite-State Machines in the Verification Environment using Software Design PatternsDarko M. Tomušilović and Mihajlo Z. Minović2017Paper2017paper
Modelling Finite-State Machines in the Verification Environment using Software Design PatternsDarko M. Tomušilović2017Presentation2017presentation
Modern methodologies in a TCL test environmentMatteo De Luigi and Alessandro Ogheri2015Presentation2015presentation
Moving SystemC to a New C++ StandardRalph Görgen and Philipp A. Hartmann2016Paper2016paper
Multi-Variant Coverage: Effective Planning and ModellingVikas Sharma and Manoj Manu2018Paper2018paper
Multi-Variant Coverage: Effective Planning and ModellingVikas Sharma and Manoj Manu2018Presentation2018presentation
Mutable Verification Environments Through Visitor and Dynamic Register Map ConfigurationMatteo Barbati, Alberto Allara2020Paper2020paper
Mutable Verification Environments through Visitor and Dynamic Register Map ConfigurationMatteo Barbati and Alberto Allara2020Presentation2020presentation
Netlist PathsJamie Hanlon, Samuel Kong2021Paper2021paper
New Trends in RTL Verification: Bug Localization, Scan- Chain-Based Methodology, GA-Based Test GenerationKhaled Salah 2015Poster2015poster
New Trends in RTL Verification: Bug Localization, Scan-Chain-Based Methodology, GA-Based Test GenerationKhaled Salah2015Paper2015paper
Next Gen System Design and Verification for TransportationBryan Ramirez, Petri Solanti and Richard Pugh2019Presentation2019presentation
Next Generation ISO 26262-basedDesign Reliability FlowsJörg Große and Sanjay Pillay2017Presentation2017presentation
No Country For Old Men – A Modern Take on Metrics Driven VerificationSvetlomir Hristozkov, James Pallister, Richard Porter2021Paper2021paper
NVVM: A Netlist-based Verilog Verification Methodology for Mixed-Signal DesignJiping Qiu, Kurt Schwartz2014Paper2014paper
NVVM: A Netlist-based Verilog Verification Methodology for Mixed-Signal DesignJiping Qiu, Kurt Schwartz2014Presentation2014presentation
One Testbench to Rule them all!Salman Tanvir, Markus Brosch, Amer Siddiqi2021Paper2021paper
Open Source Solution for RISC-V VerificationMikhail Chupilko, Alexander Kamkin and Alexander Protsenko2019Presentation2019presentation
Open Source Solution for RISC-V VerificationMikhail Chupilko, Alexander Kamkin, and Alexander Protsenko 2018Presentation2018presentation
Optimizing Design Verification using Machine LearningWilliam Hughes, Sandeep Srinivasan, Rohit Suvarna, Maithilee Kulkarni2021Paper2021paper
OSVVM and Error ReportingJim Lewis2015Paper2015paper
OSVVM and Error ReportingJim Lewis2015Presentation2015presentation
OSVVM: Advanced Verification for VHDLJim Lewis2014Paper2014paper
OSVVM: Advanced Verification for VHDLJim Lewis2014Poster2014poster
Overcoming Challenges in SoC RTL Verification of USB SubsystemTijana Mišić and Marko Mišić,2019Presentation2019presentation
Paving a Path to Hardware-Based Acceleration in a Single UVM Environment (Because there can be only one UVM environment!)Axel Scherer and Mark Azadpour2015Paper2015paper
Pedal Faster! Or Make Your Verification Environment More Efficient. You Choose.Rich Edelman, Raghu Ardeishar, and Rohit Jain2014Paper2014paper
Pedal Faster! Or Make Your Verification Environment More Efficient. You Choose.Rich Edelman, Raghu Ardeishar, and Rohit Jain2014Poster2014poster
Performance modeling and timing verification for DRAM memory subsystemsThomas Schuster, Peter Prüller, and Christian Sauer2018Presentation2018presentation
Performance modeling and timing verification for DRAM memory subsystemsThomas Schuster, Peter Prüller, and Christian Sauer2018Paper2018paper
Portable Stimuli over UVM using portable stimuli in HW verification flowEfrat Shneydor, Slava Salnikov, Liran Kosovizer and Dr’ Shlomo Greenberg2019Presentation2019presentation
Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication endpointAndrei Vintila and Ionut Tolea2018Paper2018paper
Portable Test and Stimulus: The Next Level of Verification Productivity is HereTom Fitzpatrick and Sharon Rosenberg2018Presentation2018presentation
Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) ArtifactsMark Handover, Jonathan Lovett, and Kurt Takara2015Paper2015paper
Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) ArtifactsMark Handover, Jonathan Lovett, and Kurt Takara2015Presentation2015presentation
Power Aware Models: Overcoming barriers in Power Aware SimulationMohit Jain, Amit Singh, J.S.S.S. Bharath, Amit Srivastava, and Bharti Jain2014Paper2014paper
Power Aware Models: Overcoming barriers in Power Aware SimulationMohit Jain, Amit Singh, J.S.S.S. Bharath, Amit Srivastava, and Bharti Jain2014Presentation2014presentation
Power-Aware Verification in Mixed-Signal SimulationAtul Pandey, Mattias Welponer, and Gregor Kowalczyk2014Presentation2014presentation
Practical Experience in Automatic Functional Coverage Convergence and Reusable Collection Infrastructure in UVMRoman Wang, Suresh Babu Pusphaparaj, Mike Bartley2014Presentation2014presentation
Practical experience in automatic functional coverage convergence and reusable collection infrastructure in UVM verificationRoman Wang, Suresh Babu Pusphaparaj2014Paper2014paper
Practical experience in automatic functional coverage convergence and reusable collection infrastructure in UVM verificationRoman Wang and Suresh Babu Pusphaparaj2014Presentation2014presentation
Probing UPF Dynamic Objects: Methodologies to Build Your Custom Low-Power VerificationProgyna Khondkar2020Poster, Presentation2020poster presentation
Probing UPF Dynamic Objects: Methodologies to Build Your Custom Low-Power Verification PlatformProgyna Khondkar2020Paper2020paper
Processing deliberate verification errors during regressionAlastair Lefley, Roger Witlox, Clemens Süßmuth, Thomas Ziller and Kawe Fotouhi2019Presentation2019presentation
Processing deliberate verification errors during regressionAlastair Lefley, Roger Witlox, Clemens Süßmuth, Thomas Ziller, and Kawe Fotouhi2018Presentation2018presentation
Protocol verification of an IEEE 802.3bw PHY Application of mixed signal extensions to an UVM verification environmentJoen Westendorp and Marcel Oosterhuis2018Paper2018paper
Pythonized SystemC A non-intrusive scripting approachEyck Jentzsch and Rocco Jonack2019Presentation2019presentation
QED & Symbolic QED Pre-silicon Verification, Post-silicon Validation, Industrial ResultsSubhasish Mitra, Eshan Singh and K. Devarajegowda2019Presentation2019presentation
Qualification of a Verification IP under Requirement Based Verification standards An approach to the verification of the verificationFrancois Cerisier, Adrien Carmagnat, Alessandro Basili, and Gilles Curchod2018Paper2018paper
Random Stimuli Models for UVM RegistersJacob Sander Andersen, Lars Viklund and Laura Montero2019Presentation2019presentation
Reboot your Reset Methodology: Resetting Anytime with the UVM Reset PackageCourtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm2014Paper2014paper
Reboot your Reset Methodology: Resetting Anytime with the UVM Reset PackageCourtney Schmitt, Phu Huynh, Stephanie McInnis, and Uwe Simm2014Presentation2014presentation
Refining Successive Refinement: Improving a Methodology for Incremental Specification of Power IntentDesinghu PS, Adnan Khan, Erich Marschner, and Gabriel Chidolue2015Paper2015paper
Refining Successive Refinement: Improving a Methodology for Incremental Specification of Power IntentErich Marschner and Gabriel Chidolue2015Presentation2015presentation
Requirement Driven Safety VerificationRanga Kadambi, Vladimir Litovtchenko, Jens Rosenbusch, and Antonio Vilela2016Presentation2016presentation
Requirement Driven Safety VerificationRanga Kadambi, Vladimir Litovtchenko, Jens Rosenbusch, and Antonio Vilela2016Paper2016paper
Requirements Driven Design Verification Flow TutorialAteş Berna and Ahmet Jorghanxhi 2018Presentation2018presentation
Requirements driven Verification methodology (for standards compliance)Serrie-Justine Chapman, Darren Galpin, and Mike Bart2014Paper2014paper
Requirements driven Verification methodology (for standards compliance)Serrie-justine Chapman, Mike Bartley, and Darren Galpin 2014Presentation2014presentation
Requirements-driven Verification Methodology for Standards ComplianceSerrie-justine Chapman and Mike Bartley2014Presentation2014presentation
Resetting RDC ExpectationsEamonn Quigley, Jonathan Niven, Mark Handover2021Paper2021paper
Results Checking Strategies with Portable StimulusTom Fitzpatrick and Matthew Ballance2019Presentation2019presentation
Retrascope: Open-Source Model Checkerfor HDL DescriptionsAlexander Kamkin, Mikhail Lebedev and Sergey Smolov2019Presentation2019presentation
Retrascope: Open-Source Model Checkerfor HDL DescriptionsAlexander Kamkin, Mikhail Lebedev, and Sergey Smolov2018Presentation2018presentation
Reusable Processor Verification Methodology Based on UVMMustafa Khairallah and Maged Ghoneima2014Paper2014paper
Reusable Processor Verification Methodology Based on UVMMustafa Khairallah and Maged Ghoneima2014Poster2014poster
Reuse doesn’t come for free – learnings from a UVM deploymentSumeet Gulati, Srinivasan Venkataramanan, Ketki Gosavi, Saumya Anvekar, and Azhar Ahammad2016Presentation2016presentation
Reuse doesn’t come for free – learnings from a UVM deploymentSumeet Gulati, Srinivasan Venkataramanan, Azhar Ahammad, Ketki Gosavi, and Saumya Anvekar2016Paper2016paper
Reuse of System-Level Verification Components within Chip-Level UVM EnvironmentsDiego Alagna, Marzia Annovazzi, Alessandro Cannone, Marcello Raimondi, Simone Saracino, Mukesh Chugh, Marc Erickson, Cristian Macario, Giuseppe Ridinò2021Paper2021paper
Revitalizing Automotive Safety Hard and Soft Error ApproachesNael Qudsi and Ayman Mouallem2019Presentation2019presentation
Revolutionary Debug Techniques to Improve Verification ProductivityNadav Chazan2014Presentation2014presentation
RISC-V Compliance & Verification Techniques Processor Cores and Custom ExtensionsSimon Davidmann, Lee Moore, Richard Ho, Doug Letcher and Kevin McDermott2019Presentation2019presentation
RISC-V Integrity: A Guide for Developers and IntegratorsNicolae Tusinschi2019Presentation2019presentation
RTL2RTL Formal Equivalence: Boosting the Design ConfidenceM. Achutha KiranKumar V, Aarti Gupta, and Ss. Bindumadhava2014Paper2014paper
RTL2RTL Formal Equivalence: Boosting the Design ConfidenceM. Achutha KiranKumar V, Aarti Gupta, and Ss. Bindumadhava2014Poster2014poster
Safety and Security Aware Pre-Silicon Hardware / Software Co-DevelopmentNikola Velinov and Frank Schirrmeister2019Presentation2019presentation
Safety-Verification Flow Sporting Gate-Level Accuracy and Near Virtual-Prototype SpeedB.-A. Tabacaru, M. Chaari, W. Ecker, T. Kruse, and C. Novello2016Presentation2016presentation
Safety-Verification Flow Sporting Gate-Level Accuracy and Near Virtual-Prototype SpeedBogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, and Cristiano Novello2016Paper2016paper
Same bits, different meaning – when direct execution based simulation becomes complicatedEvgeny Yulyugin2018Paper2018paper
Semi-formal Reformulation of Requirements for Formal Property VerificationKatharina Ceesay-Seitz, Hamza Boukabache and Daniel Perrin2019Presentation2019presentation
SimpleLink™ MCU Platform: IP-XACT to UVM Register Model – Standardizing IP and SoC Register VerificationJasminka Pasagic and Frank Donner2017Presentation2017presentation
SimpleLink™ MCU Platform: IP-XACT to UVM Register Model – Standardizing IP and SoC Register Verification “UVM is a perfect start”Jasminka Pasagic and Frank Donner2017Paper2017paper
Simplifying UVM in SystemCThilo Vörtler, Thomas Klotz, Karsten Einwich, and Felix Assma2015Paper2015paper
Simplifying UVM in SystemCThilo Vörtler, Thomas Klotz, Karsten Einwich, and Felix Assma2015Poster2015poster
SimPy for ChipsHachem Tassine, Daniel Wilkinson, Graham Cunnigham, Iason Myttas2021Paper2021paper
Simulation and Debug of Mixed Signal Virtual Platforms for Hardware-Software co-developmentVincent Motel, Alexandre Roybier, and Serge Imbert2014Paper2014paper
Simulation and Debug of Mixed Signal Virtual Platforms for Hardware-Software co-developmentVincent Motel, Alexandre Roybier, and Serge Imbert2014Presentation2014presentation
Single Source System to Register-Transfer Level Design Methodology Using High-Level SynthesisPetri Solanti and Thomas Arndt2020Paper2020paper
Single Source System to Register-Transfer Level Design Methodology Using High-Level SynthesisPetri Solanti and Thomas Arndt2020Presentation2020presentation
Slicing Through the UVM’s Red TapeA Frustrated User’s Survival GuideJonathan Bromley © Accellera2016Presentation2016presentation
Slicing Through the UVM’s Red Tape: A Frustrated User’s Survival GuideJonathan Bromley2016Paper2016paper
SOBEL FILTER: Software Implementation to RTL using High Level SynthesisBhavna Aggarwal, Umesh Sisodia and Snigdha Tyagi2020Paper2020paper
SOBEL FILTER: Software Implementation to RTL using High Level SynthesisBhavna Aggarwal, Umesh Sisodia, and Snigdha Tyagi2020Presentation2020presentation
Software Driven Test of FPGA PrototypeMethods & Use casesKrzysztof Szczur and Radosław Nawrot2017Presentation2017presentation
Specification by Example for Hardware Design and VerificationJussi Mäkelä2017Paper2017paper
Specification by Example for Hardware Design and VerificationJussi Mäkelä2017Presentation2017presentation
State-Space “Switching” Model of DC-DC Converters in SystemVerilogElvis Shera2017Presentation2017presentation
State-Space “Switching” Model of DC-DC Converters in SystemVerilog.Elvis Shera2017Paper2017paper
Static Analysis of SystemC/SystemC-AMS System and Architectural Level ModelsKarsten Einwich and Thilo Vörtler2020Paper2020paper
Static Analysis of SystemC/SystemC-AMS System and Architectural Level ModelsKarsten Einwich and Thilo Vörtler2020Presentation2020presentation
Static Checking for Correctness of Functional Coverage ModelsWael Mahmoud2017Presentation2017presentation
Static Checking for Correctness of Functional Coverage ModelsWael Mahmoud2017Paper2017paper
Successive Refinement – An approach to decouple Front-End and Back-end Power IntentRohit Kumar Sinha2021Paper2021paper
SysML based Architecture Definition and Platform Generation FlowRalph Görgen and Erwin de Kock2019Presentation2019presentation
System Verilog Assertions VerificationIonuț Ciocîrlan and Andra Radu2015Presentation2015presentation
System-Level Register Verification and DebugUtkarsh Bhiogade, Kautilya Joshi, Puneet Goel2021Paper2021paper
SystemC extension for power specification, simulation and verificationMikhail Moiseev, Ilya Klotchkov, and Kirill Gagarski2016Paper2016paper
SystemC extension for power specification,simulation and verificationMikhail Moiseev, Ilya Klotchkov, Maxim Petrov, and Kirill Gagarski2016Presentation2016presentation
SystemC gaps encountered in Virtual Platform developmentEyck Jentzsch2016Paper2016paper
SystemC-to-Verilog Compiler: a productivity-focused tool for hardware design in cycle-accurate SystemCMikhail Moiseev, Roman Popov and Ilya Klotchkov2019Presentation2019presentation
SystemC-to-Verilog Compiler: a productivity-focused tool for hardware design in cycle-accurate SystemCMikhail Moiseev, Roman Popov, and Ilya Klotchkov2018Presentation2018presentation
Temporal Assertions in SystemCMikhail Moiseev, Leonid Azarenkov and Ilya Klotchkov2020Paper2020paper
Temporal Decoupling – Are “Fast” and “Correct” Mutually Exclusive?Jakob Engblom2018Presentation2018presentation
Temporal Decoupling – Are “Fast” and “Correct” Mutually Exclusive?Jakob Engblom2018Paper2018paper
Testbench Flexiblity as a Foundation for SuccessAna Sanz Carretero, Katherine Garden, Wei Wei Cheong2021Paper2021paper
The Application of Formal Technology on Fixed Point Arithmetic SystemC DesignsSven Beyer, Dominik Straßer, and Dave Kelf2015Presentation2015presentation
The Application of Formal Technology on Fixed-Point Arithmetic SystemC DesignsSven Beyer, Dominik Straßer, and David Kelf2015Paper2015paper
The How To’s of Advanced Mixed-Signal VerificationJohn Brennan, Thomas Ziller, Kawe Fotouhi, and Ahmed Osman2015Presentation2015presentation
The How To’s of Metric Driven Verification to Maximize ProductivityMatt Graham and John Brennan2014Presentation2014presentation
The missing SystemC and TLM asynchronous features enabling inter-simulation synchronization.Guillaume Delbergue, Mark Burton, Bertrand Le Gal and Christophe Jego2016Paper2016paper
The Top Most Common SystemVerilog Constrained Random GotchasAhmed Yehia2014Paper2014paper
The Top Most Common SystemVerilog Constrained Random GotchasAhmed Yehia2014Presentation2014presentation
The Universal TranslatorDavid Cornfield2014Presentation2014presentation
The Universal Translator – A Fundamental UVM Component for Networking ProtocolsDavid Cornfield2014Paper2014paper
The Universal Translator – A Fundamental UVM Component for Networking ProtocolsDavid Cornfield2014Presentation2014presentation
Timing-Aware High Level Power Estimation of Industrial Interconnect ModuleAmal Ben Ameur, Antonio Genov, François Verdier and Loic Leconte2020Paper2020paper
Timing-Aware high level power estimation of industrial interconnect moduleAmal Ben Ameur, Antonio Genov, François Verdier, and Loic Leconte2020Presentation2020presentation
TLM based Virtual Platforms at Ericsson Challenges and ExperiencesOla Dahl, Michael Lebert, and Eric Frejd2016Presentation2016presentation
TLM Beyond Memory Mapped BussesBart Vanthournout and Mark Burton2016Paper2016paper
TLM modeling and simulation for NAND Flash and Solid State Drive systemsTim Kogel and Victor Reyes2017Presentation2017presentation
TLM-based Virtual Platforms at Ericsson: Challenges and ExperiencesOla Dahl, Michael Lebert, and Eric Frejd2016Paper2016paper
Towards 5G Internet of ThingsSabine Roessel2017Presentation2017presentation
Towards a UVM-based Solution for Mixed-signal VerificationAlexander W. Rath, Sebastian Simon, Volkan Esen, and Wolfgang Ecker2016Presentation2016presentation
Towards a UVM-based Solution for Mixed-signal VerificationAlexander W. Rath, Sebastian Simon, Volkan Esen, and Wolfgang Ecker2016Paper2016paper
Transaction‐Based Testing with OSVVM and the OSVVM Model LibraryJim Lewis and Patrick Lehmann2019Presentation2019presentation
Tutorial 7 Tutorial on RISC-V Design and VerificationKevin McDermott, Zdenek Prikryl, and Peter Shields2018Presentation2018presentation
TwIRTee design exploration with Capella and IP-XACTPhilippe Cuenot, Bassem Ouni, and Pierre Gaufillet2016Presentation2016presentation
TwIRTee: design exploration with Capella and IP-XACTBassem Ouni, Philippe Cuenot, and Pierre Gaufillet2016Paper2016paper
Understanding the effectiveness of your system-level SoC stimulus suiteRobert Fredieu, Alan Hunter, and Andreas Meyer2014Paper2014paper
Understanding the effectiveness of your system-level SoC stimulus suiteAlan Hunter , Robert Fredieu, and Andreas Meyer2014Poster2014poster
Unified Functional Safety Verification Platform for ISO 26262 Compliant AutomotiveJoerg Richter2019Presentation2019presentation
Unified Model/Hardware-in-the-Loop Methodology for Mixed-Signal System Design and Hardware PrototypingMartin Barnasconi, Wil Kitzen, Thieu Lammers, Paul Ehrlich, Karsten Einwich2021Paper2021paper
Unified Test Writing Framework for Pre and Post Silicon VerificationRahulkumar Patel, Pablo Cholbi, Sivasubrahmanya Evani and Raman K2019Presentation2019presentation
Unifying Mixed-Signal and Low-Power VerificationAdam Sherer, Andre Baguenier, Kawe Fotouhi, Abhijit Madhu Kumar, Qingyu Lin, Raj Mitra, and William Winkeler2018Presentation2018presentation
Universal Scripting Interface for SystemCRolf Meyer, Jan Wagner, Rainer Buchty, and Mladen Berekovic2015Paper2015paper
Universal Scripting Interface for SystemCRolf Meyer2015Presentation2015presentation
UPF Power Models: Empowering the power intent specificationAmit Srivastava and Harsh Chilwal2018Paper2018paper
UPF: How to avoid traps in a Hierarchical Implementation Low Power flow?Frederic Saint-Preux,2017Presentation2017presentation
UPF: How to avoid traps in a Hierarchical Implementation Low Power flow?Frederic Saint-Preux2017Paper2017paper
Use of CDC-jitter-modeling in clock-domaincrossing- circuits in RTL design phaseJan Hayek, Jochen Neidhardt, and Robert Richter2017Paper2017paper
Use of CDC-Jitter-Modeling inClock-Domain-Crossing-Circuits in RTL Design PhaseJan Hayek, JochenNeidhardt, and Robert Richter2017Presentation2017presentation
Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Said Hamdioui, and Christian Sauer2018Paper2018paper
Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262Felipe A. da Silva, Ahmet C. Bagbaba, Said Hamdioui and Christian Sauer2018Presentation2018presentation
Use Stimulus Domain for Systematic Exploration of Time Dimension and Automatic Testcase ConstructNing Chen and Martin Ruhwandl2018Paper2018paper
Using an Enhanced Verification Methodology for Back-to-Back RTL/TLM SimulationFrank Poppen, Ralph Görgen, Kai Schulz, Andreas Mauderer, Jan-Hendrik Oetjens, Robert Bosch, Joachim Gerlach, and Hochschule Albstadt-Sigmaringen2017Paper2017paper
Using an Enhanced Verification Methodology for Back-to-Back RTL/TLM SimulationFrank Poppen, Ralph Görgen, Kai Schulz, Andreas Mauderer, Jan-Hendrik Oetjens, Robert Bosch, Joachim Gerlach, and Hochschule, Albstadt-Sigmaringen2017Presentation2017presentation
Using Cadence and MathWorksTools Together for Mixed-Signal Design and VerificationGraham Reith and Andrew Beckett2017Presentation2017presentation
Using Constraints for SystemC AMS Design and VerificationThilo Vörtler, Karsten Einwich, Muhammad Hassan, and Daniel Große2018Paper2018paper
Using Constraints for SystemC AMS Design and VerificationThilo Vörtler, Karsten Einwich, Muhammad Hassan, and Daniel Große2018Presentation2018presentation
Using Dependency Injection Design Pattern in Power Aware TestsMehmet Tukel, Luca Sasselli, David Guthrie2021Paper2021paper
Using Formal to Prevent DeadlocksAbdelouahab Ayari, Mark Eslinger and Joe Hupcey III2020Paper2020paper
Using High-level Synthesis and Emulation to Rapidly Develop AI Algorithms in HardwareJohn Stickley and Petri Solanti2018Presentation2018presentation
Using HLS to improve Design-for-Verification of multi-pipeline designs with resource sharingSarmad Dahir, Nils Luetke-Steinhorst, Christian Sauer2021Paper2021paper
Using Mutation Coverage for Advanced Bug Hunting and Verification SignoffNicolae Tusinschi2018Presentation2018presentation
Using UVM-ML library to enable reuse of TLM2.0 models in UVM test benchesSamah Dahir2018Presentation2018presentation
Using UVM-ML library to enable reuse of TLM2.0 models in UVM test benchesSarmad Dahir, Hans-Martin Bluethgen, Rafael Zuralski, Nils Luetke-Steinhorst, and Christian Sauer2018Paper2018paper
UVM & Emulation Architecting SystemVerilog UVM Testbenches for Simulation-Emulation Portability to Boost Block-to-System Verification Productivity – TutorialHans van der Schoot and Ellie Burns-Brookens2014Presentation2014presentation
UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-upHans van der Schoot and Ahmed Yehia2015Paper2015paper
UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-upHans van der Schoot and Ahmed Yehia2015Poster2015poster
UVM Audit Tutorial Assessing UVM Testbenches to Expose Coding Errors & Improve QualityMark Litterick 2018Presentation2018presentation
UVM based Hardware/Software Co- Verification of a HW Coprocessor using Host Execution TechniquesFrançois Cerisier, Christian Rivier, Andrea Battistella, and Arnaud Grasset2018Presentation2018presentation
UVM based Hardware/Software Co-Verification of a HW Coprocessor using Host Execution TechniquesFrançois Cerisier, Christian Rivier, Andrea Battistella and Arnaud Grasset2019Presentation2019presentation
UVM goesUniversal -IntroducingUVM in SystemCStephan Schulz, Thilo Vörtler, and Martin Barnasconi2015Presentation2015presentation
UVM hardware assisted acceleration with FPGA co-emulationAlex Grove2015Presentation2015presentation
UVM Made Language Agnostic – Introducing UVM For SystemC Application of UVM-SystemCAkhila M2017Paper2017paper
UVM Made Language Agnostic: Introducing UVM For SystemCAkhila M2017Presentation2017presentation
UVM mixed signal extensionsSharing Best Practice and Standardization IdeasJoen Westendorp, Sebastian Simon, and Joachim Geishauser2018Presentation2018presentation
UVM Rapid Adoption: A Practical Subset of UVMStuart Sutherland and Tom Fitzpatrick2015Presentation2015presentation
UVM Ready: Transitioning Mixed-Signal Verification Environments to Universal Verification MethodologyArthur Freitas, Régis Santonja2014Paper2014paper
UVM Ready: Transitioning Mixed-Signal Verification Environments to Universal Verification MethodologyArthur Freitas, Régis Santonja2014Presentation2014presentation
UVM Register Map Dynamic ConfigurationMatteo Barbati and Alberto Allara2018Presentation2018presentation
UVM Register Map Dynamic ConfigurationMatteo Barbati and Alberto Allara2018Paper2018paper
UVM SystemC Functional coverage & constrained randomizationStephan Gerth, Dragos Dospinescu, Muhammad Hassan, Thilo Vörtler and Manuel Soto 2019Presentation2019presentation
UVM-Light A Subset of UVM for Rapid AdoptionStuart Sutherland and Tom Fitzpatrick2015Paper2015paper
UVM-Multi-Language Hands-OnThorsten Dworzak and Angel Hidalga2017Presentation2017presentation
UVM-Multi-Language Hands-On Integrating a System-C model into a SV-UVM testbenchThorsten Dworzak and Angel Hidalga2017Paper2017paper
UVM-SystemC Applications in the real worldStephan Schulz, Thilo Vörtler, and Martin Barnasconi2014Presentation2014presentation
UVM-SystemC based hardware in the loop simulations for accelerated Co-VerificationPaul Ehrlich, Thang Nguyen, and Thilo Vörtler2014Paper2014paper
UVM-SystemC based hardware in the loop simulations for accelerated Co-VerificationPaul Ehrlich, Thang Nguyen, and Thilo Vörtler2014Presentation2014presentation
UVM-SystemC: Migrating complex verification environmentsStephan Gerth and Akhila Madhukumar2017Presentation2017presentation
Validation of Timing Constraints on RTL Reducing Risk and Effort on Gate-LevelPeter Limmer, Dirk Moeller, Marcus Mueller and Clemens Roettgermann2016Presentation2016presentation
Validation of Timing Constraints on RTL Reducing Risk and Effort on Gate-LevelPeter Limmer, Dirk Moeller, Marcus Mueller, and Clemens Roettgermann2016Paper2016paper
Verification Challenges For Deep Color Mode In HDMISnigdha Arora and Apoorva Mathur2016Presentation2016presentation
Verification Challenges for Deep Color Mode in HDMISnigdha Arora and Apoorva Mathur2016Paper2016paper
Verification IP for Complex Analog and Mixed-Signal BehaviorThilo Vörtler and Karsten Einwich2017Presentation2017presentation
Verification IP for Complex Analog and Mixed-Signal BehaviorThilo Vörtler and Karsten Einwich2017Paper2017paper
Verification of a Multi-language Components A case Study: Specman E Env with SV UVM VIPEran Lahav2020Poster, Presentation2020poster presentation
Verification of a Multi-language Components A Case Study: Specman E Environment with SystemVerilog UVMEran Lahav2020Paper2020paper
Verifying Functional, Safety and Security Requirements (for Standards Compliance)Mike Bartley2015Presentation2015presentation
Versatile UVM ScoreboardingJacob Andersen, Peter Jensen, and Kevin Steffensen2014Paper2014paper
Versatile UVM ScoreboardingJacob Andersen, Peter Jensen, and Kevin Steffensen2014Presentation2014presentation
Vertical Reuse of functional verification from subsystem to SoC level (with seamless SoC emulation)Pranav Kumar, Digvijaya Pratap SINGH, and Ankur Jain2014Presentation2014presentation
Virtual Platforms for Automotive: Use Cases, Benefits and ChallengesAngela Kramer and Martin Vaupel 2014Presentation2014presentation
Virtual Platforms for complex IP within system contextRocco Jonack2015Presentation2015presentation
Virtual Prototypes and PlatformsA PrimerEyck Jentzsch, Rocco Jonack, and Josef Eckmüller2017Presentation2017presentation
Virtual Prototyping in SpaceFibre System-on-Chip DesignIlya Korobkov2015Presentation2015presentation
Virtual Prototyping in SpaceFibre System-on-Chip Design System-level designElena Suvorova2015Paper2015paper
Virtual Prototyping of Power Converter Systems based on AURIX™ using SystemC AMSRadovan Vuletic, Dineshkumar Selvaraj, Thomas Arndt2021Paper2021paper
Virtual Prototyping using SystemC and TLM-2.0John Aynsley2014Presentation2014presentation
VP Performance Optimization – How to analyze and optimize the speed of SystemC TLM models?Rocco Jonack and Juan Lara Ambel2014Paper2014paper
VP Performance Optimization – How to analyze and optimize the speed of SystemC TLM models?Rocco Jonack and Juan Lara Ambel2014Presentation2014presentation
Wave Digital Filter Modeling for Complex Automotive Sensor Load Case VerificationAndrei-Daniel Basa, Thang Nguyen, and Dirk Hammerschmidt2015Paper2015paper
Wave Digital Filter Modeling for Complex Automotive Sensor Load Case VerificationA. Basa, T. Nguyen, and D. Hammerschmidt2015Presentation2015presentation
Web Template Mechanisms in SOC VerificationAlberto Allara, Via Tolomeo, Rinaldo Franco, and Via Remo2015Paper2015paper
Web Template Mechanisms in SOC VerificationRinaldo Franco and Alberto Allara2015Presentation2015presentation
What is needed on top of TLM-2 for bigger Systems?Jerome Cornet and Martin Schnieringer2015Presentation2015presentation
What is next for SystemC Synthesizable Subset?Peter Frey2016Paper2016paper
Who takes the driver seat for ISO 26262 and DO 254 verification?Avidan Efody2015Paper2015paper
Who takes the driver seat for ISO 26262 and DO 254 verification?Avidan Efody2015Presentation2015presentation
YAMMYet Another Memory ManagerAndrei Vintila and Ionut Tolea2016Presentation2016presentation
Yet Another Memory Manager (YAMM)Ionut Tolea and Andrei Vintila2016Paper2016paper