DVCon: India

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“What-If” analysis of Safety Mechanism’s impacts on ETHMAC design under Functional Safety flowUdaykrishna J, Sujatha Hiremath, Kapil Kumar, Sachin Pathak, Gaurav Goel2022Presentation2022presentation
A 360 Degree View of UVM EventsVikas Billa, Nagesh Kokonda2017Presentation2017presentation
A Framework for Verification of Program Control Unit of VLIW processorsSanthosh Billava, Sharangdhar M Honwadkar2014Presentation2014presentation
A Framework for Verification of Program Control Unit of VLIW ProcessorsSanthosh Billava, Sharangdhar M Honwadkar2014Paper2014paper
A Generic Configurable Error Injection Agent for All On-Chip MemoriesNiharika Sachdeva, Arjun Suresh Kumar, Raviteja Gopagiri, Anil Deshpande, Somasunder Kattepura Sreenath, Damandeep Saini2022Presentation2022presentation
A Generic Configurable Error Injection Agent for On-Chip MemoriesNiharika Sachdeva, Arjun Suresh Kumar, Raviteja Gopagiri, Anil Deshpande, Somasunder Kattepura Sreenath2022Paper2022paper
A Holistic Overview on Preventive & Corrective Action To Handle GlitchesRohit Kumar Sinha, Parimal Das2022Poster2022poster
A Method to Accelerate SoC Implementation Cycle by Automatically Generating CDC ConstraintsAshish Hari, Sulabh Kumar Khare2015Presentation2015presentation
A Methodology for Interrupt Analysis in Virtual PlatformsPuneet Dhar2015Presentation2015presentation
A Methodology for Using Traffic Generators with Real-Time ConstraintsAvinash Mehta2015Presentation2015presentation
A Methodology to Reuse Unit Level Validation InfrastructureAshutosh Parkhi2017Presentation2017presentation
A New Epoch is Beginning: Are You Getting Ready for Stepping Into UVM-1.2?Roman Wang, Uwe Simm2014Poster2014poster
A New Epoch is Beginning: Are You Getting Ready for Stepping Into UVM-1.2?Roman Wang,Uwe Simm2014Paper2014paper
A Novel Approach to Hardware Controlled Power Aware Verification with Optimized Power Consumption Techniques at SOCEldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Paper2022paper
A Novel Approach to Reduce Power Consumption By Bridging The Gap between Standalone Functional Scenario and Real Time Scenario at SOCEldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath2022Poster2022poster
A Pragmatic Approach Leveraging Portable Stimulus from Subsystem to SoC level and SoC EmulationKarandeep Singh, Aditya Chopra, Joachim Geishauser, Nitin Verma2019Presentation2019presentation
A Pragmatic Approach Leveraging Portable Stimulus from Subsystem to SoC level and SoC EmulationKarandeep Singh, Aditya Chopra, Joachim Geishauser, Nitin Verma2019Paper2019paper
A Real-World Clock Generator Class for UVMRhitam Datta, Ankit Somani2017Presentation2017presentation
A Recipe for swift Tape-out of Derivative SoCs: A Comprehensive Validation Approach using Formal-based Sequential Equivalence and Connectivity CheckingPriyanshu Jain, Saket Gaddagi, Sandeep Kumar and Ipshita Tripathi2022Presentation2022presentation
A Reusability Combat in UVM Callbacks vs FactoryDeepak Kumar EV, Vikas Billa, Satish Dadi, Ranganath Kempanahally2015Poster2015poster
A scalable framework to validate interconnect-based firewalls to enhance SoC security coverageAshutosh Mishra, Suresh Vasu2022Paper2022paper
A scalable framework to validate interconnect-based firewalls to enhance SoC security coverageAshutosh Mishra, Suresh Vasu2022Presentation2022presentation
A Systematic Methodology for Verifying Clock Domain Crossing ReconvergencePriya Viswanathan2017Presentation2017presentation
A Unified Framework for Multilanguage Verification IPs IntegrationSurinder Sood, Selvakumar Krishnamoorthy, Guarav Jalan2015Presentation2015presentation
A UVM Based Methodology for Processor VerificationAbhineet Bhojak, Tejbal Prasad2015Presentation2015presentation
Absolute GLS Verification An Early Simulation of Design Timing ConstraintsAteet Mishra, Deepak Mahajan, Shiva Belwal2015Presentation2015presentation
Accelerating ML TB Integration for Reusability Using UVM ML OASaleem Khan, Prasanna Kumar2017Presentation2017presentation
Accelerating Semiconductor Time to ISO 26262 ComplianceKirankumar Karanam2022Presentation2022presentation
Accelerating the SoC Integration Verification Cycle Time Leveraging the Legacy Design ConfidenceAbhinav Parashar, Prasanth Kumar Narava2022Paper2022paper
Accelerating the SoC Integration Verification Cycle Time Leveraging the Legacy Design ConfidenceAbhinav Parashar, Prasanth Kumar Narava2022Presentation2022presentation
Accellera Systems Initiative SystemC Standards UpdateBishnupriya Bhattacharya2015Presentation2015presentation
Achieve Faster Debug Closure by Applying Big Data & Advanced RCA TechnologiesSundararajan Ananthakrishnan, Sundararajan PH2022Presentation2022presentation
Achieving Real Time Performance for Algorithms Using SOC TLM ModelSaurin Patel, Pushkar Sareen, Sharath Naidu, Baljinder S Sood2015Presentation2015presentation
Adaptive UVM AMOD Testbench for Configurable DSI IPKrishnapal Singh, Pavan Yeluri, Ranjith Nair2019Paper2019paper
Adding Agility to Hardware Design-Verification using UVM & AssertionsFrancois Cerisier, Ajeetha Kumari, Gurubasappa, Srujana Reddy2017Presentation2017presentation
Addressing the Challenges of ABV in Complex SOCsRithin A N, Arif M, Rupinjeet Singh, Jeevan2015Poster2015poster
Adopting UVM for FPGA VerificationKamalesh Vikramasimhan, Shridevi Biradar2017Presentation2017presentation
Advanced UVM Coding TechniquesDavid Long2016Presentation2016presentation
Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IPEldhose P.M, Sagar Jayakrishnan, Suraj Vijay Shetty, Kuntal Pandya, Parag S. Lonkar2022Paper2022paper
Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IPEldhose P.M, Sagar Jayakrishnan, Suraj Vijay Shetty, Kuntal Pandya, Parag S. Lonkar2022Presentation2022presentation
AMS Verification at SoC Level: A Practical Approach for Using VAMS vs SPICE ViewsNitin Pant, Gautham Harinarayan, Manmohan Rana2015Presentation2015presentation
An Automated Systematic CDC Verification Methodology based on SDC SetupAshish Hari, Sulabh Kumar Khare2014Presentation2014presentation
An Industry Proven UVM Reuse Methodology for Coverage Driven Block Level Verification to SW Driven Chip Level Verification Across Simulation & EmulationPradeep Salla, Keshav Joshi2016Presentation2016presentation
An Introduction to the Accellera Portable Stimulus StandardSrivatsa Vasudevan, Pradeep Salla, Sharon Rosenberg, Adnan Hamid, Karthick Gururaj, Srivatsa Vasudevan, Bishnupriya Bhattacharya2017Presentation2017presentation
ARC EM Core with Safety Package – ISO 26262 CertificationVikas Bhandari2015Poster2015poster
Architecturally Scalable Testbench for Complex SoCSenthilnath Subbarayan, Arulanandan Jacob, Sandeep Kumar2019Paper2019paper
Assisting Fault Injection Simulations for Functional Safety Sign-off using FormalPulicharla Ravindrareddy2019Presentation2019presentation
Assisting Fault Injection Simulations for Functional Safety Sign-off using FormalPulicharla Ravindrareddy2019Paper2019paper
Automated code generation for Early AURIX TM VPPratheek Mahesh and Dineshkumar Selvaraj2021Poster2021poster
Automated code generation for Early AURIX TM VPPratheek Mahesh and Dineshkumar Selvaraj2021Presentation2021presentation
Automated correct-by-construct methodology for RTL design and analog mixed-signal test bench generation: Enables early design closure of mixed-signal SoCLakshmanan Balasubramanian, Murugesh Prashanth Subramaniam, Atul Ramakant Lele, and Ranjit Kumar Dash2014Paper2014paper
Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual PrototypeS N Ranjan and Puttaiah Jagadish2021Presentation2021presentation
Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual PrototypeS N Ranjan and Puttaiah Jagadish2021Poster2021poster
Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual PrototypeS N Ranjan and Puttaiah Jagadish2021Presentation2021presentation
Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual PrototypeS N Ranjan and Puttaiah Jagadish2021Poster2021poster
Automated Traffic Simulation Framework for SoC Performance AnalysisDiviya Jain, Tarun Kathuria 2017Presentation2017presentation
Automated vManager regression using JenkinsSneha Gokarakonda2022Poster2022poster
Automated, Systematic CDC Verification Methodology Based on SDC SetupAshish Hari, Sulabh Kumar Khare2014Paper2014paper
Automatic Generation of Infineon Microcontroller Product ConfigurationsPrateek Chandra, Leily Zafari, Boyko Traykov2019Presentation2019presentation
Automatic Generation of Infineon Microcontroller Product ConfigurationsPrateek Chandra, Leily Zafari, Boyko Traykov2019Paper2019paper
Automatically Synthesizing Higher Level of Protocol Abstraction for Faster Debug and Deeper Insight Into Modern Digital DesignsAlasdair Ferro, Amar Patel, Chris Jones, Yogesh Badaya2019Paper2019paper
Automating information retrieval from EDA software reports using effective parsing algorithmsManish Bhati2022Poster2022poster
Automation of Waiver and Design Collateral generation for scalable IPsGopalakrishnan Sridhar, Vadlamuri Venkata Sateeshm, Midhun Krishna2019Paper2019paper
Automation of Waiver and Design Collateral Generation on Scalable IPsGopalakrishnan Sridhar, Midhun Krishna, Vadlamuri, Venkata Sateesh2019Presentation2019presentation
Back to Basics: Doing Formal “The Right Way”Joseph Hupcey III, Saumitra Goel 2017Presentation2017presentation
Benefits of PSS coverage at SOC & its limitationsSundararajan Haran and Saleem Khan2019Presentation2019presentation
Benefits of PSS Coverage at SOC and Its LimitationsSundararajan Haran, Saleem Khan2019Paper2019paper
Break the SoC with Random UVM Instruction DriverBogdan Todea, Pravin Wilfred, Madhukar Mahadevappa, Diana Dranga2019Paper2019paper
Bring IP Verification Closer to SoC Scalable Methods to Bridge the Gap Between IP and SoC VerificationGaurav Gupta, Tejbal Prasad, Rohit Goyal, Sachin Jain, Vipin Verma2014Paper2014paper
Bring IP Verification Closer to SoC Scalable Methods to Bridge the Gap Between IP and SoC VerificationGaurav Gupta, Tejbal Prasad, Rohit Goyal, Sachin Jain, Vipin Verma2014Presentation2014presentation
Bringing DataPath Formal to Designers’ FootstepsM, Achutha KiranKumar V, Disha Puri, Shriya Dharade2019Paper2019paper
Bringing Reset Domains and Power Domains together – Non resettable registers amplifying issues in Power-Aware RDC Verification due to UPF InstrumentationManish Bhati, Inayat Ali2022Presentation2022presentation
Building And Modelling Reset Aware Testbench For IP Functional VerificationNaishal Shah2019Paper2019paper
Building Configurable UVM Testbench for Configurable Design IP (Configurable TB)Kilaru Vamsikrishna, Sushrut B Veerapur2022Presentation2022presentation
Building UVM Testbenches for High Quality Serial Design IPs Modelling real world scenariosKilaru Vamsikrishna, Sushrut B Veerapur2022Poster2022poster
Case-study: Generating A Workload Model of the Chrome Browser from Android Execution Traces For Early Analysis of Power and Performance Trade-offsVikrant Kapila, Tim Kogel, Holger Keding, Amit Tara Amit Dudeja, Nishant Gautam2017Presentation2017presentation
Challenges in Mixed Signal VerificationAmlan Chakrabarti, Sachin-Sudhakar Kulkarni2015Presentation2015presentation
Challenges of Formal Verification on Deep Learning Hardware AcceleratorYellinidi Dasarathanaidu2019Presentation2019presentation
Challenges of Formal Verification on Deep Learning Hardware AcceleratorYellinidi Dasarathanaidu2019Paper2019paper
Challenges with Power Aware Simulation and Verification MethodologiesDivyeshkumar Vora2015Presentation2015presentation
Challenges, Complexities and Advanced Verification Techniques in Stress Testing of Elastic Buffer in High Speed SERDES IPsKamesh Velmail, Suvadeep Bose, Ankit Garg, Parag S Lonkar, Somasunder K Sreenath2019Presentation2019presentation
Challenges, Complexities and Advanced Verification Techniques in Stress Testing of Elastic Buffer in High Speed SERDES IPsKamesh Velmail, Suvadeep Bose, Parag Lonkar, Ankit Garg2019Paper2019paper
Channel Modelling in Complex Serial IPsJayesh Ranjan Majhi, Saravana Balakrishnan, Navnit Kumar Kashyap2022Poster2022poster
Channel Modelling in Complex Serial IPsJayesh Ranjan Majhi, Saravana Balakrishnan, Navnit Kumar Kashyap2022Paper2022paper
Choice is Yours: Either Struggle to Tame ‘X’ in the Wilderness of Multimillion Gates and Nets, OR Take it for a Walk in the RTL ParkNitin Jaiswal, Harsh Garg, Mayank Bindal2014Presentation2014presentation
Complementing Verification of Highly Configurable Design with Formal TechniquesManik Tyagi, Deepak Jindal2015Poster2015poster
Compliance Driven Integrated Circuit Development Based on ISO26262Haridas Vilakathara, Manikantan panchapakesan2014Presentation2014presentation
Compliance Driven Integrated Circuit Development Based on ISO26262Haridas Vilakathara and Manikandan Panchapakesan2014Paper2014paper
Compute Link Express – CXL – CXL ConsortiumNarasimha Babu2022Presentation2022presentation
Configurable Testbench (TB) for Configurable Design IPKilaru Vamsikrishna, Sushrut B Veerapur2022Paper2022paper
Configuration in UVM:The Missing ManualMark Glasser2014Presentation2014presentation
Configuration in UVM: The Missing ManualMark Glasser2014Paper2014paper
Coverage Closure – Is it a “Game of Dice” or “Top 10 Tests” or “Automated Closure”?Aditya Sharma, T. Nagasundaram, M. Nitin Kumar, Nikhita Raj J 2015Presentation2015presentation
Cross-Domain Datapath Validation Using Formal Proof AcceleratorsAarti Gupta, S. S. Bindumadhava, M. Achutha KiranKumar V, Liu Jun B2014Presentation2014presentation
Data Flow Based Memory IP Creation InfrastructureAbhilash V Nair, Praveen Buddireddy, Tor Jeremiassen, Rashmi Venkatesh, and Prajakta Bhutada2014Paper2014paper
DDR Controller IP Evaluation Studies using Trace Based MethodologyAbhilash Nair, Amit Nene, Ritesh Sojitra, Prashant Karandikar and Prajakta Bhutada2014Paper2014paper
Debug Time Reduction by Automatic Generation of Waiver List Using ML TechniquesVardhana M, Akshay Jain, Kota Subba Rao Sajja2022Presentation2022presentation
Debugging Linux Kernel Failures on Virtual PlatformSandeep Jain2017Presentation2017presentation
Design & Verify Virtual Platform with reusable TLM 2.0Ankush Kumar2015Presentation2015presentation
Design Methodology for Highly Cycle Accurate SystemC Models with Better PerformanceSimranjit Singh, Prasanth Sasidharan, Sameer Deshpande, and Sandeep Puttappa2014Paper2014paper
Design space exploration of PIM (Processing in Memory) & PNC (Processing Near Memory) based on workload characterizationAmarnath, Judhajit2022Presentation2022presentation
Designing A PSS Reuse StrategyMatthew Ballance2019Paper2019paper
Digital mixed-signal low power verification with Unified Power Format (UPF)Srilakshmi D R and Geeta Krishna Chaitanya Puli2021Poster2021poster
Digital mixed-signal low power verification with Unified power format (UPF)Srilakshmi D R and Geeta Krishna Chaitanya Puli2021Presentation2021presentation
Digital Transformation of EDA Environments To Accelerate Semiconductor InnovationGuru Charan Prasad Jonnalagadda2022Presentation2022presentation
Disciplined Post Silicon Validation using ML IntelligenceAmaresh Chellapilla, Pandithurai Sangaiyah2022Presentation2022presentation
Driving Analog Stimuli from a UVM TestbenchSatvika Challa, Amlan Chakrabarti 2015Poster2015poster
DV Methodology to Model Scalable/Reusable Component to Handle IO Delays/Noise/Crosstalk in Multilane DDR PHY IFTapas Ranjan Jena, Gowdra Bomanna Chethan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath2019Paper2019paper
DVCon India 2021 ProceedingsAccellera Systems Initiative2021Video2021video
DVCon India 2022 Proceedings2022Video2022video
Dynamic Parameter Configuration of SystemC ModelsShruti Baindur, Simranjit Singh2015Presentation2015presentation
Dynamic Power Automation UVM FrameworkRaghavendra J N, Gudidevuni Harathi2015Poster2015poster
Easier UVM – Making Verification Methodology More ProductiveJohn Aynsley, David Long2014Presentation2014presentation
Effective Formal Deadlock Verification Methodologies for Interconnect designSachin Kumar, Rajesh C M2022Presentation2022presentation
Efficacious verification of Loopback and Equalization in PCIe By Using Novel approachJaydeep Suvariya, Pinal Patel2022Presentation2022presentation
Efficient and Faster Handling of CDC/RDC ViolationsAshish Kumar Gupta2017Presentation2017presentation
Efficient Formal strategies to verify the robustness of the designSakthivel Ramaiah2022Paper2022paper
Efficient Formal strategies to verify the robustness of the designSakthivel Ramaiah2022Presentation2022presentation
Efficient methods for analog mixed signal verification Interface handling methods, trade-offs and guidelinesLakshmanan Balasubramanian, Shoeb Siddiqui, and Vijay Kumar Sankaran2014Paper2014paper
Efficient Regression Management with Smart Data Mining TechniqueTejbal Prasad2022Paper2022paper
Efficient Regression Management with Smart Data Mining Technique Tejbal Prasad2022Presentation2022presentation
Efficient Verification of Mixed-Signal SerDes IP Using UVMVarun R, Vinayak Hegde, Cadence Bangalore2017Presentation2017presentation
Effortless, Methodical and Exhaustive Register Verification using what you already haveAishwarya Sridhar, Pallavi Atha, and David Crutchfield2021Poster2021poster
Effortless, Methodical and Exhaustive Register Verification using what you already have.Aishwarya Sridhar, Pallavi Atha, and David Crutchfield2021Presentation2021presentation
Embedded UVMPuneet Goel2017Presentation2017presentation
Embrace Errors! Architecting UVM Testbenches for Dynamic Error Injection & HandlingSushrut B Veerapur, Kilaru Vamsikrishna2022Poster2022poster
Embracing Datapath Verification with Jasper C2RTL AppVaibhav Mittal, Sourav Roy, Anshul Singhal2022Presentation2022presentation
Embracing Formal Verification for Data Path Designs Using Golden SpecsAchutha Kirankumar V, Disha Puri, Bindumadhava S.S2017Presentation2017presentation
Enabling Exhaustive Reset Verification Enablement: Client PCIE Design Reset Verification Case StudyRohit Kumar Sinha, Praveen Dornala2019Presentation2019presentation
Enabling high quality design sign-off with Jasper structural and auto formal checksVishnu Haridas, Mansi Rastogi, Guruprasad Timmapur2022Paper2022paper
Enabling high quality design sign-off with structural and auto formal checksTimmapur, Guruprasad Haridas, Vishnu Rastogi, Mansi2022Presentation2022presentation
Enabling Shift-Left through FV Methodologies on Intel® Graphics DesignsM. Achutha KiranKumar V, Aarti Gupta Bindumadhava S S, Aishwarya R2015Presentation2015presentation
Engaging with IEEE through StandardsSri Chandra, Dennis Brophy2022Presentation2022presentation
Enhanced LDPC Codec Verification in UVMShriharsha Koila, Ganesh Shetti, Prateek Jain, Anand Shirahatti2019Paper2019paper
Enhancing Productivity in Formal Testbench Generation for AHB based IPsShubham Goyal, Ishan Patil, Senthilnath Subbarayan, and Sandeep Kumar2021Poster2021poster
Enhancing The Effectiveness of a Constrained Random Test Suite Using Supervised Machine Learning AlgorithmPonnambalam Lakshmanan, Rajarathinam Susaimanickam2017Presentation2017presentation
Ensuring Quality of Next Generation Automotive SoC: System’s ApproachPankaj Singh2015Presentation2015presentation
Essential Adjuncts of Verification InfrastructureKunal Panchal, Harshit Mehta2017Presentation2017presentation
Exhaustive Reset Verification Enablement: Client PCIE Design Reset Verification Case StudyRohit Kumar Sinha, Praveen Dornala2019Paper2019paper
Exhaustive validation of a cache memory controller using Formal Verification to meet performance and timing requirementsHimani Jawa, Nishant Raman, Sini Balakrishnan, Manas Karanjekar2022Paper2022paper
Exhaustive validation of a cache memory controller using Formal Verification to meet performance and timing requirementsHimani Jawa, Nishant Raman, Sini Balakrishnan, Manas Karanjekar2022Presentation2022presentation
Expedite any Simulation with DMTCP and Save Decades of ComputationBalaji R, Sathish Kumar Sugumaran, Rohan Garg, Jiajun Cao2017Presentation2017presentation
Expediting the Code Coverage Closure Using Static Formal Techniques – A Proven Approach at Block and SoC Levels2015Presentation2015presentation
Expediting Verification of Critical SoC Components Using Formal MethodsNuni Srikanth, Lakshman Easwaran, Maddipatla Shankar Naidu2014Presentation2014presentation
Extending a Traditional VIP to Solve PHY Verification ChallengesAmit Tanwar, Manoj Manu2015Presentation2015presentation
Fault Campaign Framework for FuSa Verification of ISO 26262 Compliant Automotive ProductsPrashantkumar Ravindr, Mangesh Pande, and Vinay Rawat2021Presentation2021presentation
Fault Campaign Framework for FuSa Verification of ISO 26262 Compliant Automotive ProductsPrashantkumar Ravindra, Mangesh Pande, and Vinay Rawat2021Poster2021poster
Fault Injection Made Easy Unified Formal Verification of Normal and Safety FunctionsSergio Marchese, Jörg Grosse, Ashish Darbari2017Presentation2017presentation
Fault Injection Strategy to Validate ASIL-D Requirements of BMS ComponentsPraneeth Uddagiri, Veera Satya Sai Gavirni, Prashantkumar Ravindra2022Paper2022paper
Fault Injection Strategy to Validate ASIL-D Requirements of BMS ComponentsPraneeth Uddagiri, Veera Satya Sai Gavirni, Prashantkumar Ravindra2022Presentation2022presentation
Filtering noise in RDC analysis by clockoff specificationAnupam Saxena, Inayat Ali, Sulabh Kumar Khare and Atul Sharma2021Presentation2021presentation
Formal Assisted Fault Campaign for ISO26262 CertificationNitin Ahuja, Mayank Agarwal, Sandeep Jana2019Paper2019paper
Formal For Adjacencies Expanding the Scope of Formal VerificationM Achutha KiranKumar V, Bindumadhava Ss., Vichal Verma, Savitha Manojna2019Presentation2019presentation
Formal for Adjacencies Expanding the Scope of Formal VerificationM Achutha KiranKumar V, Bindumadhava Ss., Vichal Verma, Savitha Manojna2019Paper2019paper
Formal verification of low-power RISC-V processorsAshish Darbari2019Paper2019paper
FPGA Implementation Validation and DebugRohit Goel, Rakesh Jain, Aman Rana, Ankit Goel2015Presentation2015presentation
Framework for Creating Performance Model of AI Algorithms for Early Architecture ExplorationAmit Dudeja, Amit Tara, Amit Garg, Tushar Jain2019Presentation2019presentation
Framework for Creating Performance Model of AI Algorithms for Early Architecture ExplorationAmit Dudeja, Amit Tara, Amit Garg, Tushar Jain2019Paper2019paper
Framework For Exploring Interconnect Level Cache CoherencyParvinder Pal Singh2017Presentation2017presentation
Framework for Holistic Assessment of Potential Performance Gains with Different Simulation Acceleration ModesParag Goel, Adiel Khan, Amit Sharma2015Presentation2015presentation
From Device Trees to Virtual PrototypesSakshi Arora, Vikrant Kamboj, Preeti Sharma2019Paper2019paper
Functional Coverage GeneratorMunjal Mistry2017Presentation2017presentation
Functional Safety Verification Methodology for ASIL-B Automotive DesignsOnkar Bhuskute2022Poster2022poster
Functional Verification of CSI2 Rx-PHY using AMS Co-simulationsRatheesh Mekkadan2014Presentation2014presentation
Functional Verification of CSI-2 Rx-PHY using AMS Co-simulationsRatheesh Mekkadan2014Presentation2014presentation
Functional Verification of CSI-2 Rx-PHY using AMS Co-simulationsRatheesh Mekkadan2014Paper2014paper
Functional-Coverage Sampling in UVM RAL Use of 2 Obscure MethodsMuneeb Ulla Shariff, Ravi Reddy2019Paper2019paper
Functional-Coverage Sampling in UVM RAL: Use of 2 Obscure MethodsMuneeb Ulla Shariff, Ravi Reddy2019Presentation2019presentation
Gatelevel Simulations: Continuing Value in Functional SimulationAshok Chandran, Roy Vincent2014Paper2014paper
Gatelevel Simulations: Continuing Value in Functional SimulationsAshok Chandran, Roy Vincent2014Poster2014poster
Generic Solution for NoC design explorationTushar Garg2021Poster2021poster
Generic Solution for NoC design explorationTushar Garg and Ranjan Mahajan2021Presentation2021presentation
Generic Solution for NoCdesign explorationTushar Garg and Ranjan Mahajan2021Presentation2021presentation
Generic Solution for NoCdesign explorationTushar Garg and Ranjan Mahajan2021Poster2021poster
Generic Verification Infrastructure around Serial Flash ControllersHarsimran Singh, Snehlata Gutgutia, Chanpreet Singh2015Presentation2015presentation
Get Ready for UVM-SystemCMartin Barnasconi, Anupam Bakshi2015Presentation2015presentation
Global Broadcast with UVM Custom PhasingJeremy Ridgeway, Dolly Mehta2014Presentation2014presentation
Global Broadcast with UVM Custom PhasingJeremy Ridgeway and Dolly Mehta2014Paper2014paper
Goal Driven Stimulus Solution Get Yourself Out of the Redundancy TrapRohit Bansal2019Presentation2019presentation
Goal Driven Stimulus Solution Get Yourself Out of the Redundancy TrapRohit Bansal2019Paper2019paper
Hardware Implementation of Smallscale Parameterized Neural Network Inference EngineVishnu P Bharadwaj, Shruti Narake, Saurabh D Patil2019Paper2019paper
Hardware Security – Industry Trends, Attacks and SolutionsShashank Kulkarni2022Presentation2022presentation
Hardware verification through software scheduling for USB using xHCIWasiq Zia, Navneet Jha, and Vipin Chauhan2021Poster2021poster
Hardware verification through software scheduling for USB using xHCIWasiq Zia, Navneet Jha, and Vipin Chauhan2021Presentation2021presentation
Hardware verification through software scheduling for USB using xHCITheWasiq Zia, Navneet Jha, and Vipin Chauhan2021Poster2021poster
Hardware verification through software scheduling for USB using xHCITheWasiq Zia, Navneet Jha, and Vipin Chauhan2021Presentation2021presentation
Hardware/Software Co-Verification Using Generic Software AdapterVijaya Bhaskar, Krishna Chaitanya, Kirtika Sharma2017Presentation2017presentation
Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex PMIC designed for SSD ApplicationsVijay Kumar, Shrikant Pattar, Yaswanth Chebrolu, Vinayak Hegde2022Paper2022paper
Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex PMIC designed for SSD ApplicationsVijay Kumar, Shrikant Pattar, Yaswanth Chebrolu, Vinayak Hegde2022Presentation2022presentation
Has The Performance of a Sub-System Been Beaten to DeathSubhash Joshi, Vaddineni Manohar, Sangaiyah Pandithurai2015Presentation2015presentation
High Frequency Response Tracking System micro-architectureGopalakrishnan Sridhar, Vadlamuri Venkata Sateesh2019Presentation2019presentation
High Frequency Response Tracking System Micro-architectureGopalakrishnan Sridhar, Vadlamuri Venkata Sateesh2019Paper2019paper
How to Reuse Sequences with the UVM-ML Open Architecture libraryHannes Fröhlich and Kishore Sur2014Poster2014poster
Hybrid Emulation Use CasesSylvain Bayon de Noyer2015Poster2015poster
Hybrid Emulation: Accelerating Software Driven Verification and DebugIssac P Zacharia and Jitendra Aggarwal2021Poster2021poster
Hybrid Emulation: Accelerating Software Driven Verification and DebugIssac P Zacharia and Jitendra Aggarwal2021Presentation2021presentation
Improving Simulation Performance at SoC/Subsystem Level Using LITE Environment ApproachAvni Patel, Heena Mankad2019Paper2019paper
Increase Productivity with Reflection API in Design VerificationShivayogi V. Kerudi, Vijay Mukund Srivastav, Vani S, Brad Quinton2015Poster2015poster
Indago™ Debug Platform Overview2015Presentation2015presentation
Innovative methodologies for analyzing CDC and RDC violations in complex SoC using Automations, formal verification, and Hierarchical CDC modelMaitri Mishra, Dharmendra Kumar2022Presentation2022presentation
Intelligent Coverage Driven, Modern Verification for VHDL Based Designs in Native VHDL with OSVVMVijay Mukund Srivastav, Anupam Maurya, Prabhat Kumar, Juhi2015Presentation2015presentation
Introducing IEEE 1800.2 the Next Step for UVMSrivatsa Vasudevan 2017Presentation2017presentation
Introducing UVM-SystemC For a Resilient And Structured ESL ValidationAkhila M2017Presentation2017presentation
Introduction to Accellera TLM 2.0Aravinda Thimmapuram2015Presentation2015presentation
IP Generators – A Better Reuse MethodologyAmanjyot Kaur2021Presentation2021presentation
IP Generators -A Better Reuse MethodologyAmanjyot Kaur2021Poster2021poster
IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 45 minutes!Nikita Gulliya, Asif Ahmad, Devender Khari2022Presentation2022presentation
Left shift catching of critical low power bugs with Formal VerificationManish Kumar, Madan Kumar, Srobona Mitra, Madhusudhana Lebaka2022Poster2022poster
Left shift catching of critical low power bugs with Formal VerificationManish Kumar, Madan Kumar, Madhusudhana Lebaka, Srobona Mitra2022Paper2022paper
Left shift catching of critical low power bugs with Formal VerificationManish Kumar, Madan Kumar, Madhusudhana Lebaka, Srobona Mitra2022Presentation2022presentation
Left Shift of Perf Validation Using Hardware-Based AccelerationAbhiram.L.S, Anoop.H.C, Vijayakrishnan Rousseau, Vimpesh Kankariya2017Presentation2017presentation
Leveraging ESL Approach to Formally Verify Algorithmic ImplementationsM, Achutha KiranKumar V, Bindumadhava S S, Aarti Gupta, Disha Puri2015Presentation2015presentation
Leveraging IEEE 1800.2-2017 UVM for Improved RAL ModellingVikas Sharma, Manoj Manu, Ankit Garg2019Presentation2019presentation
Leveraging IEEE 1800.2-2017 UVM for Improved RAL ModellingVikas Sharma, Manoj Manu, Ankit Garg2019Paper2019paper
Leveraging RAL and alternate automation (cocotb) techniques to improve Register Verification in UVMSougata Bhattacharjee2022Poster2022poster
Logic Equivalence Check without Low Power – you are at risk!!Aishwarya Nair, Krishna Patel2022Presentation2022presentation
Low Power Emulation for Power Intensive DesignsHarpreet Kaur, Mohit Jain, Piyush Kumar Gupta, Jitendra Aggarwal2014Presentation2014presentation
Low Power Extension In UVM Power ManagementPriyanka Gharat, Shikhadevi Katheriya, Avnita Pal2022Poster2022poster
Low Power Extension in UVM Power ManagementPriyanka Gharat, Avnita Pal, Shikhadevi Katheriya2022Paper2022paper
Low Power Techniques in EmulationPragati Mishra & Jitendra Aggarwal2019Presentation2019presentation
Low Power Validation on Emulation Using Portable Stimulus StandardJoydeep Maitra, Deepinder Singh Mohoora, Vikash Kumar Singh2019Paper2019paper
Low Power Verification Challenges and Coverage Recipe to Sign-Off PA VerificationDeepmala Sachan, Raghavendra Prakash, Venugopal Jennarapu, Syed S Thameem2014Presentation2014presentation
Low power Verification challenges and coverage recipe to sign-off Power aware VerificationDeepmala Sachan, Thameem Syed S, Raghavendra Prakash, Venugopal Jennarapu2014Paper2014paper
Making Formal Property Verification Mainstream: An Intel® Graphics ExperienceM Achutha KiranKumar V, Bindumadhava S S, Abhijith A Bharadwaj2017Presentation2017presentation
Making the Most of the UVM Register Layer and SequencesDavid Long2017Presentation2017presentation
Making Virtual Prototypes WorkKartik Jivani, Jigar Patel2015Presentation2015presentation
Mastering Unexpected Situations SafelySacha Loitz2015Presentation2015presentation
MDLL & Slave Delay Line Performance Analysis Using Novel Delay ModelingAbhijith Kashyap, Avinash Shambu, Kalpesh Shah2014Presentation2014presentation
MDLL & Slave Delay Line Performance Analysis Using Novel Delay ModelingAbhijith Kashyap, Avinash S and Kalpesh Shah2014Paper2014paper
MeSSMArch – A Memory System Simulator for Hardware Multithreading ArchitecturesSushil Menon2015Presentation2015presentation
MeSSMArch – A Memory System Simulator for Hardware Multithreading ArchitecturesSushil Menon2015Paper2015paper
Methodology for Hardware Software Co-verification of Video Systems on Pre and Post SiliconVinesh Peringat2015Presentation2015presentation
Methodology for Hardware Software Co-verification of Video Systems on Pre and Post SiliconVinesh Peringat, Balajee Premraj, Venkatesh Merugu2015Poster2015poster
Methodology for system-level comparison of ARM vs RISC-V cores for latency and power consumptionTom Jose, Deepak Shankar2022Presentation2022presentation
Methodology for Verification Regression Throughput Optimization using Machine LearningArun.K.R, Preetham Lakshmikanthan, and Ashwani Aggarwal2021Poster2021poster
Methodology for Verification Regression Throughput Optimization using Machine LearningArun K.R. Preetham Lakshmikanthan, Ashwani Aggarwal, and Sundararajan Ananthakrishnan2021Presentation2021presentation
MIPI M-PHY Analog Modeling in Verilog-AMS (Wreal) and Verification Using SV/UVM-MS MethodologyMallikarjuna Reddy Y, Venkatramana Rao K, Somanatha Shetty A2015Presentation2015presentation
Model Extraction for Designs Based on Switches for Formal VerificationAmar Patel, Naman Jain2014Paper2014paper
Model Extraction for Designs Based on Switches for Formal VerificationAmar Patel, Naman Jain2014Presentation2014presentation
Network Packet Header Generation Using Graph Based Techniques Combined with Software Testing StrategiesSridevi Navulur, Satheesh Parasumanna, Rama Chaganti 2015Presentation2015presentation
Novel Adaptive CPU Scoreboard Methodology for a Multi-language environmentPooja Madhusoodhanan, Saya Goud Langadi, Labeeb K2022Paper2022paper
Novel Adaptive CPU Scoreboard Methodology for a Multi-language environmentPooja Madhusoodhanan, Saya Goud Langadi, Labeeb K2022Presentation2022presentation
Novel approach for SoC pipeline latency and connectivity verification using FormalDeepak Mohan, Senthilnath Subbarayan, Sandeep Kumar2022Paper2022paper
Novel approach for SoC pipeline latency and connectivity verification using FormalDeepak Mohan, Senthilnath Subbarayan, Sandeep Kumar2022Presentation2022presentation
Novel Methodology for TLM Model Unit VerificationNavaneet Kumar, Archna Verma, Ashish Mathur2022Presentation2022presentation
NRFs Indentification & Signoff with GLS ValidationRohit Kumar Sinha, Rakesh Misra, Nagesh Kulkarni2022Poster2022poster
Obscure Face of UVM RAL: To Tackle Verification of Error ScenariosSubhash Pai, Lavanya Polineni2017Paper2017paper
Obscure face of UVM RAL: To Tackle Verification of Error ScenariosSubhash Pai, Lavanya Polineni2017Presentation2017presentation
OIL check of PCIe with Formal VerificationVedprakash Mishra, Carlston Lim, Zhi Feng Lee, Jian Zhong Wang, Anshul Jain and Achutha KiranKumar V M2022Presentation2022presentation
Open Source Virtual Platforms for SW Prototyping on FPGA Based HWChen Qian, Praveen Wadikar, Mark Burton2019Paper2019paper
Our Experience of Glitches at Clock Trees, CDC Paths and Reset TreesJebin Mohandas2019Paper2019paper
Overcoming Challenges in Functional Verification of Automotive Traffic SchedulersHarshit Jaiswal, Hemlata Bist, Rohit Mishra, Ori Tal2022Presentation2022presentation
Paged and Alternate View Registers in UVMKirti Srivastava, Harshit Kumar Baghel2017Presentation2017presentation
Parameterized and Re-usable Jitter Model for Serial and Parallel InterfacesAmlan Chakrabarti, Malathi Chikkanna2014Presentation2014presentation
Part 9 An Efficient Methodology for Development of Cryptographic EnginesSandesh Kanchodu, Tarun Rajendra Mittal, Sachin Kashyap, Subramanian Parameswaran2022Presentation2022presentation
Performance Modelling for the Control BackboneRaghav Tenneti, Padam Krishnani, Praveen Wadikar2017Presentation2017presentation
Performance Validation Strategy for collaborative SoC developments where two worlds meets in GDS onlyChirag Kedia and Rahul Gupta2021Poster2021poster
Performance Validation Strategy for collaborative SoC developments where two worlds meets in GDS onlyChirag Kedia, Mukesh Ameria, and Rahul Gupta2021Presentation2021presentation
Performance Verification of a 6 Gbps HSlink Receiver Including Equalization and Clock Recovery Using Mixed Signal SimulationsAashish Ram Bhide, Abhishek Chowdhary, Alok Kaushik, and Vivek Uppal2014Poster2014poster
Perspec System Verifier Overview2015Presentation2015presentation
PHY IP Verification – Are Conventional Digital DV Techniques Sufficient?Somasunder Kattepura Sreenath2015Presentation2015presentation
Please! Can Someone Make UVM Easier to Use?Raghu Ardeishar, Rich Edelman2014Paper2014paper
Please! Can Someone Make UVM Easy to Use?Rich Edelman, Raghu Ardeishar2014Presentation2014presentation
Portable Stimulus Standard Update PSS in the Real WorldAccellera Portable Stimulus Working Group2022Presentation2022presentation
Power Aware CDC Verification at RTL for Faster SoC Verification ClosureAnindya Chakraborty, Naman Jain, Saumitra Goel2014Paper2014paper
Power-Aware CDC Verification at RTL for Faster SoC Verification ClosureAnindya Chakraborty, Naman Jain, Saumitra Goel2014Presentation2014presentation
Pre-Silicon Debug Automation using Transaction Tagging and Data-MiningKamalesh Vikramsimhan, SenthilKumar Narayanaswamy, Deepak Sadasivam, Kaustubh Godbole2014Paper2014paper
Pre-Silicon Debug Automation Using Transaction Tagging and Data-MiningKamalesh V, Senthilkumar N, Kaustubh G, Deepak S2014Poster2014poster
Pre-Silicon Host-based Unit Testing of Driver Software using SystemC ModelsAravinda Thimmapuram, Somarka Chakravarti, Tamal Saha, Rathina Thalaiappan2015Presentation2015presentation
Profiling Virtual Prototypes: Simulation Performance Analysis & OptimizationSandeep Jain2019Presentation2019presentation
Profiling Virtual Prototypes: Simulation Performance Analysis & OptimizationSandeep Jain2019Paper2019paper
Prototyping Next-Gen Tegra SoCSivarama Prasad Valluri, Ramanan Sanjeevi Krishnan2015Presentation2015presentation
Rapid Virtual Prototype Model development using UML and IP-XACT SystemC Code GenerationDeepak S Kurapati and Aravinda Thimmapuram2014Paper2014paper
Recipes for Better Simulation Acceleration PerformanceVijayakrishnan Rousseau, Gaurang Nagrecha2015Presentation2015presentation
Reconfigurable Radio Design and VerificationVladimir Ivanov, Markus Mueck, Seungwon Choi2015Presentation2015presentation
Reset Verification using formal toolArju Khatun, Shiva Nagendar Pokala2022Poster2022poster
Responding to TAT Improvement Challenge Through Testbench Configurability and Re-useAkhila M, Kartik Jain, Renuka Devi, Mukesh Bhartiya2014Presentation2014presentation
Responding to TAT Improvement Challenge through Testbench Configurability and Re-useKartik Jain, Renuka Devi Nagarajan, M Akhila, Mukesh Bhartiya2014Paper2014paper
Retention based low power DV challenges in DDR SystemsSubhash Joshi, Sangaiyah Pandithurai, and Halavarthi Math Revana Siddesh2014Paper2014paper
Retry with Confidence: Use Formal Property Verification to Verify Link Layer Retry (LLR) Mechanism of Compute Express Link (CXL)Anshul Jain, Aman Vyas, Binal Sodavadia, Sava Krstic, Achutha KiranKumar V M2022Presentation2022presentation
Reusable DPI flow across Verification, Validation & SWPrasad Haldule, Pushkar Naik2017Presentation2017presentation
Reusable UVM_REG Backdoor AutomationBalasubramanian G., Allan Peeters, Bob Blais2014Paper2014paper
Reusable UVM_REG Backdoor AutomationBalasubramanian G., Allan Peeters, Bob Blais2014Presentation2014presentation
Reusing Sequences in a Multi-Language environment using UVM-ML OAHannes Fröhlich, Kishore Sur2014Poster2014poster
RTL Quality for TLM ModelsPreeti Sharma 2014Paper2014paper
Runtime Fault-Injection Tool for Executable SystemC ModelsBogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, and Thomas Kruse2014Paper2014paper
Scalable Multi-Domain Multi-Variant Reset Management in Complex Verification IPsKaustubh Kumar, Munnangi Sirisha, Lokesh Kumar2019Paper2019paper
Scalable Multi-Domain, Multi-Variant Reset Management in Verification IPsKaustubh Kumar, Munnangi Sirisha, and Lokesh Kumar2019Presentation2019presentation
Scalable Test bench Architecture and Methodology for Faster Codec and Computer Vision Scenario VerificationAzhar Ahammad, Shreekara Murthy2022Paper2022paper
Scalable Test bench Architecture and Methodology for Faster Codec and Computer Vision Scenario VerificationAzhar Ahammad, Shreekara Murthy2022Presentation2022presentation
SERDES Rx CDR Verification Using Jitter, Spread-Spectrum Clocking (SSC) StimulusSomasunder Sreenath, Raghuram Kolipaka, Chirag Shah, Parag Lonkar2014Presentation2014presentation
SERDES Rx CDR Verification Using Jitter, Spread-Spectrum Clocking (SSC) StimulusSomasunder Sreenath, Raghuram Kolipaka, Chirag Shah, and Parag Lonkar2014Paper2014paper
Shifting Left CXL Interop using Simulation TechniquesJohn Shinto K S, Suhas Pai2022Presentation2022presentation
Simplifying Hierarchical Low Power Designs Using Power Models in Intel DesignRohit Kumar Sinha2019Presentation2019presentation
Simplifying Hierarchical Low Power Designs Using Power Models in Intel DesignRohit Kumar Sinha2019Paper2019paper
Simulation Analog Fault Injection Flow for Mixed-Signal DesignsPablo Cholbi Alenda, Dylan OConnor Desmond, Raman K2019Presentation2019presentation
Simulation Analog Fault Injection Flow for Mixed-Signal DesignsPablo Cholbi Alenda, Dylan OConnor Desmond, Raman K2019Paper2019paper
Simulation Based Pre-Silicon CharacterizationSaurabh Pandey, Venkatseema Das, Arif Mohammed, Nishant Gurunath2014Presentation2014presentation
Simulation Based Pre-Silicon CharacterizationSaurabh Pandey, Venkatseema Das, Arif Mohammed, Nishant Gurunath2014Paper2014paper
Simulation Guided Formal Verification with “River Fishing” TechniquesBathri Narayanan Subramanian, Ping Yeung2019Paper2019paper
Small Scale Parameterized Inference EngineVishnu Bharadwaj, Shruti Narake, and Saurabh Patil2019Presentation2019presentation
Smart Centralized Regression (SCR)Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath, Siddhant Kumar Yadav, Ajay Pennam, Aman Jain2017Presentation2017presentation
Smart Recipe for Quick Bug Hunting: Boosting functional sign-off with Low-Power AssertionsJeevan G R, Deepmala Sachan, Thameem Syed, Raghavendra Prakash2017Presentation2017presentation
Sneak Preview of UVM-SystemC: The Missing Piece in ESL VerificationMartin Barnasconi, Karsten Einwich2014Presentation2014presentation
SoC Verification Enablement Using HM ModelVineet Tanwar, Chirag Kedia, Rahul Gupta2019Paper2019paper
SoC verification of Security x Safety aspects for memory programmed into secure and non-secure regions in Automotive devicesRuchi Bora, Ramit Rastogi2022Poster2022poster
Software Driven Hardware Verification: A UVM/DPI ApproachMilan Purohit, Santanu Bhattacharyya, Puneet Goel, Amit Sharma2015Presentation2015presentation
Solving Problems with hierarchical CDC analysis of large designs with encrypted blocksAbdul Moyeen, Arpita Agarwal, Aman Shaikh, Abhay Deshpande2022Presentation2022presentation
Static Power Intent Verification of Power State Switching ExpressionsSrobona Mitra, Bhaskar Pal, Kaushik De, Soumen Ghosh, Rajarshi Mukherjee2015Poster2015poster
Step-up your Register Access VerificationNisha Kadhirvelu, Sundar Krishnakumar, and Wesley Park2019Presentation2019presentation
Step-up your Register Access VerificationNisha Kadhirvelu, Sundar Krishnakumar, and Rimpy Chugh2019Paper2019paper
Stimulus Generation for Functional Verification of Memory SystemsVaibhav Anant Ashtikar2015Presentation2015presentation
Stimulus Generation for Functional Verification of Memory Systems in Advanced MicroprocessorsBhanuPratap Singh Chouhan, Vaibhav Anant Ashtikar, Basavaraj Talawar, Vani M., Krishnakumar Ranganathan2015Paper2015paper
SwiftCov: Automated Coverage Closure ToolNisha Mallya, Kunal Panchal, Pushkar Naik2017Presentation2017presentation
SystemUVM™ Driving Portable Stimulus Ease-Of-UseNambi Ju2022Presentation2022presentation
SystemVerilog for DesignSaminathan Chockalingam, Deepa Anantharaman2014Presentation2014presentation
The Art of Writing Predictors Efficiently Using UVMDolly Mehta, Jeremy Ridgeway2015Presentation2015presentation
The Formal Way – Fast and Accurate Hashing Algorithm VerificationSini Balakrishnan, Sireesha Tulluri, Bindumadhava SS, Disha Puri2022Presentation2022presentation
The Industry eFPGA soft IP fully customizable, for hardware reconfiguration in the fieldMrs Imen Baili2022Presentation2022presentation
Thinking Ahead – Advanced Verification and Debug Techniques for the Imminent IoT WaveVamsi Krishna Doppalapudi2016Presentation2016presentation
Thinking Beyond the Box Adopt the Reusable UVM Thread Management and Customized UVM Reset Package to Attack Thread Aware Verification ChallengesRoman Wang, Uwe Simm, Malathi Chikkanna2015Poster2015poster
Thinking In TransactionsVisualizing and ValidatingRich Edelman, Mustufa Kanchwala2017Presentation2017presentation
Towards Early Validation of Firmware Using UVM Simulation FrameworkAmaresh Chellapilla, Pandithurai Sangaiyah2019Presentation2019presentation
Towards Early Validation of Firmware Using UVM Simulation FrameworkAmaresh Chellapilla, Pandithurai Sangaiyah2019Paper2019paper
Transactional Memory Subsystem Verification for an ARMv8 Server Class CPURamdas M., Parveez Ahamed, Brijesh Reddy, Jayanto Minocha2015Presentation2015presentation
Transactional Memory Subsystem Verification for an ARMv8 Server Class CPURamdas Mozhikunnath, Parveez Ahamed, Brijesh Reddy, Jayanto Minocha2015Paper2015paper
Trials and Tribulations of Migrating a Native UVM Testbench from Simulation to EmulationVikas Billa, Sundar Haran2017Presentation2017presentation
Uncover: Functional Coverage Made EasyAkash S, Rahul Jain, Gaurav Agarwal2019Presentation2019presentation
Uncover: Functional Coverage Made EasyAkash S, Rahul Jain, Gaurav Agarwal, Nvidia Graphics2019Paper2019paper
Unified Functional and Performance FrameworkA Case Study of Cache: Using SystemC TLM Non Blocking InterfacesChaitra K V2017Presentation2017presentation
Unified Test Writing Framework for Pre and Post Silicon VerificationRahulkumar Patel, Pablo Cholbi, Sivasubrahmanya Evani, Raman K2019Presentation2019presentation
Unified Test Writing Framework for Pre and Post Silicon VerificationRahulkumar Patel, Pablo Cholbi, Sivasubrahmanya Evani, Raman K2019Paper2019paper
Unleashing the Power of UPF 3.0: An Innovative Approach for Faster and Robust Low-power CoverageAwashesh Kumar, Madhur Bhargava2017Presentation2017presentation
Use of Message Bus Interface to Verify Lane Margining in PCIeAnkita Vashisht, Narasimha Babu G V L2019Paper2019paper
Using a Generic Plug and Play Performance Monitor for SoC VerificationAmbar Sarkar, Kaushal Modi, Janak Patel, Bhavin Patel, Ajay Tiwari2015Presentation2015presentation
Using a Generic Plug and Play Performance Monitor for SoC VerificationAjay Tiwari, Bhavin Patel, Janak Patel, Kaushal Modi2015Paper2015paper
Using IP-XACT IEEE1685-2014Prashant Karandikar 2015Presentation2015presentation
Using Simulation Acceleration to Achieve 100X Performance Improvement with UVM Based TestbenchesNarla Venkateswara Rao, Ranjith Kumar K, Vikas Verma, Gautam Kumar2014Presentation2014presentation
Using Simulation Acceleration to Achieve 100X Performance Improvement with UVM Based TestbenchesNarla Venkateswara Rao, K Ranjith Kumar, Vikas Verma, Gautam Kumar2014Paper2014paper
Using Software Design Patterns in Testbench Development for a Multi-layer ProtocolPavan Yeluri, Ranjith Nair2019Paper2019paper
Using UVM-e Testbenches Utilizing Metric-Driven Verification and Advanced Debug CapabilitiesHimanshu Rawal, Vijay Kumar Birange, Daniel Bayer2022Poster2022poster
Utilization of Emulation for accelerating the Functional Verification ClosureVarun Kumar C, Sekhar Dangudubiyyam, Madhukar Ramegowda2022Poster2022poster
UVM & Emulation Creating SystemVerilog & UVM Testbenches for Simulation & Emulation Platform Portability to Boost Block-to-System Verification ProductivityHans van der Schoot2015Presentation2015presentation
UVM based configurable FSM model for System level verification of DDR5 DIMM High end Server ChipsetVinoth Kumar Subramani and Gagandeep Singh2021Presentation2021presentation
UVM based configurable FSM model for System level verification of DDR5 DIMM High end Server ChipsetVinoth Kumar Subramani and Gagandeep Singh2021Poster2021poster
UVM Based Generic Interrupt Handler (UGIH)Nikhil Singla, Debarati Banerjee2022Presentation2022presentation
UVM for RTL DesignersSrinivasan Venkataramanan, Krishna Thottempudi, Praneshsairam A, Mani S2017Presentation2017presentation
UVM Usage for Selective Dynamic Re-configuration of Complex DesignsKunal Panchal, Pushkar Naik2014Presentation2014presentation
UVM Usage for Selective Dynamic Re-configuration of Complex DesignsKunal Panchal, Pushkar Naik2014Paper2014paper
UVM-RAL: Registers on Demand Elimination of the UnnecessarySailaja Akkem2015Presentation2015presentation
UVM, VMM and Native SV: Enabling Full Random Verification at System LevelAshok Chandran2014Presentation2014presentation
UVM, VMM and Native SV: Enabling Full Random Verification at System LevelAshok Chandran2014Paper2014paper
Verification Methodology for Functional Safety Critical Work LoadsG Prashanth Reddy and Debajyoti Mukherjee2021Poster2021poster
Verification Methodology for Functional Safety Critical Work LoadsG Prashanth Reddy and Debajyoti Mukherjee2021Presentation2021presentation
Verification Reuse Strategy for RTL Quality SoC Functional Virtual PrototypesRajesh Kumar Jain, Gaurav Sharma, Marcel Achim, Ashish Mathur, Prateek Sikka2022Presentation2022presentation
Verification Strategies and Modelling for the Uninvited Guest in the System: Clock JitterDeepak Nagaria, Vikas Makhija, Apoorva Mathur2019Paper2019paper
Verification Techniques for CPU Simulation ModelSandeep Jain, Gaurav Sharma2015Presentation2015presentation
Verifying the I/O peripherals of OpenTitan SOC using the Portable Stimulus StandardMahesh R, Bidisha Das, Raj S Mitra, Loganath Ramachandran Ph.D., Viraphol Chaiyakul Ph.D.2022Paper2022paper
Verifying the I/O peripherals of OpenTitan SOC using the Portable Stimulus StandardMahesh R, Bidisha Das, Raj S Mitra, Loganath Ramachandran Ph.D., Viraphol Chaiyakul Ph.D.2022Presentation2022presentation
VirtIO based GPU modelPratik Parvati2022Presentation2022presentation
Virtual Platform for a Multi-Chip WLAN System Using a Generic IO Connectivity SchemeRajesh Jain, Sandeep Jain2017Presentation2017presentation
Virtual Platform for Software Enablement and Hardware VerificationRajesh Jain, Sandeep Jain, Sumail Singh Brar, Sourav Roy2015Presentation2015presentation
VirtualATE: SystemC support for Automatic Test EquipmentNitin Garg, Shabarish Sundar, Amaranath Reddy, Sacha Loitz2015Poster2015poster
Vlang A System Level Verification PerspectivePuneet Goel2015Paper2015paper
Vlang A System Level Verification PerspectivePuneet Goel2015Presentation2015presentation
VP Quality Improvement MethodologyMeghana Moorthy, Melwyn Scudder, Kartik Shah2015Poster2015poster
Walking the Graph: A Holistic Approach to Graph-based Verification for Logic with Sparse State SpaceSandeep Korrapati, Holger Horbach, Klaus Keuerleber, Alexander Jung2015Presentation2015presentation
What-If analysis of Safety Mechanism’s impacts on ETHMAC design under Functional Safety flowUdaykrishna J, Sujatha Hiremath, Kapil Kumar, Sachin Pathak, Gaurav Goel2022Paper2022paper