| “What-If” analysis of Safety Mechanism’s impacts on ETHMAC design under Functional Safety flow | Udaykrishna J, Sujatha Hiremath, Kapil Kumar, Sachin Pathak, Gaurav Goel | | | | | |
| A 360 Degree View of UVM Events | Vikas Billa, Nagesh Kokonda | | | | | |
| A Faster and Efficient Timing Constraint Verification Methodology for GFX SOCs | Vineeth B, Deepmala Sachan | | | | | |
| A Faster and Efficient Timing Constraint Verification Methodology for GFX SOCs | Vineeth B, Deepmala Sachan | | | | | |
| A Framework for Verification of Program Control Unit of VLIW processors | Santhosh Billava, Sharangdhar M Honwadkar | | | | | |
| A Framework for Verification of Program Control Unit of VLIW Processors | Santhosh Billava, Sharangdhar M Honwadkar | | | | | |
| A Generic Configurable Error Injection Agent for All On-Chip Memories | Niharika Sachdeva, Arjun Suresh Kumar, Raviteja Gopagiri, Anil Deshpande, Somasunder Kattepura Sreenath, Damandeep Saini | | | | | |
| A Generic Configurable Error Injection Agent for On-Chip Memories | Niharika Sachdeva, Arjun Suresh Kumar, Raviteja Gopagiri, Anil Deshpande, Somasunder Kattepura Sreenath | | | | | |
| A Generic Verification Methodology for Chip to Chip Interrupt Handling in a Multi-Chip SoC (3DIC) | Vignesh Adiththan, Padma Vutukuru, Lalithraj Mailappa, Sekhar Dangudubiyyam | | | | | |
| A Generic Verification Methodology for Chip to Chip Interrupt Handling in a Multi-Chip SoC (3DIC) | Vignesh Adiththan, Padma Vutukuru, Lalithraj Mailappa, Sekhar Dangudubiyyam | | | | | |
| A Holistic Overview on Preventive & Corrective Action To Handle Glitches | Rohit Kumar Sinha, Parimal Das | | | | | |
| A Method to Accelerate SoC Implementation Cycle by Automatically Generating CDC Constraints | Ashish Hari, Sulabh Kumar Khare | | | | | |
| A Methodology for Interrupt Analysis in Virtual Platforms | Puneet Dhar | | | | | |
| A Methodology for Using Traffic Generators with Real-Time Constraints | Avinash Mehta | | | | | |
| A Methodology to Reuse Unit Level Validation Infrastructure | Ashutosh Parkhi | | | | | |
| A New Epoch is Beginning: Are You Getting Ready for Stepping Into UVM-1.2? | Roman Wang,Uwe Simm | | | | | |
| A New Epoch is Beginning: Are You Getting Ready for Stepping Into UVM-1.2? | Roman Wang, Uwe Simm | | | | | |
| A Novel Approach to Hardware Controlled Power Aware Verification with Optimized Power Consumption Techniques at SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A Novel Approach to Reduce Power Consumption By Bridging The Gap between Standalone Functional Scenario and Real Time Scenario at SOC | Eldin Ben Jacob, Harshal Kothari, Sriram Kazhiyur Soundarrajan, Somasunder Kattepura Sreenath | | | | | |
| A Pragmatic Approach Leveraging Portable Stimulus from Subsystem to SoC level and SoC Emulation | Karandeep Singh, Aditya Chopra, Joachim Geishauser, Nitin Verma | | | | | |
| A Pragmatic Approach Leveraging Portable Stimulus from Subsystem to SoC level and SoC Emulation | Karandeep Singh, Aditya Chopra, Joachim Geishauser, Nitin Verma | | | | | |
| A Real-World Clock Generator Class for UVM | Rhitam Datta, Ankit Somani | | | | | |
| A Recipe for swift Tape-out of Derivative SoCs: A Comprehensive Validation Approach using Formal-based Sequential Equivalence and Connectivity Checking | Priyanshu Jain, Saket Gaddagi, Sandeep Kumar and Ipshita Tripathi | | | | | |
| A Reconfigurable And Fully Automated SRAM Environment Generation Flow for Robust Verification And To Accelerate DV Closure | Vinay Swargam, Lakshmana Kumar Arumugasamy, Sriram Kazhiyur Sounderrajan | | | | | |
| A Reusability Combat in UVM Callbacks vs Factory | Deepak Kumar EV, Vikas Billa, Satish Dadi, Ranganath Kempanahally | | | | | |
| A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage | Ashutosh Mishra, Suresh Vasu | | | | | |
| A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage | Ashutosh Mishra, Suresh Vasu | | | | | |
| A Systematic Methodology for Verifying Clock Domain Crossing Reconvergence | Priya Viswanathan | | | | | |
| A Unified Framework for Multilanguage Verification IPs Integration | Surinder Sood, Selvakumar Krishnamoorthy, Guarav Jalan | | | | | |
| A UVM Based Methodology for Processor Verification | Abhineet Bhojak, Tejbal Prasad | | | | | |
| Absolute GLS Verification An Early Simulation of Design Timing Constraints | Ateet Mishra, Deepak Mahajan, Shiva Belwal | | | | | |
| Accelerating ML TB Integration for Reusability Using UVM ML OA | Saleem Khan, Prasanna Kumar | | | | | |
| Accelerating Semiconductor Time to ISO 26262 Compliance | Kirankumar Karanam | | | | | |
| Accelerating SoC Sensor Network Verification Sign-off through Dynamic and Formal Synergy | Vinod Usha, Shreeram Hegde, Prasad Reddy | | | | | |
| Accelerating SoC Sensor Network Verification Sign-off through Dynamic and Formal Synergy | Vinod Usha, Shreeram Hegde, Prasad Reddy | | | | | |
| Accelerating SOC Verification, Reducing Simulation Turnaround Time & Diskspace Optimization using Dynamic Test Reload (DTR) | Prashant Hota & Shekhar Jha | | | | | |
| Accelerating the SoC Integration Verification Cycle Time Leveraging the Legacy Design Confidence | Abhinav Parashar, Prasanth Kumar Narava | | | | | |
| Accelerating the SoC Integration Verification Cycle Time Leveraging the Legacy Design Confidence | Abhinav Parashar, Prasanth Kumar Narava | | | | | |
| Accellera Systems Initiative SystemC Standards Update | Bishnupriya Bhattacharya | | | | | |
| Accellera Update | Lu Dai | | | | | |
| Achieve Faster Debug Closure by Applying Big Data & Advanced RCA Technologies | Sundararajan Ananthakrishnan, Sundararajan PH | | | | | |
| Achieving Real Time Performance for Algorithms Using SOC TLM Model | Saurin Patel, Pushkar Sareen, Sharath Naidu, Baljinder S Sood | | | | | |
| Adaptive UVM AMOD Testbench for Configurable DSI IP | Krishnapal Singh, Pavan Yeluri, Ranjith Nair | | | | | |
| Adding Agility to Hardware Design-Verification using UVM & Assertions | Francois Cerisier, Ajeetha Kumari, Gurubasappa, Srujana Reddy | | | | | |
| Addressing the Challenges of ABV in Complex SOCs | Rithin A N, Arif M, Rupinjeet Singh, Jeevan | 2015 | Poster | | y2015 | poster |
| Adopting UVM for FPGA Verification | Kamalesh Vikramasimhan, Shridevi Biradar | | | | | |
| Advanced RISC-V Verification Technique Learnings for SoC Validation | David Kelf, Nambi Ju | | | | | |
| Advanced RISC-V Verification Technique Learnings for SoC Validation | David Kelf, Nambi Ju | | | | | |
| Advanced specification driven methodology for quick and accurate RDC signoff | Sai Jagadeesh Ambati, Sulabh Kumar Khare, Atul Sharma | | | | | |
| Advanced UVM Coding Techniques | David Long | | | | | |
| Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IP | Eldhose P.M, Sagar Jayakrishnan, Suraj Vijay Shetty, Kuntal Pandya, Parag S. Lonkar | | | | | |
| Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IP | Eldhose P.M, Sagar Jayakrishnan, Suraj Vijay Shetty, Kuntal Pandya, Parag S. Lonkar | | | | | |
| AMS Verification at SoC Level: A Practical Approach for Using VAMS vs SPICE Views | Nitin Pant, Gautham Harinarayan, Manmohan Rana | | | | | |
| An Automated Systematic CDC Verification Methodology based on SDC Setup | Ashish Hari, Sulabh Kumar Khare | | | | | |
| An Efficient Verification Methodology to Achieve DV Sign-off with Emphasis on Quality and Quicker DV Cycle | Piyush Agnihotri, Nirmal Kumar, Arnab Ghosh, Parag S Lonkar | | | | | |
| An Efficient Verification Methodology to Achieve DV Sign-off with Emphasis on Quality and Quicker DV Cycle | Piyush Agnihotri, Nirmal Kumar, Arnab Ghosh, Parag S Lonkar | | | | | |
| An Industry Proven UVM Reuse Methodology for Coverage Driven Block Level Verification to SW Driven Chip Level Verification Across Simulation & Emulation | Pradeep Salla, Keshav Joshi | | | | | |
| An Introduction to the Accellera Portable Stimulus Standard | Srivatsa Vasudevan, Pradeep Salla, Sharon Rosenberg, Adnan Hamid, Karthick Gururaj, Srivatsa Vasudevan, Bishnupriya Bhattacharya | | | | | |
| An Overview of Ethernet 10Base-T1S in Automotive SoC and its Verification | Bipul Halder, Jagtar Singh, Sahana S, Pushpal Nautiyal, Gaurav Chugh | | | | | |
| ARC EM Core with Safety Package – ISO 26262 Certification | Vikas Bhandari | | | | | |
| Architecturally Scalable Testbench for Complex SoC | Senthilnath Subbarayan, Arulanandan Jacob, Sandeep Kumar | | | | | |
| ASIL B/D Fault Campaign Strategy for Computer Vision core using Soft Test Library (STL) | Shiva Pokala, Vasista A | | | | | |
| Assisting Fault Injection Simulations for Functional Safety Sign-off using Formal | Pulicharla Ravindrareddy | | | | | |
| Assisting Fault Injection Simulations for Functional Safety Sign-off using Formal | Pulicharla Ravindrareddy | | | | | |
| Automated code generation for Early AURIX TM VP | Pratheek Mahesh and Dineshkumar Selvaraj | | | | | |
| Automated code generation for Early AURIX TM VP | Pratheek Mahesh and Dineshkumar Selvaraj | | | | | |
| Automated correct-by-construct methodology for RTL design and analog mixed-signal test bench generation: Enables early design closure of mixed-signal SoC | Lakshmanan Balasubramanian, Murugesh Prashanth Subramaniam, Atul Ramakant Lele, and Ranjit Kumar Dash | | | | | |
| Automated Floating Trash Collecting Boat | Karamalaputti Rahul, Gandham Magaraju | | | | | |
| Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual Prototype | S N Ranjan and Puttaiah Jagadish | | | | | |
| Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual Prototype | S N Ranjan and Puttaiah Jagadish | | | | | |
| Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual Prototype | S N Ranjan and Puttaiah Jagadish | | | | | |
| Automated Toggle Coverage Framework for AURIX TM TC4xx Virtual Prototype | S N Ranjan and Puttaiah Jagadish | | | | | |
| Automated Traffic Simulation Framework for SoC Performance Analysis | Diviya Jain, Tarun Kathuria | | | | | |
| Automated vManager regression using Jenkins | Sneha Gokarakonda | | | | | |
| Automated, Systematic CDC Verification Methodology Based on SDC Setup | Ashish Hari, Sulabh Kumar Khare | | | | | |
| Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDL | Sudhir Bisht, Nikita Gulliya | | | | | |
| Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDL | Sudhir Bisht | | | | | |
| Automatic Generation of Infineon Microcontroller Product Configurations | Prateek Chandra, Leily Zafari, Boyko Traykov | | | | | |
| Automatic Generation of Infineon Microcontroller Product Configurations | Prateek Chandra, Leily Zafari, Boyko Traykov | | | | | |
| Automatically Synthesizing Higher Level of Protocol Abstraction for Faster Debug and Deeper Insight Into Modern Digital Designs | Alasdair Ferro, Amar Patel, Chris Jones, Yogesh Badaya | | | | | |
| Automating information retrieval from EDA software reports using effective parsing algorithms | Manish Bhati | | | | | |
| Automation of Waiver and Design Collateral generation for scalable IPs | Gopalakrishnan Sridhar, Vadlamuri Venkata Sateeshm, Midhun Krishna | | | | | |
| Automation of Waiver and Design Collateral Generation on Scalable IPs | Gopalakrishnan Sridhar, Midhun Krishna, Vadlamuri, Venkata Sateesh | | | | | |
| Automotive RADAR Bitfields Verification to support Validation of Silicon bring-up | Amol Dhok, Paulraj M K | | | | | |
| Automotive RADAR Bitfields Verification to support Validation of Silicon bring-up | Amol Dhok, Paulraj M K | | | | | |
| Back to Basics: Doing Formal “The Right Way” | Joseph Hupcey III, Saumitra Goel | | | | | |
| Benefits of PSS coverage at SOC & its limitations | Sundararajan Haran and Saleem Khan | | | | | |
| Benefits of PSS Coverage at SOC and Its Limitations | Sundararajan Haran, Saleem Khan | | | | | |
| Break the SoC with Random UVM Instruction Driver | Bogdan Todea, Pravin Wilfred, Madhukar Mahadevappa, Diana Dranga | | | | | |
| Breaking Down Barriers: Seamless Protocol Conversion with UVM Component Layering | Santosh Mahale, Shantanu Lele | | | | | |
| Breaking Down Barriers: Seamless Protocol Conversion with UVM Component Layering | Santosh Mahale, Shantanu Lele | | | | | |
| Bring IP Verification Closer to SoC Scalable Methods to Bridge the Gap Between IP and SoC Verification | Gaurav Gupta, Tejbal Prasad, Rohit Goyal, Sachin Jain, Vipin Verma | | | | | |
| Bring IP Verification Closer to SoC Scalable Methods to Bridge the Gap Between IP and SoC Verification | Gaurav Gupta, Tejbal Prasad, Rohit Goyal, Sachin Jain, Vipin Verma | | | | | |
| Bringing DataPath Formal to Designers’ Footsteps | M, Achutha KiranKumar V, Disha Puri, Shriya Dharade | | | | | |
| Bringing Reset Domains and Power Domains together – Non resettable registers amplifying issues in Power-Aware RDC Verification due to UPF Instrumentation | Manish Bhati, Inayat Ali | | | | | |
| Building And Modelling Reset Aware Testbench For IP Functional Verification | Naishal Shah | | | | | |
| Building Configurable UVM Testbench for Configurable Design IP (Configurable TB) | Kilaru Vamsikrishna, Sushrut B Veerapur | | | | | |
| Building UVM Testbenches for High Quality Serial Design IPs Modelling real world scenarios | Kilaru Vamsikrishna, Sushrut B Veerapur | | | | | |
| Case-study: Generating A Workload Model of the Chrome Browser from Android Execution Traces For Early Analysis of Power and Performance Trade-offs | Vikrant Kapila, Tim Kogel, Holger Keding, Amit Tara Amit Dudeja, Nishant Gautam | | | | | |
| Challenges in Mixed Signal Verification | Amlan Chakrabarti, Sachin-Sudhakar Kulkarni | | | | | |
| Challenges of Formal Verification on Deep Learning Hardware Accelerator | Yellinidi Dasarathanaidu | | | | | |
| Challenges of Formal Verification on Deep Learning Hardware Accelerator | Yellinidi Dasarathanaidu | | | | | |
| Challenges with Power Aware Simulation and Verification Methodologies | Divyeshkumar Vora | | | | | |
| Challenges, Complexities and Advanced Verification Techniques in Stress Testing of Elastic Buffer in High Speed SERDES IPs | Kamesh Velmail, Suvadeep Bose, Ankit Garg, Parag S Lonkar, Somasunder K Sreenath | | | | | |
| Challenges, Complexities and Advanced Verification Techniques in Stress Testing of Elastic Buffer in High Speed SERDES IPs | Kamesh Velmail, Suvadeep Bose, Parag Lonkar, Ankit Garg | | | | | |
| Channel Modelling in Complex Serial IPs | Jayesh Ranjan Majhi, Saravana Balakrishnan, Navnit Kumar Kashyap | | | | | |
| Channel Modelling in Complex Serial IPs | Jayesh Ranjan Majhi, Saravana Balakrishnan, Navnit Kumar Kashyap | | | | | |
| Choice is Yours: Either Struggle to Tame ‘X’ in the Wilderness of Multimillion Gates and Nets, OR Take it for a Walk in the RTL Park | Nitin Jaiswal, Harsh Garg, Mayank Bindal | | | | | |
| Code-Test-Verify all for free – Assertions + Verilator | Hemamalini Sundaram, Kasthuri Srinivas, Supriya Ummadisetty | | | | | |
| Code-Test-Verify all for free – Assertions + Verilator | Hemamalini Sundaram, Kasthuri Srinivas, Supriya Ummadisetty | | | | | |
| Complementing Verification of Highly Configurable Design with Formal Techniques | Manik Tyagi, Deepak Jindal | | | | | |
| Compliance Driven Integrated Circuit Development Based on ISO26262 | Haridas Vilakathara and Manikandan Panchapakesan | | | | | |
| Compliance Driven Integrated Circuit Development Based on ISO26262 | Haridas Vilakathara, Manikantan panchapakesan | | | | | |
| Comprehensive Benchmark Results: Comparing Processing-in-Memory Architecture Effectiveness using UPMEM Hardware | Ambati Rajashekar, Pranjit Das, Avi kumar Shrivastava, Partha Acharya | | | | | |
| Compute Link Express – CXL – CXL Consortium | Narasimha Babu | | | | | |
| Configurable Testbench (TB) for Configurable Design IP | Kilaru Vamsikrishna, Sushrut B Veerapur | | | | | |
| Configuration in UVM:The Missing Manual | Mark Glasser | | | | | |
| Configuration in UVM: The Missing Manual | Mark Glasser | | | | | |
| Counterintuitive approaches to have better communication between UVM and Python for registers with Single Controlling Algorithm | Sougata Bhattacharjee | | | | | |
| Coverage Acceleration and Testcase Pruning using Smart Stimuli Generator in SOC Verification | Rahul Laxkar, Naveen Srivastava, Sekhar Dangudubiyyam | | | | | |
| Coverage Acceleration and Testcase Pruning using Smart Stimuli Generator in SOC Verification | Rahul Laxkar, Naveen Srivastava, Sekhar Dangudubiyyam | | | | | |
| Coverage Closure – Is it a “Game of Dice” or “Top 10 Tests” or “Automated Closure”? | Aditya Sharma, T. Nagasundaram, M. Nitin Kumar, Nikhita Raj J | | | | | |
| Covering All the bases: Coverage-driven Formal Verification Sign-off of Pipelined Error Detection Filter | Harbaksh Gupta, Anshul Jain | | | | | |
| Covering All the bases: Coverage-driven Formal Verification Sign-off of Pipelined Error Detection Filter | Harbaksh Gupta, Anshul Jain | | | | | |
| Cross-Domain Datapath Validation Using Formal Proof Accelerators | Aarti Gupta, S. S. Bindumadhava, M. Achutha KiranKumar V, Liu Jun B | | | | | |
| CXL verification using portable stimulus | Karthick Gururaj | | | | | |
| Data Flow Based Memory IP Creation Infrastructure | Abhilash V Nair, Praveen Buddireddy, Tor Jeremiassen, Rashmi Venkatesh, and Prajakta Bhutada | | | | | |
| DDR Controller IP Evaluation Studies using Trace Based Methodology | Abhilash Nair, Amit Nene, Ritesh Sojitra, Prashant Karandikar and Prajakta Bhutada | | | | | |
| Debug Time Reduction by Automatic Generation of Waiver List Using ML Techniques | Vardhana M, Akshay Jain, Kota Subba Rao Sajja | | | | | |
| Debugging Linux Kernel Failures on Virtual Platform | Sandeep Jain | | | | | |
| Design & Verify Virtual Platform with reusable TLM 2.0 | Ankush Kumar | | | | | |
| Design Methodology for Highly Cycle Accurate SystemC Models with Better Performance | Simranjit Singh, Prasanth Sasidharan, Sameer Deshpande, and Sandeep Puttappa | | | | | |
| Design space exploration of PIM (Processing in Memory) & PNC (Processing Near Memory) based on workload characterization | Amarnath, Judhajit | | | | | |
| Design verification of a cascaded mmWave FMCW Radar | Shweta Pujar, Vijay M, Sainath Karlapalem, Dharani Sharavanan, Kavya P S | | | | | |
| Designing A PSS Reuse Strategy | Matthew Ballance | | | | | |
| Digital Eye For Aid of Blind People | Jagu Naveen Kumar, Pabbuleti Venu | | | | | |
| Digital mixed-signal low power verification with Unified Power Format (UPF) | Srilakshmi D R and Geeta Krishna Chaitanya Puli | | | | | |
| Digital mixed-signal low power verification with Unified power format (UPF) | Srilakshmi D R and Geeta Krishna Chaitanya Puli | | | | | |
| Digital Transformation of EDA Environments To Accelerate Semiconductor Innovation | Guru Charan Prasad Jonnalagadda | | | | | |
| Disaggregated methodology in Multi-die SoC– A Server SoC Case Study | Rohit Kumar Sinha | | | | | |
| Disaggregated methodology in Multi-die SoC– A Server SoC Case Study | Rohit Kumar Sinha | | | | | |
| Disciplined Post Silicon Validation using ML Intelligence | Amaresh Chellapilla, Pandithurai Sangaiyah | 2022 | Presentation | | y2022 | presentation |
| Driving Analog Stimuli from a UVM Testbench | Satvika Challa, Amlan Chakrabarti | | | | | |
| DV Methodology to Model Scalable/Reusable Component to Handle IO Delays/Noise/Crosstalk in Multilane DDR PHY IF | Tapas Ranjan Jena, Gowdra Bomanna Chethan, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | |
| DVCon India 2021 Proceedings | Accellera Systems Initiative | | | | | |
| DVCon India 2022 Proceedings | Accellera Systems Initiative | | | | | |
| Dynamic Parameter Configuration of SystemC Models | Shruti Baindur, Simranjit Singh | | | | | |
| Dynamic Power Automation UVM Framework | Raghavendra J N, Gudidevuni Harathi | | | | | |
| Easier UVM – Making Verification Methodology More Productive | John Aynsley, David Long | | | | | |
| Effective Formal Deadlock Verification Methodologies for Interconnect design | Sachin Kumar, Rajesh C M | 2022 | Presentation | | y2022 | presentation |
| Efficacious Verification of Irreproachable and Steady Data Transfer Protocol for high-speed die-to-die communication on a 3DIC Chip | Varun Kumar C, Jyoti Verma, Sekhar Dangudubiyyam | | | | | |
| Efficacious Verification of Irreproachable and Steady Data Transfer Protocol for high-speed die-to-die communication on a 3DIC Chip | Varun Kumar C, Jyoti Verma, Sekhar Dangudubiyyam | | | | | |
| Efficacious verification of Loopback and Equalization in PCIe By Using Novel approach | Jaydeep Suvariya, Pinal Patel | | | | | |
| Efficient and Faster Handling of CDC/RDC Violations | Ashish Kumar Gupta | | | | | |
| Efficient Formal strategies to verify the robustness of the design | Sakthivel Ramaiah | | | | | |
| Efficient Formal strategies to verify the robustness of the design | Sakthivel Ramaiah | | | | | |
| Efficient methodology to uncover common root causes for RDC violations using intelligent data analytics | Manish Bhati, Rajagopal Anantharaman, Inayat Ali | | | | | |
| Efficient methods for analog mixed signal verification Interface handling methods, trade-offs and guidelines | Lakshmanan Balasubramanian, Shoeb Siddiqui, and Vijay Kumar Sankaran | | | | | |
| Efficient Regression Management with Smart Data Mining Technique | Tejbal Prasad | | | | | |
| Efficient Regression Management with Smart Data Mining Technique | Tejbal Prasad | | | | | |
| Efficient Verification of Arbitration Design with a Generic Model | Kevin Kotadiya, Ishita Agrawal | | | | | |
| Efficient Verification of Arbitration Design with a Generic Model | Kevin Kotadiya, Ishita Agrawal | | | | | |
| Efficient Verification of Mixed-Signal SerDes IP Using UVM | Varun R, Vinayak Hegde, Cadence Bangalore | | | | | |
| Effortless, Methodical and Exhaustive Register Verification using what you already have | Aishwarya Sridhar, Pallavi Atha, and David Crutchfield | | | | | |
| Effortless, Methodical and Exhaustive Register Verification using what you already have. | Aishwarya Sridhar, Pallavi Atha, and David Crutchfield | | | | | |
| Embedded UVM | Puneet Goel | | | | | |
| Embrace Errors! Architecting UVM Testbenches for Dynamic Error Injection & Handling | Sushrut B Veerapur, Kilaru Vamsikrishna | | | | | |
| Embracing Datapath Verification with Jasper C2RTL App | Vaibhav Mittal, Sourav Roy, Anshul Singhal | | | | | |
| Embracing Formal Verification for Data Path Designs Using Golden Specs | Achutha Kirankumar V, Disha Puri, Bindumadhava S.S | | | | | |
| Enabling Exhaustive Reset Verification Enablement: Client PCIE Design Reset Verification Case Study | Rohit Kumar Sinha, Praveen Dornala | | | | | |
| Enabling high quality design sign-off with Jasper structural and auto formal checks | Vishnu Haridas, Mansi Rastogi, Guruprasad Timmapur | | | | | |
| Enabling high quality design sign-off with structural and auto formal checks | Timmapur, Guruprasad Haridas, Vishnu Rastogi, Mansi | | | | | |
| Enabling Shift-Left through FV Methodologies on Intel® Graphics Designs | M. Achutha KiranKumar V, Aarti Gupta Bindumadhava S S, Aishwarya R | | | | | |
| Engaging with IEEE through Standards | Sri Chandra, Dennis Brophy | | | | | |
| Enhanced LDPC Codec Verification in UVM | Shriharsha Koila, Ganesh Shetti, Prateek Jain, Anand Shirahatti | | | | | |
| Enhancing Productivity in Formal Testbench Generation for AHB based IPs | Shubham Goyal, Ishan Patil, Senthilnath Subbarayan, and Sandeep Kumar | | | | | |
| Enhancing The Effectiveness of a Constrained Random Test Suite Using Supervised Machine Learning Algorithm | Ponnambalam Lakshmanan, Rajarathinam Susaimanickam | | | | | |
| Ensuring Quality of Next Generation Automotive SoC: System’s Approach | Pankaj Singh | | | | | |
| Essential Adjuncts of Verification Infrastructure | Kunal Panchal, Harshit Mehta | | | | | |
| Exhaustive Reset Verification Enablement: Client PCIE Design Reset Verification Case Study | Rohit Kumar Sinha, Praveen Dornala | | | | | |
| Exhaustive validation of a cache memory controller using Formal Verification to meet performance and timing requirements | Himani Jawa, Nishant Raman, Sini Balakrishnan, Manas Karanjekar | | | | | |
| Exhaustive validation of a cache memory controller using Formal Verification to meet performance and timing requirements | Himani Jawa, Nishant Raman, Sini Balakrishnan, Manas Karanjekar | | | | | |
| Expedite any Simulation with DMTCP and Save Decades of Computation | Balaji R, Sathish Kumar Sugumaran, Rohan Garg, Jiajun Cao | | | | | |
| Expediting the Code Coverage Closure Using Static Formal Techniques – A Proven Approach at Block and SoC Levels | | | | | | |
| Expediting Verification of Critical SoC Components Using Formal Methods | Nuni Srikanth, Lakshman Easwaran, Maddipatla Shankar Naidu | | | | | |
| Extending a Traditional VIP to Solve PHY Verification Challenges | Amit Tanwar, Manoj Manu | | | | | |
| Fast Convergence Modular Advanced Smart-Hybrid Testbench (FCMAST) to automate and expedite SoC gate level simulations closure | Harshal Kothari, Eldin Ben Jacob, Chandrachud Murali, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | |
| Fast Convergence Modular Advanced Smart-Hybrid Testbench (FCMAST) to automate and expedite SoC gate level simulations closure | Harshal Kothari, Eldin Ben Jacob, Chandrachud Murali, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath | | | | | |
| Fast Track RISC-V System Validation Using Hardware Assisted Verification Platforms | Prasad Kadookar, Mohan Singh | | | | | |
| Faster Elaborations with Cloud Storage | Shobhit Shukla, Amit Kumar | | | | | |
| Fault Campaign Framework for FuSa Verification of ISO 26262 Compliant Automotive Products | Prashantkumar Ravindr, Mangesh Pande, and Vinay Rawat | | | | | |
| Fault Campaign Framework for FuSa Verification of ISO 26262 Compliant Automotive Products | Prashantkumar Ravindra, Mangesh Pande, and Vinay Rawat | | | | | |
| Fault Injection Made Easy Unified Formal Verification of Normal and Safety Functions | Sergio Marchese, Jörg Grosse, Ashish Darbari | | | | | |
| Fault Injection Strategy to Validate ASIL-D Requirements of BMS Components | Praneeth Uddagiri, Veera Satya Sai Gavirni, Prashantkumar Ravindra | | | | | |
| Fault Injection Strategy to Validate ASIL-D Requirements of BMS Components | Praneeth Uddagiri, Veera Satya Sai Gavirni, Prashantkumar Ravindra | | | | | |
| Filtering noise in RDC analysis by clockoff specification | Anupam Saxena, Inayat Ali, SulabhKumar Khare, and Atul Sharma | | | | | |
| Filtering noise in RDC analysis by clockoff specification | Anupam Saxena, Inayat Ali, Sulabh Kumar Khare and Atul Sharma | | | | | |
| Formal Assisted Fault Campaign for ISO26262 Certification | Nitin Ahuja, Mayank Agarwal, Sandeep Jana | | | | | |
| Formal For Adjacencies Expanding the Scope of Formal Verification | M Achutha KiranKumar V, Bindumadhava Ss., Vichal Verma, Savitha Manojna | | | | | |
| Formal for Adjacencies Expanding the Scope of Formal Verification | M Achutha KiranKumar V, Bindumadhava Ss., Vichal Verma, Savitha Manojna | | | | | |
| Formal Verification + CIA Triad: Winning Formula for Hardware Security | Vedprakash Mishra, Anshul Jain | | | | | |
| Formal Verification + CIA Triad: Winning Formula for Hardware Security | Vedprakash Mishra, Anshul Jain | | | | | |
| Formal Verification Accelerating Coherent Bridge IP Development and Fast Forward DV | Pulicharla Ravindrareddy, Chayan Pathak, Venkatesh Chepuri, Nitin Neralkar, Sourabh Bhattacharjee, Piyush Upadhyay, Madhusudhan Koothapaakkam | | | | | |
| Formal verification of low-power RISC-V processors | Ashish Darbari | | | | | |
| Formalize the Cache: Formal Verification Techniques to Verify Different Cache Configurations | Sudhanshu Srivastava, Rupali Tewari, Aman Vyas, Sachin Kumawat | | | | | |
| FPGA Implementation Validation and Debug | Rohit Goel, Rakesh Jain, Aman Rana, Ankit Goel | 2015 | Presentation | | y2015 | presentation |
| Framework for Creating Performance Model of AI Algorithms for Early Architecture Exploration | Amit Dudeja, Amit Tara, Amit Garg, Tushar Jain | | | | | |
| Framework for Creating Performance Model of AI Algorithms for Early Architecture Exploration | Amit Dudeja, Amit Tara, Amit Garg, Tushar Jain | | | | | |
| Framework For Exploring Interconnect Level Cache Coherency | Parvinder Pal Singh | | | | | |
| Framework for Holistic Assessment of Potential Performance Gains with Different Simulation Acceleration Modes | Parag Goel, Adiel Khan, Amit Sharma | | | | | |
| From Device Trees to Virtual Prototypes | Sakshi Arora, Vikrant Kamboj, Preeti Sharma | | | | | |
| Functional Coverage Generator | Munjal Mistry | | | | | |
| Functional Safety Verification Methodology for ASIL-B Automotive Designs | Onkar Bhuskute | | | | | |
| Functional Verification of CSI2 Rx-PHY using AMS Co-simulations | Ratheesh Mekkadan | | | | | |
| Functional Verification of CSI-2 Rx-PHY using AMS Co-simulations | Ratheesh Mekkadan | | | | | |
| Functional Verification of CSI-2 Rx-PHY using AMS Co-simulations | Ratheesh Mekkadan | | | | | |
| Functional-Coverage Sampling in UVM RAL Use of 2 Obscure Methods | Muneeb Ulla Shariff, Ravi Reddy | | | | | |
| Functional-Coverage Sampling in UVM RAL: Use of 2 Obscure Methods | Muneeb Ulla Shariff, Ravi Reddy | | | | | |
| FV: A Robust Solution for Tackling Design Complexities – A Case Study on In-Band ECC | Yash Sachin Pawar, Aarti Gupta, Disha Puri | | | | | |
| FV: A Robust Solution for Tackling Design Complexities – A Case Study on In-Band ECC | Yash Sachin Pawar, Aarti Gupta, Disha Puri | | | | | |
| Gatelevel Simulations: Continuing Value in Functional Simulation | Ashok Chandran, Roy Vincent | | | | | |
| Gatelevel Simulations: Continuing Value in Functional Simulations | Ashok Chandran, Roy Vincent | | | | | |
| Generic Solution for NoC design exploration | Tushar Garg | | | | | |
| Generic Solution for NoC design exploration | Tushar Garg and Ranjan Mahajan | | | | | |
| Generic Solution for NoCdesign exploration | Tushar Garg and Ranjan Mahajan | | | | | |
| Generic Solution for NoCdesign exploration | Tushar Garg and Ranjan Mahajan | | | | | |
| Generic Verification Infrastructure around Serial Flash Controllers | Harsimran Singh, Snehlata Gutgutia, Chanpreet Singh | | | | | |
| Get Ready for UVM-SystemC | Martin Barnasconi, Anupam Bakshi | | | | | |
| Global Broadcast with UVM Custom Phasing | Jeremy Ridgeway and Dolly Mehta | | | | | |
| Global Broadcast with UVM Custom Phasing | Jeremy Ridgeway, Dolly Mehta | | | | | |
| Goal Driven Stimulus Solution Get Yourself Out of the Redundancy Trap | Rohit Bansal | | | | | |
| Goal Driven Stimulus Solution Get Yourself Out of the Redundancy Trap | Rohit Bansal | | | | | |
| Hardware Implementation of Smallscale Parameterized Neural Network Inference Engine | Vishnu P Bharadwaj, Shruti Narake, Saurabh D Patil | | | | | |
| Hardware Security – Industry Trends, Attacks and Solutions | Shashank Kulkarni | | | | | |
| Hardware verification through software scheduling for USB using xHCI | Wasiq Zia, Navneet Jha, and Vipin Chauhan | | | | | |
| Hardware verification through software scheduling for USB using xHCI | Wasiq Zia, Navneet Jha, and Vipin Chauhan | | | | | |
| Hardware verification through software scheduling for USB using xHCIThe | Wasiq Zia, Navneet Jha, and Vipin Chauhan | | | | | |
| Hardware verification through software scheduling for USB using xHCIThe | Wasiq Zia, Navneet Jha, and Vipin Chauhan | | | | | |
| Hardware/Software Co-Verification Using Generic Software Adapter | Vijaya Bhaskar, Krishna Chaitanya, Kirtika Sharma | | | | | |
| Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex PMIC designed for SSD Applications | Vijay Kumar, Shrikant Pattar, Yaswanth Chebrolu, Vinayak Hegde | | | | | |
| Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex PMIC designed for SSD Applications | Vijay Kumar, Shrikant Pattar, Yaswanth Chebrolu, Vinayak Hegde | | | | | |
| Has The Performance of a Sub-System Been Beaten to Death | Subhash Joshi, Vaddineni Manohar, Sangaiyah Pandithurai | | | | | |
| High Frequency Response Tracking System micro-architecture | Gopalakrishnan Sridhar, Vadlamuri Venkata Sateesh | | | | | |
| High Frequency Response Tracking System Micro-architecture | Gopalakrishnan Sridhar, Vadlamuri Venkata Sateesh | | | | | |
| Highly Flexible and Robust System Level HW-SW Power Management Verification based on RISC-V | Subramanian Ravichandran, Sekhar Dangudubiyyam | | | | | |
| HISIG- An Efficient Gate Level Simulation Flow for a Hard IP Inside a Soft IP | Ishwar Ganiger, Vishal Dalal, Johannes Grinschgl | | | | | |
| HISIG- An Efficient Gate Level Simulation Flow for a Hard IP Inside a Soft IP | Ishwar Ganiger, Vishal Dalal, Johannes Grinschgl | | | | | |
| Holistic Verification of Bus Health Monitor in Automotive SoC using BHMVC and ParaHunter | Gaurav Kumar Yadav, Abhisek Hota, Prashantkumar Shukranath Sonavane, Garima Srivastava | | | | | |
| Holistic Verification of Bus Health Monitor in Automotive SoC using BHMVC and ParaHunter | Gaurav Kumar Yadav, Abhisek Hota, Prashantkumar Shukranath Sonavane, Garima Srivastava | | | | | |
| How to make debug more efficient in day-to-day life using Verisium Debug | Kiran Kumar Indrakanti, Sai Asrith Tabdil | | | | | |
| How to Reuse Sequences with the UVM-ML Open Architecture library | Hannes Fröhlich and Kishore Sur | | | | | |
| Hybrid Emulation Use Cases | Sylvain Bayon de Noyer | | | | | |
| Hybrid Emulation: Accelerating Software Driven Verification and Debug | Issac P Zacharia and Jitendra Aggarwal | | | | | |
| Hybrid Emulation: Accelerating Software Driven Verification and Debug | Issac P Zacharia and Jitendra Aggarwal | | | | | |
| Identifying and Overcoming Multi-Die System Verification Challenges | Varun Agrawal | | | | | |
| Improving Debug Productivity using latest AI & ML Techniques | Amod Khandekar, Sundararajan Ananthakrishnan, Amit Verma | | | | | |
| Improving Simulation Performance at SoC/Subsystem Level Using LITE Environment Approach | Avni Patel, Heena Mankad | | | | | |
| Increase Productivity with Reflection API in Design Verification | Shivayogi V. Kerudi, Vijay Mukund Srivastav, Vani S, Brad Quinton | | | | | |
| Indago™ Debug Platform Overview | | | | | | |
| Innovative methodologies for analyzing CDC and RDC violations in complex SoC using Automations, formal verification, and Hierarchical CDC model | Maitri Mishra, Dharmendra Kumar | | | | | |
| Intelligent Coverage Driven, Modern Verification for VHDL Based Designs in Native VHDL with OSVVM | Vijay Mukund Srivastav, Anupam Maurya, Prabhat Kumar, Juhi | | | | | |
| Introducing IEEE 1800.2 the Next Step for UVM | Srivatsa Vasudevan | | | | | |
| Introducing UVM-SystemC For a Resilient And Structured ESL Validation | Akhila M | | | | | |
| Introduction to Accellera TLM 2.0 | Aravinda Thimmapuram | | | | | |
| IP Generators – A Better Reuse Methodology | Amanjyot Kaur | | | | | |
| IP Generators -A Better Reuse Methodology | Amanjyot Kaur | | | | | |
| IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 45 minutes! | Nikita Gulliya, Asif Ahmad, Devender Khari | | | | | |
| Left shift catching of critical low power bugs with Formal Verification | Manish Kumar, Madan Kumar, Madhusudhana Lebaka, Srobona Mitra | | | | | |
| Left shift catching of critical low power bugs with Formal Verification | Manish Kumar, Madan Kumar, Srobona Mitra, Madhusudhana Lebaka | | | | | |
| Left shift catching of critical low power bugs with Formal Verification | Manish Kumar, Madan Kumar, Madhusudhana Lebaka, Srobona Mitra | | | | | |
| Left Shift of Perf Validation Using Hardware-Based Acceleration | Abhiram.L.S, Anoop.H.C, Vijayakrishnan Rousseau, Vimpesh Kankariya | | | | | |
| Leveraging ESL Approach to Formally Verify Algorithmic Implementations | M, Achutha KiranKumar V, Bindumadhava S S, Aarti Gupta, Disha Puri | | | | | |
| Leveraging IEEE 1800.2-2017 UVM for Improved RAL Modelling | Vikas Sharma, Manoj Manu, Ankit Garg | | | | | |
| Leveraging IEEE 1800.2-2017 UVM for Improved RAL Modelling | Vikas Sharma, Manoj Manu, Ankit Garg | | | | | |
| Leveraging RAL and alternate automation (cocotb) techniques to improve Register Verification in UVM | Sougata Bhattacharjee | | | | | |
| Logic Equivalence Check without Low Power – you are at risk!! | Aishwarya Nair, Krishna Patel | | | | | |
| Low Power Emulation for Power Intensive Designs | Harpreet Kaur, Mohit Jain, Piyush Kumar Gupta, Jitendra Aggarwal | | | | | |
| Low Power Extension In UVM Power Management | Priyanka Gharat, Shikhadevi Katheriya, Avnita Pal | | | | | |
| Low Power Extension in UVM Power Management | Priyanka Gharat, Avnita Pal, Shikhadevi Katheriya | | | | | |
| Low Power Techniques in Emulation | Pragati Mishra & Jitendra Aggarwal | | | | | |
| Low Power Validation on Emulation Using Portable Stimulus Standard | Joydeep Maitra, Deepinder Singh Mohoora, Vikash Kumar Singh | | | | | |
| Low Power Verification Challenges and Coverage Recipe to Sign-Off PA Verification | Deepmala Sachan, Raghavendra Prakash, Venugopal Jennarapu, Syed S Thameem | | | | | |
| Low power Verification challenges and coverage recipe to sign-off Power aware Verification | Deepmala Sachan, Thameem Syed S, Raghavendra Prakash, Venugopal Jennarapu | | | | | |
| Making Formal Property Verification Mainstream: An Intel® Graphics Experience | M Achutha KiranKumar V, Bindumadhava S S, Abhijith A Bharadwaj | | | | | |
| Making the Most of the UVM Register Layer and Sequences | David Long | | | | | |
| Making Virtual Prototypes Work | Kartik Jivani, Jigar Patel | | | | | |
| Mastering Unexpected Situations Safely | Sacha Loitz | | | | | |
| MDLL & Slave Delay Line Performance Analysis Using Novel Delay Modeling | Abhijith Kashyap, Avinash S and Kalpesh Shah | | | | | |
| MDLL & Slave Delay Line Performance Analysis Using Novel Delay Modeling | Abhijith Kashyap, Avinash Shambu, Kalpesh Shah | | | | | |
| MeSSMArch – A Memory System Simulator for Hardware Multithreading Architectures | Sushil Menon | | | | | |
| MeSSMArch – A Memory System Simulator for Hardware Multithreading Architectures | Sushil Menon | | | | | |
| Methodology for Abstract Power Intent Specification and Generation | Pramod Warrier, Bhavesh Jeewani, Juergen Karmann, Michael Velten | | | | | |
| Methodology for Hardware Software Co-verification of Video Systems on Pre and Post Silicon | Vinesh Peringat | | | | | |
| Methodology for Hardware Software Co-verification of Video Systems on Pre and Post Silicon | Vinesh Peringat, Balajee Premraj, Venkatesh Merugu | | | | | |
| Methodology for system-level comparison of ARM vs RISC-V cores for latency and power consumption | Tom Jose, Deepak Shankar | 2022 | Presentation | | y2022 | presentation |
| Methodology for Verification Regression Throughput Optimization using Machine Learning | Arun.K.R, Preetham Lakshmikanthan, and Ashwani Aggarwal | | | | | |
| Methodology for Verification Regression Throughput Optimization using Machine Learning | Arun K.R. Preetham Lakshmikanthan, Ashwani Aggarwal, and Sundararajan Ananthakrishnan | | | | | |
| MIPI M-PHY Analog Modeling in Verilog-AMS (Wreal) and Verification Using SV/UVM-MS Methodology | Mallikarjuna Reddy Y, Venkatramana Rao K, Somanatha Shetty A | | | | | |
| Model Extraction for Designs Based on Switches for Formal Verification | Amar Patel, Naman Jain | | | | | |
| Model Extraction for Designs Based on Switches for Formal Verification | Amar Patel, Naman Jain | | | | | |
| Netlist Enabled Emulation Platform for Accelerated Gate Level Verification | Samhith Pottem, Vasudeva Reddy, Rahul S S, Sarang Kalbande, Garima Srivastava, Hyundon Kim | | | | | |
| Netlist Enabled Emulation Platform for Accelerated Gate Level Verification | Samhith Pottem, Vasudeva Reddy, Rahul S S, Sarang Kalbande, Garima Srivastava, Hyundon Kim | 2023 | Paper | | y2023 | paper |
| Network Packet Header Generation Using Graph Based Techniques Combined with Software Testing Strategies | Sridevi Navulur, Satheesh Parasumanna, Rama Chaganti | | | | | |
| No gain without RISC- A novel approach for accelerating and streamlining RISC-V Processor functional verification with register change dump methodology | Damandeep Saini, Chethan AS, Anil Deshpande, Raviteja Gopagiri, Somasundar, Niharika Sachdeva | | | | | |
| No gain without RISC- A novel approach for accelerating and streamlining RISC-V Processor functional verification with register change dump methodology | Damandeep Saini, Chethan AS, Anil Deshpande, Raviteja Gopagiri, Somasundar, Niharika Sachdeva | | | | | |
| Novel Adaptive CPU Scoreboard Methodology for a Multi-language environment | Pooja Madhusoodhanan, Saya Goud Langadi, Labeeb K | | | | | |
| Novel Adaptive CPU Scoreboard Methodology for a Multi-language environment | Pooja Madhusoodhanan, Saya Goud Langadi, Labeeb K | | | | | |
| Novel approach for SoC pipeline latency and connectivity verification using Formal | Deepak Mohan, Senthilnath Subbarayan, Sandeep Kumar | | | | | |
| Novel approach for SoC pipeline latency and connectivity verification using Formal | Deepak Mohan, Senthilnath Subbarayan, Sandeep Kumar | | | | | |
| Novel Methodology for TLM Model Unit Verification | Navaneet Kumar, Archna Verma, Ashish Mathur | 2022 | Presentation | | y2022 | presentation |
| Novel Model First Approach to Shift-Left Soft-Logic RTL Development on Intel Agilex FPGA for Data Centre IPU Design | Pravat K Nayak, Vikrant Kapila, Pushpa Naik, Niketkumar Sharma | | | | | |
| NRFs Indentification & Signoff with GLS Validation | Rohit Kumar Sinha, Rakesh Misra, Nagesh Kulkarni | | | | | |
| Obscure Face of UVM RAL: To Tackle Verification of Error Scenarios | Subhash Pai, Lavanya Polineni | | | | | |
| Obscure face of UVM RAL: To Tackle Verification of Error Scenarios | Subhash Pai, Lavanya Polineni | | | | | |
| OIL check of PCIe with Formal Verification | Vedprakash Mishra, Carlston Lim, Zhi Feng Lee, Jian Zhong Wang, Anshul Jain and Achutha KiranKumar V M | | | | | |
| Open Source Virtual Platforms for SW Prototyping on FPGA Based HW | Chen Qian, Praveen Wadikar, Mark Burton | | | | | |
| Our Experience of Glitches at Clock Trees, CDC Paths and Reset Trees | Jebin Mohandas | | | | | |
| Overcoming Challenges in Functional Verification of Automotive Traffic Schedulers | Harshit Jaiswal, Hemlata Bist, Rohit Mishra, Ori Tal | | | | | |
| Paged and Alternate View Registers in UVM | Kirti Srivastava, Harshit Kumar Baghel | | | | | |
| Paradigm Shift in Power Aware Simulation Using Formal Techniques | Sachin Bansal, Girish Marudwar, Sandeep Jana, Kamalesh Ghosh, Yogananda Mesa | 2023 | Presentation | | y2023 | presentation |
| Paradigm Shift in Power Aware Simulation Using Formal Techniques | Sachin Bansal, Girish Marudwar, Sandeep Jana, Kamalesh Ghosh, Yogananda Mesa | | | | | |
| Parameterized and Re-usable Jitter Model for Serial and Parallel Interfaces | Amlan Chakrabarti, Malathi Chikkanna | | | | | |
| Part 9 An Efficient Methodology for Development of Cryptographic Engines | Sandesh Kanchodu, Tarun Rajendra Mittal, Sachin Kashyap, Subramanian Parameswaran | | | | | |
| Performance Analysis and Acceleration of High Bandwidth Memory System | Rohit Devidas Chavan, Jyoti Verma, Sekhar Dangudubiyyam | | | | | |
| Performance Analysis and Acceleration of High Bandwidth Memory System | Rohit Devidas Chavan, Jyoti Verma, Sekhar Dangudubiyyam | | | | | |
| Performance Modelling for the Control Backbone | Raghav Tenneti, Padam Krishnani, Praveen Wadikar | | | | | |
| Performance Validation Strategy for collaborative SoC developments where two worlds meets in GDS only | Chirag Kedia and Rahul Gupta | | | | | |
| Performance Validation Strategy for collaborative SoC developments where two worlds meets in GDS only | Chirag Kedia, Mukesh Ameria, and Rahul Gupta | | | | | |
| Performance Verification of a 6 Gbps HSlink Receiver Including Equalization and Clock Recovery Using Mixed Signal Simulations | Aashish Ram Bhide, Abhishek Chowdhary, Alok Kaushik, and Vivek Uppal | | | | | |
| Perspec System Verifier Overview | | | | | | |
| PHY IP Verification – Are Conventional Digital DV Techniques Sufficient? | Somasunder Kattepura Sreenath | | | | | |
| Please! Can Someone Make UVM Easier to Use? | Raghu Ardeishar, Rich Edelman | | | | | |
| Please! Can Someone Make UVM Easy to Use? | Rich Edelman, Raghu Ardeishar | | | | | |
| Portable Stimulus Standard Update PSS in the Real World | Accellera Portable Stimulus Working Group | | | | | |
| Power Aware CDC Verification at RTL for Faster SoC Verification Closure | Anindya Chakraborty, Naman Jain, Saumitra Goel | | | | | |
| Power-Aware CDC Verification at RTL for Faster SoC Verification Closure | Anindya Chakraborty, Naman Jain, Saumitra Goel | | | | | |
| Pre-Silicon Debug Automation using Transaction Tagging and Data-Mining | Kamalesh Vikramsimhan, SenthilKumar Narayanaswamy, Deepak Sadasivam, Kaustubh Godbole | | | | | |
| Pre-Silicon Debug Automation Using Transaction Tagging and Data-Mining | Kamalesh V, Senthilkumar N, Kaustubh G, Deepak S | | | | | |
| Pre-Silicon Host-based Unit Testing of Driver Software using SystemC Models | Aravinda Thimmapuram, Somarka Chakravarti, Tamal Saha, Rathina Thalaiappan | | | | | |
| Profiling Virtual Prototypes: Simulation Performance Analysis & Optimization | Sandeep Jain | | | | | |
| Profiling Virtual Prototypes: Simulation Performance Analysis & Optimization | Sandeep Jain | | | | | |
| PropGen: An Automated Flow to Generate SVA Properties for Formal and Simulation methods | Amith Shambhu, Vishal Dalal, Basavaraj Naik | | | | | |
| PropGen: An Automated Flow to Generate SVA Properties for Formal and Simulation methods | Amith Shambhu, Vishal Dalal, Basavaraj Naik | | | | | |
| Prototyping Next-Gen Tegra SoC | Sivarama Prasad Valluri, Ramanan Sanjeevi Krishnan | | | | | |
| Pseudo-LRU Not Efficient in Real World? Use Formal Verification to Bridge the Gap | Paras Gupta, Sachin Kumawat, and Kevin Bhensdadiya | 2023 | Presentation | | y2023 | presentation |
| Pseudo-LRU Not Efficient in Real World? Use Formal Verification to Bridge the Gap | Paras Gupta, Sachin Kumawat, and Kevin Bhensdadiya | | | | | |
| Python empowered GLS Bringup Vehicle | Debarati Banerjee, Nikhil Singla, Shantha B, Pandithurai Sangaiyah | | | | | |
| Python empowered GLS Bringup Vehicle | Debarati Banerjee, Nikhil Singla, Shantha B, Pandithurai Sangaiyah | | | | | |
| Quiescent Formal Checks (QFC) for Detecting Deep Design Bugs – Sooner and Faster | Somesh Mishra, Mayank, Kumar, Ketan Mishra, Anshul Jain, Bharath Varma Gottumukkala | | | | | |
| Quiescent Formal Checks (QFC) for Detecting Deep Design Bugs – Sooner and Faster | Somesh Mishra, Mayank, Kumar, Ketan Mishra, Anshul Jain, Bharath Varma Gottumukkala | | | | | |
| Raising the Bar: Achieving Formal Verification Sign-Off for Complex Algorithmic Designs, with a Dot Product Accumulate Case Study | Disha Puri, Madhurima Eranki, Shravya Jampana | | | | | |
| Raising the Bar: Achieving Formal Verification Sign-Off for Complex Algorithmic Designs, with a Dot Product Accumulate Case Study | Disha Puri, Madhurima Eranki, Shravya Jampana | | | | | |
| Rapid Virtual Prototype Model development using UML and IP-XACT SystemC Code Generation | Deepak S Kurapati and Aravinda Thimmapuram | | | | | |
| Recipes for Better Simulation Acceleration Performance | Vijayakrishnan Rousseau, Gaurang Nagrecha | | | | | |
| Reconfigurable Radio Design and Verification | Vladimir Ivanov, Markus Mueck, Seungwon Choi | | | | | |
| Reset Verification using formal tool | Arju Khatun, Shiva Nagendar Pokala | | | | | |
| Responding to TAT Improvement Challenge through Testbench Configurability and Re-use | Kartik Jain, Renuka Devi Nagarajan, M Akhila, Mukesh Bhartiya | | | | | |
| Responding to TAT Improvement Challenge Through Testbench Configurability and Re-use | Akhila M, Kartik Jain, Renuka Devi, Mukesh Bhartiya | | | | | |
| Retention based low power DV challenges in DDR Systems | Subhash Joshi, Sangaiyah Pandithurai, and Halavarthi Math Revana Siddesh | | | | | |
| Retry with Confidence: Use Formal Property Verification to Verify Link Layer Retry (LLR) Mechanism of Compute Express Link (CXL) | Anshul Jain, Aman Vyas, Binal Sodavadia, Sava Krstic, Achutha KiranKumar V M | | | | | |
| Reusable DPI flow across Verification, Validation & SW | Prasad Haldule, Pushkar Naik | | | | | |
| Reusable UVM_REG Backdoor Automation | Balasubramanian G., Allan Peeters, Bob Blais | | | | | |
| Reusable UVM_REG Backdoor Automation | Balasubramanian G., Allan Peeters, Bob Blais | | | | | |
| Reusing Sequences in a Multi-Language environment using UVM-ML OA | Hannes Fröhlich, Kishore Sur | | | | | |
| Revolutionizing Proof Convergence for Algorithmic Designs: Combining Multiple Formal Verification Tools | Suraj Kamble, Rajib Lochan Jana, Disha Puri | | | | | |
| Revolutionizing Proof Convergence for Algorithmic Designs: Combining Multiple Formal Verification Tools | Suraj Kamble, Rajib Lochan Jana, Disha Puri | | | | | |
| Robust Low Power Verification Strategy for a Complex 3DIC System with Split Power Management Architecture | Atiq Jamadar, Ayush Agrawal, Subramanian R, Sekhar Dangudubiyyam | | | | | |
| Robust Low Power Verification Strategy for a Complex 3DIC System with Split Power Management Architecture | Atiq Jamadar, Ayush Agrawal, Subramanian R, Sekhar Dangudubiyyam | | | | | |
| RTL Quality for TLM Models | Preeti Sharma | | | | | |
| Runtime Fault-Injection Tool for Executable SystemC Models | Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, and Thomas Kruse | | | | | |
| Scalable Multi-Domain Multi-Variant Reset Management in Complex Verification IPs | Kaustubh Kumar, Munnangi Sirisha, Lokesh Kumar | | | | | |
| Scalable Multi-Domain, Multi-Variant Reset Management in Verification IPs | Kaustubh Kumar, Munnangi Sirisha, and Lokesh Kumar | | | | | |
| Scalable Test bench Architecture and Methodology for Faster Codec and Computer Vision Scenario Verification | Azhar Ahammad, Shreekara Murthy | | | | | |
| Scalable Test bench Architecture and Methodology for Faster Codec and Computer Vision Scenario Verification | Azhar Ahammad, Shreekara Murthy | | | | | |
| Securing design confidence for Low power and Functional features of Image Sensor SOC – Reuse of UVM simulation testbench on HW acceleration platform | Vivek Kumar, Manish Mallan, Karthik Majeti | | | | | |
| SERDES Rx CDR Verification Using Jitter, Spread-Spectrum Clocking (SSC) Stimulus | Somasunder Sreenath, Raghuram Kolipaka, Chirag Shah, and Parag Lonkar | | | | | |
| SERDES Rx CDR Verification Using Jitter, Spread-Spectrum Clocking (SSC) Stimulus | Somasunder Sreenath, Raghuram Kolipaka, Chirag Shah, Parag Lonkar | | | | | |
| Shifting Left CXL Interop using Simulation Techniques | John Shinto K S, Suhas Pai | | | | | |
| Simplifying Hierarchical Low Power Designs Using Power Models in Intel Design | Rohit Kumar Sinha | | | | | |
| Simplifying Hierarchical Low Power Designs Using Power Models in Intel Design | Rohit Kumar Sinha | | | | | |
| Simulation Analog Fault Injection Flow for Mixed-Signal Designs | Pablo Cholbi Alenda, Dylan OConnor Desmond, Raman K | | | | | |
| Simulation Analog Fault Injection Flow for Mixed-Signal Designs | Pablo Cholbi Alenda, Dylan OConnor Desmond, Raman K | | | | | |
| Simulation Based Pre-Silicon Characterization | Saurabh Pandey, Venkatseema Das, Arif Mohammed, Nishant Gurunath | | | | | |
| Simulation Based Pre-Silicon Characterization | Saurabh Pandey, Venkatseema Das, Arif Mohammed, Nishant Gurunath | | | | | |
| Simulation Guided Formal Verification with “River Fishing” Techniques | Bathri Narayanan Subramanian, Ping Yeung | | | | | |
| Small Scale Parameterized Inference Engine | Vishnu Bharadwaj, Shruti Narake, and Saurabh Patil | | | | | |
| Smart Centralized Regression (SCR) | Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath, Siddhant Kumar Yadav, Ajay Pennam, Aman Jain | | | | | |
| Smart Recipe for Quick Bug Hunting: Boosting functional sign-off with Low-Power Assertions | Jeevan G R, Deepmala Sachan, Thameem Syed, Raghavendra Prakash | | | | | |
| Sneak Preview of UVM-SystemC: The Missing Piece in ESL Verification | Martin Barnasconi, Karsten Einwich | | | | | |
| SoC Verification Enablement Using HM Model | Vineet Tanwar, Chirag Kedia, Rahul Gupta | | | | | |
| SoC verification of Security x Safety aspects for memory programmed into secure and non-secure regions in Automotive devices | Ruchi Bora, Ramit Rastogi | | | | | |
| Software Driven Hardware Verification: A UVM/DPI Approach | Milan Purohit, Santanu Bhattacharyya, Puneet Goel, Amit Sharma | | | | | |
| Solving Problems with hierarchical CDC analysis of large designs with encrypted blocks | Abdul Moyeen, Arpita Agarwal, Aman Shaikh, Abhay Deshpande | | | | | |
| Static Power Intent Verification of Power State Switching Expressions | Srobona Mitra, Bhaskar Pal, Kaushik De, Soumen Ghosh, Rajarshi Mukherjee | | | | | |
| Static Sign-Off Best Practices Learnings and Experiences from Industry Use Cases | Vikas Sachdeva | | | | | |
| Statistical Analysis of Clock Domain Crossing | Rajat Singla, Tanneru Sai Pavan, Naveen Dugar, Varun Sharma | | | | | |
| Statistical Analysis of Clock Domain Crossing | Rajat Singla, Tanneru Sai Pavan, Naveen Dugar, Varun Sharma | | | | | |
| Step-up your Register Access Verification | Nisha Kadhirvelu, Sundar Krishnakumar, and Wesley Park | 2019 | Presentation | | y2019 | presentation |
| Step-up your Register Access Verification | Nisha Kadhirvelu, Sundar Krishnakumar, and Rimpy Chugh | | | | | |
| Stimulus Generation for Functional Verification of Memory Systems | Vaibhav Anant Ashtikar | | | | | |
| Stimulus Generation for Functional Verification of Memory Systems in Advanced Microprocessors | BhanuPratap Singh Chouhan, Vaibhav Anant Ashtikar, Basavaraj Talawar, Vani M., Krishnakumar Ranganathan | | | | | |
| SwiftCov: Automated Coverage Closure Tool | Nisha Mallya, Kunal Panchal, Pushkar Naik | | | | | |
| SystemUVM™ Driving Portable Stimulus Ease-Of-Use | Nambi Ju | | | | | |
| SystemVerilog for Design | Saminathan Chockalingam, Deepa Anantharaman | | | | | |
| Tabled Data Into Query Able Data, ‘Key’ Concepts Demonstrated Using DDR5 | Rahil Jha, Joseph Bauer | 2023 | Presentation | | y2023 | presentation |
| Tabled Data Into Query Able Data, ‘Key’ Concepts Demonstrated Using DDR5 | Rahil Jha, Joseph Bauer | | | | | |
| Tackling the verification complexities of a processor subsystem through Portable stimulus | Vivek Gopalkrishna, Ponnambalam Lakshmanan, Nitish Swamy | | | | | |
| Tackling the verification complexities of a processor subsystem through Portable stimulus | Vivek Gopalkrishna, Ponnambalam Lakshmanan, Nitish Swamy | | | | | |
| Techniques to identify reset metastability issues due to soft resets | Reetika, Sulabh Kumar Khare | | | | | |
| Techniques to identify reset metastability issues due to soft resets | Reetika, Sulabh Kumar Khare | 2023 | Paper | | y2023 | paper |
| The Art of Writing Predictors Efficiently Using UVM | Dolly Mehta, Jeremy Ridgeway | | | | | |
| The Formal Way – Fast and Accurate Hashing Algorithm Verification | Sini Balakrishnan, Sireesha Tulluri, Bindumadhava SS, Disha Puri | | | | | |
| The Industry eFPGA soft IP fully customizable, for hardware reconfiguration in the field | Mrs Imen Baili | | | | | |
| Thinking Ahead – Advanced Verification and Debug Techniques for the Imminent IoT Wave | Vamsi Krishna Doppalapudi | | | | | |
| Thinking Beyond the Box Adopt the Reusable UVM Thread Management and Customized UVM Reset Package to Attack Thread Aware Verification Challenges | Roman Wang, Uwe Simm, Malathi Chikkanna | | | | | |
| Thinking In TransactionsVisualizing and Validating | Rich Edelman, Mustufa Kanchwala | | | | | |
| Towards Early Validation of Firmware Using UVM Simulation Framework | Amaresh Chellapilla, Pandithurai Sangaiyah | | | | | |
| Towards Early Validation of Firmware Using UVM Simulation Framework | Amaresh Chellapilla, Pandithurai Sangaiyah | | | | | |
| Transactional Memory Subsystem Verification for an ARMv8 Server Class CPU | Ramdas M., Parveez Ahamed, Brijesh Reddy, Jayanto Minocha | | | | | |
| Transactional Memory Subsystem Verification for an ARMv8 Server Class CPU | Ramdas Mozhikunnath, Parveez Ahamed, Brijesh Reddy, Jayanto Minocha | | | | | |
| Trials and Tribulations of Migrating a Native UVM Testbench from Simulation to Emulation | Vikas Billa, Sundar Haran | | | | | |
| UCIe based Design Verification | Anunay Bajaj, Sundararajan Ananthakrishnan | | | | | |
| Uncover: Functional Coverage Made Easy | Akash S, Rahul Jain, Gaurav Agarwal | | | | | |
| Uncover: Functional Coverage Made Easy | Akash S, Rahul Jain, Gaurav Agarwal, Nvidia Graphics | | | | | |
| Unified Functional and Performance FrameworkA Case Study of Cache: Using SystemC TLM Non Blocking Interfaces | Chaitra K V | | | | | |
| Unified Test Writing Framework for Pre and Post Silicon Verification | Rahulkumar Patel, Pablo Cholbi, Sivasubrahmanya Evani, Raman K | | | | | |
| Unified Test Writing Framework for Pre and Post Silicon Verification | Rahulkumar Patel, Pablo Cholbi, Sivasubrahmanya Evani, Raman K | | | | | |
| Unleashing the Power of UPF 3.0: An Innovative Approach for Faster and Robust Low-power Coverage | Awashesh Kumar, Madhur Bhargava | | | | | |
| Use of Message Bus Interface to Verify Lane Margining in PCIe | Ankita Vashisht, Narasimha Babu G V L | | | | | |
| Using a Generic Plug and Play Performance Monitor for SoC Verification | Ambar Sarkar, Kaushal Modi, Janak Patel, Bhavin Patel, Ajay Tiwari | | | | | |
| Using a Generic Plug and Play Performance Monitor for SoC Verification | Ajay Tiwari, Bhavin Patel, Janak Patel, Kaushal Modi | | | | | |
| Using IP-XACT IEEE1685-2014 | Prashant Karandikar | | | | | |
| Using Simulation Acceleration to Achieve 100X Performance Improvement with UVM Based Testbenches | Narla Venkateswara Rao, K Ranjith Kumar, Vikas Verma, Gautam Kumar | | | | | |
| Using Simulation Acceleration to Achieve 100X Performance Improvement with UVM Based Testbenches | Narla Venkateswara Rao, Ranjith Kumar K, Vikas Verma, Gautam Kumar | | | | | |
| Using Software Design Patterns in Testbench Development for a Multi-layer Protocol | Pavan Yeluri, Ranjith Nair | | | | | |
| Using UVM-e Testbenches Utilizing Metric-Driven Verification and Advanced Debug Capabilities | Himanshu Rawal, Vijay Kumar Birange, Daniel Bayer | | | | | |
| Utilization of Emulation for accelerating the Functional Verification Closure | Varun Kumar C, Sekhar Dangudubiyyam, Madhukar Ramegowda | | | | | |
| UVM & Emulation Creating SystemVerilog & UVM Testbenches for Simulation & Emulation Platform Portability to Boost Block-to-System Verification Productivity | Hans van der Schoot | | | | | |
| UVM based configurable FSM model for System level verification of DDR5 DIMM High end Server Chipset | Vinoth Kumar Subramani and Gagandeep Singh | | | | | |
| UVM based configurable FSM model for System level verification of DDR5 DIMM High end Server Chipset | Vinoth Kumar Subramani and Gagandeep Singh | | | | | |
| UVM Based Generic Interrupt Handler (UGIH) | Nikhil Singla, Debarati Banerjee | | | | | |
| UVM for RTL Designers | Srinivasan Venkataramanan, Krishna Thottempudi, Praneshsairam A, Mani S | | | | | |
| UVM Sequence Layering for Register Sequences | Muneeb Ulla Shariff, Sangeetha Sekar, Ravi Reddy | | | | | |
| UVM Sequence Layering for Register Sequences | Muneeb Ulla Shariff, Sangeetha Sekar, Ravi Reddy | | | | | |
| UVM Usage for Selective Dynamic Re-configuration of Complex Designs | Kunal Panchal, Pushkar Naik | | | | | |
| UVM Usage for Selective Dynamic Re-configuration of Complex Designs | Kunal Panchal, Pushkar Naik | | | | | |
| UVM-RAL: Registers on Demand Elimination of the Unnecessary | Sailaja Akkem | | | | | |
| UVM, VMM and Native SV: Enabling Full Random Verification at System Level | Ashok Chandran | | | | | |
| UVM, VMM and Native SV: Enabling Full Random Verification at System Level | Ashok Chandran | | | | | |
| Verification Methodology for Functional Safety Critical Work Loads | G Prashanth Reddy and Debajyoti Mukherjee | | | | | |
| Verification Methodology for Functional Safety Critical Work Loads | G Prashanth Reddy and Debajyoti Mukherjee | | | | | |
| Verification Reuse Strategy for RTL Quality SoC Functional Virtual Prototypes | Rajesh Kumar Jain, Gaurav Sharma, Marcel Achim, Ashish Mathur, Prateek Sikka | | | | | |
| Verification Strategies and Modelling for the Uninvited Guest in the System: Clock Jitter | Deepak Nagaria, Vikas Makhija, Apoorva Mathur | | | | | |
| Verification Techniques for CPU Simulation Model | Sandeep Jain, Gaurav Sharma | | | | | |
| Verifying the I/O peripherals of OpenTitan SOC using the Portable Stimulus Standard | Mahesh R, Bidisha Das, Raj S Mitra, Loganath Ramachandran Ph.D., Viraphol Chaiyakul Ph.D. | | | | | |
| Verifying the I/O peripherals of OpenTitan SOC using the Portable Stimulus Standard | Mahesh R, Bidisha Das, Raj S Mitra, Loganath Ramachandran Ph.D., Viraphol Chaiyakul Ph.D. | | | | | |
| VirtIO based GPU model | Pratik Parvati | | | | | |
| Virtual Platform for a Multi-Chip WLAN System Using a Generic IO Connectivity Scheme | Rajesh Jain, Sandeep Jain | | | | | |
| Virtual Platform for Software Enablement and Hardware Verification | Rajesh Jain, Sandeep Jain, Sumail Singh Brar, Sourav Roy | | | | | |
| VirtualATE: SystemC support for Automatic Test Equipment | Nitin Garg, Shabarish Sundar, Amaranath Reddy, Sacha Loitz | | | | | |
| Vlang A System Level Verification Perspective | Puneet Goel | | | | | |
| Vlang A System Level Verification Perspective | Puneet Goel | | | | | |
| VP Quality Improvement Methodology | Meghana Moorthy, Melwyn Scudder, Kartik Shah | | | | | |
| Walking the Graph: A Holistic Approach to Graph-based Verification for Logic with Sparse State Space | Sandeep Korrapati, Holger Horbach, Klaus Keuerleber, Alexander Jung | | | | | |
| What-If analysis of Safety Mechanism’s impacts on ETHMAC design under Functional Safety flow | Udaykrishna J, Sujatha Hiremath, Kapil Kumar, Sachin Pathak, Gaurav Goel | | | | | |
| When Last Minute FV Strikes Gold: A Case Study on Finding Starvations & Deadlocks in a Project Nearing Tape-in | Abhishek Potdar, Sachin Kumawat, Sudhanshu Srivastava, Anshul Jain | 2023 | Presentation | | y2023 | presentation |
| When Last Minute FV Strikes Gold: A Case Study on Finding Starvations & Deadlocks in a Project Nearing Tape-in | Abhishek Potdar, Sachin Kumawat, Sudhanshu Srivastava, Anshul Jain | | | | | |
| Wrong clamps can kill your chip!!….find them early | Akhil Arora, Rajiv Kumar, Sonik Sachdeva | | | | | |
| Wrong clamps can kill your chip!!….find them early | Akhil Arora, Rajiv Kumar, Sonik Sachdeva | | | | | |
| XploR, a Platform to Accelerate Silicon Transformation | | | | | | |
