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Event Location: United States

DVCon U.S. 2022 Proceedings

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DVCon US 2022 Proceedings

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Bringing UVM to VHDL

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Accellera UVM-AMS Standard Update

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The Best Verification Strategy You’ve Never Heard Of

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System Verification with MatchLib

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Portable Stimulus Standard Update: PSS in the Real World

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Proven Strategies for Better Verification Planning: DVCon 2022 Workshop

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Machine Learning Driven Verification A Step Function in Productivity and Throughput

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Virtual Platforms to Shift-Left Software Development and System Verification

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Is Your Hardware Dependable?

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IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 90 minutes!

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Introduction to the 5 Levels of RISC-V Processor Verification

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“In-Emulator” UVM++ Randomized Testbenches for High Performance Functional Verification

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Finding Hidden Bugs In Deep Cycles: Advanced Debug Methodologies for Software-first System Validation

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Estimating Power Dissipation of End-User Application on RTL

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Building a Comprehensive Hardware Security Methodology

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An Overview of Security Annotation for Electronic Design Integration (SA-EDI) Standard

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Why Not “Connect” Using UVM Connect: Mixed Language Communication Got Easier with UVMC

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What Does The Sequence Say? Powering Productivity with Polymorphism

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Using PSS-2.0 Hardware-Software Interface to validate 4G/5G Forward Error Correction Encoder/Decoder IP in Emulation & Silicon

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Two-Stage Framework for Corner Case Stimuli Generation Using Transformer and Reinforcement Learning

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Test Parameter Tuning with Blackbox Optimization: A Simple Yet Effective Way to Improve Coverage

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Read More… from Test Parameter Tuning with Blackbox Optimization: A Simple Yet Effective Way to Improve Coverage

SystemC Virtual Prototype: Ride the earliest train for Time-To-Market!

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Systematic Constraint Relaxation (SCR): Hunting for Over-Constrained Stimulus

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Successive Refinement – An Approach to Decouple Front End and Back End Power Intent

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Raising the Level of Formal Signoff with End-to-End Checking Methodology

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PSS Action Sequence Modeling Using Machine Learning

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Read More… from PSS Action Sequence Modeling Using Machine Learning

Problematic Bi-Directional Port Connections: How Well Is Your Simulator Filling the UPF LRM Void?

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Read More… from Problematic Bi-Directional Port Connections: How Well Is Your Simulator Filling the UPF LRM Void?

Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads Using Hybrid System Level Emulation SoC Platform

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Path-Based UPF Strategies: Optimally Manage Power on Your Designs

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Optimizing Turnaround Times in a Continuous Integration Flow Using a Scheduler Based Implementation

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Novel GUI Based UVM Test Bench Template Builder

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Never Too Late With Formal: Stepwise Guide for Applying Formal Verification in Post-Silicon Phase to Avoid Re-Spins

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Modeling Memory Coherency During Concurrent/Simultaneous Accesses

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Modeling Analog Devices using SV-RNM

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Mixed-Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP Simulation

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Read More… from Mixed-Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP Simulation

Mixed-Signal Design Verification: Leveraging the Best of AMS and DMS

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Metadata Based Testbench Generation Automation

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Maximizing Formal ROI through Accelerated IP Verification Sign-off

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Machine Learning Based Verification Planning Methodology Using Design and Verification Data

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Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges

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Leaping Left: Seamless IP to SoC Hand-off

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Is It a Software Bug? Is It a Hardware Bug?

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Innovative Uses of SystemVerilog Bind Statements within Formal Verification

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Hybrid Emulation: Accelerating Software Driven Verification and Debug

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How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage

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Hopscotch: A Scalable Flow-Graph Based Approach to Formally Specify and Verify Memory-Tagged Store Execution in Arm CPUs

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Hierarchical UPF: Uniform UPF across FE & BE

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Fnob: Command Line-Dynamic Random Generator

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Flattening the UVM Learning Curve Automated Solutions for DSP Filter Verification

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Finding a Needle in a Haystack: A Novel Log Analysis Method with Test Clustering in Distributed Systems

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Reusable System-Level Power-Aware IP Modeling Approach

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Evaluating the Feasibility of a RISCV Core for Real-Time Applications Using a Virtual Prototype

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Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software Verification

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Emulation Based Power and Performance Workloads on ML NPUs

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Read More… from Emulation Based Power and Performance Workloads on ML NPUs

Confidently Sign-Off Any Low-Power Designs Without Consequences

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Co-Developing Firmware and IP with PSS

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Case Study: Successes and Challenges of Validation Content Reuse

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CAMEL: A Flexible Cache Model for Cache Verification

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Read More… from CAMEL: A Flexible Cache Model for Cache Verification

Caching Tool Run Results in Large-Scale RTL Development Projects

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Read More… from Caching Tool Run Results in Large-Scale RTL Development Projects

BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering Problem

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Avoiding Confounding Configurations An RDC Methodology for Configurable Designs

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Automatic Translation of Natural Language to SystemVerilog Assertions

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Advanced UVM Command Line Processor for Central Maintenance and Randomization of Control Knobs

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Advanced Functional Verification for Automotive System on a Chip

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Adaptive Test Generation for Fast Functional Coverage Closure

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Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing Products

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Read More… from Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing Products

Accelerating Error Handling Verification of Complex Systems: A Formal Approach

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A UVM SystemVerilog Testbench for Analog/Mixed-Signal Verification: A Digitally-Programmable Analog Filter Example

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A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain Crossings

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A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation

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Read More… from A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation

A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISCV Core

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Read More… from A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISCV Core

Why Not “Connect” Using UVM Connect: Mixed Language Communication Got Easier with UVMC

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Read More… from Why Not “Connect” Using UVM Connect: Mixed Language Communication Got Easier with UVMC

Successive Refinement – An Approach to Decouple Front Front-End and Back Back-End Power Intent

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Read More… from Successive Refinement – An Approach to Decouple Front Front-End and Back Back-End Power Intent

Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads using Hybrid System Level Emulation SoC Platform

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Read More… from Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads using Hybrid System Level Emulation SoC Platform

Novel GUI Based UVM Test Bench Template Builder

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Read More… from Novel GUI Based UVM Test Bench Template Builder

Modeling Analog Devices Using SV-RNM

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Read More… from Modeling Analog Devices Using SV-RNM

Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges

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Read More… from Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges

Hybrid Emulation: Accelerating Software Driven Verification and Debug

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Read More… from Hybrid Emulation: Accelerating Software Driven Verification and Debug

Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software Verification

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Read More… from Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software Verification

Emulation Based Power and Performance Workloads on ML NPUs

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Read More… from Emulation Based Power and Performance Workloads on ML NPUs

Confidently Sign-off Any low-Power Designs without Consequences

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Read More… from Confidently Sign-off Any low-Power Designs without Consequences

Successes and Challenges of Validation Content Reuse

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Read More… from Successes and Challenges of Validation Content Reuse

Avoiding Confounding Configurations an RDC Methodology for Configurable Designs

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Read More… from Avoiding Confounding Configurations an RDC Methodology for Configurable Designs

Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing Products

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Read More… from Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing Products

A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation

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Read More… from A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation

What Does The Sequence Say? Powering Productivity with Polymorphism

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Read More… from What Does The Sequence Say? Powering Productivity with Polymorphism

Portable Stimulus Standard’s Hardware Software Interface (HSI) to validate 4G 5G Forward Error Correction Encoder/Decoder IP in Emulation Silicon

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Read More… from Portable Stimulus Standard’s Hardware Software Interface (HSI) to validate 4G 5G Forward Error Correction Encoder/Decoder IP in Emulation Silicon

Two Stage Framework for Corner Case Stimuli Generation Using Transformer and Reinforcement Learning

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Test Parameter Tuning with Blackbox Optimization: A Simple Yet Effective Way to Improve Coverage

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Read More… from Test Parameter Tuning with Blackbox Optimization: A Simple Yet Effective Way to Improve Coverage

SystemC Virtual Prototype: Ride the Earliest Train for Time-To-Market

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Read More… from SystemC Virtual Prototype: Ride the Earliest Train for Time-To-Market

Systematic Constraint Relaxation (SCR): Hunting for Over Constrained Stimulus

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Read More… from Systematic Constraint Relaxation (SCR): Hunting for Over Constrained Stimulus

Raising the level of Formal Signoff with End to End Checking Methodology

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Read More… from Raising the level of Formal Signoff with End to End Checking Methodology

PSS Action Sequence Modeling Using Machine Learning

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Read More… from PSS Action Sequence Modeling Using Machine Learning

Problematic Bi-Directional Port Connections: How Well is Your Simulator Filling the UPF LRM Void?

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Read More… from Problematic Bi-Directional Port Connections: How Well is Your Simulator Filling the UPF LRM Void?

Path-based UPF Strategies: Optimally Manage Power on your Designs

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Read More… from Path-based UPF Strategies: Optimally Manage Power on your Designs

Optimizing Turnaround Times In A CI Flow Using a Scheduler Implementation

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Read More… from Optimizing Turnaround Times In A CI Flow Using a Scheduler Implementation

Never Too Late with Formal: Stepwise Guide for Applying FV in Post Si Phase to Avoid Re-Spins

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Read More… from Never Too Late with Formal: Stepwise Guide for Applying FV in Post Si Phase to Avoid Re-Spins

Modeling Memory Coherency for Concurrent/Parallel Accesses

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Read More… from Modeling Memory Coherency for Concurrent/Parallel Accesses

Hierarchical UPF: Uniform UPF across FE & BE

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Read More… from Hierarchical UPF: Uniform UPF across FE & BE

Fnob: Command Line-Dynamic Random Generator

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Read More… from Fnob: Command Line-Dynamic Random Generator

Flattening the UVM Learning Curve: Automated Solutions for DSP Filter Verification

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Read More… from Flattening the UVM Learning Curve: Automated Solutions for DSP Filter Verification

Finding a Needle in a Haystack: A Novel Log Analysis Method with Test Clustering in Distributed System

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Read More… from Finding a Needle in a Haystack: A Novel Log Analysis Method with Test Clustering in Distributed System

Extension of the Power-Aware IP Reuse Approach to ESL

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Read More… from Extension of the Power-Aware IP Reuse Approach to ESL

Evaluating the Feasibility of a RISC V Core for Real Time Applications Using a Virtual Prototype

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Read More… from Evaluating the Feasibility of a RISC V Core for Real Time Applications Using a Virtual Prototype

Co-Developing IP and SoC Bring-Up Firmware with PSS

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Read More… from Co-Developing IP and SoC Bring-Up Firmware with PSS

CAMEL – A Flexible Cache Model for Cache Verification

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Read More… from CAMEL – A Flexible Cache Model for Cache Verification

Caching Tool Run Results in Large Scale RTL Development Projects

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Read More… from Caching Tool Run Results in Large Scale RTL Development Projects

BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering Problem

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Read More… from BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering Problem

Automatic Translation of Natural Language to SystemVerilog Assertions

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Read More… from Automatic Translation of Natural Language to SystemVerilog Assertions

Advanced UVM Command Line Processor

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Read More… from Advanced UVM Command Line Processor

Advanced Functional Verification for Automotive System on a Chip

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Read More… from Advanced Functional Verification for Automotive System on a Chip

Adaptive Test Generation for Fast Functional Coverage Closure

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Read More… from Adaptive Test Generation for Fast Functional Coverage Closure

Accelerating Error Handling Verification Of Complex Systems: A Formal Approach

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Read More… from Accelerating Error Handling Verification Of Complex Systems: A Formal Approach

A Hybrid Verification Solution to RISC V Vector Extension

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Read More… from A Hybrid Verification Solution to RISC V Vector Extension

A UVM Testbench for Analog Verification: A Programmable Filter Example

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Read More… from A UVM Testbench for Analog Verification: A Programmable Filter Example

A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain Crossings

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Read More… from A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain Crossings

A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISC V Core

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Read More… from A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISC V Core

Mixed Signal Design Verification: Leveraging the Best of AMS and DMS

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Read More… from Mixed Signal Design Verification: Leveraging the Best of AMS and DMS

Modeling Memory Coherency for concurrent/parallel accesses

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Read More… from Modeling Memory Coherency for concurrent/parallel accesses

Mixed Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP Simulation

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Read More… from Mixed Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP Simulation

Metadata Based Testbench Generation

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Read More… from Metadata Based Testbench Generation

Maximizing Formal ROI through Accelerated IP Verification Sign-off

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Read More… from Maximizing Formal ROI through Accelerated IP Verification Sign-off

Machine Learning Based Verification Planning Methodology Using Design and Verification Data

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Read More… from Machine Learning Based Verification Planning Methodology Using Design and Verification Data

Leaping Left: Seamless IP to SoC Hand off

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Read More… from Leaping Left: Seamless IP to SoC Hand off

Is It a Software Bug? It Is a Hardware Bug?

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Read More… from Is It a Software Bug? It Is a Hardware Bug?

Innovative Uses of SystemVerilog Bind Statements within Formal Verification

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Read More… from Innovative Uses of SystemVerilog Bind Statements within Formal Verification

How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage

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Read More… from How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage

Hopscotch: A Scalable Flow-Graph Based Approach to Verify CPU Store Execution

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Read More… from Hopscotch: A Scalable Flow-Graph Based Approach to Verify CPU Store Execution

Low Power Apps (Shaping the Future of Low Power Verification)

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Read More… from Low Power Apps (Shaping the Future of Low Power Verification)

Unveil the Mystery of Code Coverage in Low Power Designs (Achieving Power Aware Verification Closure)

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Read More… from Unveil the Mystery of Code Coverage in Low Power Designs (Achieving Power Aware Verification Closure)

Error Injection in a Subsystem Level Constrained Random UVM Testbench

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Using Automation to Close the Loop Between Functional Requirements and Their Verification

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Read More… from Using Automation to Close the Loop Between Functional Requirements and Their Verification

Formal Verification of Floating-Point Hardware with Assertion-Based VIP

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Read More… from Formal Verification of Floating-Point Hardware with Assertion-Based VIP

Synthesis of Decoder Tables using Formal Verification Tools

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Read More… from Synthesis of Decoder Tables using Formal Verification Tools

Managing Highly Configurable Design and Verification

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Read More… from Managing Highly Configurable Design and Verification

Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation)

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Read More… from Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation)

Practical Scheme to Enhance Verification Turn-Around-Time by Using Reusable Harness Interface (RHI)

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Formal Verification of Connections at SoC-level

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Formal Architectural Specification and Verification of A Complex SOC

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Read More… from Formal Architectural Specification and Verification of A Complex SOC

Architectural Formal Verification of System-Level Deadlocks

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Read More… from Architectural Formal Verification of System-Level Deadlocks

An Efficient and Modular Approach for Formally Verifying Cache implementations

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Read More… from An Efficient and Modular Approach for Formally Verifying Cache implementations

UVM for HLS: An Expedient Approach to the Functional Verification of HLS Designs

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Read More… from UVM for HLS: An Expedient Approach to the Functional Verification of HLS Designs

How to Stay Out of the News with ISO26262-Compliant Verification

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Read More… from How to Stay Out of the News with ISO26262-Compliant Verification

My Testbench Used to Break! Now it Bends (Adapting to Changing Design Configurations)

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Read More… from My Testbench Used to Break! Now it Bends (Adapting to Changing Design Configurations)

Deploying Customized Solution for Graphics Registers with UVM1.2 RAL

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Simpler Register Model

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Read More… from Simpler Register Model

Making Autonomous Cars Safer – One chip at a time

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Read More… from Making Autonomous Cars Safer – One chip at a time

Automated Seed Selection Algorithm for an Arbitrary Test Suite

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Read More… from Automated Seed Selection Algorithm for an Arbitrary Test Suite

Debugging Functional Coverage Models Get The Most Out of Your Cover Crosses

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Read More… from Debugging Functional Coverage Models Get The Most Out of Your Cover Crosses

UVM Acceleration using Hardware Emulator at Pre-silicon Stage

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Read More… from UVM Acceleration using Hardware Emulator at Pre-silicon Stage

Transparently Checkpointing Software Test Benches to Improve Productivity of SOC Verification in an Emulation Environment

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Read More… from Transparently Checkpointing Software Test Benches to Improve Productivity of SOC Verification in an Emulation Environment

Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-Chips

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Read More… from Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-Chips

Just do it! Who cares if a Structural Analysis tool is using Formal Verification

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Read More… from Just do it! Who cares if a Structural Analysis tool is using Formal Verification

Automated Physical Hierarchy Generation: Tools and Methodology

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Read More… from Automated Physical Hierarchy Generation: Tools and Methodology

IDEs SHOULD BE AVAILABLE TO HARDWARE ENGINEERS TOO!

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VHDL 2018 New and Noteworthy

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IEEE-Compatible UVM Reference Implementation and Verification Components

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Read More… from IEEE-Compatible UVM Reference Implementation and Verification Components

Formal Verification in the Real World

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Read More… from Formal Verification in the Real World

Bridge the Portable Test and Stimulus to UVM Simulation Environment

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Read More… from Bridge the Portable Test and Stimulus to UVM Simulation Environment

Building Portable Stimulus Into your IP-XACT Flow

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Portable Stimulus vs Formal vs UVM: A Comparative Analysis of Verification Methodologies Throughout the Life of an IP Block

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Read More… from Portable Stimulus vs Formal vs UVM: A Comparative Analysis of Verification Methodologies Throughout the Life of an IP Block

Leveraging more from GLS: Using metric driven GLS stimuli to boost timing verification

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Using Formal to Exhaustively Determine Unsafe Clock Ratios Between Asynchronous Blocks

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Read More… from Using Formal to Exhaustively Determine Unsafe Clock Ratios Between Asynchronous Blocks

Clock Domain Crossing Challenges in Latch Based Designs

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Read More… from Clock Domain Crossing Challenges in Latch Based Designs

Improving Verification Predictability and Efficiency Using Big Data

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Read More… from Improving Verification Predictability and Efficiency Using Big Data

Don’t delay catching bugs: Using UVM based architecture to model external board delays

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Read More… from Don’t delay catching bugs: Using UVM based architecture to model external board delays

Making Security Verification “SECURE”

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Read More… from Making Security Verification “SECURE”

Ultimate Shift Left: Unleash the Power of UVM Virtual LAB Methodology upon SoC Verification

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Read More… from Ultimate Shift Left: Unleash the Power of UVM Virtual LAB Methodology upon SoC Verification

UVM testbench design for ISA functional verification of a microprocessor

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Read More… from UVM testbench design for ISA functional verification of a microprocessor

SoC Verification of Analog IP Integration through Automated, Formal-Based, Rule-driven Spec Generation

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Read More… from SoC Verification of Analog IP Integration through Automated, Formal-Based, Rule-driven Spec Generation

Is Specman Still Relevant? Using UVM-ML to Take Advantage of Multiple Verification Languages

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Read More… from Is Specman Still Relevant? Using UVM-ML to Take Advantage of Multiple Verification Languages

Fast Track Formal Verification Signoff

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Read More… from Fast Track Formal Verification Signoff

REUSABLE UPF: Transitioning from RTL to Gate Level Verification

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Read More… from REUSABLE UPF: Transitioning from RTL to Gate Level Verification

Managing and Automating Hw/Sw Tests from IP to SoC

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Read More… from Managing and Automating Hw/Sw Tests from IP to SoC

Holistic Approach to IO Timing Verification Using Portable Stimulus and Assertions

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Read More… from Holistic Approach to IO Timing Verification Using Portable Stimulus and Assertions

Unraveling the Complexities of Functional Coverage: An advanced guide to simplify your use model

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Read More… from Unraveling the Complexities of Functional Coverage: An advanced guide to simplify your use model

UVM and C – Perfect Together

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Read More… from UVM and C – Perfect Together

Coverage Driven Distribution of Constrained Random Stimuli

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Read More… from Coverage Driven Distribution of Constrained Random Stimuli

UVM Sans UVM An approach to automating UVM testbench writing

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Read More… from UVM Sans UVM An approach to automating UVM testbench writing

Run-Time Phasing in UVM: Ready for the Big Time or Dead in the Water?

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Read More… from Run-Time Phasing in UVM: Ready for the Big Time or Dead in the Water?

UVM’s MAM to the Rescue

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UVM Rapid Adoption: A Practical Subset of UVM

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Read More… from UVM Rapid Adoption: A Practical Subset of UVM

Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to Simulation

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Read More… from Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to Simulation

Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication bridge

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