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Event Location: United States

DVCon USA 2023 Proceedings

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The CHIPS ACT and Its Impact On The Design & Verification Markets

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UVM Working Group Releases 1800.2-2020-2.0 Library

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User Experiences with the Portable Stimulus Standard

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Getting Beyond ISA Compliance: Advanced Core/SoC Verification for RISC-V and other Beasts

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Understanding the RISC-V Verification Ecosystem

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What is new in IP-XACT Std. IEEE 1685-2022?

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The Growing Need for End-to-end Protocol Verification for IP to Multi-die Systems

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A Wholistic Approach to Optimizing Your System Verification Flow

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Verification 2.0 – Multi-Engine, Multi-Run AI Driven Verification

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Richard Weber, Jamsheed Agahi, Josh Rensch, Eric Sherk

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Hardware/Software Interface Formats A Discussion

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Democratizing Digital-centric Mixed-signal Verification methodologies

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Harnessing the Power of UVM for AMS Verification with XMODEL

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Next Frontier in Formal Verification

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Pushbutton Complete IP Generation

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Verification of Inferencing Algorithm Accelerators

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Evolutionary and Revolutionary Innovation for Effective Verification Management & Closure

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Accelerate Coverage Closure from Day-1 with AI-driven Verification

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Static Sign-Off Best Practices Learnings and Experiences from Industry Use Cases

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A Methodology for Power and Energy Efficient Systems Design

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Migrating from UVM to UVM-AMS

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User Experiences with the Portable Stimulus Standard

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Regvue Modern Hardware/Software Interface Documentation

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Survey of Machine Learning (ML) Applications in Functional Verification (FV)

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Using a modern build system to speed up complex hardware design

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Tree Data Framework for Code Generation: Application of Generating UVM Testbench for Complex Designs

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Read More… from Tree Data Framework for Code Generation: Application of Generating UVM Testbench for Complex Designs

The Evolution of RISC-V Processor Verification

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Avoiding Configuration Madness The Easy Way

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Verifying RO registers: Challenges and the solution

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Read More… from Verifying RO registers: Challenges and the solution

What’s Next for SystemVerilog in the Upcoming IEEE 1800 standard

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Read More… from What’s Next for SystemVerilog in the Upcoming IEEE 1800 standard

A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers

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Read More… from A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers

Random Testcase Generation and Verification of Debug Unit for a RISC-V Processor Core

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What I Wish My Regression Run Manager’s Vendor Knew!

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Security Verification using Perspec/Portable Stimulus

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Dr. Shahid Ikram, Distinguished Engineer, Marvell Semi Mark Eslinger, Product Engineer, Siemens

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Demystifying Formal Testbenches: Tips, Tricks, and Recommendations

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Debarshi Chatterjee, Spandan Kachhadia, Chen Luo, Kumar Kushal, Siddhanth Dhodhi

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GraphCov: RTL Graph Based Test Biasing for Exploring Uncharted Coverage Landscape

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Improve Emulator Test Quality By Applying Synthesizable Functional Coverage

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UVM-SV Feedback Loop – The foundation of Self-Improving Testbenches

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Read More… from UVM-SV Feedback Loop – The foundation of Self-Improving Testbenches

A Simulation Expert’s Guide to Formally Proving SW Status and Interrupts

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The Untapped Power of UVM Resources and Why Engineers Should Use the uvm_resource_db API

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Automated Thread Evaluation of Various RISC-V Alternatives using Random Instruction Generation

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See the Forest for the Trees – How to Effectively Model and Randomize a DRT Structure

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Power models & Terminal Boundary: Get your IP Ready for Low Power

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Automation for Early Detection of X-propagation in Power-Aware Simulation Verification using UPF IEEE 1801

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Strategies to Maximize Reusability of UVM Test Scenarios in SoC Verification

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Complex Safety Mechanisms Require Interoperability and Automation For Validation And Metric Closure

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Closing Functional Coverage With Deep Reinforcement Learning A Compression Encoder Example

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Hierarchical UPF Design – The ‘Easy’ Way

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DatagenDV: Python Constrained Random Test Stimulus Framework

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Deadlock Free Design Assurance Using Architectural Formal Verification

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Read More… from Deadlock Free Design Assurance Using Architectural Formal Verification

Exploring Machine Learning to assign debug priorities to improve the design quality

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Read More… from Exploring Machine Learning to assign debug priorities to improve the design quality

Doing the Impossible: Using Formal Verification on Packet Based Data Paths

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It’s Not Too Late to Adopt: The Full Power of UVM

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Is Your System’s Security preserved? Verification of Security IP integration

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Read More… from Is Your System’s Security preserved? Verification of Security IP integration

Automated Modeling Testbench Methodology Tested with four Types of PLL Models

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Read More… from Automated Modeling Testbench Methodology Tested with four Types of PLL Models

FSM Minesweeper – Scalable FV Methodology for Detecting Hangs in Interacting FSMs

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Identifying unique power scenarios with data mining techniques at full SoC level with real workloads

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Creating 5G Test Scenarios, the Constrained-Random way

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Take AIM! Introducing the Analog Information Model

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An Enhanced DV Approach for Effectively Verifying High Speed, Low Power MIPI-MPHY 5.0 Designs

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Accelerating Functional Verification Through Stabilization of Testbench Using AI/ML

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Do not forget to ‘Cover’ your SystemC code with UVMC

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Read More… from Do not forget to ‘Cover’ your SystemC code with UVMC

Improvement of UVM IP Validation using Portable Stimulus (PSS)

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Read More… from Improvement of UVM IP Validation using Portable Stimulus (PSS)

A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers

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Read More… from A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers

Pragmatic Formal Verification of Sequential Error Detection and Correction Codes (ECCs) used in Safety-Critical Design

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Read More… from Pragmatic Formal Verification of Sequential Error Detection and Correction Codes (ECCs) used in Safety-Critical Design

Verification Macros: Maintain the integrity of verifiable IP UPF through integration

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Read More… from Verification Macros: Maintain the integrity of verifiable IP UPF through integration

System-Level Power Estimation of SSDs under Real Workloads using Emulation

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Read More… from System-Level Power Estimation of SSDs under Real Workloads using Emulation

A Hardware and Software Integrated Power Optimization Approach with Power Aware Simulations at SOC

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Read More… from A Hardware and Software Integrated Power Optimization Approach with Power Aware Simulations at SOC

UVM Based Mixed-Signal Verification of a Display PMIC Designed for OLED Display Applications

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Read More… from UVM Based Mixed-Signal Verification of a Display PMIC Designed for OLED Display Applications

Accelerated Verification of NAND Flash Memory using HW Emulator

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Read More… from Accelerated Verification of NAND Flash Memory using HW Emulator

Leveraging UVM-based Low Power Package Library to SOC Designs

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Read More… from Leveraging UVM-based Low Power Package Library to SOC Designs

Automation Methodology for Bus Performance Verification using IP-XACT

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Read More… from Automation Methodology for Bus Performance Verification using IP-XACT

Discover Over-Constraints by Leveraging Formal Tool

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Read More… from Discover Over-Constraints by Leveraging Formal Tool

Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal Verification

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Read More… from Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal Verification

A Study on Virtual Prototyping based Design Verification Methodology

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Read More… from A Study on Virtual Prototyping based Design Verification Methodology

Check Low-Power Violations by Using Machine Learning Based Classifier

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DVCon US 2023 Proceedings

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Read More… from DVCon US 2023 Proceedings

An Enhanced DV Approach for Effectively Verifying High Speed, Low Power MIPI-MPHY5.0 Designs

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Accelerating Functional Verification Through Stabilization of Testbench Using AI/ML

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Regvue Modern Hardware/Software Interface (HSI) Documentation

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Read More… from Regvue Modern Hardware/Software Interface (HSI) Documentation

A Survey of Machine Learning Applications in Functional Verification

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Read More… from A Survey of Machine Learning Applications in Functional Verification

Do not forget to ‘Cover’ your SystemC code with UVMC

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Read More… from Do not forget to ‘Cover’ your SystemC code with UVMC

Using a modern software build system to speed up complex hardware design

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Read More… from Using a modern software build system to speed up complex hardware design

Improvement of UVM Scenario Generation, Control and Reproducibility using Portable Stimulus (PSS) for IP Validation

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Read More… from Improvement of UVM Scenario Generation, Control and Reproducibility using Portable Stimulus (PSS) for IP Validation

Tree Data Framework for Code Generation: Application of Generating UVM Testbench for Complex Designs

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The Evolution of RISC-V Processor Verification: Open Standards and Verification IP

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Read More… from The Evolution of RISC-V Processor Verification: Open Standards and Verification IP

Avoiding Configuration Madness The Easy Way

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Verifying RO registers: Challenges and the solution

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What’s Next for SystemVerilog in the Upcoming IEEE 1800 standard

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Read More… from What’s Next for SystemVerilog in the Upcoming IEEE 1800 standard

Do not forget to ‘Cover’ your SystemC code with UVMC

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Read More… from Do not forget to ‘Cover’ your SystemC code with UVMC

Random Testcase Generation and Verification of Debug Unit for a RISC-V Processor Core

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What I Wish My Regression Run Manager’s Vendor Knew!

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Pragmatic Formal Verification of Sequential Error Detection and Correction Codes (ECCs) used in Safety-Critical Design

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Read More… from Pragmatic Formal Verification of Sequential Error Detection and Correction Codes (ECCs) used in Safety-Critical Design

RISC-V Security Verification using Perspec/Portable Stimulus

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SystemVerilog Real Models for an InMemory Compute Design

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Verification Macros: Maintain the integrity of verifiable IP UPF through integration

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Read More… from Verification Macros: Maintain the integrity of verifiable IP UPF through integration

System-Level Power Estimation of SSDs under Real Workloads using Emulation

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Read More… from System-Level Power Estimation of SSDs under Real Workloads using Emulation

Demystifying Formal Testbenches: Tips, Tricks, and Recommendations

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Read More… from Demystifying Formal Testbenches: Tips, Tricks, and Recommendations

Early Detection of Functional Corner Case Bugs using Methodologies of the ISO 26262

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Read More… from Early Detection of Functional Corner Case Bugs using Methodologies of the ISO 26262

A Hardware and Software integrated power optimization approach with power aware simulations at SOC

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Read More… from A Hardware and Software integrated power optimization approach with power aware simulations at SOC

GraphCov: RTL Graph Based Test Biasing for Exploring Uncharted Coverage Landscape

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Read More… from GraphCov: RTL Graph Based Test Biasing for Exploring Uncharted Coverage Landscape

UVM Based Mixed-Signal Verification of a Display PMIC Designed for OLED Display Applications

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Accelerated Verification of NAND Flash Memory using HW Emulator

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Read More… from Accelerated Verification of NAND Flash Memory using HW Emulator

Improve emulator test quality by applying synthesizable functional coverage

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UVM-SV Feedback Loop – The Foundation of Self-Improving Testbenches

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A Simulation Expert’s Guide to Formally Verifying Software Status and Interrupts

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Successive Refinement of UPF Power Switches

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The Untapped Power of UVM Resources and Why Engineers Should Use the uvm_resource_db API

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Automated Thread Evaluation of Various RISC-V Alternatives using Random Instruction Generators

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See the Forest for the Trees – How to Effectively Model and Randomize a Directed Rooted Tree Structure

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Power Models and Terminal Boundary: Get your IP Ready for Low Power

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Leveraging UVM-based Low Power Package Library to SOC Designs

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Automation for Early Detection of Xpropagation in Power-Aware Simulation Verification using UPF IEEE 1801

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Functional Instruction Set Simulator (ISS) of a Neural Network Accelerator IP with native “brain float16” format

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Automation Methodology for Bus Performance Verification using IP-XACT

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Read More… from Automation Methodology for Bus Performance Verification using IP-XACT

Discover Over-Constraints by Leveraging Formal Tool

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Read More… from Discover Over-Constraints by Leveraging Formal Tool

Strategies to Maximize Reusability of UVM Test Scenarios in SoC Verification

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Read More… from Strategies to Maximize Reusability of UVM Test Scenarios in SoC Verification

Complex Safety Mechanisms Require Interoperability and Automation For Validation And Metric Closure

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Read More… from Complex Safety Mechanisms Require Interoperability and Automation For Validation And Metric Closure

Closing Functional Coverage With Deep Reinforcement Learning: A Compression Encoder Example

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Read More… from Closing Functional Coverage With Deep Reinforcement Learning: A Compression Encoder Example

DatagenDV: Python Constrained Random Test Stimulus Framework

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Read More… from DatagenDV: Python Constrained Random Test Stimulus Framework

Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal Verification

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Read More… from Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal Verification

A Study on Virtual Prototyping based Design Verification Methodology

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Read More… from A Study on Virtual Prototyping based Design Verification Methodology

Deadlock Free Design Assurance Using Architectural Formal Verification

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Read More… from Deadlock Free Design Assurance Using Architectural Formal Verification

Exploring Machine Learning to assign debug priorities to improve the design quality

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Read More… from Exploring Machine Learning to assign debug priorities to improve the design quality

Doing the Impossible: Using Formal Verification on Packet Based Data Paths

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Read More… from Doing the Impossible: Using Formal Verification on Packet Based Data Paths

It’s Not Too Late to Adopt: The Full Power of UVM

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Read More… from It’s Not Too Late to Adopt: The Full Power of UVM

Is Your System’s Security preserved? Verification of Security IP integration

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Read More… from Is Your System’s Security preserved? Verification of Security IP integration

Check Low-Power Violations by Using Machine Learning Based Classifier

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Automated Modeling Testbench Methodology Tested with four Types of PLL Models

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Read More… from Automated Modeling Testbench Methodology Tested with four Types of PLL Models

FSM Minesweeper – Scalable Formal Verification Methodology for Detecting Hangs in Interacting FSMs

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Read More… from FSM Minesweeper – Scalable Formal Verification Methodology for Detecting Hangs in Interacting FSMs

Identifying unique power scenarios with data mining techniques at full SoC level with real workloads

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Read More… from Identifying unique power scenarios with data mining techniques at full SoC level with real workloads

Creating 5G Test Scenarios, the Constrained-Random way

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Read More… from Creating 5G Test Scenarios, the Constrained-Random way

Take AIM! Introducing the Analog Information Model

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Read More… from Take AIM! Introducing the Analog Information Model

Hierarchical UPF Design – The ‘Easy’ Way

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Read More… from Hierarchical UPF Design – The ‘Easy’ Way

DVCon U.S. 2022 Proceedings

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DVCon US 2022 Proceedings

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Bringing UVM to VHDL

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Accellera UVM-AMS Standard Update

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The Best Verification Strategy You’ve Never Heard Of

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System Verification with MatchLib

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Portable Stimulus Standard Update: PSS in the Real World

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Proven Strategies for Better Verification Planning: DVCon 2022 Workshop

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Machine Learning Driven Verification A Step Function in Productivity and Throughput

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Virtual Platforms to Shift-Left Software Development and System Verification

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Is Your Hardware Dependable?

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IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 90 minutes!

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Introduction to the 5 Levels of RISC-V Processor Verification

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“In-Emulator” UVM++ Randomized Testbenches for High Performance Functional Verification

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Finding Hidden Bugs In Deep Cycles: Advanced Debug Methodologies for Software-first System Validation

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Estimating Power Dissipation of End-User Application on RTL

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Building a Comprehensive Hardware Security Methodology

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An Overview of Security Annotation for Electronic Design Integration (SA-EDI) Standard

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Why Not “Connect” Using UVM Connect: Mixed Language Communication Got Easier with UVMC

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What Does The Sequence Say? Powering Productivity with Polymorphism

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Using PSS-2.0 Hardware-Software Interface to validate 4G/5G Forward Error Correction Encoder/Decoder IP in Emulation & Silicon

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Two-Stage Framework for Corner Case Stimuli Generation Using Transformer and Reinforcement Learning

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Test Parameter Tuning with Blackbox Optimization: A Simple Yet Effective Way to Improve Coverage

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SystemC Virtual Prototype: Ride the earliest train for Time-To-Market!

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Systematic Constraint Relaxation (SCR): Hunting for Over-Constrained Stimulus

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Successive Refinement – An Approach to Decouple Front End and Back End Power Intent

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Raising the Level of Formal Signoff with End-to-End Checking Methodology

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PSS Action Sequence Modeling Using Machine Learning

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Problematic Bi-Directional Port Connections: How Well Is Your Simulator Filling the UPF LRM Void?

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Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads Using Hybrid System Level Emulation SoC Platform

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Path-Based UPF Strategies: Optimally Manage Power on Your Designs

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Optimizing Turnaround Times in a Continuous Integration Flow Using a Scheduler Based Implementation

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Novel GUI Based UVM Test Bench Template Builder

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Never Too Late With Formal: Stepwise Guide for Applying Formal Verification in Post-Silicon Phase to Avoid Re-Spins

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Modeling Memory Coherency During Concurrent/Simultaneous Accesses

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Modeling Analog Devices using SV-RNM

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Read More… from Modeling Analog Devices using SV-RNM

Mixed-Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP Simulation

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Read More… from Mixed-Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP Simulation

Mixed-Signal Design Verification: Leveraging the Best of AMS and DMS

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Metadata Based Testbench Generation Automation

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Maximizing Formal ROI through Accelerated IP Verification Sign-off

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Machine Learning Based Verification Planning Methodology Using Design and Verification Data

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Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges

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Leaping Left: Seamless IP to SoC Hand-off

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Is It a Software Bug? Is It a Hardware Bug?

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Innovative Uses of SystemVerilog Bind Statements within Formal Verification

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Hybrid Emulation: Accelerating Software Driven Verification and Debug

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How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage

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Hopscotch: A Scalable Flow-Graph Based Approach to Formally Specify and Verify Memory-Tagged Store Execution in Arm CPUs

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Hierarchical UPF: Uniform UPF across FE & BE

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Fnob: Command Line-Dynamic Random Generator

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Supercharge Your Verification Using Rapid Expression Coverage as the Basis of a MC/DC-Compliant Coverage Methodology

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Verifying Multiple DUV Representations with a Single UVM-e Testbench

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Demystifying the UVM Configuration Database

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Making RAL Jump, an Introspection

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Applying Transaction-level Debug and Analysis Techniques to DUT Simulated Activity Using Data- Mining Techniques

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Resetting Anytime with the Cadence UVM Reset Package

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Novel Verification Techniques for ARM A15 Multi-core Subsystem Using IEEE 1647

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Title: Using Test-IP Based Verification Techniques in a UVM Environment

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