PSS Case Studies in Real-Life Projects: H/W Sequence Programming Guides with PSS, PSS Functional Tests for ATE / HVM […] Read More… from PSS Case Studies in Real-Life Projects: H/W Sequence Programming Guides with PSS, PSS Functional Tests for ATE / HVM
What Just Happened? Behavioral Coverage Tracking in PSS […] Read More… from What Just Happened? Behavioral Coverage Tracking in PSS
PSS Comes of Age: Runtime Behavioral Coverage, Methodology and More […] Read More… from PSS Comes of Age: Runtime Behavioral Coverage, Methodology and More
Introduction of IEEE 1801-2024 (UPF4.0) improvements for the specification and verification of low-power intent […] Read More… from Introduction of IEEE 1801-2024 (UPF4.0) improvements for the specification and verification of low-power intent
Accelerating Design & Verification with AI Agents […] Read More… from Accelerating Design & Verification with AI Agents
Accelerating Functional Verification with Machine Learning: Survey Applications […] Read More… from Accelerating Functional Verification with Machine Learning: Survey Applications
Modernizing the Hardware / Software Interface – Life beyond spreadsheets […] Read More… from Modernizing the Hardware / Software Interface – Life beyond spreadsheets
Moving Application-level Power Optimization to Pre-silicon with Advanced Hybrid Emulation and Power Exploration Technologies […] Read More… from Moving Application-level Power Optimization to Pre-silicon with Advanced Hybrid Emulation and Power Exploration Technologies
Next-Gen Verification Technologies for Processor-Based Systems […] Read More… from Next-Gen Verification Technologies for Processor-Based Systems
Emulation Driven Power Estimation for Real World Applications […] Read More… from Emulation Driven Power Estimation for Real World Applications
Step Functional Leaps in RTL Function Verification […] Read More… from Step Functional Leaps in RTL Function Verification
Power Dynamics Shaping the future of the data centric era […] Read More… from Power Dynamics Shaping the future of the data centric era
Comprehensive Glitch and Connectivity Sign-Off […] Read More… from Comprehensive Glitch and Connectivity Sign-Off
Beyond Integers and Floating Point: Designing and Verifying with Alternate Number Representations […] Read More… from Beyond Integers and Floating Point: Designing and Verifying with Alternate Number Representations
A Novel Approach for faster diagnostic coverage closure aided by STL of CPU Cores […] Read More… from A Novel Approach for faster diagnostic coverage closure aided by STL of CPU Cores
Future Proofing Power Intent Specification through Unified Power Format (UPF) 4.0 for Evolving Advanced State Retention Strategies […] Read More… from Future Proofing Power Intent Specification through Unified Power Format (UPF) 4.0 for Evolving Advanced State Retention Strategies
A Low-cost yet effective coverage model for fast functional coverage closure […] Read More… from A Low-cost yet effective coverage model for fast functional coverage closure
A Novel AI-ML Regression Flow for SoC verification […] Read More… from A Novel AI-ML Regression Flow for SoC verification
Catching the Elusive Voltage Spike with Analog/Mixed-Signal SVA/PSL Assertions […] Read More… from Catching the Elusive Voltage Spike with Analog/Mixed-Signal SVA/PSL Assertions
Applications of Supply Tunneling in Unified Power Format 4.0 for Mixed Signal Design […] Read More… from Applications of Supply Tunneling in Unified Power Format 4.0 for Mixed Signal Design
PSS and Protocol VIP: Like a Hand in a Glove […] Read More… from PSS and Protocol VIP: Like a Hand in a Glove
Leverage Real USB Device for USB Host DUT verification […] Read More… from Leverage Real USB Device for USB Host DUT verification
Sequencer Containers – A Unified and Simple Technique to Execute Both Sequences and Virtual Sequences […] Read More… from Sequencer Containers – A Unified and Simple Technique to Execute Both Sequences and Virtual Sequences
Guardians of the Chip: Mastering Next-Gen Security for SoCs and IPs […] Read More… from Guardians of the Chip: Mastering Next-Gen Security for SoCs and IPs
Expedite multi-die coherency verification through adaptive VIP subsystem […] Read More… from Expedite multi-die coherency verification through adaptive VIP subsystem
AI – accelerating coverage closure using intelligent stimulus generation […] Read More… from AI – accelerating coverage closure using intelligent stimulus generation
Functional Coverage Closure in SoC Interconnect Verification with Iterative Machine Learning […] Read More… from Functional Coverage Closure in SoC Interconnect Verification with Iterative Machine Learning
Register Access by Intent: Towards Generative RAL based Algorithms […] Read More… from Register Access by Intent: Towards Generative RAL based Algorithms
Test bench Framework for Fully Automated Register Tests of Numerous IPs in SoC […] Read More… from Test bench Framework for Fully Automated Register Tests of Numerous IPs in SoC
Don’t Go Changing: How to Code Immutable UVM Objects […] Read More… from Don’t Go Changing: How to Code Immutable UVM Objects
Accelerating Device Sign-off through a Unified Environment for DV, SV, and ATE with PSS […] Read More… from Accelerating Device Sign-off through a Unified Environment for DV, SV, and ATE with PSS
Reset Sweep Verification for Elimination of Reset Domain Crossing Blind Spots in Design […] Read More… from Reset Sweep Verification for Elimination of Reset Domain Crossing Blind Spots in Design
Accelerating Pre-Silicon Verification Coverage with Transaction Sequence Modeling […] Read More… from Accelerating Pre-Silicon Verification Coverage with Transaction Sequence Modeling
Refinable Macros and Terminal Boundaries in UPF 4.0: Empowering Soft IPs of the Future – Non-Intrusive Refinements for Seamless Soft IP (SIP) Integration […] Read More… from Refinable Macros and Terminal Boundaries in UPF 4.0: Empowering Soft IPs of the Future – Non-Intrusive Refinements for Seamless Soft IP (SIP) Integration
End-to-End Framework for Novel Datatype Arithmetic Verification […] Read More… from End-to-End Framework for Novel Datatype Arithmetic Verification
Real-Time Synchronization of C model with UVM Testbench […] Read More… from Real-Time Synchronization of C model with UVM Testbench
User Programmable Targeted UVM Debug Verbosity Escalation […] Read More… from User Programmable Targeted UVM Debug Verbosity Escalation
A Comprehensive Safety Verification Solution for SEooC Automotive SoC […] Read More… from A Comprehensive Safety Verification Solution for SEooC Automotive SoC
Robust Verification of Clock Tree Network using “Clock Monitor” Integrated by ACRMG […] Read More… from Robust Verification of Clock Tree Network using “Clock Monitor” Integrated by ACRMG
A Scalable Gray-Box Instance-Based Reachability Predictor for Automated DV Regression Scheduling […] Read More… from A Scalable Gray-Box Instance-Based Reachability Predictor for Automated DV Regression Scheduling
Stimulus Diversification and Coverage Closure of 3D NAND Flash with Artificial Intelligence […] Read More… from Stimulus Diversification and Coverage Closure of 3D NAND Flash with Artificial Intelligence
Lessons Learned Using Formal for Functional Safety […] Read More… from Lessons Learned Using Formal for Functional Safety
Addressing Advanced Mixed-Signal Verification Scenarios by Developing a UVM Framework for Analog Models […] Read More… from Addressing Advanced Mixed-Signal Verification Scenarios by Developing a UVM Framework for Analog Models
VerifLLMBench: An Open-Source Benchmark for Testbenches Generated with Large Language Models […] Read More… from VerifLLMBench: An Open-Source Benchmark for Testbenches Generated with Large Language Models
Automating Regression Triage and Reporting in Design Verification using AI-Based Random Forest Models […] Read More… from Automating Regression Triage and Reporting in Design Verification using AI-Based Random Forest Models
Reuse of System-level Circuit Models in Mixed-Signal Verification […] Read More… from Reuse of System-level Circuit Models in Mixed-Signal Verification
Automated Formal Verification of Area-Optimized Safety Registers in Automotive SoCs […] Read More… from Automated Formal Verification of Area-Optimized Safety Registers in Automotive SoCs
Automatic Test Pattern Generation Using Formal Verification and Fault Injection Methods […] Read More… from Automatic Test Pattern Generation Using Formal Verification and Fault Injection Methods
Performance verification for AI Heterogenous Multicore Systems using Portable Stimuli Standard […] Read More… from Performance verification for AI Heterogenous Multicore Systems using Portable Stimuli Standard
Saarthi: The First AI Formal Verification Engineer […] Read More… from Saarthi: The First AI Formal Verification Engineer
A Large Language Model-Based Framework for Enhancing Integrated Regression […] Read More… from A Large Language Model-Based Framework for Enhancing Integrated Regression
Time-Travel Debugging for High-Level Synthesis […] Read More… from Time-Travel Debugging for High-Level Synthesis
Breaking the Formal Verification Bottleneck […] Read More… from Breaking the Formal Verification Bottleneck
An Effective Digital Logic Verification Methodology of High Speed Interface IP Using a Configurable AFE Behavioral and Channel Model […] Read More… from An Effective Digital Logic Verification Methodology of High Speed Interface IP Using a Configurable AFE Behavioral and Channel Model
An Early Stage Coverage Measurement Methodology For Common Features Of System-On-Chip Verification, Using Design Metadata And Large Language Models […] Read More… from An Early Stage Coverage Measurement Methodology For Common Features Of System-On-Chip Verification, Using Design Metadata And Large Language Models
Continuous Integration in SoC Design: Challenges and Solutions […] Read More… from Continuous Integration in SoC Design: Challenges and Solutions
Technical Documents Version Management System Based on Large Language Models […] Read More… from Technical Documents Version Management System Based on Large Language Models
Hierarchical Formal Verification and Progress Checking of Network-On-Chip Design […] Read More… from Hierarchical Formal Verification and Progress Checking of Network-On-Chip Design
Reaching 100% Functional Coverage Using Machine Learning: A Journey of Persistent Efforts […] Read More… from Reaching 100% Functional Coverage Using Machine Learning: A Journey of Persistent Efforts
Accelerating the Functional Coverage through Machine Learning within a UVM Framework […] Read More… from Accelerating the Functional Coverage through Machine Learning within a UVM Framework
Towards Automated Verification IP Instantiation via LLMs […] Read More… from Towards Automated Verification IP Instantiation via LLMs
Design scheme for Emulator-friendly Memory Verification IP […] Read More… from Design scheme for Emulator-friendly Memory Verification IP
Automating Datapath Verification and Bug Correction via Equality Saturation […] Read More… from Automating Datapath Verification and Bug Correction via Equality Saturation
Bridging the Verification Gap in DSP Designs: A Case Study on LMS Adaptive Filter Datapath Cycle-Accurate Verification Using Generative AI and MATLAB DPIGEN […] Read More… from Bridging the Verification Gap in DSP Designs: A Case Study on LMS Adaptive Filter Datapath Cycle-Accurate Verification Using Generative AI and MATLAB DPIGEN
A Survey of Predictor Implementation using High-Level Language Co-simulation […] Read More… from A Survey of Predictor Implementation using High-Level Language Co-simulation
Session 3.5: Boost SoC Development Efficiency with Arteris SoC Integration Automation Software – Automate Design Flow and Register Management […] Read More… from Session 3.5: Boost SoC Development Efficiency with Arteris SoC Integration Automation Software – Automate Design Flow and Register Management
Session 3.1: AutoDV: Boost SoC Verification by Automatic Construction […] Read More… from Session 3.1: AutoDV: Boost SoC Verification by Automatic Construction
Session 2.8: A Comprehensive Data-Driven Function Verification Process […] Read More… from Session 2.8: A Comprehensive Data-Driven Function Verification Process
Session 2.7: Better Late Than Never – Collecting Coverage From Ones and Zeroes […] Read More… from Session 2.7: Better Late Than Never – Collecting Coverage From Ones and Zeroes
Session 2.3: Integrated verification ecosystem for regression management, coverage convergence, and debug automation […] Read More… from Session 2.3: Integrated verification ecosystem for regression management, coverage convergence, and debug automation
Session 2.2: Trojan Horse Detection for RISC-V Cores Using Cross-Auditing […] Read More… from Session 2.2: Trojan Horse Detection for RISC-V Cores Using Cross-Auditing
Session 2.1: The ASIC Renaissance – A glance into the future SoC enablement […] Read More… from Session 2.1: The ASIC Renaissance – A glance into the future SoC enablement
Session 1.8: Adopts ISA-Formal On High-End Out-Of-Order Execute RISC-V Cores […] Read More… from Session 1.8: Adopts ISA-Formal On High-End Out-Of-Order Execute RISC-V Cores
Session 1.7: Left-shifting Testbench Development Using Environment Inversion in UVM […] Read More… from Session 1.7: Left-shifting Testbench Development Using Environment Inversion in UVM
Session 1.6: Verifying Configurable AndesCore Processors by Using Portable Testing and Stimulus Standard (PSS) […] Read More… from Session 1.6: Verifying Configurable AndesCore Processors by Using Portable Testing and Stimulus Standard (PSS)
Session 1.5: Exploring Token-Based Strategies to Enhance Data Security and Memory Management in PCIe Devices […] Read More… from Session 1.5: Exploring Token-Based Strategies to Enhance Data Security and Memory Management in PCIe Devices
Session 1.3: Solving Memory Configurations Challenge with SVRAND Verification Flow […] Read More… from Session 1.3: Solving Memory Configurations Challenge with SVRAND Verification Flow
Session 1.2: Improving UVM test benches using UVM Run time phases […] Read More… from Session 1.2: Improving UVM test benches using UVM Run time phases
Keynote 3: Empowering Innovation in Logic Verification: Harnessing Collective Wisdom Across Tools, Processes, and People […] Read More… from Keynote 3: Empowering Innovation in Logic Verification: Harnessing Collective Wisdom Across Tools, Processes, and People
A Holistic Approach to RISC-V Processor Verification […] Read More… from A Holistic Approach to RISC-V Processor Verification
A Software infrastructure for Hardware Performance Assessment […] Read More… from A Software infrastructure for Hardware Performance Assessment
Breakthrough in CDC-RDC Verification Defining a Standard for Interoperable Abstract Model […] Read More… from Breakthrough in CDC-RDC Verification Defining a Standard for Interoperable Abstract Model
Calling All Engines – Faster Coverage Closure with Simulation, Formal, and Emulation […] Read More… from Calling All Engines – Faster Coverage Closure with Simulation, Formal, and Emulation
cocotb 2.0 – How to get the best out of the new major version of the Python-based testbench framework […] Read More… from cocotb 2.0 – How to get the best out of the new major version of the Python-based testbench framework
Comprehensive Glitch and Connectivity Sign-Off […] Read More… from Comprehensive Glitch and Connectivity Sign-Off
Developing Complex Systems using Model-Based Cybertronic Systems Engineering Methodology […] Read More… from Developing Complex Systems using Model-Based Cybertronic Systems Engineering Methodology
Efficient AI – Mastering Shallow Neural Networks from Training to RTL Implementation […] Read More… from Efficient AI – Mastering Shallow Neural Networks from Training to RTL Implementation
Exploring the Next-Generation of Debugging with Verification Management System and Integrated Development Environment […] Read More… from Exploring the Next-Generation of Debugging with Verification Management System and Integrated Development Environment
Novel Approach to Verification and Validation for Multi-die Systems […] Read More… from Novel Approach to Verification and Validation for Multi-die Systems
Harnessing the Strength of Statistics and Visualization in Verification […] Read More… from Harnessing the Strength of Statistics and Visualization in Verification
Solving verification challenges for complex devices with a limited number of ports using Debugports […] Read More… from Solving verification challenges for complex devices with a limited number of ports using Debugports
Trustworthiness Evaluation of Deep Learning Accelerators Using UVM-based Verification with Error Injection […] Read More… from Trustworthiness Evaluation of Deep Learning Accelerators Using UVM-based Verification with Error Injection
An easy to use Python framework for circuit sizing from designers for designers […] Read More… from An easy to use Python framework for circuit sizing from designers for designers
Modernizing the Hardware/Software Interface […] Read More… from Modernizing the Hardware/Software Interface
USF-based FMEDA-driven Functional Safety Verification […] Read More… from USF-based FMEDA-driven Functional Safety Verification
Unleash the Full Potential of Your Waveforms […] Read More… from Unleash the Full Potential of Your Waveforms
Keynote: Next 10x in AI – System, Silicon, Algorithms, Data […] Read More… from Keynote: Next 10x in AI – System, Silicon, Algorithms, Data
Keynote: Dependable microcontroller architectures – challenges and opportunities in a fast changing automotive market […] Read More… from Keynote: Dependable microcontroller architectures – challenges and opportunities in a fast changing automotive market
Your SoC, Your Topology: Interconnects used within SoCs […] Read More… from Your SoC, Your Topology: Interconnects used within SoCs
USF-based FMEDA-driven Functional Safety Verification […] Read More… from USF-based FMEDA-driven Functional Safety Verification
Large Language Models to generate SystemC Model Code […] Read More… from Large Language Models to generate SystemC Model Code
Streamlining Low Power Verification: From UPF to Signoff […] Read More… from Streamlining Low Power Verification: From UPF to Signoff
RISC-V Core Verification: A New Normal in Verification Techniques […] Read More… from RISC-V Core Verification: A New Normal in Verification Techniques
mL: Shrinking the Verification volume using Machine Learning […] Read More… from mL: Shrinking the Verification volume using Machine Learning
Hierarchical CDC and RDC closure with standard abstract models […] Read More… from Hierarchical CDC and RDC closure with standard abstract models
Expanding role of Static Signoff in Verification Coverage […] Read More… from Expanding role of Static Signoff in Verification Coverage
Emulation Moves Into 4-State Logic and Real Number Modeling DVCon US 2024 […] Read More… from Emulation Moves Into 4-State Logic and Real Number Modeling DVCon US 2024
Accellera Functional Safety Working Group Update and Next Steps […] Read More… from Accellera Functional Safety Working Group Update and Next Steps
Automatic generation of Programmer Reference Manual and Device Driver from PSS […] Read More… from Automatic generation of Programmer Reference Manual and Device Driver from PSS
Automating the Integration Workflow with IP-Centric Design […] Read More… from Automating the Integration Workflow with IP-Centric Design
Automatic generation of Programmer Reference Manual and Device Driver from PSS […] Read More… from Automatic generation of Programmer Reference Manual and Device Driver from PSS
Advanced UCIe-based Chiplets verification from IP to SoC […] Read More… from Advanced UCIe-based Chiplets verification from IP to SoC
DV UVM based AMS co-simulation and verification methodology for mixed signal designs […] Read More… from DV UVM based AMS co-simulation and verification methodology for mixed signal designs
SV_LUT: A SystemVerilog Look Up Table package for developing complex AMS Real Number Modeling […] Read More… from SV_LUT: A SystemVerilog Look Up Table package for developing complex AMS Real Number Modeling
A UVM SystemVerilog Testbench for Directed & Random Testing of an AMS LDO Voltage Regulator […] Read More… from A UVM SystemVerilog Testbench for Directed & Random Testing of an AMS LDO Voltage Regulator
Enabling True System-Level Mixed-Signal Emulation […] Read More… from Enabling True System-Level Mixed-Signal Emulation
New Innovative Way to Verify Package Connectivity […] Read More… from New Innovative Way to Verify Package Connectivity
UVM Testbench Automation for AMS Designs […] Read More… from UVM Testbench Automation for AMS Designs
Extending the RISC-V Verification Interface for Debug Module Co-Simulation […] Read More… from Extending the RISC-V Verification Interface for Debug Module Co-Simulation
Large Language Model for Verification: A Review and Its Application in Data Augmentation […] Read More… from Large Language Model for Verification: A Review and Its Application in Data Augmentation
Four Problems with Policy-Based Constraints and How to Fix Them […] Read More… from Four Problems with Policy-Based Constraints and How to Fix Them
Gherkin Implementation in SystemVerilog Brings Agile Behavior-Driven Development to UVM […] Read More… from Gherkin Implementation in SystemVerilog Brings Agile Behavior-Driven Development to UVM
Without Objection – Touring the uvm_objection implementations – uses and improvements […] Read More… from Without Objection – Touring the uvm_objection implementations – uses and improvements
Advanced UVM Based Chip Verification Methodologies with Full Analog Functionality […] Read More… from Advanced UVM Based Chip Verification Methodologies with Full Analog Functionality
Efficient application of AI algorithms for large-scale verification environments based on NoC architecture […] Read More… from Efficient application of AI algorithms for large-scale verification environments based on NoC architecture
Leveraging Interface Class to Improve UVM TLM […] Read More… from Leveraging Interface Class to Improve UVM TLM
Formal Verification Approach to Verifying Stream Decoders: Methodology & Findings […] Read More… from Formal Verification Approach to Verifying Stream Decoders: Methodology & Findings
Novel Method To Speed-Up UVM Testbench Development […] Read More… from Novel Method To Speed-Up UVM Testbench Development
Functional Verification from Chaos to Order: Using Continuous Integration for Hardware Functional Verification […] Read More… from Functional Verification from Chaos to Order: Using Continuous Integration for Hardware Functional Verification
Variation-Aware Modeling Method for MRAM Behavior Model using System-Verilog […] Read More… from Variation-Aware Modeling Method for MRAM Behavior Model using System-Verilog
Working within the Parameters that System Verilog has constrained us to […] Read More… from Working within the Parameters that System Verilog has constrained us to
All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification […] Read More… from All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification
RISC-V Testing Status and current state of the art […] Read More… from RISC-V Testing Status and current state of the art
Bus Trace System: Automating Bus Traffic Debugging in IP-XACT Based SoC […] Read More… from Bus Trace System: Automating Bus Traffic Debugging in IP-XACT Based SoC
Automated Generation of Interval Properties From Trace-Based Function Models […] Read More… from Automated Generation of Interval Properties From Trace-Based Function Models
Tackling Missing Bins: Refining Functional Coverage in SystemVerilog for Deterministic Coverage Closure […] Read More… from Tackling Missing Bins: Refining Functional Coverage in SystemVerilog for Deterministic Coverage Closure
Metric Driven Microcode Verification: Navigating Microcode Coverage Complexities […] Read More… from Metric Driven Microcode Verification: Navigating Microcode Coverage Complexities
Unleashing the Power of Whisper for block-level verification in high performance RISC-V CPU […] Read More… from Unleashing the Power of Whisper for block-level verification in high performance RISC-V CPU
AI based Media Functional Safety and Reliability Verification in Safety-Critical Autonomous Systems […] Read More… from AI based Media Functional Safety and Reliability Verification in Safety-Critical Autonomous Systems
Functional Verification of Analog Devices modeled using SV-RNM […] Read More… from Functional Verification of Analog Devices modeled using SV-RNM
A UVM Multi-Agent Verification IP architecture to enable Next-Gen protocols with enhanced reusability, controllability and observability […] Read More… from A UVM Multi-Agent Verification IP architecture to enable Next-Gen protocols with enhanced reusability, controllability and observability
Requirements Recognition for Verification IP Design Using Large Language Models […] Read More… from Requirements Recognition for Verification IP Design Using Large Language Models
Functional Safety Workflow of Internal IP (NPU) Within Large Automotive IC Through Analysis and Emulation Usage […] Read More… from Functional Safety Workflow of Internal IP (NPU) Within Large Automotive IC Through Analysis and Emulation Usage
Next-Generation Formal Property Verification: Lightweight Theorem Proving Integrated into Model Checking […] Read More… from Next-Generation Formal Property Verification: Lightweight Theorem Proving Integrated into Model Checking
Practical Asynchronous SystemVerilog Assertions […] Read More… from Practical Asynchronous SystemVerilog Assertions
Leveraging Model Based Verification for Automotive SoC Development […] Read More… from Leveraging Model Based Verification for Automotive SoC Development
Automated Formal Verification of a Highly-Configurable Register Generator […] Read More… from Automated Formal Verification of a Highly-Configurable Register Generator
Automating the Formal Verification of Firmware: A Novel Foundation and Scalable Methodology […] Read More… from Automating the Formal Verification of Firmware: A Novel Foundation and Scalable Methodology
Leveraging Functional Safety Methodologies to Enhance Design Quality in Automotive IC […] Read More… from Leveraging Functional Safety Methodologies to Enhance Design Quality in Automotive IC
Forward Progress in Formal Verification Liveness vs Safety […] Read More… from Forward Progress in Formal Verification Liveness vs Safety
Verification Plan in Requirements Management Tool: Simple Traceability and Automated Interface to Regression Manager […] Read More… from Verification Plan in Requirements Management Tool: Simple Traceability and Automated Interface to Regression Manager
Crafting a Million Instructions/Sec RISCV-DV HPC Techniques to Boost UVM Testbench Performance by Over 100x […] Read More… from Crafting a Million Instructions/Sec RISCV-DV HPC Techniques to Boost UVM Testbench Performance by Over 100x
PyRDV: a Python-based solution to the requirements traceability problem […] Read More… from PyRDV: a Python-based solution to the requirements traceability problem
Verification of an AXI cache controller using multi-thread approach based on OOP design pattern […] Read More… from Verification of an AXI cache controller using multi-thread approach based on OOP design pattern
Unified Architecture of L1 L2 Cache with Low Power Extensions for MultiCore UVM-based Library Package […] Read More… from Unified Architecture of L1 L2 Cache with Low Power Extensions for MultiCore UVM-based Library Package
Plug and Play Verification: Leveraging Block-Level Components for Seamless Top-Level Integration […] Read More… from Plug and Play Verification: Leveraging Block-Level Components for Seamless Top-Level Integration
Planning for RISC-V Success Verification Planning and Functional Coverage […] Read More… from Planning for RISC-V Success Verification Planning and Functional Coverage
Fault-injection-Enhanced Virtual Prototypes Enable Early SW Development for Automotive Applications […] Read More… from Fault-injection-Enhanced Virtual Prototypes Enable Early SW Development for Automotive Applications
An Elegant scoreboard eco-system deploying UVM Callbacks, Parameterization for Multimedia designs from Imaging perspective […] Read More… from An Elegant scoreboard eco-system deploying UVM Callbacks, Parameterization for Multimedia designs from Imaging perspective
Virtual Testing of Overtemperature Protection Algorithms in Automotive Smart Fuses […] Read More… from Virtual Testing of Overtemperature Protection Algorithms in Automotive Smart Fuses
Virtual ECUs with QEMU and SystemC TLM-2.0 […] Read More… from Virtual ECUs with QEMU and SystemC TLM-2.0
Towards a Hybrid Verification Environment for Signal Processing SoCs […] Read More… from Towards a Hybrid Verification Environment for Signal Processing SoCs
The Three Body Problem There’s more to building Silicon than EDA currently helps […] Read More… from The Three Body Problem There’s more to building Silicon than EDA currently helps
System-Level Simulation of a SPAD-Based Time-of-Flight Sensor in SystemVerilog […] Read More… from System-Level Simulation of a SPAD-Based Time-of-Flight Sensor in SystemVerilog
SysML v2 – An overview with SysMD demonstration […] Read More… from SysML v2 – An overview with SysMD demonstration
Smart TSV Repair Automation in 3DIC Designs […] Read More… from Smart TSV Repair Automation in 3DIC Designs
Scalable agile processor verification using SystemC UVM and friends […] Read More… from Scalable agile processor verification using SystemC UVM and friends
Reverse Hypervisor Hypervisor for fast SoC Simulation […] Read More… from Reverse Hypervisor Hypervisor for fast SoC Simulation
Pragmatic Formal Verification Methodology for Clock Domain Crossing […] Read More… from Pragmatic Formal Verification Methodology for Clock Domain Crossing
Open-Source Virtual Platforms for Industry and Research […] Read More… from Open-Source Virtual Platforms for Industry and Research
Model-Based Approach for Developing Optimal HW/SW Architectures for AI systems […] Read More… from Model-Based Approach for Developing Optimal HW/SW Architectures for AI systems
MetaPSS: An Automation Framework for Generation of Portable Stimulus Model […] Read More… from MetaPSS: An Automation Framework for Generation of Portable Stimulus Model
MapGL: Interactive Application Mapping and Profiling on a Grid of Processing Cells […] Read More… from MapGL: Interactive Application Mapping and Profiling on a Grid of Processing Cells
Pervasive and Sustainable AI with Adaptive Computing Architectures […] Read More… from Pervasive and Sustainable AI with Adaptive Computing Architectures
Energy-efficient High Performance Compute, at the heart of Europe […] Read More… from Energy-efficient High Performance Compute, at the heart of Europe
Integration Verification of Safety Components in Automotive Chip Modules […] Read More… from Integration Verification of Safety Components in Automotive Chip Modules
How to leverage the power of MATLAB from Functional Verification Test Benches […] Read More… from How to leverage the power of MATLAB from Functional Verification Test Benches
Grid-based Mapping and Analysis of a GoogLeNet CNN using MapGL Editor […] Read More… from Grid-based Mapping and Analysis of a GoogLeNet CNN using MapGL Editor
Fuzzing Firmware Running on Intel® Simics® Virtual Platforms […] Read More… from Fuzzing Firmware Running on Intel® Simics® Virtual Platforms
Exploring New Frontiers of High-Performance Verification with UVM-AMS […] Read More… from Exploring New Frontiers of High-Performance Verification with UVM-AMS
Efficient Debugging on Virtual Prototype using Reverse Engineering Method […] Read More… from Efficient Debugging on Virtual Prototype using Reverse Engineering Method
DSA Monitoring Framework for HW/SW Partitioning of Application Kernels leveraging VP […] Read More… from DSA Monitoring Framework for HW/SW Partitioning of Application Kernels leveraging VP
Co-Design of Automotive Boardnet Topology and Architecture […] Read More… from Co-Design of Automotive Boardnet Topology and Architecture
Closed-Loop Model-First SoC Development With the Intel® Simics® Simulator […] Read More… from Closed-Loop Model-First SoC Development With the Intel® Simics® Simulator
Accellera Functional Safety Working Group Update and Next Steps […] Read More… from Accellera Functional Safety Working Group Update and Next Steps
Accelerating Complex System Simulation using Parallel SystemC and FPGAs […] Read More… from Accelerating Complex System Simulation using Parallel SystemC and FPGAs
Accelerate Functional Coverage Closure Using Machine-Learning-Based Test Selection […] Read More… from Accelerate Functional Coverage Closure Using Machine-Learning-Based Test Selection
A scalable VIP component to increase robustness of co-verification within an ASIC […] Read More… from A scalable VIP component to increase robustness of co-verification within an ASIC
A Novel Approach to Standardize Verification Configurations using YAML […] Read More… from A Novel Approach to Standardize Verification Configurations using YAML
A Hybrid Approach For Interrupts Verification […] Read More… from A Hybrid Approach For Interrupts Verification
Autonomous Verification: Are We There Yet? […] Read More… from Autonomous Verification: Are We There Yet?
Accellera, Standards, and Semiconductor Supply Chain […] Read More… from Accellera, Standards, and Semiconductor Supply Chain
Techniques to identify reset metastability issues due to soft resets […] Read More… from Techniques to identify reset metastability issues due to soft resets
PropGen: An Automated Flow to Generate SVA Properties for Formal and Simulation methods […] Read More… from PropGen: An Automated Flow to Generate SVA Properties for Formal and Simulation methods
Statistical Analysis of Clock Domain Crossing […] Read More… from Statistical Analysis of Clock Domain Crossing
Formal Verification + CIA Triad: Winning Formula for Hardware Security […] Read More… from Formal Verification + CIA Triad: Winning Formula for Hardware Security
ASIL B/D Fault Campaign Strategy for Computer Vision core using Soft Test Library (STL) […] Read More… from ASIL B/D Fault Campaign Strategy for Computer Vision core using Soft Test Library (STL)
Holistic Verification of Bus Health Monitor in Automotive SoC using BHMVC and ParaHunter […] Read More… from Holistic Verification of Bus Health Monitor in Automotive SoC using BHMVC and ParaHunter
Fast Convergence Modular Advanced Smart-Hybrid Testbench (FCMAST) to automate and expedite SoC gate level simulations closure […] Read More… from Fast Convergence Modular Advanced Smart-Hybrid Testbench (FCMAST) to automate and expedite SoC gate level simulations closure
Robust Low Power Verification Strategy for a Complex 3DIC System with Split Power Management Architecture […] Read More… from Robust Low Power Verification Strategy for a Complex 3DIC System with Split Power Management Architecture
Wrong clamps can kill your chip!!….find them early […] Read More… from Wrong clamps can kill your chip!!….find them early
Disaggregated methodology in Multi-die SoC– A Server SoC Case Study […] Read More… from Disaggregated methodology in Multi-die SoC– A Server SoC Case Study
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