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AI-Driven Design and Verification – Scaling Complexity with Intelligence

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DVCON 2025 India Agenda

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DVCon India 2025: Selected Posters List

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DVCon India 2025: Selected Papers List

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DVCon India Awards 2025

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Accelerated Coverage Closure with Emulation: Covering Real-Time Use Case Corners

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A Hybrid Functional Verification Approach of complex designs using Python based Models

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Offline FSDB based Data-Integrity Debugger for Sub-System Emulation based Runs

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Efficient Verification of Multi-Die Systems using Multi-Die Co-Simulation Framework

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Novel Approach for Verification of Multi Die Booting Using Disruptive Distributed Simulation Methodology

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Breaking barriers in Advanced Multi-Chiplet AI SoCs using scalable UCIe and Boot Verification and Emulation techniques

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Catching the Unseen: A Case Study on Conquering Caching and Ordering Verification Challenges in Release Critical Unit

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Implementing and Verifying RISC-V Nexus Trace Compliant Trace Encoder for High Performance Cores

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Decoding the RAS Maze: Microscopic Complexity Meets Verification

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High-Bandwidth Memory (HBM) in Custom Compute Systems: An Architectural Exploration for Future Computing Paradigms

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System design exploration with fully customizable NoC

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PCIe and AXI domain traffic ordering – A Novel Approach

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Design and development of a Hybrid Out-of- Order RISC-V Processor Model

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Adaptive Multi-Modal Sensor Fusion Accelerator with Real-Time On-Device Learning for Dynamic Environments

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Efficient Booth Multiplier for FIR Filter Structure

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Decoding the Unknown: A Synergy of Formal and Simulation Methods for Unclassified Faults

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Uncovering Hardware Vulnerabilities: Formal Verification for Security-Focused Negative Testing

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Novel Formal Equivalence Approach to Verify Scalable Architecture in GPU

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Breaking Barriers: Formal Verification in Complex Compressor Controller Architecture

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Breaking Barriers: Formal Verification in Complex Compressor Controller

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Cherry-picking Assertions to Enhance Convergence

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Halstead, McCabe, and Lint in Action Quality Metrics for SystemVerilog Testbenches

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Solving Formal Complexity for Linked List Hardware Designs

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Navigating Complexity to Convergence: Formal Verification for Single Precision

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Reducing Area and Leakage Power: Novel Formal Methodology for Retention Sufficiency in Low Power Designs

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Robust Verification of Clock Tree Network using “Clock Monitor” Integrated by ACRMG

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Ensuring Deadlock-Free ASIC Operation: A Comprehensive Integration of Frequency and Operation Coverage Matrices

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Optimizing CPU-Based Configuration Path Verification Through Automated C Test Case Generation with UVM RAL

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CVM – A Library for Unified C++ and SystemVerilog Testbench Development

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Sequencer Coverage Exclusion Optimiser: Streamlining Coverage Closure in Dynamic Sequencer-Based Designs

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A Summary and Examination of UVM Virtual Sequence Techniques

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Pumping Up Test Development with Task Based, C-callable, UVM based Tests

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Pumping Up Test Development with Task Based, C-callable, UVM based Tests

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Accelerating Debug with Experience-Driven Insights: A Tool-Based Approach for IP and SoC-Level Verification

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Accelerating Debug with Experience-Driven Insights: A Tool-Based Approach for IP and SoC-Level Verification

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UVM Based Generic Interrupt Service Routine (gISR)

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UVM based Generic Interrupt Service Routine (gISR)

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9660:Analog feature modeling for memory devices in digital simulation

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Test Smarter, Not Harder: GNN-Powered Automation for Post-Silicon Validation

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Test Smarter, Not Harder : GNN-Powered Automation for Post-Silicon Validation

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Precision Unveiled: Formal Methods in Dot Product Accumulate ULP Analysis

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Precision Unveiled: Formal Methods in Dot Product Accumulate ULP Analysis

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An Ideal FuSa Verification Solution!

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An Ideal FuSa Verification Solution!

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Novel Use of Symbolic Map Based Constraints for Synchronization Block Verification Using Formal Methods

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Novel Use of Symbolic Map Based Constraints for Synchronization Block Verification Using Formal Methods

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Novel and optimized solution to accelerate gate level simulation for complex SOC

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Chain of Responsibility Design Pattern for scalable UVM drivers

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Chain of Responsibility Design Pattern for scalable UVM drivers

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Advancing Early Enablement, Validation, and Signoff of Manageability IP for Seamless dGPU-Server Paring

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Advancing Early Enablement, Validation, and Signoff of Manageability IP for Seamless dGPU-Server Paring

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SmartLint Booster: Automation of UVM Testbench Linting with AMIQ Verissimo

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SmartLint Booster: Automation of UVM Testbench Linting with AMIQ Verissimo

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TiDe : Timing diagram to Design verification model

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TiDe : Timing diagram to Design verification model

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Novel Customized Algorithm and Verification Checklist to Improve the Process of Register Verification in UVM

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Bridging RISC-V Core Verification and PSS: A Portable-Stimulus Stress-Testing Approach

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Bridging RISC-V Core Verification and PSS : A Portable-Stimulus Stress-Testing Approach

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Overcoming the roadblocks in Display Port Automotive Extensions verification

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Overcoming the roadblocks in Display Port Automotive Extensions verification

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Remote and Probeless Debug Methodology for Data Center Silicon Debugs

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Remote and Probeless Debug Methodology for Data Center Silicon Debugs

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Securing and Optimizing Data Flow by Validating Die Level Interconnect Stress with AES XTS 256-bit Encryption and Ring Interconnect Analysis on edge client SoCs

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Securing and Optimizing Data Flow by Validating Die Level Interconnect Stress with AES XTS 256-bit Encryption and Ring Interconnect Analysis on edge client SoCs

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Next-Generation CDC and RDC Closure: An AI/ML-Driven Approach for Automated and Validated Constraint

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Next-Generation CDC and RDC Closure

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PSS beyond reuse: Streamlining the DV effort for a low power multi-core SOC

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PSS beyond reuse: Streamlining the DV effort for a low power multi-core SOC

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Truth Beneath the trace : Formal Revealing Silicon Secrets

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Cognitive smoke testing

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Cognitive Smoke Testing

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Adaptive Multi-Modal Sensor Fusion Accelerator with Real-Time On-Device Learning for Dynamic Environments

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Adaptive Multi-Modal Sensor Fusion Accelerator with Real-Time On-Device Learning for Dynamic Environments

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AI-Enabled Formal Verification Flow: From Spec to Sign-off

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AI-Enabled Formal Verification Flow : From Spec to Sign-off

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Beyond Traditional Testing: Integrating DV and DFT for Zero-Defect Goals

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Beyond Traditional Testing: Integrating DV and DFT for Zero-Defect Goals

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AI-powered Chip Design: Spec to Silicon

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Re-Engineering Engineering

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Day 2 TPC Updates

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Introduction of IEEE 1801-2024 (UPF4.0) Improvements for the Specification and Verification of Low-Power

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System Verilog Assertions -Bindfiles & Best Known Practices for Simple SVA Usage

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Power Dynamics: Shaping the future of the data centric era and the role of AI

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PSS in Action: Scalable Test Reuse from Design Verification to Silicon

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PSS Comes of Age: Runtime Behavioral Coverage, Methodology and More

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Supercharge your RISC-V Designs with Higher Abstraction Shift-Left

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Breakthrough in CDC-RDC Verification Defining a Standard for Interoperable Abstract Model

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Unleashing the Potential of Agentic AI Within Design & Functional Verification

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Addressing Formal Verification Challenges with GenAI Technology and RISC-V Solutions

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Addressing Protocol Verification Challenges in the Evolving Landscape of AI and High-Performance Computing (HPC)

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Verify your next AI/ML design with QuestaOne Avery VIP

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Liberating Verification from Boolean Shackles

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Achieve software prototyping verification success with Veloce proFPGA CS

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Real-Time Handwriting Detection using an AI Model running on HAPS-200

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Boost Verification Efficiency with VC Execution Manager

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Agentic AI in Action: Enhancing Debug, Diagnostics, and Decision-Making

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Power. Performance. Proofs – Scaling Formal for the AI-Driven Compute Revolution

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Harnessing AI for Next-Gen EDA

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The SDC ‘Root-of-Trust’ Problem, and How We Solve It

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Software-defined Hardware Design Relies on AI and Intelligent Verification

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An Automated approach for optimizing Circuit Marginality Validation methodologies

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Enhancing Post-Silicon Validation Through Generative Adversarial Networks (GANs) for Test Case Generation

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Video/JPEG Performance Analysis and UseCases Validation in Post Silicon using SystemC and OpenVINO based Neural Network models

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Unveiling Advance Hybrid Emulation Methodology for Accelerated Android Home Screen Bring-up and System Level Verification

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Simulated Emulation: Enabling Multiple Iterations in a Day During Early-Stage Emulation Bring-up

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Expedited Gate Level Verification: Unleashing the Potential of Netlist Integrated Emulation Platforms

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Pragmatic use cases of ChatGPT in Chip Verification

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Expanding Verification Horizons: OOPs- Enhanced Script-Driven Verification using Auto PSS Gen Utility (APGU)

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Accelerating Sign-Off Cycles: Automated Scenario Extraction from Large Design Landscapes

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Verification Methodology for Debug Unit of a Superscalar RISC-V Processor

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An Extension to RISC-V Test Generator: A Quick Exception Check

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Leveraging Statistical Random Fault (SRF) Sampling for efficient Functional Safety with Reduced efforts

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Power Probe: Addressing Power Noise Signal Integrity Challenges for Wide IO HBM Memories Through Advanced Verification Approach

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Signal Integrity Challenges in rail-to-rail Parallel Interfaces designed for MEMS, Automotive & Infotainment Applications

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Next-Gen Low Power Verification: Empowering Shift-Left Predictive Analysis with Virtual Instrumentation

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Analog Mixed Signal Verification and Validation(V&V) Methodology: Bridging the Gap between Pre Silicon Verification and Post Silicon Validation

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ChipGuard: A Robust Automated System to Streamline Design Verification Quality Parameters

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Accelerating Silicon Bug Detection and Optimizing Execution Flow through Intelligent Adaptive Glitch Detectors in AMS Verification

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Simulation Performance improvement with Dynamic memory load & C model export

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Unified Coverage Methodology: Accelerated Coverage Closure at SoC and IP level

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Register model backdoor register access automation for a complex IP

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DVCON India 2024 Agenda

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Navigating the Maze: Verifying Multi-Module PHY designs in UCIe Multi-Die Systems

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Beyond Boundaries: Overcoming Chiplet Verification Challenges

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Protocol Environment: A Dynamic approach to Enable Multi-Protocol UCIe Design Verification

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Generic Clock UVC for Generating and Testing of High Speed PLL and CDR

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SVRAND – Random Configuration – One class to resolve all parts

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Sparking UVM stimulus via state design pattern

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Pioneering Software Formal Verification Methodology for Firmware

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Read More… from Pioneering Software Formal Verification Methodology for Firmware

Efficiently Analyzing Unreachable Properties in Configuration-Based Designs with Automated Mode-Aware Coverage Analysis

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Enhancing Arbitration Integrity: Formal Verification of Weighted Round Robin Arbiter in High-Performance Graphics

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GenAI Leap in Formal Verification Testplanning

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Who watches the watchman? FuSa Verification of DCLS Configuration through Formal and Static Checks

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Towards Rigorous Fairness: Formal Verification of Multi-Level Arbitration through Hierarchical Family Chains

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Early Bird Catches the Bug – The Arch Formal Way

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Complexity Conquered: Pioneering Formal Verification Methods for Systolic Controllers in Advanced Computing

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Read More… from Complexity Conquered: Pioneering Formal Verification Methods for Systolic Controllers in Advanced Computing

Navigating Instruction Length Decode: TAP into IP using Formal Verification

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Early Performance Exploration of Memory based on JEDEC Specifications

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SDV Aware Verification : Verification Challenges, Opportunities and Evolution around Software Defined Vehicles and Zonal Architectures

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Read More… from SDV Aware Verification : Verification Challenges, Opportunities and Evolution around Software Defined Vehicles and Zonal Architectures

Early Architecture Exploration Of Multi Die Designs

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Generative AI based RTL Code Generator

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Voltage Slack Analysis as part of design robustness analysis to avoid failures due to Voltage Variations

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Automation of Delay Tuning in TSV aware Heterogeneous 3D Inter-Die memory controller

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A data driven, shift-left CAD Automation approach for expedited integration of Digital IPs for SoCs

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Data-Driven Design for Adaptive Multi-Die SoC

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Design Implementation of Generic Architecture for Image Processing Applications and its Verification with UVM Framework

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Read More… from Design Implementation of Generic Architecture for Image Processing Applications and its Verification with UVM Framework

GenAI Based Assertion Code Pattern Generation

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ML based regression accelerator

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Synergizing Functional Safety and Fault Simulation: Towards Robust and Reliable Systems in Safety Critical SoCs.

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Automation of Glitch Checker Implementation on Various Design Interfaces/Boundaries

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Generic Configurable Checker Architecture for functional verification accelerated with AI/ML

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Optimized Technique for Implementation of IOL Test-Suite

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Read More… from Optimized Technique for Implementation of IOL Test-Suite

Methodology for Efficient Fault Injection using Random Sampling

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A New Approach Of Hardware Verification Through Natural Language Queries

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Read More… from A New Approach Of Hardware Verification Through Natural Language Queries

Methodology for SDF back annotated Gatesims for a Mixed signal IP

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Read More… from Methodology for SDF back annotated Gatesims for a Mixed signal IP

Framework for Automated Connectivity Checks for core and SOCs

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Leveraging AI/ML Models for Enhanced VLSI Design and Verification

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Design and Implementation of a Protocol Agnostic Serial Bus Analyzer for Real Time Waveform Debugging and Verification

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Welcome & TPC Updates

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The Increasing Verification Horizon in the Era of AI-Driven Pervasive Intelligence

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Emergence of DIR-V and VEGA Processor Ecosystem

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Efficient RISC V Compute Platforms for Enabling the AI Revolution

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Read More… from Efficient RISC V Compute Platforms for Enabling the AI Revolution

Harnessing AI for Enhanced Verification Efficiency

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What’s New in SystemC 3.0 (IEEE 1666-2023)

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What’s new in SystemC 3.0 – IEEE 1666-2023

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FPGA Prototyping for Large Multi-Die/Multi-Core Designs

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Optimizing Functional Safety and High Reliability for FPGA-based Design

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Power Dynamics: Shaping the future of the data centric era

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Read More… from Power Dynamics: Shaping the future of the data centric era

Find and Fix Excessive Power Dissipation of your Chip Very Early in the Design Cycle

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Portable Stimulus is the Next Big Thing. Here’s Why

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Hardware Verification for High-Performance Designs in the Next Generation: Towards More Scalable and AI-Driven Techniques

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Next Generation Verdi : Overview of New Debug and Verification Management

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Accellera Overview

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HISIG- An Efficient Gate Level Simulation Flow for a Hard IP Inside a Soft IP

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When Last Minute FV Strikes Gold: A Case Study on Finding Starvations & Deadlocks in a Project Nearing Tape-in

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Efficacious Verification of Irreproachable and Steady Data Transfer Protocol for high-speed die-to-die communication on a 3DIC Chip

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Code-Test-Verify all for free – Assertions + Verilator

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No gain without RISC- A novel approach for accelerating and streamlining RISC-V Processor functional verification with register change dump methodology

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UCIe based Design Verification

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Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDL

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Advanced RISC-V Verification Technique Learnings for SoC Validation

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Accellera Update

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Fast Track RISC-V System Validation Using Hardware Assisted Verification Platforms

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Static Sign-Off Best Practices Learnings and Experiences from Industry Use Cases

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Advanced specification driven methodology for quick and accurate RDC signoff

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A Reconfigurable And Fully Automated SRAM Environment Generation Flow for Robust Verification And To Accelerate DV Closure

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Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDL

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Formalize the Cache: Formal Verification Techniques to Verify Different Cache Configurations

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Efficient methodology to uncover common root causes for RDC violations using intelligent data analytics

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Accelerating SoC Sensor Network Verification Sign-off through Dynamic and Formal Synergy

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How to make debug more efficient in day-to-day life using Verisium Debug

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Novel Model First Approach to Shift-Left Soft-Logic RTL Development on Intel Agilex FPGA for Data Centre IPU Design

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Formal Verification Accelerating Coherent Bridge IP Development and Fast Forward DV

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Comprehensive Benchmark Results: Comparing Processing-in-Memory Architecture Effectiveness using UPMEM Hardware

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DVCon India 2022 Proceedings

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Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IP

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Verifying the I/O peripherals of OpenTitan SOC using the Portable Stimulus Standard

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Left shift catching of critical low power bugs with Formal Verification

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Scalable Test bench Architecture and Methodology for Faster Codec and Computer Vision Scenario Verification

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Efficient Regression Management with Smart Data Mining Technique

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A Novel Approach to Hardware Controlled Power Aware Verification with Optimized Power Consumption Techniques at SOC

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Configurable Testbench (TB) for Configurable Design IP

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Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex PMIC designed for SSD Applications

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What-If analysis of Safety Mechanism’s impacts on ETHMAC design under Functional Safety flow

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A Generic Configurable Error Injection Agent for On-Chip Memories

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Novel approach for SoC pipeline latency and connectivity verification using Formal

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Fault Injection Strategy to Validate ASIL-D Requirements of BMS Components

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Novel Adaptive CPU Scoreboard Methodology for a Multi-language environment

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A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage

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Digital Transformation of EDA Environments To Accelerate Semiconductor Innovation

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Functional Safety Verification Methodology for ASIL-B Automotive Designs

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Utilization of Emulation for accelerating the Functional Verification Closure

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NRFs Indentification & Signoff with GLS Validation

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Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex PMIC designed for SSD Applications

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Left shift catching of critical low power bugs with Formal Verification

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Disciplined Post Silicon Validation using ML Intelligence

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Debug Time Reduction by Automatic Generation of Waiver List Using ML Techniques

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A Generic Configurable Error Injection Agent for All On-Chip Memories

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Novel approach for SoC pipeline latency and connectivity verification using Formal

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Effective Formal Deadlock Verification Methodologies for Interconnect design

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Retry with Confidence: Use Formal Property Verification to Verify Link Layer Retry (LLR) Mechanism of Compute Express Link (CXL)

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Automated Traffic Simulation Framework for SoC Performance Analysis

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A Systematic Methodology for Verifying Clock Domain Crossing Reconvergence

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A Real-World Clock Generator Class for UVM

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Enhancing The Effectiveness of a Constrained Random Test Suite Using Supervised Machine Learning Algorithm

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A Methodology to Reuse Unit Level Validation Infrastructure

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Efficient Verification of Mixed-Signal SerDes IP Using UVM

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Methodology for Hardware Software Co-verification of Video Systems on Pre and Post Silicon

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A Methodology for Interrupt Analysis in Virtual Platforms

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Recipes for Better Simulation Acceleration Performance

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Stimulus Generation for Functional Verification of Memory Systems in Advanced Microprocessors

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Using a Generic Plug and Play Performance Monitor for SoC Verification

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Transactional Memory Subsystem Verification for an ARMv8 Server Class CPU

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Walking the Graph: A Holistic Approach to Graph-based Verification for Logic with Sparse State Space

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Network Packet Header Generation Using Graph Based Techniques Combined with Software Testing Strategies

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Using a Generic Plug and Play Performance Monitor for SoC Verification

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SERDES Rx CDR Verification Using Jitter, Spread-Spectrum Clocking (SSC) Stimulus

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Filtering noise in RDC analysis by clockoff specification

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