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Large-scale Gatelevel Optimization Leveraging Property Checking […] Read More… from Large-scale Gatelevel Optimization Leveraging Property Checking
DSA Monitoring Framework for HW/SW Partitioning of Application Kernels leveraging VPs […] Read More… from DSA Monitoring Framework for HW/SW Partitioning of Application Kernels leveraging VPs
MapGL: Interactive Application Mapping and Profiling on a Grid of Processing Cells […] Read More… from MapGL: Interactive Application Mapping and Profiling on a Grid of Processing Cells
A Compositional Simulation Framework for Testing Adversarial Robustness of Deep Neural Networks […] Read More… from A Compositional Simulation Framework for Testing Adversarial Robustness of Deep Neural Networks
MetaPSS: An Automation Framework for Generation of Portable Stimulus Model […] Read More… from MetaPSS: An Automation Framework for Generation of Portable Stimulus Model
Variation-Aware Performance Verification of Analog Mixed-Signal Systems […] Read More… from Variation-Aware Performance Verification of Analog Mixed-Signal Systems
Clock Tree Design Considerations in The Presence of Asymmetric Transistor Aging […] Read More… from Clock Tree Design Considerations in The Presence of Asymmetric Transistor Aging
A Tool for Investigating Cyber-Physical Systems via SystemC AMS Virtual Prototypes Derived from SysML Models […] Read More… from A Tool for Investigating Cyber-Physical Systems via SystemC AMS Virtual Prototypes Derived from SysML Models
On the Performance Differences of SystemC and SystemC AMS: A Guideline for Real Number Modeling and Beyond […] Read More… from On the Performance Differences of SystemC and SystemC AMS: A Guideline for Real Number Modeling and Beyond
Evaluation of the RISC-V Floating Point Extensions […] Read More… from Evaluation of the RISC-V Floating Point Extensions
Co-Design of Automotive Boardnet Topology and Architecture […] Read More… from Co-Design of Automotive Boardnet Topology and Architecture
Control Flow Analysis for Bottom-up Portable Models Creation […] Read More… from Control Flow Analysis for Bottom-up Portable Models Creation
Verification of an AXI cache controller using multi-thread approach based on OOP design pattern […] Read More… from Verification of an AXI cache controller using multi-thread approach based on OOP design pattern
Unified Architecture of L1 L2 Cache with Low Power Extensions for MultiCore UVM-based Library Package […] Read More… from Unified Architecture of L1 L2 Cache with Low Power Extensions for MultiCore UVM-based Library Package
Plug and Play Verification: Leveraging Block-Level Components for Seamless Top-Level Integration […] Read More… from Plug and Play Verification: Leveraging Block-Level Components for Seamless Top-Level Integration
Planning for RISC-V Success Verification Planning and Functional Coverage […] Read More… from Planning for RISC-V Success Verification Planning and Functional Coverage
Fault-injection-Enhanced Virtual Prototypes Enable Early SW Development for Automotive Applications […] Read More… from Fault-injection-Enhanced Virtual Prototypes Enable Early SW Development for Automotive Applications
An Elegant scoreboard eco-system deploying UVM Callbacks, Parameterization for Multimedia designs from Imaging perspective […] Read More… from An Elegant scoreboard eco-system deploying UVM Callbacks, Parameterization for Multimedia designs from Imaging perspective
A Novel Approach to Standardize Verification Configurations using YAML […] Read More… from A Novel Approach to Standardize Verification Configurations using YAML
A Compositional Simulation Framework for Testing Adversarial Robustness of Deep Neural Networks […] Read More… from A Compositional Simulation Framework for Testing Adversarial Robustness of Deep Neural Networks
Virtual ECUs with QEMU and SystemC TLM-2.0 […] Read More… from Virtual ECUs with QEMU and SystemC TLM-2.0
Effective Design Verification – Constrained Random with Python and Cocotb […] Read More… from Effective Design Verification – Constrained Random with Python and Cocotb
Break the SoC with UVM Dynamically Generated Program Code […] Read More… from Break the SoC with UVM Dynamically Generated Program Code
Efficient Verification of a RADAR SoC Using Formal and Simulation-Based Methods […] Read More… from Efficient Verification of a RADAR SoC Using Formal and Simulation-Based Methods
400G IPU Case Study: Demonstrating Shift-left of Soft Logic RTL Development on Real World Design using Intel Agilex FPGA SystemC Model […] Read More… from 400G IPU Case Study: Demonstrating Shift-left of Soft Logic RTL Development on Real World Design using Intel Agilex FPGA SystemC Model
Smart TSV (Through Silicon Via) Repair Automation in 3DIC Designs […] Read More… from Smart TSV (Through Silicon Via) Repair Automation in 3DIC Designs
Efficient Debugging on Virtual Prototype using Reverse Engineering Method […] Read More… from Efficient Debugging on Virtual Prototype using Reverse Engineering Method
Integration Verification of Safety Components in Automotive Chip Modules […] Read More… from Integration Verification of Safety Components in Automotive Chip Modules
System-Level Simulation of a SPAD-Based Time-of-Flight Sensor in SystemVerilog […] Read More… from System-Level Simulation of a SPAD-Based Time-of-Flight Sensor in SystemVerilog
Bridging the gap between system-level and chip-level performance optimization […] Read More… from Bridging the gap between system-level and chip-level performance optimization
Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC) […] Read More… from Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)
Self-Triggering Mechanism for Modeling a Low-Dropout Regulator with Load Capacitor […] Read More… from Self-Triggering Mechanism for Modeling a Low-Dropout Regulator with Load Capacitor
An Elegant scoreboard eco-system deploying UVM Callbacks, Parameterization for Multimedia designs from Imaging perspective […] Read More… from An Elegant scoreboard eco-system deploying UVM Callbacks, Parameterization for Multimedia designs from Imaging perspective
Reverse Hypervisor – Hypervisor as fast SoC simulator. […] Read More… from Reverse Hypervisor – Hypervisor as fast SoC simulator.
The Road to Robustness: Addressing LPDDR5X PHY Verification Challenges with DFE […] Read More… from The Road to Robustness: Addressing LPDDR5X PHY Verification Challenges with DFE
Closed-Loop Model-First SoC Development With the Intel® Simics® Simulator […] Read More… from Closed-Loop Model-First SoC Development With the Intel® Simics® Simulator
Virtual testing of overtemperature protection algorithms in automotive smart fuses […] Read More… from Virtual testing of overtemperature protection algorithms in automotive smart fuses
VPSim: Virtual Prototyping Simulator with best accuracy & execution time trade-off for High Performance Computing systems evaluation and benchmarking […] Read More… from VPSim: Virtual Prototyping Simulator with best accuracy & execution time trade-off for High Performance Computing systems evaluation and benchmarking
Plug and Play Verification: Leveraging Block-Level Components for Seamless Top-Level Integration […] Read More… from Plug and Play Verification: Leveraging Block-Level Components for Seamless Top-Level Integration
SV VQC UDN for Modeling Switch-Capacitor-based Circuits […] Read More… from SV VQC UDN for Modeling Switch-Capacitor-based Circuits
Unified Architecture of L1 and L2 Cache with Low Power Extensions for Multi-Core UVM-based Library Package […] Read More… from Unified Architecture of L1 and L2 Cache with Low Power Extensions for Multi-Core UVM-based Library Package
Initialization Techniques for D-Flip-Flop Based Scan Chain with Scan Flush Architecture in Gate-Level Simulation […] Read More… from Initialization Techniques for D-Flip-Flop Based Scan Chain with Scan Flush Architecture in Gate-Level Simulation
Grid-based Mapping and Analysis of a GoogLeNet CNN using MapGL Editor […] Read More… from Grid-based Mapping and Analysis of a GoogLeNet CNN using MapGL Editor
Low-Power Validation Framework for Standard Cell Library Including Front-End and Back-End Implementation […] Read More… from Low-Power Validation Framework for Standard Cell Library Including Front-End and Back-End Implementation
Design Verification of the Quantum Control Stack […] Read More… from Design Verification of the Quantum Control Stack
Fault-injection-Enhanced Virtual Prototypes Enable Early SW Development for Automotive Applications […] Read More… from Fault-injection-Enhanced Virtual Prototypes Enable Early SW Development for Automotive Applications
Fuzzing Firmware Running on Intel® Simics® Virtual Platforms […] Read More… from Fuzzing Firmware Running on Intel® Simics® Virtual Platforms
A perfect blend of verification techniques, platforms, and AI-empowered debugging in Ethernet Subsystem Verification […] Read More… from A perfect blend of verification techniques, platforms, and AI-empowered debugging in Ethernet Subsystem Verification
Accelerating Complex System Simulation using Parallel SystemC and FPGAs […] Read More… from Accelerating Complex System Simulation using Parallel SystemC and FPGAs
Towards a Hybrid Verification Environment for Signal Processing SoCs […] Read More… from Towards a Hybrid Verification Environment for Signal Processing SoCs
A UVM Test-bench Skeleton Leveraging the Event Pool and Sequence Layering […] Read More… from A UVM Test-bench Skeleton Leveraging the Event Pool and Sequence Layering
Hybrid Emulation for faster Android Home screen bring up and Software Development […] Read More… from Hybrid Emulation for faster Android Home screen bring up and Software Development
Accelerate Functional Coverage Closure Using Machine-Learning-Based Test Selection […] Read More… from Accelerate Functional Coverage Closure Using Machine-Learning-Based Test Selection
A Novel Framework to Accelerate System Validation on Emulation […] Read More… from A Novel Framework to Accelerate System Validation on Emulation
A scalableVIP component to increase robustness of co-verification within an ASIC […] Read More… from A scalableVIP component to increase robustness of co-verification within an ASIC
An Improved Methodology for Debugging UPF Issues at SoC level Power Aware Simulations […] Read More… from An Improved Methodology for Debugging UPF Issues at SoC level Power Aware Simulations
Verilator + UVM-SystemC: a match made in heaven […] Read More… from Verilator + UVM-SystemC: a match made in heaven
A Model-Based Reusable Framework to Parallelize Hardware and Software Development […] Read More… from A Model-Based Reusable Framework to Parallelize Hardware and Software Development
Verification of an AXI cache controller with a multi-thread approach based on OOP design patterns […] Read More… from Verification of an AXI cache controller with a multi-thread approach based on OOP design patterns
A Hybrid Approach To Interrupt Verification […] Read More… from A Hybrid Approach To Interrupt Verification
Virtual Testing of Overtemperature Protection Algorithms in Automotive Smart Fuses […] Read More… from Virtual Testing of Overtemperature Protection Algorithms in Automotive Smart Fuses
Virtual ECUs with QEMU and SystemC TLM-2.0 […] Read More… from Virtual ECUs with QEMU and SystemC TLM-2.0
Towards a Hybrid Verification Environment for Signal Processing SoCs […] Read More… from Towards a Hybrid Verification Environment for Signal Processing SoCs
The Three Body Problem There’s more to building Silicon than EDA currently helps […] Read More… from The Three Body Problem There’s more to building Silicon than EDA currently helps
System-Level Simulation of a SPAD-Based Time-of-Flight Sensor in SystemVerilog […] Read More… from System-Level Simulation of a SPAD-Based Time-of-Flight Sensor in SystemVerilog
SysML v2 – An overview with SysMD demonstration […] Read More… from SysML v2 – An overview with SysMD demonstration
Smart TSV Repair Automation in 3DIC Designs […] Read More… from Smart TSV Repair Automation in 3DIC Designs
Scalable agile processor verification using SystemC UVM and friends […] Read More… from Scalable agile processor verification using SystemC UVM and friends
Reverse Hypervisor Hypervisor for fast SoC Simulation […] Read More… from Reverse Hypervisor Hypervisor for fast SoC Simulation
Pragmatic Formal Verification Methodology for Clock Domain Crossing […] Read More… from Pragmatic Formal Verification Methodology for Clock Domain Crossing
Open-Source Virtual Platforms for Industry and Research […] Read More… from Open-Source Virtual Platforms for Industry and Research
Model-Based Approach for Developing Optimal HW/SW Architectures for AI systems […] Read More… from Model-Based Approach for Developing Optimal HW/SW Architectures for AI systems
MetaPSS: An Automation Framework for Generation of Portable Stimulus Model […] Read More… from MetaPSS: An Automation Framework for Generation of Portable Stimulus Model
MapGL: Interactive Application Mapping and Profiling on a Grid of Processing Cells […] Read More… from MapGL: Interactive Application Mapping and Profiling on a Grid of Processing Cells
Pervasive and Sustainable AI with Adaptive Computing Architectures […] Read More… from Pervasive and Sustainable AI with Adaptive Computing Architectures
Energy-efficient High Performance Compute, at the heart of Europe […] Read More… from Energy-efficient High Performance Compute, at the heart of Europe
Integration Verification of Safety Components in Automotive Chip Modules […] Read More… from Integration Verification of Safety Components in Automotive Chip Modules
How to leverage the power of MATLAB from Functional Verification Test Benches […] Read More… from How to leverage the power of MATLAB from Functional Verification Test Benches
Grid-based Mapping and Analysis of a GoogLeNet CNN using MapGL Editor […] Read More… from Grid-based Mapping and Analysis of a GoogLeNet CNN using MapGL Editor
Fuzzing Firmware Running on Intel® Simics® Virtual Platforms […] Read More… from Fuzzing Firmware Running on Intel® Simics® Virtual Platforms
Exploring New Frontiers of High-Performance Verification with UVM-AMS […] Read More… from Exploring New Frontiers of High-Performance Verification with UVM-AMS
Efficient Debugging on Virtual Prototype using Reverse Engineering Method […] Read More… from Efficient Debugging on Virtual Prototype using Reverse Engineering Method
DSA Monitoring Framework for HW/SW Partitioning of Application Kernels leveraging VP […] Read More… from DSA Monitoring Framework for HW/SW Partitioning of Application Kernels leveraging VP
Co-Design of Automotive Boardnet Topology and Architecture […] Read More… from Co-Design of Automotive Boardnet Topology and Architecture
Closed-Loop Model-First SoC Development With the Intel® Simics® Simulator […] Read More… from Closed-Loop Model-First SoC Development With the Intel® Simics® Simulator
Accellera Functional Safety Working Group Update and Next Steps […] Read More… from Accellera Functional Safety Working Group Update and Next Steps
Accelerating Complex System Simulation using Parallel SystemC and FPGAs […] Read More… from Accelerating Complex System Simulation using Parallel SystemC and FPGAs
Accelerate Functional Coverage Closure Using Machine-Learning-Based Test Selection […] Read More… from Accelerate Functional Coverage Closure Using Machine-Learning-Based Test Selection
A scalable VIP component to increase robustness of co-verification within an ASIC […] Read More… from A scalable VIP component to increase robustness of co-verification within an ASIC
A Novel Approach to Standardize Verification Configurations using YAML […] Read More… from A Novel Approach to Standardize Verification Configurations using YAML
A Hybrid Approach For Interrupts Verification […] Read More… from A Hybrid Approach For Interrupts Verification
Model-Based Design The Top-Level System Design Method […] Read More… from Model-Based Design The Top-Level System Design Method
A Novel Approach to Accelerate Latency of Assertion Simulation […] Read More… from A Novel Approach to Accelerate Latency of Assertion Simulation
Formal Sign-off Methodology for IP Blocks […] Read More… from Formal Sign-off Methodology for IP Blocks
Verification Challenges & Solutions of 10BaseT1s Automotive Ethernet PHY […] Read More… from Verification Challenges & Solutions of 10BaseT1s Automotive Ethernet PHY
Reducing the simulation life cycle time using Artificial Intelligence and Machine learning techniques on Big Data dataset […] Read More… from Reducing the simulation life cycle time using Artificial Intelligence and Machine learning techniques on Big Data dataset
Design and Verification of the PLL using the new DCO and Its Applications to Built-In Speed Grading of Arithmetic Circuits […] Read More… from Design and Verification of the PLL using the new DCO and Its Applications to Built-In Speed Grading of Arithmetic Circuits
SAR ADC Layout Generation Using Digital Place-and-Route Tools […] Read More… from SAR ADC Layout Generation Using Digital Place-and-Route Tools
Improve the quality of SystemC IPs through coverage-driven random verification […] Read More… from Improve the quality of SystemC IPs through coverage-driven random verification
UVM Scoreboards and Checkers Memory, TLB and Cache […] Read More… from UVM Scoreboards and Checkers Memory, TLB and Cache
UVM-based extended Low Power Library package with Low Power Multi-Core Architectures […] Read More… from UVM-based extended Low Power Library package with Low Power Multi-Core Architectures
Scalable Mixed Features Stimulus Generation for Cluster Network Using Sequence Decorator […] Read More… from Scalable Mixed Features Stimulus Generation for Cluster Network Using Sequence Decorator
Autonomous Verification: Are We There Yet? […] Read More… from Autonomous Verification: Are We There Yet?
Accellera, Standards, and Semiconductor Supply Chain […] Read More… from Accellera, Standards, and Semiconductor Supply Chain
Techniques to identify reset metastability issues due to soft resets […] Read More… from Techniques to identify reset metastability issues due to soft resets
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PropGen: An Automated Flow to Generate SVA Properties for Formal and Simulation methods […] Read More… from PropGen: An Automated Flow to Generate SVA Properties for Formal and Simulation methods
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Statistical Analysis of Clock Domain Crossing […] Read More… from Statistical Analysis of Clock Domain Crossing
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Formal Verification + CIA Triad: Winning Formula for Hardware Security […] Read More… from Formal Verification + CIA Triad: Winning Formula for Hardware Security
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ASIL B/D Fault Campaign Strategy for Computer Vision core using Soft Test Library (STL) […] Read More… from ASIL B/D Fault Campaign Strategy for Computer Vision core using Soft Test Library (STL)
Holistic Verification of Bus Health Monitor in Automotive SoC using BHMVC and ParaHunter […] Read More… from Holistic Verification of Bus Health Monitor in Automotive SoC using BHMVC and ParaHunter
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Fast Convergence Modular Advanced Smart-Hybrid Testbench (FCMAST) to automate and expedite SoC gate level simulations closure […] Read More… from Fast Convergence Modular Advanced Smart-Hybrid Testbench (FCMAST) to automate and expedite SoC gate level simulations closure
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Robust Low Power Verification Strategy for a Complex 3DIC System with Split Power Management Architecture […] Read More… from Robust Low Power Verification Strategy for a Complex 3DIC System with Split Power Management Architecture
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Wrong clamps can kill your chip!!….find them early […] Read More… from Wrong clamps can kill your chip!!….find them early
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Disaggregated methodology in Multi-die SoC– A Server SoC Case Study […] Read More… from Disaggregated methodology in Multi-die SoC– A Server SoC Case Study
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An Efficient Verification Methodology to Achieve DV Sign-off with Emphasis on Quality and Quicker DV Cycle […] Read More… from An Efficient Verification Methodology to Achieve DV Sign-off with Emphasis on Quality and Quicker DV Cycle
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Performance Analysis and Acceleration of High Bandwidth Memory System […] Read More… from Performance Analysis and Acceleration of High Bandwidth Memory System
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HISIG- An Efficient Gate Level Simulation Flow for a Hard IP Inside a Soft IP […] Read More… from HISIG- An Efficient Gate Level Simulation Flow for a Hard IP Inside a Soft IP
HISIG- An Efficient Gate Level Simulation Flow for a Hard IP Inside a Soft IP […] Read More… from HISIG- An Efficient Gate Level Simulation Flow for a Hard IP Inside a Soft IP
UVM Sequence Layering for Register Sequences […] Read More… from UVM Sequence Layering for Register Sequences
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Tackling the verification complexities of a processor subsystem through Portable stimulus […] Read More… from Tackling the verification complexities of a processor subsystem through Portable stimulus
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Efficient Verification of Arbitration Design with a Generic Model […] Read More… from Efficient Verification of Arbitration Design with a Generic Model
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Coverage Acceleration and Testcase Pruning using Smart Stimuli Generator in SOC Verification […] Read More… from Coverage Acceleration and Testcase Pruning using Smart Stimuli Generator in SOC Verification
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Accelerating SoC Sensor Network Verification Sign-off through Dynamic and Formal Synergy […] Read More… from Accelerating SoC Sensor Network Verification Sign-off through Dynamic and Formal Synergy
Raising the Bar: Achieving Formal Verification Sign-Off for Complex Algorithmic Designs, with a Dot Product Accumulate Case Study […] Read More… from Raising the Bar: Achieving Formal Verification Sign-Off for Complex Algorithmic Designs, with a Dot Product Accumulate Case Study
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When Last Minute FV Strikes Gold: A Case Study on Finding Starvations & Deadlocks in a Project Nearing Tape-in […] Read More… from When Last Minute FV Strikes Gold: A Case Study on Finding Starvations & Deadlocks in a Project Nearing Tape-in
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Covering All the bases: Coverage-driven Formal Verification Sign-off of Pipelined Error Detection Filter […] Read More… from Covering All the bases: Coverage-driven Formal Verification Sign-off of Pipelined Error Detection Filter
Covering All the bases: Coverage-driven Formal Verification Sign-off of Pipelined Error Detection Filter […] Read More… from Covering All the bases: Coverage-driven Formal Verification Sign-off of Pipelined Error Detection Filter
Paradigm Shift in Power Aware Simulation Using Formal Techniques […] Read More… from Paradigm Shift in Power Aware Simulation Using Formal Techniques
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Pseudo-LRU Not Efficient in Real World? Use Formal Verification to Bridge the Gap […] Read More… from Pseudo-LRU Not Efficient in Real World? Use Formal Verification to Bridge the Gap
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FV: A Robust Solution for Tackling Design Complexities – A Case Study on In-Band ECC […] Read More… from FV: A Robust Solution for Tackling Design Complexities – A Case Study on In-Band ECC
FV: A Robust Solution for Tackling Design Complexities – A Case Study on In-Band ECC […] Read More… from FV: A Robust Solution for Tackling Design Complexities – A Case Study on In-Band ECC
Quiescent Formal Checks (QFC) for Detecting Deep Design Bugs – Sooner and Faster […] Read More… from Quiescent Formal Checks (QFC) for Detecting Deep Design Bugs – Sooner and Faster
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Revolutionizing Proof Convergence for Algorithmic Designs: Combining Multiple Formal Verification Tools […] Read More… from Revolutionizing Proof Convergence for Algorithmic Designs: Combining Multiple Formal Verification Tools
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Automotive RADAR Bitfields Verification to support Validation of Silicon bring-up […] Read More… from Automotive RADAR Bitfields Verification to support Validation of Silicon bring-up
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A Generic Verification Methodology for Chip to Chip Interrupt Handling in a Multi-Chip SoC (3DIC) […] Read More… from A Generic Verification Methodology for Chip to Chip Interrupt Handling in a Multi-Chip SoC (3DIC)
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Tabled Data Into Query Able Data, ‘Key’ Concepts Demonstrated Using DDR5 […] Read More… from Tabled Data Into Query Able Data, ‘Key’ Concepts Demonstrated Using DDR5
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Breaking Down Barriers: Seamless Protocol Conversion with UVM Component Layering […] Read More… from Breaking Down Barriers: Seamless Protocol Conversion with UVM Component Layering
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A Faster and Efficient Timing Constraint Verification Methodology for GFX SOCs […] Read More… from A Faster and Efficient Timing Constraint Verification Methodology for GFX SOCs
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Netlist Enabled Emulation Platform for Accelerated Gate Level Verification […] Read More… from Netlist Enabled Emulation Platform for Accelerated Gate Level Verification
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Efficacious Verification of Irreproachable and Steady Data Transfer Protocol for high-speed die-to-die communication on a 3DIC Chip […] Read More… from Efficacious Verification of Irreproachable and Steady Data Transfer Protocol for high-speed die-to-die communication on a 3DIC Chip
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Code-Test-Verify all for free – Assertions + Verilator […] Read More… from Code-Test-Verify all for free – Assertions + Verilator
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No gain without RISC- A novel approach for accelerating and streamlining RISC-V Processor functional verification with register change dump methodology […] Read More… from No gain without RISC- A novel approach for accelerating and streamlining RISC-V Processor functional verification with register change dump methodology
No gain without RISC- A novel approach for accelerating and streamlining RISC-V Processor functional verification with register change dump methodology […] Read More… from No gain without RISC- A novel approach for accelerating and streamlining RISC-V Processor functional verification with register change dump methodology
An Overview of Ethernet 10Base-T1S in Automotive SoC and its Verification […] Read More… from An Overview of Ethernet 10Base-T1S in Automotive SoC and its Verification
XploR, a Platform to Accelerate Silicon Transformation […] Read More… from XploR, a Platform to Accelerate Silicon Transformation
Identifying and Overcoming Multi-Die System Verification Challenges […] Read More… from Identifying and Overcoming Multi-Die System Verification Challenges
CXL verification using portable stimulus […] Read More… from CXL verification using portable stimulus
Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDL […] Read More… from Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDL
Advanced RISC-V Verification Technique Learnings for SoC Validation […] Read More… from Advanced RISC-V Verification Technique Learnings for SoC Validation
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Fast Track RISC-V System Validation Using Hardware Assisted Verification Platforms […] Read More… from Fast Track RISC-V System Validation Using Hardware Assisted Verification Platforms
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Static Sign-Off Best Practices Learnings and Experiences from Industry Use Cases […] Read More… from Static Sign-Off Best Practices Learnings and Experiences from Industry Use Cases
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Securing design confidence for Low power and Functional features of Image Sensor SOC – Reuse of UVM simulation testbench on HW acceleration platform […] Read More… from Securing design confidence for Low power and Functional features of Image Sensor SOC – Reuse of UVM simulation testbench on HW acceleration platform
A Reconfigurable And Fully Automated SRAM Environment Generation Flow for Robust Verification And To Accelerate DV Closure […] Read More… from A Reconfigurable And Fully Automated SRAM Environment Generation Flow for Robust Verification And To Accelerate DV Closure
Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDL […] Read More… from Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDL
Formalize the Cache: Formal Verification Techniques to Verify Different Cache Configurations […] Read More… from Formalize the Cache: Formal Verification Techniques to Verify Different Cache Configurations
Efficient methodology to uncover common root causes for RDC violations using intelligent data analytics […] Read More… from Efficient methodology to uncover common root causes for RDC violations using intelligent data analytics
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