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Techniques to identify reset metastability issues due to soft resets

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Techniques to identify reset metastability issues due to soft resets

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PropGen: An Automated Flow to Generate SVA Properties for Formal and Simulation methods

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PropGen: An Automated Flow to Generate SVA Properties for Formal and Simulation methods

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Statistical Analysis of Clock Domain Crossing

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Statistical Analysis of Clock Domain Crossing

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Formal Verification + CIA Triad: Winning Formula for Hardware Security

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Formal Verification + CIA Triad: Winning Formula for Hardware Security

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ASIL B/D Fault Campaign Strategy for Computer Vision core using Soft Test Library (STL)

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Holistic Verification of Bus Health Monitor in Automotive SoC using BHMVC and ParaHunter

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Holistic Verification of Bus Health Monitor in Automotive SoC using BHMVC and ParaHunter

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Fast Convergence Modular Advanced Smart-Hybrid Testbench (FCMAST) to automate and expedite SoC gate level simulations closure

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Fast Convergence Modular Advanced Smart-Hybrid Testbench (FCMAST) to automate and expedite SoC gate level simulations closure

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Robust Low Power Verification Strategy for a Complex 3DIC System with Split Power Management Architecture

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Robust Low Power Verification Strategy for a Complex 3DIC System with Split Power Management Architecture

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Wrong clamps can kill your chip!!….find them early

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Wrong clamps can kill your chip!!….find them early

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Disaggregated methodology in Multi-die SoC– A Server SoC Case Study

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Disaggregated methodology in Multi-die SoC– A Server SoC Case Study

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An Efficient Verification Methodology to Achieve DV Sign-off with Emphasis on Quality and Quicker DV Cycle

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An Efficient Verification Methodology to Achieve DV Sign-off with Emphasis on Quality and Quicker DV Cycle

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Performance Analysis and Acceleration of High Bandwidth Memory System

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Performance Analysis and Acceleration of High Bandwidth Memory System

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HISIG- An Efficient Gate Level Simulation Flow for a Hard IP Inside a Soft IP

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HISIG- An Efficient Gate Level Simulation Flow for a Hard IP Inside a Soft IP

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UVM Sequence Layering for Register Sequences

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UVM Sequence Layering for Register Sequences

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Tackling the verification complexities of a processor subsystem through Portable stimulus

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Tackling the verification complexities of a processor subsystem through Portable stimulus

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Python empowered GLS Bringup Vehicle

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Python empowered GLS Bringup Vehicle

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Efficient Verification of Arbitration Design with a Generic Model

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Efficient Verification of Arbitration Design with a Generic Model

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Coverage Acceleration and Testcase Pruning using Smart Stimuli Generator in SOC Verification

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Coverage Acceleration and Testcase Pruning using Smart Stimuli Generator in SOC Verification

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Accelerating SoC Sensor Network Verification Sign-off through Dynamic and Formal Synergy

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Raising the Bar: Achieving Formal Verification Sign-Off for Complex Algorithmic Designs, with a Dot Product Accumulate Case Study

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Raising the Bar: Achieving Formal Verification Sign-Off for Complex Algorithmic Designs, with a Dot Product Accumulate Case Study

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When Last Minute FV Strikes Gold: A Case Study on Finding Starvations & Deadlocks in a Project Nearing Tape-in

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When Last Minute FV Strikes Gold: A Case Study on Finding Starvations & Deadlocks in a Project Nearing Tape-in

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Covering All the bases: Coverage-driven Formal Verification Sign-off of Pipelined Error Detection Filter

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Covering All the bases: Coverage-driven Formal Verification Sign-off of Pipelined Error Detection Filter

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Paradigm Shift in Power Aware Simulation Using Formal Techniques

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Paradigm Shift in Power Aware Simulation Using Formal Techniques

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Pseudo-LRU Not Efficient in Real World? Use Formal Verification to Bridge the Gap

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Pseudo-LRU Not Efficient in Real World? Use Formal Verification to Bridge the Gap

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FV: A Robust Solution for Tackling Design Complexities – A Case Study on In-Band ECC

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FV: A Robust Solution for Tackling Design Complexities – A Case Study on In-Band ECC

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Quiescent Formal Checks (QFC) for Detecting Deep Design Bugs – Sooner and Faster

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Quiescent Formal Checks (QFC) for Detecting Deep Design Bugs – Sooner and Faster

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Revolutionizing Proof Convergence for Algorithmic Designs: Combining Multiple Formal Verification Tools

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Revolutionizing Proof Convergence for Algorithmic Designs: Combining Multiple Formal Verification Tools

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Automotive RADAR Bitfields Verification to support Validation of Silicon bring-up

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Automotive RADAR Bitfields Verification to support Validation of Silicon bring-up

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A Generic Verification Methodology for Chip to Chip Interrupt Handling in a Multi-Chip SoC (3DIC)

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A Generic Verification Methodology for Chip to Chip Interrupt Handling in a Multi-Chip SoC (3DIC)

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Tabled Data Into Query Able Data, ‘Key’ Concepts Demonstrated Using DDR5

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Tabled Data Into Query Able Data, ‘Key’ Concepts Demonstrated Using DDR5

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Breaking Down Barriers: Seamless Protocol Conversion with UVM Component Layering

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Breaking Down Barriers: Seamless Protocol Conversion with UVM Component Layering

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A Faster and Efficient Timing Constraint Verification Methodology for GFX SOCs

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A Faster and Efficient Timing Constraint Verification Methodology for GFX SOCs

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Netlist Enabled Emulation Platform for Accelerated Gate Level Verification

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Netlist Enabled Emulation Platform for Accelerated Gate Level Verification

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Efficacious Verification of Irreproachable and Steady Data Transfer Protocol for high-speed die-to-die communication on a 3DIC Chip

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Efficacious Verification of Irreproachable and Steady Data Transfer Protocol for high-speed die-to-die communication on a 3DIC Chip

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Code-Test-Verify all for free – Assertions + Verilator

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Code-Test-Verify all for free – Assertions + Verilator

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No gain without RISC- A novel approach for accelerating and streamlining RISC-V Processor functional verification with register change dump methodology

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No gain without RISC- A novel approach for accelerating and streamlining RISC-V Processor functional verification with register change dump methodology

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UCIe based Design Verification

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An Overview of Ethernet 10Base-T1S in Automotive SoC and its Verification

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Read More… from An Overview of Ethernet 10Base-T1S in Automotive SoC and its Verification

XploR, a Platform to Accelerate Silicon Transformation

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Identifying and Overcoming Multi-Die System Verification Challenges

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CXL verification using portable stimulus

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Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDL

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Advanced RISC-V Verification Technique Learnings for SoC Validation

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Advanced RISC-V Verification Technique Learnings for SoC Validation

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Accellera Update

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Fast Track RISC-V System Validation Using Hardware Assisted Verification Platforms

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Improving Debug Productivity using latest AI & ML Techniques

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Static Sign-Off Best Practices Learnings and Experiences from Industry Use Cases

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Advanced specification driven methodology for quick and accurate RDC signoff

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Faster Elaborations with Cloud Storage

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Securing design confidence for Low power and Functional features of Image Sensor SOC – Reuse of UVM simulation testbench on HW acceleration platform

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A Reconfigurable And Fully Automated SRAM Environment Generation Flow for Robust Verification And To Accelerate DV Closure

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Automatic Generation of Implementation Layer for Embedded System using PSS and SystemRDL

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Formalize the Cache: Formal Verification Techniques to Verify Different Cache Configurations

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Efficient methodology to uncover common root causes for RDC violations using intelligent data analytics

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Design verification of a cascaded mmWave FMCW Radar

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Highly Flexible and Robust System Level HW-SW Power Management Verification based on RISC-V

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Counterintuitive approaches to have better communication between UVM and Python for registers with Single Controlling Algorithm

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Accelerating SOC Verification, Reducing Simulation Turnaround Time & Diskspace Optimization using Dynamic Test Reload (DTR)

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Accelerating SoC Sensor Network Verification Sign-off through Dynamic and Formal Synergy

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How to make debug more efficient in day-to-day life using Verisium Debug

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Novel Model First Approach to Shift-Left Soft-Logic RTL Development on Intel Agilex FPGA for Data Centre IPU Design

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Digital Eye For Aid of Blind People

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Formal Verification Accelerating Coherent Bridge IP Development and Fast Forward DV

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Comprehensive Benchmark Results: Comparing Processing-in-Memory Architecture Effectiveness using UPMEM Hardware

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Automated Floating Trash Collecting Boat

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DVCon India 2022 Proceedings

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Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IP

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Accelerating the SoC Integration Verification Cycle Time Leveraging the Legacy Design Confidence

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Enabling high quality design sign-off with Jasper structural and auto formal checks

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Read More… from Enabling high quality design sign-off with Jasper structural and auto formal checks

Verifying the I/O peripherals of OpenTitan SOC using the Portable Stimulus Standard

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Read More… from Verifying the I/O peripherals of OpenTitan SOC using the Portable Stimulus Standard

Exhaustive validation of a cache memory controller using Formal Verification to meet performance and timing requirements

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Left shift catching of critical low power bugs with Formal Verification

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Scalable Test bench Architecture and Methodology for Faster Codec and Computer Vision Scenario Verification

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Read More… from Scalable Test bench Architecture and Methodology for Faster Codec and Computer Vision Scenario Verification

Efficient Regression Management with Smart Data Mining Technique

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Channel Modelling in Complex Serial IPs

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Low Power Extension in UVM Power Management

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A Novel Approach to Hardware Controlled Power Aware Verification with Optimized Power Consumption Techniques at SOC

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Read More… from A Novel Approach to Hardware Controlled Power Aware Verification with Optimized Power Consumption Techniques at SOC

Configurable Testbench (TB) for Configurable Design IP

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Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex PMIC designed for SSD Applications

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What-If analysis of Safety Mechanism’s impacts on ETHMAC design under Functional Safety flow

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A Generic Configurable Error Injection Agent for On-Chip Memories

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Read More… from A Generic Configurable Error Injection Agent for On-Chip Memories

Efficient Formal strategies to verify the robustness of the design

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Read More… from Efficient Formal strategies to verify the robustness of the design

Novel approach for SoC pipeline latency and connectivity verification using Formal

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Read More… from Novel approach for SoC pipeline latency and connectivity verification using Formal

Fault Injection Strategy to Validate ASIL-D Requirements of BMS Components

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Novel Adaptive CPU Scoreboard Methodology for a Multi-language environment

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Read More… from Novel Adaptive CPU Scoreboard Methodology for a Multi-language environment

A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage

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Read More… from A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage

The Industry eFPGA soft IP fully customizable, for hardware reconfiguration in the field

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Read More… from The Industry eFPGA soft IP fully customizable, for hardware reconfiguration in the field

Engaging with IEEE through Standards

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Portable Stimulus Standard Update PSS in the Real World

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IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 45 minutes!

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Digital Transformation of EDA Environments To Accelerate Semiconductor Innovation

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Embracing Datapath Verification with Jasper C2RTL App

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VirtIO based GPU model

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SystemUVM™ Driving Portable Stimulus Ease-Of-Use

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Achieve Faster Debug Closure by Applying Big Data & Advanced RCA Technologies

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Read More… from Achieve Faster Debug Closure by Applying Big Data & Advanced RCA Technologies

Design space exploration of PIM (Processing in Memory) & PNC (Processing Near Memory) based on workload characterization

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Hardware Security – Industry Trends, Attacks and Solutions

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Read More… from Hardware Security – Industry Trends, Attacks and Solutions

Compute Link Express – CXL – CXL Consortium

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Accelerating Semiconductor Time to ISO 26262 Compliance

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Using UVM-e Testbenches Utilizing Metric-Driven Verification and Advanced Debug Capabilities

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Functional Safety Verification Methodology for ASIL-B Automotive Designs

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Building UVM Testbenches for High Quality Serial Design IPs Modelling real world scenarios

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A Novel Approach to Reduce Power Consumption By Bridging The Gap between Standalone Functional Scenario and Real Time Scenario at SOC

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Utilization of Emulation for accelerating the Functional Verification Closure

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Low Power Extension In UVM Power Management

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Embrace Errors! Architecting UVM Testbenches for Dynamic Error Injection & Handling

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Read More… from Embrace Errors! Architecting UVM Testbenches for Dynamic Error Injection & Handling

Channel Modelling in Complex Serial IPs

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NRFs Indentification & Signoff with GLS Validation

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Reset Verification using formal tool

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Leveraging RAL and alternate automation (cocotb) techniques to improve Register Verification in UVM

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Left shift catching of critical low power bugs with Formal Verification

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Automated vManager regression using Jenkins

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SoC verification of Security x Safety aspects for memory programmed into secure and non-secure regions in Automotive devices

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A Holistic Overview on Preventive & Corrective Action To Handle Glitches

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Automating information retrieval from EDA software reports using effective parsing algorithms

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Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex PMIC designed for SSD Applications

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Logic Equivalence Check without Low Power – you are at risk!!

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Verifying the I/O peripherals of OpenTitan SOC using the Portable Stimulus Standard

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Read More… from Verifying the I/O peripherals of OpenTitan SOC using the Portable Stimulus Standard

Solving Problems with hierarchical CDC analysis of large designs with encrypted blocks

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Read More… from Solving Problems with hierarchical CDC analysis of large designs with encrypted blocks

Innovative methodologies for analyzing CDC and RDC violations in complex SoC using Automations, formal verification, and Hierarchical CDC model

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Bringing Reset Domains and Power Domains together – Non resettable registers amplifying issues in Power-Aware RDC Verification due to UPF Instrumentation

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Left shift catching of critical low power bugs with Formal Verification

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Disciplined Post Silicon Validation using ML Intelligence

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Debug Time Reduction by Automatic Generation of Waiver List Using ML Techniques

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A Generic Configurable Error Injection Agent for All On-Chip Memories

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Read More… from A Generic Configurable Error Injection Agent for All On-Chip Memories

Accelerating the SoC Integration Verification Cycle Time Leveraging the Legacy Design Confidence

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Read More… from Accelerating the SoC Integration Verification Cycle Time Leveraging the Legacy Design Confidence

Part 9 An Efficient Methodology for Development of Cryptographic Engines

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Efficient Regression Management with Smart Data Mining Technique 

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Scalable Test bench Architecture and Methodology for Faster Codec and Computer Vision Scenario Verification

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Novel Adaptive CPU Scoreboard Methodology for a Multi-language environment

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Verification Reuse Strategy for RTL Quality SoC Functional Virtual Prototypes

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Methodology for system-level comparison of ARM vs RISC-V cores for latency and power consumption

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Novel Methodology for TLM Model Unit Verification

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Efficacious verification of Loopback and Equalization in PCIe By Using Novel approach

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Building Configurable UVM Testbench for Configurable Design IP (Configurable TB)

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UVM Based Generic Interrupt Handler (UGIH)

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Shifting Left CXL Interop using Simulation Techniques

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Overcoming Challenges in Functional Verification of Automotive Traffic Schedulers

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Read More… from Overcoming Challenges in Functional Verification of Automotive Traffic Schedulers

Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IP

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A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage

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“What-If” analysis of Safety Mechanism’s impacts on ETHMAC design under Functional Safety flow

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Fault Injection Strategy to Validate ASIL-D Requirements of BMS Components

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Transactional Memory Subsystem Verification for an ARMv8 Server Class CPU

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Filtering noise in RDC analysis by clockoff specification

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Low Power Validation on Emulation Using Portable Stimulus Standard

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