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Demystifying the UVM Configuration Database […] Read More… from Demystifying the UVM Configuration Database
Resetting Anytime with the Cadence UVM Reset Package […] Read More… from Resetting Anytime with the Cadence UVM Reset Package
Checking Security Path with Formal Verification Tool: New Application Development […] Read More… from Checking Security Path with Formal Verification Tool: New Application Development
The Future of Formal Model Checking is NOW! […] Read More… from The Future of Formal Model Checking is NOW!
NO.015: A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores […] Read More… from NO.015: A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores
NO.014: An Intelligent SOC Verification Platform […] Read More… from NO.014: An Intelligent SOC Verification Platform
NO.013: Sequential Equivalence Checking Beyond Clock Gating Verification […] Read More… from NO.013: Sequential Equivalence Checking Beyond Clock Gating Verification
NO.012: How Fast Can You Run SLEC For Verifying Design Optimizations and Bug Fixes […] Read More… from NO.012: How Fast Can You Run SLEC For Verifying Design Optimizations and Bug Fixes
NO.011: Completely Release the Power of VerificationIP–A Step-by-Step Guidance for In-HouseIPDevelopment […] Read More… from NO.011: Completely Release the Power of VerificationIP–A Step-by-Step Guidance for In-HouseIPDevelopment
NO.010: Silicon Bug Hunt with“Deep Sea Fishing”Formal Verification […] Read More… from NO.010: Silicon Bug Hunt with“Deep Sea Fishing”Formal Verification
NO.009: Transaction Equivalence Formal Check (DPV) in Video Algorithm/FPU/AI Area […] Read More… from NO.009: Transaction Equivalence Formal Check (DPV) in Video Algorithm/FPU/AI Area
NO.008: LiteX: a novel open source framework for SoC […] Read More… from NO.008: LiteX: a novel open source framework for SoC
NO.006: A Systematic IP Verification Solution of Complex Memory Management for Storage SOC […] Read More… from NO.006: A Systematic IP Verification Solution of Complex Memory Management for Storage SOC
NO.005: Improvement of chip verification automation technology […] Read More… from NO.005: Improvement of chip verification automation technology
NO.003: RISC-V Processor Core Verification Based on Open Source Tools […] Read More… from NO.003: RISC-V Processor Core Verification Based on Open Source Tools
NO.002: Accurate Charge-pump Regulator Modeling using SV EEnet […] Read More… from NO.002: Accurate Charge-pump Regulator Modeling using SV EEnet
NO.001: Applicable to eSim Development for Automatic Construction of UVM Verification Platform For Large-Scale Data Communication Chips […] Read More… from NO.001: Applicable to eSim Development for Automatic Construction of UVM Verification Platform For Large-Scale Data Communication Chips
Next-generation Power Aware CDC Verification What have we learned? […] Read More… from Next-generation Power Aware CDC Verification What have we learned?
Highly Configurable UVM Environment for Parameterized IP Verification […] Read More… from Highly Configurable UVM Environment for Parameterized IP Verification
The Big Brain Theory – Visualizing SoC Design & Verification Data […] Read More… from The Big Brain Theory – Visualizing SoC Design & Verification Data
Conditional Delays for Negative Limit Timing Checks in Event Driven Simulation […] Read More… from Conditional Delays for Negative Limit Timing Checks in Event Driven Simulation
Are You Smarter Than Your Testbench? With a little work you could be […] Read More… from Are You Smarter Than Your Testbench? With a little work you could be
Virtual Test: Simulating ATE Vectors in a SystemVerilog Testbench for Faster Time to Market […] Read More… from Virtual Test: Simulating ATE Vectors in a SystemVerilog Testbench for Faster Time to Market
Automatic Partitioning for Multi-core HDL Simulation […] Read More… from Automatic Partitioning for Multi-core HDL Simulation
SystemVerilog Constraint Layering via Reusable Randomization Policy Classes […] Read More… from SystemVerilog Constraint Layering via Reusable Randomization Policy Classes
Testpoint Synthesis Using Symbolic Simulation […] Read More… from Testpoint Synthesis Using Symbolic Simulation
Goldilocks and System Performance Modelling A SystemVerilog Adaptive Rate Control (ARC) Stimulus Generation Methodology […] Read More… from Goldilocks and System Performance Modelling A SystemVerilog Adaptive Rate Control (ARC) Stimulus Generation Methodology
Advancing traceability and consistency in Verification and Validation […] Read More… from Advancing traceability and consistency in Verification and Validation
Low-Power Verification Methodology using UPF Query functions and Bind checkers […] Read More… from Low-Power Verification Methodology using UPF Query functions and Bind checkers
ISO 26262: Better be safe with modelling and simulation on system-level […] Read More… from ISO 26262: Better be safe with modelling and simulation on system-level
Hardware/Software Co-Simulation of SPI enabled ASICs and Software Drivers for Fault Injection and Regression Tests […] Read More… from Hardware/Software Co-Simulation of SPI enabled ASICs and Software Drivers for Fault Injection and Regression Tests
Understanding the effectiveness of your system-level SoC stimulus suite […] Read More… from Understanding the effectiveness of your system-level SoC stimulus suite
An Open and Fast Virtual Platform for TriCore™-based SoCs Using QEMU […] Read More… from An Open and Fast Virtual Platform for TriCore™-based SoCs Using QEMU
Pedal Faster! Or Make Your Verification Environment More Efficient. You Choose. […] Read More… from Pedal Faster! Or Make Your Verification Environment More Efficient. You Choose.
Reusable Processor Verification Methodology Based on UVM […] Read More… from Reusable Processor Verification Methodology Based on UVM
Automatic Netlist Modifications required by Functional Safety […] Read More… from Automatic Netlist Modifications required by Functional Safety
RTL2RTL Formal Equivalence: Boosting the Design Confidence […] Read More… from RTL2RTL Formal Equivalence: Boosting the Design Confidence
A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance Analysis […] Read More… from A Complete SystemC Process Instrumentation Interface and Its Application to Simulation Performance Analysis
De-mystifying synchronization between various verification components by employing novel UVM classes […] Read More… from De-mystifying synchronization between various verification components by employing novel UVM classes
Data path verification on cross domain with formal scoreboard […] Read More… from Data path verification on cross domain with formal scoreboard
Jump-Start Portable Stimulus Test Creation with SystemVerilog Reuse […] Read More… from Jump-Start Portable Stimulus Test Creation with SystemVerilog Reuse
DVS Interface Element—A Novel Approach in Multi-Power Domain, Mixed-Signal Design Verification […] Read More… from DVS Interface Element—A Novel Approach in Multi-Power Domain, Mixed-Signal Design Verification
Automated Specification Driven Verification by Generation of SystemVerilog Assertions […] Read More… from Automated Specification Driven Verification by Generation of SystemVerilog Assertions
An Effective Design and Verification Methodology for Digital PLL […] Read More… from An Effective Design and Verification Methodology for Digital PLL
The Evolution of Triage – Real-time Improvements in Debug Productivity […] Read More… from The Evolution of Triage – Real-time Improvements in Debug Productivity
A Guide To Using Continuous Integration Within The Verification Environment […] Read More… from A Guide To Using Continuous Integration Within The Verification Environment
Reset and Initialization, the Good, the Bad and the Ugly […] Read More… from Reset and Initialization, the Good, the Bad and the Ugly
Introspection Into Systemverilog Without Turning It Inside Out […] Read More… from Introspection Into Systemverilog Without Turning It Inside Out
A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power Intent […] Read More… from A Holistic Approach to Low-Power, Mixed-Signal Design Verification Using Power Intent
Coverage Driven Signoff with Formal Verification on Power Management IPs […] Read More… from Coverage Driven Signoff with Formal Verification on Power Management IPs
Molding Functional Coverage for Highly Configurable IP […] Read More… from Molding Functional Coverage for Highly Configurable IP
A SystemC-based UVM verification infrastructure […] Read More… from A SystemC-based UVM verification infrastructure
Efficient Constrained Random Generation of Address Blocks: A comparative study of simulation speeds […] Read More… from Efficient Constrained Random Generation of Address Blocks: A comparative study of simulation speeds
A concept for expanding a UVM testbenchto the analog-centric toplevel […] Read More… from A concept for expanding a UVM testbenchto the analog-centric toplevel
UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-up […] Read More… from UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-up
New Trends in RTL Verification: Bug Localization, Scan- Chain-Based Methodology, GA-Based Test Generation […] Read More… from New Trends in RTL Verification: Bug Localization, Scan- Chain-Based Methodology, GA-Based Test Generation
Verification of a Multi-language Components A case Study: Specman E Env with SV UVM VIP […] Read More… from Verification of a Multi-language Components A case Study: Specman E Env with SV UVM VIP
Achieving Faster Reset Verification Closure with Intelligent Reset Domain Crossings Detection […] Read More… from Achieving Faster Reset Verification Closure with Intelligent Reset Domain Crossings Detection
Formal Verification Experiences: Silicon Bug Hunt with “Deep Sea Fishing” […] Read More… from Formal Verification Experiences: Silicon Bug Hunt with “Deep Sea Fishing”
Automatic Diagram Creation for Design and Testbenches […] Read More… from Automatic Diagram Creation for Design and Testbenches
Probing UPF Dynamic Objects: Methodologies to Build Your Custom Low-Power Verification […] Read More… from Probing UPF Dynamic Objects: Methodologies to Build Your Custom Low-Power Verification
IP-Coding Style Variants in a Multi-layer Generator Framework […] Read More… from IP-Coding Style Variants in a Multi-layer Generator Framework
A Step towards Zero Silicon Bugs: SVA Protocol Based Assumption Validation […] Read More… from A Step towards Zero Silicon Bugs: SVA Protocol Based Assumption Validation
Analog Modelling to Suit Emulation for Hardware-Software Co-Verification […] Read More… from Analog Modelling to Suit Emulation for Hardware-Software Co-Verification
Experience of using Formal Verification for a Complex Memory Subsystem Design […] Read More… from Experience of using Formal Verification for a Complex Memory Subsystem Design
Deploying HLS in a DO-254/ED-80 Workflow […] Read More… from Deploying HLS in a DO-254/ED-80 Workflow
An Automated Pre-silicon IP Trustworthiness Assessment for Hardware Assurance […] Read More… from An Automated Pre-silicon IP Trustworthiness Assessment for Hardware Assurance
A New Approach for Generating View Generators […] Read More… from A New Approach for Generating View Generators
Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee […] Read More… from Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee
Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF […] Read More… from Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Transparent SystemC Model Factory for Scripting Languages […] Read More… from Transparent SystemC Model Factory for Scripting Languages
Debug APIs – next wave of innovation in DV space […] Read More… from Debug APIs – next wave of innovation in DV space
Systematic Speedup Techniques for Functional CDC Verification Closure […] Read More… from Systematic Speedup Techniques for Functional CDC Verification Closure
End to End Formal Verification Strategies for IP Verification […] Read More… from End to End Formal Verification Strategies for IP Verification
FUNCTIONAL COVERAGE OF REGISTER ACCESS VIA SERIAL BUS INTERFACE USING UVM […] Read More… from FUNCTIONAL COVERAGE OF REGISTER ACCESS VIA SERIAL BUS INTERFACE USING UVM
System Responsiveness Verification of large Multi Processor System Configurations using Micro Benchmarks and a Multi Level Analysis […] Read More… from System Responsiveness Verification of large Multi Processor System Configurations using Micro Benchmarks and a Multi Level Analysis
An Analytical View of Test Results Using CityScapes […] Read More… from An Analytical View of Test Results Using CityScapes
Hybrid Approach to Testbench and Software Driven Verification on Emulation […] Read More… from Hybrid Approach to Testbench and Software Driven Verification on Emulation
What Time Is It: Implementing a SystemVerilog Object-Oriented Wrapper for Interacting with the C Library time […] Read More… from What Time Is It: Implementing a SystemVerilog Object-Oriented Wrapper for Interacting with the C Library time
SGEN2: Evolution of a Sequence-Based Stimulus Engine for Micro-Processor Verification […] Read More… from SGEN2: Evolution of a Sequence-Based Stimulus Engine for Micro-Processor Verification
Synthesis of Decoder Tables Using Formal Verification Tools […] Read More… from Synthesis of Decoder Tables Using Formal Verification Tools
Comprehensive IP to SoC CDC Verification Using Hybrid Data Model […] Read More… from Comprehensive IP to SoC CDC Verification Using Hybrid Data Model
Cleaning Out Your Pipes – Pipeline Debug in UVM Testbenches […] Read More… from Cleaning Out Your Pipes – Pipeline Debug in UVM Testbenches
Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation Requirements […] Read More… from Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation Requirements
Rockin’ the Polymorphism for an Elegant UVM Testbench Architecture […] Read More… from Rockin’ the Polymorphism for an Elegant UVM Testbench Architecture
UVM-FM: Reusable Extension Layer for UVMto Simplify Functional Modeling […] Read More… from UVM-FM: Reusable Extension Layer for UVMto Simplify Functional Modeling
Verification Strategy for Pipeline Type of Design […] Read More… from Verification Strategy for Pipeline Type of Design
Traditional top level static low power rule check […] Read More… from Traditional top level static low power rule check
A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic […] Read More… from A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic
Context-Aware DFM Rule Analysis and Scoring Using Machine Learning […] Read More… from Context-Aware DFM Rule Analysis and Scoring Using Machine Learning
Proper Probing: Flexibility on the TLM Level […] Read More… from Proper Probing: Flexibility on the TLM Level
Preventing Chip-Killing Glitches on CDC Paths with Automated Formal Analysis […] Read More… from Preventing Chip-Killing Glitches on CDC Paths with Automated Formal Analysis
Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC. […] Read More… from Advantages of using UVM/System Verilog IEEE standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC.
Are You Safe Yet? Safety Mechanism Insertion and Validation […] Read More… from Are You Safe Yet? Safety Mechanism Insertion and Validation
Saving and Restoring Simulation Methodology using UVM Factory Overriding to Reduce Simulation Turnaround Time […] Read More… from Saving and Restoring Simulation Methodology using UVM Factory Overriding to Reduce Simulation Turnaround Time
Deadlock Verification For Dummies – The Easy Way of Using SVA and Formal […] Read More… from Deadlock Verification For Dummies – The Easy Way of Using SVA and Formal
Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail Macros […] Read More… from Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail Macros
Use of Aliasing in SystemVerilog Verification Environment […] Read More… from Use of Aliasing in SystemVerilog Verification Environment
Safety and Security Aware Pre-silicon Concurrent Software Development and Verification […] Read More… from Safety and Security Aware Pre-silicon Concurrent Software Development and Verification
SoC Firmware Debugging Tracer in Emulation Platform […] Read More… from SoC Firmware Debugging Tracer in Emulation Platform
Key Gochas in implementing CDC for various Bus Protocols […] Read More… from Key Gochas in implementing CDC for various Bus Protocols
How UPF 3.1 Reduces the Complexities of Reusing PA Macros […] Read More… from How UPF 3.1 Reduces the Complexities of Reusing PA Macros
Emulation Testbench Optimizations for better Hardware Software Co-Validation […] Read More… from Emulation Testbench Optimizations for better Hardware Software Co-Validation
How to Create Reusable Portable Testing and Stimulus Standard (PSS) Verification IP […] Read More… from How to Create Reusable Portable Testing and Stimulus Standard (PSS) Verification IP
Utilizing Technology Implementation Data in blended hardware/software power optimization. […] Read More… from Utilizing Technology Implementation Data in blended hardware/software power optimization.
System Model – A Testbench Library Component Aided for Emulating User Interaction […] Read More… from System Model – A Testbench Library Component Aided for Emulating User Interaction
Moving beyond Assertions: An Innovative approach to Low-Power Checking using UPF Tcl Apps […] Read More… from Moving beyond Assertions: An Innovative approach to Low-Power Checking using UPF Tcl Apps
Clock Domain Crossing Verification in Transistor-level Design […] Read More… from Clock Domain Crossing Verification in Transistor-level Design
Multiplier-Adder-Converter Linear Piecewise Approximation for Low Power Graphics Applications […] Read More… from Multiplier-Adder-Converter Linear Piecewise Approximation for Low Power Graphics Applications
Verification of Accelerators in System Context […] Read More… from Verification of Accelerators in System Context
Using UPF Information Model APIs to write re-usable Low Power Testbenches and customized coverage models for Low Power […] Read More… from Using UPF Information Model APIs to write re-usable Low Power Testbenches and customized coverage models for Low Power
In pursuit of Faster Register Abstract Layer (RAL) Model […] Read More… from In pursuit of Faster Register Abstract Layer (RAL) Model
Verification Reuse for a Non-Transaction Based Design across Multiple Platforms […] Read More… from Verification Reuse for a Non-Transaction Based Design across Multiple Platforms
Conquer the Graphics Legacy: Develop the Customized UVM VIP Embedded a Cycle-based C++ Reference Model […] Read More… from Conquer the Graphics Legacy: Develop the Customized UVM VIP Embedded a Cycle-based C++ Reference Model
Timing Coverage: An Approach to Analyzing Performance Holes […] Read More… from Timing Coverage: An Approach to Analyzing Performance Holes
Interfacing Python with a Systemverilog Test Bench […] Read More… from Interfacing Python with a Systemverilog Test Bench
SystemC FMU for Verification of Advanced Driver Assistance Systems […] Read More… from SystemC FMU for Verification of Advanced Driver Assistance Systems
Dynamic Control Over UVM Register Backdoor Hierarchy […] Read More… from Dynamic Control Over UVM Register Backdoor Hierarchy
An efficient analog fault-injection flow harnessing the power of abstraction […] Read More… from An efficient analog fault-injection flow harnessing the power of abstraction
Flexible Checker: A one-stop shop for all your checkers and a methodology for elastic scoreboarding […] Read More… from Flexible Checker: A one-stop shop for all your checkers and a methodology for elastic scoreboarding
An Enhanced Stimulus and Checking Mechanism on Cache Verification […] Read More… from An Enhanced Stimulus and Checking Mechanism on Cache Verification
SystemVerilog Format of Portable Stimulus […] Read More… from SystemVerilog Format of Portable Stimulus
Efficient hierarchical low power verification of custom designs using static and dynamic techniques […] Read More… from Efficient hierarchical low power verification of custom designs using static and dynamic techniques
