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A Novel Approach to Accelerate Latency of Assertion SimulationJack Yen, Felix Tung2023Papery2023paper
Accellera, Standards, and Semiconductor Supply ChainLu Dai2023Presentationy2023presentation
AI Driven VerificationCurtis Tsai2023Papery2023paper
Autonomous Verification: Are We There Yet?Ajay Singh2023Presentationy2023presentation
Building a Virtual Driver for EmulatorChen Chih-Chiang2023Papery2023paper
Debug Automation with AICraig Yang, Jaw Lee, Sherwin Lai2023Papery2023paper
Design and Verification of the PLL using the new DCO and Its Applications to Built-In Speed Grading of Arithmetic CircuitsYi-Sheng Wang, Hsiang-Kai Teng, Shi-Yu Huang2023Papery2023paper
Formal Sign-off Methodology for IP BlocksAnna Chang, Chia-An Hsu2023Papery2023paper
Improve the quality of SystemC IPs through coverage-driven random verificationTrung Pham, Huy Phan, Masayuki Masuda2023Papery2023paper
Model-Based Design The Top-Level System Design MethodAlan P. Su2023Papery2023paper
Reducing the simulation life cycle time using Artificial Intelligence and Machine learning techniques on Big Data datasetDarshan Sarod, Pratham Khande, Gopi Srinivas Deepala, Priyanka Gharat, Avnita Pal2023Papery2023paper
SAR ADC Layout Generation Using Digital Place-and-Route ToolsYao-Hung Tsai and Shen-Iuan Liu2023Papery2023paper
Scalable Mixed Features Stimulus Generation for Cluster Network Using Sequence DecoratorChi-Ming Li2023Papery2023paper
UVM Scoreboards and Checkers Memory, TLB and CacheRich Edelman, C. H. Liu2023Papery2023paper
UVM-based extended Low Power Library package with Low Power Multi-Core ArchitecturesAvnita Pal, Priyanka Gharat2023Papery2023paper
Verification Challenges & Solutions of 10BaseT1s Automotive Ethernet PHYHarshdeep Verma, Vedansh Seth2023Papery2023paper