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TitleAuthor(s)YearTypeLinkhf:tax:event_yearhf:tax:document_type
A Novel Approach to Accelerate Latency of Assertion SimulationJack Yen, Felix Tung
Accellera, Standards, and Semiconductor Supply ChainLu Dai
AI Driven VerificationCurtis Tsai
Autonomous Verification: Are We There Yet?Ajay Singh
Building a Virtual Driver for EmulatorChen Chih-Chiang
Debug Automation with AICraig Yang, Jaw Lee, Sherwin Lai
Design and Verification of the PLL using the new DCO and Its Applications to Built-In Speed Grading of Arithmetic CircuitsYi-Sheng Wang, Hsiang-Kai Teng, Shi-Yu Huang
Formal Sign-off Methodology for IP BlocksAnna Chang, Chia-An Hsu
Improve the quality of SystemC IPs through coverage-driven random verificationTrung Pham, Huy Phan, Masayuki Masuda
Model-Based Design The Top-Level System Design MethodAlan P. Su
Reducing the simulation life cycle time using Artificial Intelligence and Machine learning techniques on Big Data datasetDarshan Sarod, Pratham Khande, Gopi Srinivas Deepala, Priyanka Gharat, Avnita Pal
SAR ADC Layout Generation Using Digital Place-and-Route ToolsYao-Hung Tsai and Shen-Iuan Liu
Scalable Mixed Features Stimulus Generation for Cluster Network Using Sequence DecoratorChi-Ming Li
UVM Scoreboards and Checkers Memory, TLB and CacheRich Edelman, C. H. Liu
UVM-based extended Low Power Library package with Low Power Multi-Core ArchitecturesAvnita Pal, Priyanka Gharat
Verification Challenges & Solutions of 10BaseT1s Automotive Ethernet PHYHarshdeep Verma, Vedansh Seth