| A Novel Approach to Accelerate Latency of Assertion Simulation | Jack Yen, Felix Tung | 2023 | Paper | | y2023 | paper |
| A Video Entropy Coder Design and Verification Using HLS and HLV | Yuan-Teng Chang , Wenbo Zheng | 2025 | Presentation | | y2025 | presentation |
| Accelerate Verification, Streamline Challenges: A Comprehensive HBM Model Solution | Vatsal Patel, Ritesh Desai, Dharini Subashchandran, Ujash Poshiya | 2025 | Presentation | | y2025 | presentation |
| Accellera, Standards, and Semiconductor Supply Chain | Lu Dai | 2023 | Presentation | | y2023 | presentation |
| AI Driven Verification | Curtis Tsai | 2023 | Paper | | y2023 | paper |
| AutoDV – Click, Vhf, and Relax | Shi Feng Chen, Ning Yuan Cheng | 2025 | Presentation | | y2025 | presentation |
| Automatically Fix RTL Lint Violations with GenAI | Chih Jen Wei | 2025 | Presentation | | y2025 | presentation |
| Autonomous Verification: Are We There Yet? | Ajay Singh | 2023 | Presentation | | y2023 | presentation |
| Building a Virtual Driver for Emulator | Chen Chih-Chiang | 2023 | Paper | | y2023 | paper |
| Debug Automation with AI | Craig Yang, Jaw Lee, Sherwin Lai | 2023 | Paper | | y2023 | paper |
| Debugging RTL with Transactions – Small, simple changes enabling higher level understanding | Rich Edelman | 2025 | Presentation | | y2025 | presentation |
| Design and Verification of the PLL using the new DCO and Its Applications to Built-In Speed Grading of Arithmetic Circuits | Yi-Sheng Wang, Hsiang-Kai Teng, Shi-Yu Huang | 2023 | Paper | | y2023 | paper |
| Dynamic Switching Performance of GaN HEMTs in Boost Converter Topology Using Double Pulse Test (DPT) with Parasitic-Induced Effects | Susmita Mistri | 2025 | Presentation | | y2025 | presentation |
| Efficient Debug Strategies for PCIe Gen6 Verification Using Verification IP | Satish Kumar Padhi | 2025 | Presentation | | y2025 | presentation |
| EP-Ready Hardware-Assisted-Verification Platforms | Andy Lee | 2025 | Presentation | | y2025 | presentation |
| Fast IP/SoC Test Generation with SystemVIPs and Test Suite Synthesis | Andy Stein | 2025 | Presentation | | y2025 | presentation |
| Formal Sign-off Methodology for IP Blocks | Anna Chang, Chia-An Hsu | 2023 | Paper | | y2023 | paper |
| Formal-driven assurance of RISC-V Cores with AI-Ready FPUs | CY Chang | 2025 | Presentation | | y2025 | presentation |
| Harnessing AI/ML for Superior Regression Management – Boost Verification Efficiency | Vita Liao | 2025 | Presentation | | y2025 | presentation |
| How Agentic AI is Reinventing Chip Design and Verification | William Wang | 2025 | Presentation | | y2025 | presentation |
| Improve the quality of SystemC IPs through coverage-driven random verification | Trung Pham, Huy Phan, Masayuki Masuda | 2023 | Paper | | y2023 | paper |
| Keynote 3: Empowering Innovation in Logic Verification: Harnessing Collective Wisdom Across Tools, Processes, and People | Chilai Huang, Gordon Allan | 2024 | Presentation | | y2024 | presentation |
| Model-Based Design The Top-Level System Design Method | Alan P. Su | 2023 | Paper | | y2023 | paper |
| Modernizing the Hardware / Software Interface – Life beyond spreadsheets, how to bring your SoC register design into the 21st Century | Yichiang Chang | 2025 | Presentation | | y2025 | presentation |
| Nailing Down the Debug Complexities of Complex Device Inter-Connect’s Signal Pattern | Rahil Jha, Shyam Shar , Krunal Kapadiya | 2025 | Presentation | | y2025 | presentation |
| Reducing the simulation life cycle time using Artificial Intelligence and Machine learning techniques on Big Data dataset | Darshan Sarod, Pratham Khande, Gopi Srinivas Deepala, Priyanka Gharat, Avnita Pal | 2023 | Paper | | y2023 | paper |
| Sanity Test Case Selection by Machine Learning Approach | Tsung-Yu Tsai | 2025 | Presentation | | y2025 | presentation |
| SAR ADC Layout Generation Using Digital Place-and-Route Tools | Yao-Hung Tsai and Shen-Iuan Liu | 2023 | Paper | | y2023 | paper |
| Scalable Mixed Features Stimulus Generation for Cluster Network Using Sequence Decorator | Chi-Ming Li | 2023 | Paper | | y2023 | paper |
| Secure Multi-CPU Memory Access in PCIe via Tokenized Address Space Management | Sridhar Mukund | 2025 | Presentation | | y2025 | presentation |
| Session 1.2: Improving UVM test benches using UVM Run time phases | Karthik Palepu, Lingkai Shi, Prosper Chen | 2024 | Presentation | | y2024 | presentation |
| Session 1.3: Solving Memory Configurations Challenge with SVRAND Verification Flow | Kaushal Vala, Krunal Kapadiya, Joseph Bauer, Shyam Sharma | 2024 | Presentation | | y2024 | presentation |
| Session 1.5: Exploring Token-Based Strategies to Enhance Data Security and Memory Management in PCIe Devices | Gopi Srinivas Deepala, Lakshya Miglani, Sastry Puranapanda | 2024 | Presentation | | y2024 | presentation |
| Session 1.6: Verifying Configurable AndesCore Processors by Using Portable Testing and Stimulus Standard (PSS) | Luther Lee, Andy Lo, Brett Yeh | 2024 | Presentation | | y2024 | presentation |
| Session 1.7: Left-shifting Testbench Development Using Environment Inversion in UVM | Chi-Ming Li, Yu-Ju Su | 2024 | Presentation | | y2024 | presentation |
| Session 1.8: Adopts ISA-Formal On High-End Out-Of-Order Execute RISC-V Cores | Huang Yu-Tse, Wu Sheng-Jhan, Hsiao Yung-Ching | 2024 | Presentation | | y2024 | presentation |
| Session 2.1: The ASIC Renaissance – A glance into the future SoC enablement | Keh-Ching Huang | 2024 | Presentation | | y2024 | presentation |
| Session 2.2: Trojan Horse Detection for RISC-V Cores Using Cross-Auditing | Siang-Cheng Huang, Shi-Yu Huang | 2024 | Presentation | | y2024 | presentation |
| Session 2.3: Integrated verification ecosystem for regression management, coverage convergence, and debug automation | Ching-Yi Huang, William Huang, Craig Yang | 2024 | Presentation | | y2024 | presentation |
| Session 2.7: Better Late Than Never – Collecting Coverage From Ones and Zeroes | Rich Edelman, Tsung-Yu Tsai | 2024 | Presentation | | y2024 | presentation |
| Session 2.8: A Comprehensive Data-Driven Function Verification Process | Tsung-Yu Tsai | 2024 | Presentation | | y2024 | presentation |
| Session 3.1: AutoDV: Boost SoC Verification by Automatic Construction | Robert / Chi-Kang Chen | 2024 | Presentation | | y2024 | presentation |
| Session 3.5: Boost SoC Development Efficiency with Arteris SoC Integration Automation Software – Automate Design Flow and Register Management | YiChiang Chang | 2024 | Presentation | | y2024 | presentation |
| Taming Operational Power in Early Design Stage | Seungwhun Paik | 2025 | Presentation | | y2025 | presentation |
| Taming the Waveform Tsunami: Agentic AI for Smarter Debugging | Tanay Biradar | 2025 | Presentation | | y2025 | presentation |
| UPF Centric Agentic Tool for UPVM frameworks Seamessly Integrated to Low Power ASICs | Chandini Prudvi | 2025 | Presentation | | y2025 | presentation |
| UVM Scoreboards and Checkers Memory, TLB and Cache | Rich Edelman, C. H. Liu | 2023 | Paper | | y2023 | paper |
| UVM-based extended Low Power Library package with Low Power Multi-Core Architectures | Avnita Pal, Priyanka Gharat | 2023 | Paper | | y2023 | paper |
| Verification Challenges & Solutions of 10BaseT1s Automotive Ethernet PHY | Harshdeep Verma, Vedansh Seth | 2023 | Paper | | y2023 | paper |
