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Event Year: 2015

Perspec System Verifier Overview

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Indago™ Debug Platform Overview

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UVM & Emulation Creating SystemVerilog & UVM Testbenches for Simulation & Emulation Platform Portability to Boost Block-to-System Verification Productivity

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FPGA Implementation Validation and Debug

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Expediting the Code Coverage Closure Using Static Formal Techniques – A Proven Approach at Block and SoC Levels

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ARC EM Core with Safety Package – ISO 26262 Certification

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Static Power Intent Verification of Power State Switching Expressions

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Increase Productivity with Reflection API in Design Verification

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Methodology for Hardware Software Co-verification of Video Systems on Pre and Post Silicon

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Driving Analog Stimuli from a UVM Testbench

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A Reusability Combat in UVM Callbacks vs Factory

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Addressing the Challenges of ABV in Complex SOCs

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Thinking Beyond the Box Adopt the Reusable UVM Thread Management and Customized UVM Reset Package to Attack Thread Aware Verification Challenges

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A Unified Framework for Multilanguage Verification IPs Integration

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Complementing Verification of Highly Configurable Design with Formal Techniques

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Methodology for Hardware Software Co-verification of Video Systems on Pre and Post Silicon

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Dynamic Power Automation UVM Framework

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Introduction to Accellera TLM 2.0

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Accellera Systems Initiative SystemC Standards Update

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Mastering Unexpected Situations Safely

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Using IP-XACT IEEE1685-2014

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Get Ready for UVM-SystemC

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Reconfigurable Radio Design and Verification

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Ensuring Quality of Next Generation Automotive SoC: System’s Approach

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Has The Performance of a Sub-System Been Beaten to Death

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Leveraging ESL Approach to Formally Verify Algorithmic Implementations

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Achieving Real Time Performance for Algorithms Using SOC TLM Model

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Vlang A System Level Verification Perspective

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Vlang A System Level Verification Perspective

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A Methodology for Interrupt Analysis in Virtual Platforms

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Pre-Silicon Host-based Unit Testing of Driver Software using SystemC Models

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MeSSMArch – A Memory System Simulator for Hardware Multithreading Architectures

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MeSSMArch – A Memory System Simulator for Hardware Multithreading Architectures

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Making Virtual Prototypes Work

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Dynamic Parameter Configuration of SystemC Models

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Verification Techniques for CPU Simulation Model

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A Methodology for Using Traffic Generators with Real-Time Constraints

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Virtual Platform for Software Enablement and Hardware Verification

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Design & Verify Virtual Platform with reusable TLM 2.0

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Hybrid Emulation Use Cases

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VirtualATE: SystemC support for Automatic Test Equipment

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VP Quality Improvement Methodology

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Recipes for Better Simulation Acceleration Performance

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Stimulus Generation for Functional Verification of Memory Systems in Advanced Microprocessors

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Using a Generic Plug and Play Performance Monitor for SoC Verification

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Transactional Memory Subsystem Verification for an ARMv8 Server Class CPU

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Framework for Holistic Assessment of Potential Performance Gains with Different Simulation Acceleration Modes

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Walking the Graph: A Holistic Approach to Graph-based Verification for Logic with Sparse State Space

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Coverage Closure – Is it a “Game of Dice” or “Top 10 Tests” or “Automated Closure”?

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Network Packet Header Generation Using Graph Based Techniques Combined with Software Testing Strategies

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Prototyping Next-Gen Tegra SoC

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Stimulus Generation for Functional Verification of Memory Systems

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Using a Generic Plug and Play Performance Monitor for SoC Verification

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Read More… from Using a Generic Plug and Play Performance Monitor for SoC Verification

Transactional Memory Subsystem Verification for an ARMv8 Server Class CPU

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Intelligent Coverage Driven, Modern Verification for VHDL Based Designs in Native VHDL with OSVVM

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Read More… from Intelligent Coverage Driven, Modern Verification for VHDL Based Designs in Native VHDL with OSVVM

Challenges in Mixed Signal Verification

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Read More… from Challenges in Mixed Signal Verification

Absolute GLS Verification An Early Simulation of Design Timing Constraints

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Read More… from Absolute GLS Verification An Early Simulation of Design Timing Constraints

Challenges with Power Aware Simulation and Verification Methodologies

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Read More… from Challenges with Power Aware Simulation and Verification Methodologies

Generic Verification Infrastructure around Serial Flash Controllers

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Read More… from Generic Verification Infrastructure around Serial Flash Controllers

A Method to Accelerate SoC Implementation Cycle by Automatically Generating CDC Constraints

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Read More… from A Method to Accelerate SoC Implementation Cycle by Automatically Generating CDC Constraints

MIPI M-PHY Analog Modeling in Verilog-AMS (Wreal) and Verification Using SV/UVM-MS Methodology

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Read More… from MIPI M-PHY Analog Modeling in Verilog-AMS (Wreal) and Verification Using SV/UVM-MS Methodology

AMS Verification at SoC Level: A Practical Approach for Using VAMS vs SPICE Views

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PHY IP Verification – Are Conventional Digital DV Techniques Sufficient?

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Software Driven Hardware Verification: A UVM/DPI Approach

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Read More… from Software Driven Hardware Verification: A UVM/DPI Approach

The Art of Writing Predictors Efficiently Using UVM

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Read More… from The Art of Writing Predictors Efficiently Using UVM

Enabling Shift-Left through FV Methodologies on Intel® Graphics Designs

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Read More… from Enabling Shift-Left through FV Methodologies on Intel® Graphics Designs

Extending a Traditional VIP to Solve PHY Verification Challenges

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Read More… from Extending a Traditional VIP to Solve PHY Verification Challenges

UVM-RAL: Registers on Demand Elimination of the Unnecessary

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Read More… from UVM-RAL: Registers on Demand Elimination of the Unnecessary

A UVM Based Methodology for Processor Verification

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Read More… from A UVM Based Methodology for Processor Verification

DVCon EU 2015 Proceedings

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Read More… from DVCon EU 2015 Proceedings

Coverage Driven Distribution of Constrained Random Stimuli

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Read More… from Coverage Driven Distribution of Constrained Random Stimuli

UVM Sans UVM An approach to automating UVM testbench writing

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Read More… from UVM Sans UVM An approach to automating UVM testbench writing

Run-Time Phasing in UVM: Ready for the Big Time or Dead in the Water?

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Read More… from Run-Time Phasing in UVM: Ready for the Big Time or Dead in the Water?

UVM’s MAM to the Rescue

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Read More… from UVM’s MAM to the Rescue

UVM Rapid Adoption: A Practical Subset of UVM

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Read More… from UVM Rapid Adoption: A Practical Subset of UVM

Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to Simulation

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Read More… from Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to Simulation

Every Cloud – Post-Silicon Bug Spurs Formal Verification Adoption

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Read More… from Every Cloud – Post-Silicon Bug Spurs Formal Verification Adoption

Automatic Generation of Formal Properties for Logic Related to Clock Gating

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Read More… from Automatic Generation of Formal Properties for Logic Related to Clock Gating

Detecting Harmful Race Conditions in SystemC Models Using Formal Techniques

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Read More… from Detecting Harmful Race Conditions in SystemC Models Using Formal Techniques

What Ever Happened to AOP?

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Read More… from What Ever Happened to AOP?

I created the Verification Gap

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Read More… from I created the Verification Gap

Successive Refinement: A Methodology for Incremental Specification of Power Intent

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Read More… from Successive Refinement: A Methodology for Incremental Specification of Power Intent

A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation Acceleration

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Read More… from A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation Acceleration

Parameter Passing From SystemVerilog to SystemC

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Read More… from Parameter Passing From SystemVerilog to SystemC

Co-Simulating Matlab/Simulink Models in a UVM Environment

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Read More… from Co-Simulating Matlab/Simulink Models in a UVM Environment

Addressing the Challenges of Reset Verification in SoC Designs

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Read More… from Addressing the Challenges of Reset Verification in SoC Designs

Parameterized and Re-usable Jitter Model for Serial and Parallel Interfaces

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Read More… from Parameterized and Re-usable Jitter Model for Serial and Parallel Interfaces

A Unified Testbench Architecture Solution for Verifying Variants of A PLL IP

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Read More… from A Unified Testbench Architecture Solution for Verifying Variants of A PLL IP

An Easy VE/DUV Integration Approach

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Read More… from An Easy VE/DUV Integration Approach

Application Abstraction Layer: The Carpool Lane on the SoC Verification Freeway

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Read More… from Application Abstraction Layer: The Carpool Lane on the SoC Verification Freeway

Automatic SOC Test Bench Creation

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Read More… from Automatic SOC Test Bench Creation

Unleashing the Full Power of UPF Power States

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Read More… from Unleashing the Full Power of UPF Power States

Methodology for Separation of Design Concerns Using Conservative RTL Flipflop Inference

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Read More… from Methodology for Separation of Design Concerns Using Conservative RTL Flipflop Inference

Design Guidelines for Formal Verification

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Read More… from Design Guidelines for Formal Verification

Engineered SystemVerilog Constraints

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Read More… from Engineered SystemVerilog Constraints

Automated Test Generation to Verify IP Modified for System Level Power Management

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Read More… from Automated Test Generation to Verify IP Modified for System Level Power Management

Reuse C test and UVM sequence utilizing TLM2, register model and interrupt handler

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Read More… from Reuse C test and UVM sequence utilizing TLM2, register model and interrupt handler

Mixed Signal Verification of UPF based designs A Practical Example

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Read More… from Mixed Signal Verification of UPF based designs A Practical Example

Advanced Digital-Centric Mixed-Signal Methodology

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Read More… from Advanced Digital-Centric Mixed-Signal Methodology

Specification Driven Analog and Mixed-Signal Verification

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Read More… from Specification Driven Analog and Mixed-Signal Verification

Lets disCOVER Power States

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Read More… from Lets disCOVER Power States

PA-APIs: Looking beyond power intent specification formats

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Read More… from PA-APIs: Looking beyond power intent specification formats

The UPF 2.1 Library Commands: Truly Unifying the Power Specification Formats

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Read More… from The UPF 2.1 Library Commands: Truly Unifying the Power Specification Formats

Debug Challenges in Low-Power Design and Verification

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Read More… from Debug Challenges in Low-Power Design and Verification

Meta Design Framework

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GIT for Hardware Designers

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Read More… from GIT for Hardware Designers

Coverage Data Exchange is no robbery…or is it?

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Read More… from Coverage Data Exchange is no robbery…or is it?

Easy uvm_config_db use: A simplified and reusable uvm_config_db methodology for environment developers and test writers

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Read More… from Easy uvm_config_db use: A simplified and reusable uvm_config_db methodology for environment developers and test writers

Wrapping Verilog Bus Functional Model (BFM) and RTL as Drivers in Customized UVM VIP Using Abstract Classes

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Read More… from Wrapping Verilog Bus Functional Model (BFM) and RTL as Drivers in Customized UVM VIP Using Abstract Classes

Taming a Complex UVM Environment

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Read More… from Taming a Complex UVM Environment

Designing Portable UVM Test Benches for Reusable IPs

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Read More… from Designing Portable UVM Test Benches for Reusable IPs

Want a Boost in your Regression Throughput? Simulate common setup phase only once.

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Read More… from Want a Boost in your Regression Throughput? Simulate common setup phase only once.

Successive Refinement: A Methodology for Incremental Specification of Power Intent

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Read More… from Successive Refinement: A Methodology for Incremental Specification of Power Intent

NOT JUST FOR HARDWARE DEBUG: PROTOTYPE DEBUGGERS FOR SYSTEM VALIDATION AND OPTIMIZATION

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Read More… from NOT JUST FOR HARDWARE DEBUG: PROTOTYPE DEBUGGERS FOR SYSTEM VALIDATION AND OPTIMIZATION

Jump-Start Software-Driven Hardware Verification with a Verification Framework

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Read More… from Jump-Start Software-Driven Hardware Verification with a Verification Framework

Design and Verification of a Multichip Coherence Protocol

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Read More… from Design and Verification of a Multichip Coherence Protocol

Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis

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Read More… from Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis

Matrix Math package for VHDL

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Read More… from Matrix Math package for VHDL

Verification Environment Automation from RTL

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Read More… from Verification Environment Automation from RTL

Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage Modeling

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Read More… from Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage Modeling

Method for Generating Unique Coverage Classes to Enable Meaningful Covergroup Merges Across Testbenches

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Read More… from Method for Generating Unique Coverage Classes to Enable Meaningful Covergroup Merges Across Testbenches

Table-based Functional Coverage Management for SOC Protocols

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Read More… from Table-based Functional Coverage Management for SOC Protocols

Lies, Damned Lies, and Coverage

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Read More… from Lies, Damned Lies, and Coverage

Mining Coverage Data for Test Set Coverage Efficiency

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Read More… from Mining Coverage Data for Test Set Coverage Efficiency

Advanced Usage Models for Continuous Integration in Verification Environments

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Read More… from Advanced Usage Models for Continuous Integration in Verification Environments

Standard Regression Testing Does Not Work

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Read More… from Standard Regression Testing Does Not Work

Multi-Domain Verification: When Clock, Power and Reset Domains Collide

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Read More… from Multi-Domain Verification: When Clock, Power and Reset Domains Collide

Portable Stimulus Models for C/SystemC, UVM and Emulation

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Read More… from Portable Stimulus Models for C/SystemC, UVM and Emulation

Automated Performance Verification to Maximize your ARMv8 pulling power

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Read More… from Automated Performance Verification to Maximize your ARMv8 pulling power

SystemVerilog Assertions for Clock-Domain-Crossing Data Paths

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Read More… from SystemVerilog Assertions for Clock-Domain-Crossing Data Paths

Next-generation Power Aware CDC Verification What have we learned?

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Read More… from Next-generation Power Aware CDC Verification What have we learned?

Highly Configurable UVM Environment for Parameterized IP Verification

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Read More… from Highly Configurable UVM Environment for Parameterized IP Verification

The Big Brain Theory – Visualizing SoC Design & Verification Data

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Read More… from The Big Brain Theory – Visualizing SoC Design & Verification Data

Conditional Delays for Negative Limit Timing Checks in Event Driven Simulation

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Read More… from Conditional Delays for Negative Limit Timing Checks in Event Driven Simulation

Randomizing UVM Config DB Parameters

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Read More… from Randomizing UVM Config DB Parameters

Are You Smarter Than Your Testbench? With a little work you could be

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Read More… from Are You Smarter Than Your Testbench? With a little work you could be

Virtual Test: Simulating ATE Vectors in a SystemVerilog Testbench for Faster Time to Market

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Read More… from Virtual Test: Simulating ATE Vectors in a SystemVerilog Testbench for Faster Time to Market

Automatic Partitioning for Multi-core HDL Simulation

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Read More… from Automatic Partitioning for Multi-core HDL Simulation

Versatile UVM Scoreboarding

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Read More… from Versatile UVM Scoreboarding

SystemVerilog Constraint Layering via Reusable Randomization Policy Classes

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Read More… from SystemVerilog Constraint Layering via Reusable Randomization Policy Classes

Testpoint Synthesis Using Symbolic Simulation

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Read More… from Testpoint Synthesis Using Symbolic Simulation

Goldilocks and System Performance Modelling A SystemVerilog Adaptive Rate Control (ARC) Stimulus Generation Methodology

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Read More… from Goldilocks and System Performance Modelling A SystemVerilog Adaptive Rate Control (ARC) Stimulus Generation Methodology

Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage Modeling

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Read More… from Navigating The Functional Coverage Black Hole: Be More Effective At Functional Coverage Modeling

Method for Generating Unique Coverage Classes to Enable Meaningful Covergroup Merges Across Testbenches

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Read More… from Method for Generating Unique Coverage Classes to Enable Meaningful Covergroup Merges Across Testbenches

Coverage Driven Distribution of Constrained Random Stimuli

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Read More… from Coverage Driven Distribution of Constrained Random Stimuli

Table-based Functional Coverage Management for SOC Protocols

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Read More… from Table-based Functional Coverage Management for SOC Protocols

UVM Sans UVM: An approach to automating UVM testbench writing

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Read More… from UVM Sans UVM: An approach to automating UVM testbench writing

Run-Time Phasing in UVM: Ready for the Big Time or Dead in the Water?

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Read More… from Run-Time Phasing in UVM: Ready for the Big Time or Dead in the Water?

UVM’s MAM to the Rescue

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Read More… from UVM’s MAM to the Rescue

UVM Rapid Adoption: A Practical Subset of UVM

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Read More… from UVM Rapid Adoption: A Practical Subset of UVM

Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to Simulation

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Read More… from Double the Return from your Property Portfolio: Reuse of Verification Assets from Formal to Simulation

Every Cloud – Post-Silicon Bug Spurs Formal Verification Adoption

[…]

Read More… from Every Cloud – Post-Silicon Bug Spurs Formal Verification Adoption

Automatic Generation of Formal Properties for Logic Related to Clock Gating

[…]

Read More… from Automatic Generation of Formal Properties for Logic Related to Clock Gating

Detecting Harmful Race Conditions in SystemC Models Using Formal Techniques

[…]

Read More… from Detecting Harmful Race Conditions in SystemC Models Using Formal Techniques

What Ever Happened to AOP?

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Read More… from What Ever Happened to AOP?

Lies, Damned Lies, and Coverage

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Read More… from Lies, Damned Lies, and Coverage

I created the Verification Gap

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Read More… from I created the Verification Gap

Mining Coverage Data for Test Set Coverage Efficiency

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Read More… from Mining Coverage Data for Test Set Coverage Efficiency

Advanced Usage Models for Continuous Integration in Verification Environments

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Read More… from Advanced Usage Models for Continuous Integration in Verification Environments

Standard Regression Testing Does not Work

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Read More… from Standard Regression Testing Does not Work

UPF Code Coverage and Corresponding Power Domain Hierarchical Tree for Debugging

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Read More… from UPF Code Coverage and Corresponding Power Domain Hierarchical Tree for Debugging

Multi-Domain Verification: When Clock, Power and Reset Domains Collide

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Read More… from Multi-Domain Verification: When Clock, Power and Reset Domains Collide

A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation Acceleration

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Read More… from A Methodology to Port a Complex Multi-Language Design and Testbench for Simulation Acceleration

Parameter Passing from SystemVerilog to SystemC for Highly Configurable Mixed-Language Designs

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Read More… from Parameter Passing from SystemVerilog to SystemC for Highly Configurable Mixed-Language Designs

Portable Stimulus Models for C/SystemC, UVM and Emulation

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Read More… from Portable Stimulus Models for C/SystemC, UVM and Emulation

Co-Simulating Matlab/Simulink Models in a UVM Environment

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Read More… from Co-Simulating Matlab/Simulink Models in a UVM Environment

Addressing the Challenges of Reset Verification in SoC Designs

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Read More… from Addressing the Challenges of Reset Verification in SoC Designs

Automated Performance Verification to Maximize your ARMv8 pulling power

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Read More… from Automated Performance Verification to Maximize your ARMv8 pulling power

SystemVerilog Assertions for Clock-Domain-Crossing Data Paths

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Read More… from SystemVerilog Assertions for Clock-Domain-Crossing Data Paths

Parameterized and Re-usable Jitter Model for Serial and Parallel Interfaces

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Read More… from Parameterized and Re-usable Jitter Model for Serial and Parallel Interfaces

A Unified Testbench Architecture Solution for Verifying Variants of the PLL IP

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Read More… from A Unified Testbench Architecture Solution for Verifying Variants of the PLL IP

Application Abstraction Layer: The Carpool Lane on the SoC Verification Freeway

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Read More… from Application Abstraction Layer: The Carpool Lane on the SoC Verification Freeway

Automatic SOC Test Bench Creation

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Read More… from Automatic SOC Test Bench Creation

Let’s DisCOVER Power States

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Read More… from Let’s DisCOVER Power States

PA-APIs: Looking beyond power intent specification formats

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Read More… from PA-APIs: Looking beyond power intent specification formats

Automation of Power On Reset Assertion

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Read More… from Automation of Power On Reset Assertion

Next-generation Power Aware CDC Verification – What have we learned?

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Read More… from Next-generation Power Aware CDC Verification – What have we learned?

The UPF 2.1 library commands: Truly unifying the power specification formats

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Read More… from The UPF 2.1 library commands: Truly unifying the power specification formats

Debug Challenges in Low-Power Design and Verification

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Read More… from Debug Challenges in Low-Power Design and Verification

Successive Refinement: A Methodology for Incremental Specification of Power Intent

[…]

Read More… from Successive Refinement: A Methodology for Incremental Specification of Power Intent

Highly Configurable UVM Environment for Parameterized IP Verification

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Read More… from Highly Configurable UVM Environment for Parameterized IP Verification

Meta Design Framework: Building Designs Programmatically

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Read More… from Meta Design Framework: Building Designs Programmatically

The Big Brain Theory: Visualizing SoC Design & Verification Data

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Read More… from The Big Brain Theory: Visualizing SoC Design & Verification Data

Git for Hardware Designers

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Read More… from Git for Hardware Designers

Conditional Delays for Negative Limit Timing Checks in Event Driven Simulation

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Read More… from Conditional Delays for Negative Limit Timing Checks in Event Driven Simulation

Coverage Data Exchange is no robbery…or is it?

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Read More… from Coverage Data Exchange is no robbery…or is it?

Randomizing UVM Config DB Parameters

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Read More… from Randomizing UVM Config DB Parameters

Are You Smarter Than Your Testbench? With a little work you can be.

[…]

Read More… from Are You Smarter Than Your Testbench? With a little work you can be.

Easy uvm_config_db use: A simplified and reusable uvm_config_db methodology for environment developers and test writers

[…]

Read More… from Easy uvm_config_db use: A simplified and reusable uvm_config_db methodology for environment developers and test writers

Wrapping Verilog Bus Functional Model (BFM) and RTL as Drivers in Customized UVM VIP Using Abstract Classes

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Read More… from Wrapping Verilog Bus Functional Model (BFM) and RTL as Drivers in Customized UVM VIP Using Abstract Classes

Taming a Complex UVM Environment

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Read More… from Taming a Complex UVM Environment

Designing Portable UVM Test Benches for Reusable IPs

[…]

Read More… from Designing Portable UVM Test Benches for Reusable IPs

Virtual Test: Simulating ATE Vectors in a SystemVerilog Testbench for Faster Time to Market

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Read More… from Virtual Test: Simulating ATE Vectors in a SystemVerilog Testbench for Faster Time to Market

Want a Boost in your Regression Throughput? Simulate common setup phase only once.

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Read More… from Want a Boost in your Regression Throughput? Simulate common setup phase only once.

Automatic Partitioning for Multi-core HDL Simulation

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Read More… from Automatic Partitioning for Multi-core HDL Simulation

Versatile UVM Scoreboarding

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Read More… from Versatile UVM Scoreboarding

SystemVerilog Constraint Layering via Reusable Randomization Policy Classes

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Read More… from SystemVerilog Constraint Layering via Reusable Randomization Policy Classes

Not Just for Hardware Debug: Prototype Debuggers for System Validation and Optimization

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Read More… from Not Just for Hardware Debug: Prototype Debuggers for System Validation and Optimization

Jump-Start Software-Driven Hardware Verification with a Verification Framework

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Read More… from Jump-Start Software-Driven Hardware Verification with a Verification Framework

Design and Verification of a Multichip Coherence Protocol

[…]

Read More… from Design and Verification of a Multichip Coherence Protocol

Testpoint Synthesis Using Symbolic Simulation

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Read More… from Testpoint Synthesis Using Symbolic Simulation

Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis

[…]

Read More… from Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis

Matrix Math package for VHDL

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Read More… from Matrix Math package for VHDL

Verification Environment Automation from RTL

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Read More… from Verification Environment Automation from RTL

Goldilocks and System Performance Modeling

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Read More… from Goldilocks and System Performance Modeling

Unleashing the Full Power of UPF Power States

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