DVCon: China

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TitleAuthor(s)YearTypeLinkevent_year_hfilterdocument_type_hfilter
5.1 Smart Verification leveraging PSS; 5.2 When Automotive FuSa Met ICDavid Hwang and Sera Gao2021Presentation2021presentation
Acceleration Startup Design & VerificationTim Sun, Barry Yin, and Haifeng Jiang2021Presentation2021presentation
Applying Big Data to Next-Generation Coverage Analysis and ClosureTom Fitzpatrick, Darron May, Thom Ellis, Athira Panicker and Francisco Chen2021Presentation2021presentation
Computational Logistics for Intelligent System DesignSimon Chang2021Presentation2021presentation
Early Design and Validation of an AI Accelerator’s System Level Performance Using an HLS Design MethodologyWenbo Zheng2021Presentation2021presentation
Fast forward Software Development using Advanced Hybrid TechnologiesXiaowei Pan2021Presentation2021presentation
NO.001: Applicable to eSim Development for Automatic Construction of UVM Verification Platform For Large-Scale Data Communication ChipsAnkui Ge, Lei Wang, and Feng Wang2021Poster2021poster
NO.002: Accurate Charge-pump Regulator Modeling using SV EEnetSherry Li, Tulong Yang, and Ayesha Huq2021Poster2021poster
NO.003: RISC-V Processor Core Verification Based on Open Source ToolsYanbing Xu2021Poster2021poster
NO.005: Improvement of chip verification automation technologyMa Yao, Shao Haibo, Yue Yaping, and Cao Zhu2021Poster2021poster
NO.006: A Systematic IP Verification Solution of Complex Memory Management for Storage SOCJinsong Liu and Shuhui Wang2021Poster2021poster
NO.008: LiteX: a novel open source framework for SoCFeng Li2021Poster2021poster
NO.009: Transaction Equivalence Formal Check (DPV) in Video Algorithm/FPU/AI AreaMinqi Bao2021Poster2021poster
NO.010: Silicon Bug Hunt with“Deep Sea Fishing”Formal VerificationPing Yeung and Jin Hou2021Poster2021poster
NO.011: Completely Release the Power of VerificationIP–A Step-by-Step Guidance for In-HouseIPDevelopmentBin Liu, Xiaoming Ma, Kailong Wang, and Qiaochu Zhu2021Poster2021poster
NO.012: How Fast Can You Run SLEC For Verifying Design Optimizations and Bug FixesJin Hou Wenli Liang, and Lina Guo2021Poster2021poster
NO.013: Sequential Equivalence Checking Beyond Clock Gating VerificationXiushan Feng, Xiaolin Chen, and Sarah Li2021Poster2021poster
NO.014: An Intelligent SOC Verification PlatformDeyong Yang and Fabo Deng2021Poster2021poster
NO.015: A Methodology to Verify Functionality, Security, and Trust for RISC-V CoresNicolae Tusinschi, Wei Wei Chen, and Tom Anderson2021Poster2021poster
Paper Session 1: Applicable to the Development Of Large-Scale Data Communication Chip Performance Analysis ToolsDinglai He, Guanfeng Wang, Feng Wang, and Lirong Zhang2021Paper2021paper
Paper Session 2: UVM is Now IEEE1800.2-2020 Standard: A 2020 Adoption PrimerRoman Wang2021Paper2021paper
Paper Session 3: Co-simulation platform of SystemC and System-Verilog for algorithm verificationLi Jinghui, Shao Haibo and Gou Jiazhen2021Paper2021paper
Paper Session 4: Unified Automation Verification Management ApproachLiu Wenbo, Tian Libo, and Shao Haibo2021Paper2021paper
Paper Session 5: Cache Coherency Verification for Multi-Core Processors Based on the PSSYang Yang2021Paper2021paper
Paper Session 6: High Reliability Reset Domain Checking Solution for the Modern Soc DesignWanggen Shi, Yuxin You and Kurt Takara2021Paper2021paper
Paper Session 7: Best Practice Coding Assertion IP (AIP) to Get More Predictable ResultsSJ Wu and Leon Yin2021Paper2021paper
Paper Session 8: Advanced Techniques for Enabling Gate-level CDC Verification ClosureGunjan Jain, Kurt Takara, and Yuxin You2021Paper2021paper
PCIe Gen5 Validation – The Real WorldYuan Chen2021Presentation2021presentation
Smarter Verification ManagementDavid Zhang2021Presentation2021presentation
The New Power Perspective – Realistic Workloads – Real ResultsXiaoming Li2021Presentation2021presentation
The Next Generation Of EDALuke Yang2021Presentation2021presentation
Veloce HYCON: Software-enabled SoC verification and validation on day 1Jeffrey Chen2021Presentation2021presentation