DVCon: China

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TitleAuthor(s)YearTypeLinkhf:tax:event_yearhf:tax:document_type
5.1 Smart Verification leveraging PSS; 5.2 When Automotive FuSa Met ICDavid Hwang and Sera Gao
Acceleration Startup Design & VerificationTim Sun, Barry Yin, and Haifeng Jiang
Applying Big Data to Next-Generation Coverage Analysis and ClosureTom Fitzpatrick, Darron May, Thom Ellis, Athira Panicker and Francisco Chen
Computational Logistics for Intelligent System DesignSimon Chang
Early Design and Validation of an AI Accelerator’s System Level Performance Using an HLS Design MethodologyWenbo Zheng
Fast forward Software Development using Advanced Hybrid TechnologiesXiaowei Pan
NO.001: Applicable to eSim Development for Automatic Construction of UVM Verification Platform For Large-Scale Data Communication ChipsAnkui Ge, Lei Wang, and Feng Wang
NO.002: Accurate Charge-pump Regulator Modeling using SV EEnetSherry Li, Tulong Yang, and Ayesha Huq
NO.003: RISC-V Processor Core Verification Based on Open Source ToolsYanbing Xu2021Postery2021poster
NO.005: Improvement of chip verification automation technologyMa Yao, Shao Haibo, Yue Yaping, and Cao Zhu2021Postery2021poster
NO.006: A Systematic IP Verification Solution of Complex Memory Management for Storage SOCJinsong Liu and Shuhui Wang
NO.008: LiteX: a novel open source framework for SoCFeng Li
NO.009: Transaction Equivalence Formal Check (DPV) in Video Algorithm/FPU/AI AreaMinqi Bao
NO.010: Silicon Bug Hunt with“Deep Sea Fishing”Formal VerificationPing Yeung and Jin Hou
NO.011: Completely Release the Power of VerificationIP–A Step-by-Step Guidance for In-HouseIPDevelopmentBin Liu, Xiaoming Ma, Kailong Wang, and Qiaochu Zhu
NO.012: How Fast Can You Run SLEC For Verifying Design Optimizations and Bug FixesJin Hou Wenli Liang, and Lina Guo
NO.013: Sequential Equivalence Checking Beyond Clock Gating VerificationXiushan Feng, Xiaolin Chen, and Sarah Li
NO.014: An Intelligent SOC Verification PlatformDeyong Yang and Fabo Deng
NO.015: A Methodology to Verify Functionality, Security, and Trust for RISC-V CoresNicolae Tusinschi, Wei Wei Chen, and Tom Anderson
NO.015: A Methodology to Verify Functionality, Security, and Trust for RISC-V CoresNicolae Tusinschi, Wei Wei Chen, and Tom Anderson
Paper Session 1: Applicable to the Development Of Large-Scale Data Communication Chip Performance Analysis ToolsDinglai He, Guanfeng Wang, Feng Wang, and Lirong Zhang
Paper Session 2: UVM is Now IEEE1800.2-2020 Standard: A 2020 Adoption PrimerRoman Wang
Paper Session 3: Co-simulation platform of SystemC and System-Verilog for algorithm verificationLi Jinghui, Shao Haibo and Gou Jiazhen
Paper Session 4: Unified Automation Verification Management ApproachLiu Wenbo, Tian Libo, and Shao Haibo
Paper Session 5: Cache Coherency Verification for Multi-Core Processors Based on the PSSYang Yang
Paper Session 6: High Reliability Reset Domain Checking Solution for the Modern Soc DesignWanggen Shi, Yuxin You and Kurt Takara
Paper Session 7: Best Practice Coding Assertion IP (AIP) to Get More Predictable ResultsSJ Wu and Leon Yin
Paper Session 8: Advanced Techniques for Enabling Gate-level CDC Verification ClosureGunjan Jain, Kurt Takara, and Yuxin You
PCIe Gen5 Validation – The Real WorldYuan Chen
Smarter Verification ManagementDavid Zhang
The New Power Perspective – Realistic Workloads – Real ResultsXiaoming Li
The Next Generation Of EDALuke Yang
Veloce HYCON: Software-enabled SoC verification and validation on day 1Jeffrey Chen