| 5.1 Smart Verification leveraging PSS; 5.2 When Automotive FuSa Met IC | David Hwang and Sera Gao | | | | | |
| Acceleration Startup Design & Verification | Tim Sun, Barry Yin, and Haifeng Jiang | | | | | |
| Applying Big Data to Next-Generation Coverage Analysis and Closure | Tom Fitzpatrick, Darron May, Thom Ellis, Athira Panicker and Francisco Chen | | | | | |
| Computational Logistics for Intelligent System Design | Simon Chang | | Presentation | | | presentation |
| NO.001: Applicable to eSim Development for Automatic Construction of UVM Verification Platform For Large-Scale Data Communication Chips | Ankui Ge, Lei Wang, and Feng Wang | | | | | |
| NO.002: Accurate Charge-pump Regulator Modeling using SV EEnet | Sherry Li, Tulong Yang, and Ayesha Huq | | | | | |
| NO.005: Improvement of chip verification automation technology | Ma Yao, Shao Haibo, Yue Yaping, and Cao Zhu | | | | | |
| NO.006: A Systematic IP Verification Solution of Complex Memory Management for Storage SOC | Jinsong Liu and Shuhui Wang | | | | | |
| NO.010: Silicon Bug Hunt with“Deep Sea Fishing”Formal Verification | Ping Yeung and Jin Hou | | | | | |
| NO.011: Completely Release the Power of VerificationIP–A Step-by-Step Guidance for In-HouseIPDevelopment | Bin Liu, Xiaoming Ma, Kailong Wang, and Qiaochu Zhu | | | | | |
| NO.012: How Fast Can You Run SLEC For Verifying Design Optimizations and Bug Fixes | Jin Hou Wenli Liang, and Lina Guo | | | | | |
| NO.013: Sequential Equivalence Checking Beyond Clock Gating Verification | Xiushan Feng, Xiaolin Chen, and Sarah Li | | | | | |
| NO.014: An Intelligent SOC Verification Platform | Deyong Yang and Fabo Deng | | | | | |
| NO.015: A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores | Nicolae Tusinschi, Wei Wei Chen, and Tom Anderson | | | | | |
| NO.015: A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores | Nicolae Tusinschi, Wei Wei Chen, and Tom Anderson | | | | | |
| Paper Session 1: Applicable to the Development Of Large-Scale Data Communication Chip Performance Analysis Tools | Dinglai He, Guanfeng Wang, Feng Wang, and Lirong Zhang | | | | | |
| Paper Session 3: Co-simulation platform of SystemC and System-Verilog for algorithm verification | Li Jinghui, Shao Haibo and Gou Jiazhen | | | | | |
| Paper Session 4: Unified Automation Verification Management Approach | Liu Wenbo, Tian Libo, and Shao Haibo | | | | | |
| Paper Session 6: High Reliability Reset Domain Checking Solution for the Modern Soc Design | Wanggen Shi, Yuxin You and Kurt Takara | | | | | |
| Paper Session 8: Advanced Techniques for Enabling Gate-level CDC Verification Closure | Gunjan Jain, Kurt Takara, and Yuxin You | | | | | |
| PCIe Gen5 Validation – The Real World | Yuan Chen | | Presentation | | | presentation |
| Smarter Verification Management | David Zhang | | | | | |
| The Next Generation Of EDA | Luke Yang | | | | | |
