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Extendable Messaging Techniques for Debugging and Analyzing UVM Testbench Structure and Transaction Flow […] Read More… from Extendable Messaging Techniques for Debugging and Analyzing UVM Testbench Structure and Transaction Flow
Guaranteed Vertical Reuse – C Execution In A UVM Environment […] Read More… from Guaranteed Vertical Reuse – C Execution In A UVM Environment
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fsim_logic – A VHDL type for testing of FLYTRAP […] Read More… from fsim_logic – A VHDL type for testing of FLYTRAP
Weathering the Verification Storm: Methodology Enhancements used on a Next Generation Weather Satellite CDH Program […] Read More… from Weathering the Verification Storm: Methodology Enhancements used on a Next Generation Weather Satellite CDH Program
Bringing Constrained Random into SoC SW-driven Verification […] Read More… from Bringing Constrained Random into SoC SW-driven Verification
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Using Advanced OOP Concepts To Integrate Templatized Algorithms for Standard Protocols With UVM […] Read More… from Using Advanced OOP Concepts To Integrate Templatized Algorithms for Standard Protocols With UVM
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Using Formal Verification to Exhaustively Verify SoC Assemblies […] Read More… from Using Formal Verification to Exhaustively Verify SoC Assemblies
How to Kill 4 Birds with 1 Stone: Using Formal Verification to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software Specifications […] Read More… from How to Kill 4 Birds with 1 Stone: Using Formal Verification to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software Specifications
How to Succeed Against Increasing Pressure: Automated Techniques for Unburdening Verification Engineers […] Read More… from How to Succeed Against Increasing Pressure: Automated Techniques for Unburdening Verification Engineers
Memory Subsystem Verification – Can it be taken for granted? […] Read More… from Memory Subsystem Verification – Can it be taken for granted?
Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath Scoreboards […] Read More… from Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath Scoreboards
Systematic Application of UCIS to Improve the Automation on Verification Closure […] Read More… from Systematic Application of UCIS to Improve the Automation on Verification Closure
Unconstrained UVM SystemVerilog Performance […] Read More… from Unconstrained UVM SystemVerilog Performance
Run-Time Configuration of a Verification Environment: A Novel Use of the OVM/UVM Analysis Pattern […] Read More… from Run-Time Configuration of a Verification Environment: A Novel Use of the OVM/UVM Analysis Pattern
A SMART GENERATION OF DESIGN ATTRIBUTES FOR VERIFICATION CLOSURE USING SPECMAN […] Read More… from A SMART GENERATION OF DESIGN ATTRIBUTES FOR VERIFICATION CLOSURE USING SPECMAN
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An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 Experience […] Read More… from An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 Experience
The Need for Speed: Understanding design factors that make multi-core parallel simulations efficient […] Read More… from The Need for Speed: Understanding design factors that make multi-core parallel simulations efficient
Switch the Gears of the UVM Register Package to cruise through the street named “Register Verification”. […] Read More… from Switch the Gears of the UVM Register Package to cruise through the street named “Register Verification”.
Real Number Modeling Enables Fast, Accurate Functional Verification […] Read More… from Real Number Modeling Enables Fast, Accurate Functional Verification
Using Formal Techniques to Verify SoC Reset Schemes […] Read More… from Using Formal Techniques to Verify SoC Reset Schemes
Verifying Layered Protocols – Leveraging Advanced UVM Capabilities […] Read More… from Verifying Layered Protocols – Leveraging Advanced UVM Capabilities
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SVA Encapsulation in UVM: enabling phase and configuration aware assertions […] Read More… from SVA Encapsulation in UVM: enabling phase and configuration aware assertions
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Boost Verification Results by Bridging the Hw/Sw Testbench Gap […] Read More… from Boost Verification Results by Bridging the Hw/Sw Testbench Gap
Mixed-abstraction Modeling Approach with Fault Injection for Hardware-Firmware Co-design and Functional Co-verification of an Automotive Airbag System on Chip Product […] Read More… from Mixed-abstraction Modeling Approach with Fault Injection for Hardware-Firmware Co-design and Functional Co-verification of an Automotive Airbag System on Chip Product
Quantification of Formal Properties for Productive Automotive Microcontroller Verification […] Read More… from Quantification of Formal Properties for Productive Automotive Microcontroller Verification
UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process […] Read More… from UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process
Maximize Vertical Reuse, Building Module to System Verification Environments with UVMe […] Read More… from Maximize Vertical Reuse, Building Module to System Verification Environments with UVMe
A SystemVerilog Framework for Easy Method Advice in Object-oriented Test Benches […] Read More… from A SystemVerilog Framework for Easy Method Advice in Object-oriented Test Benches
ASIC-Strength Verification in a Fast-Moving FPGA World […] Read More… from ASIC-Strength Verification in a Fast-Moving FPGA World
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BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMS […] Read More… from BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMS
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Register Verification: Do We Have Reliable Specification? […] Read More… from Register Verification: Do We Have Reliable Specification?
LOW-POWER VERIFICATION AUTOMATION: A PRACTICAL APPROACH […] Read More… from LOW-POWER VERIFICATION AUTOMATION: A PRACTICAL APPROACH
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Seven Separate Sequence Styles Speed Stimulus Scenarios […] Read More… from Seven Separate Sequence Styles Speed Stimulus Scenarios
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Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI […] Read More… from Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI
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C through UVM: Effectively using C based models with UVM based Verification IP […] Read More… from C through UVM: Effectively using C based models with UVM based Verification IP
SVA Encapsulation in UVM: enabling phase and configuration aware assertions […] Read More… from SVA Encapsulation in UVM: enabling phase and configuration aware assertions
One Compile to Rule Them All: An Elegant Solution for OVM/UVM Testbench Topologies […] Read More… from One Compile to Rule Them All: An Elegant Solution for OVM/UVM Testbench Topologies
Extendable Messaging Techniques for Debugging and Analyzing UVM Testbench Structure and Transaction Flow […] Read More… from Extendable Messaging Techniques for Debugging and Analyzing UVM Testbench Structure and Transaction Flow
Design and Verification of an Image Processing CPU using UVM […] Read More… from Design and Verification of an Image Processing CPU using UVM
Guaranteed Vertical Reuse – C Execution In a UVM Environment […] Read More… from Guaranteed Vertical Reuse – C Execution In a UVM Environment
MS-SoC Best Practices – Advanced Modeling & Verification Techniques for first-pass success […] Read More… from MS-SoC Best Practices – Advanced Modeling & Verification Techniques for first-pass success
Power Aware Verification Strategy for SoCs […] Read More… from Power Aware Verification Strategy for SoCs
A Systematic Approach to Power State Table (PST) Debugging […] Read More… from A Systematic Approach to Power State Table (PST) Debugging
Beyond UVM: Creating Truly Reusable Protocol Layering […] Read More… from Beyond UVM: Creating Truly Reusable Protocol Layering
The Finer Points of UVM: Tasting Tips for the Connoisseur […] Read More… from The Finer Points of UVM: Tasting Tips for the Connoisseur
Practical Issues in Implementing Fast and Accurate SystemC-Constructed Virtual Platform Simulation […] Read More… from Practical Issues in Implementing Fast and Accurate SystemC-Constructed Virtual Platform Simulation
A Tale of Two Languages – SystemVerilog and SystemC […] Read More… from A Tale of Two Languages – SystemVerilog and SystemC
Transaction-Level Friending: An Open-Source, Standards-Based Library for Connecting TLM Models in SystemC and SystemVerilog […] Read More… from Transaction-Level Friending: An Open-Source, Standards-Based Library for Connecting TLM Models in SystemC and SystemVerilog
Sequence, Sequence on the Wall – Who’s the Fairest of Them All? […] Read More… from Sequence, Sequence on the Wall – Who’s the Fairest of Them All?
fsim_logic – A VHDL type for testing of FLYTRAP […] Read More… from fsim_logic – A VHDL type for testing of FLYTRAP
I’m Still In Love With My X! (but, do I want my X to be an optimist, a pessimist, or eliminated?) […] Read More… from I’m Still In Love With My X! (but, do I want my X to be an optimist, a pessimist, or eliminated?)
Weathering the Verification Storm: Methodology Enhancements used on a Next Generation Weather Satellite C&DH Program […] Read More… from Weathering the Verification Storm: Methodology Enhancements used on a Next Generation Weather Satellite C&DH Program
Boost Verification Results by Bridging the Hardware/Software Testbench Gap […] Read More… from Boost Verification Results by Bridging the Hardware/Software Testbench Gap
Bringing Constrained Random into SoC SW-driven Verification […] Read More… from Bringing Constrained Random into SoC SW-driven Verification
Lessons from the field – IP/SoC integration techniques that work […] Read More… from Lessons from the field – IP/SoC integration techniques that work
Mixed-abstraction Modeling Approach with Fault Injection for Hardware-Firmware Co-design and Functional Co-verification of an Automotive Airbag System on Chip Product […] Read More… from Mixed-abstraction Modeling Approach with Fault Injection for Hardware-Firmware Co-design and Functional Co-verification of an Automotive Airbag System on Chip Product
Using Advanced OOP Concepts To Integrate Templatized Algorithms for Standard Protocols With UVM […] Read More… from Using Advanced OOP Concepts To Integrate Templatized Algorithms for Standard Protocols With UVM
Who’s Watching the Watchmen? The Time has Come to Objectively Measure the Quality of Your Verification Environment […] Read More… from Who’s Watching the Watchmen? The Time has Come to Objectively Measure the Quality of Your Verification Environment
Using UVM: The Condensed Guide For Designers, Debuggers, Test-Writers And Other Skeptics […] Read More… from Using UVM: The Condensed Guide For Designers, Debuggers, Test-Writers And Other Skeptics
Qualification of Formal Properties for Productive Automotive Microcontroller Verification […] Read More… from Qualification of Formal Properties for Productive Automotive Microcontroller Verification
Using Formal Verification to Exhaustively Verify SoC Assemblies […] Read More… from Using Formal Verification to Exhaustively Verify SoC Assemblies
How to Kill 4 Birds with 1 Stone: Using Formal Verification to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software Specifications […] Read More… from How to Kill 4 Birds with 1 Stone: Using Formal Verification to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software Specifications
How to Succeed Against Increasing Pressure: Automated Techniques for Unburdening Verification Engineers […] Read More… from How to Succeed Against Increasing Pressure: Automated Techniques for Unburdening Verification Engineers
Memory Subsystem Verification: Can it be taken for granted? […] Read More… from Memory Subsystem Verification: Can it be taken for granted?
Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath Scoreboards […] Read More… from Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath Scoreboards
Unconstrained UVM SystemVerilog Performance […] Read More… from Unconstrained UVM SystemVerilog Performance
Maximize Vertical Reuse, Building Module to System Verification Environments with UVM e […] Read More… from Maximize Vertical Reuse, Building Module to System Verification Environments with UVM e
Run-time Configuration of a Verification Environment – A Novel Use of the OVM/UVM Analysis Pattern […] Read More… from Run-time Configuration of a Verification Environment – A Novel Use of the OVM/UVM Analysis Pattern
A SystemVerilog Framework for Easy Method Advice in Object-oriented Test Benches […] Read More… from A SystemVerilog Framework for Easy Method Advice in Object-oriented Test Benches
ASIC-Strength Verification in a Fast-Moving FPGA World […] Read More… from ASIC-Strength Verification in a Fast-Moving FPGA World
Taming the beast: A smart generation of Design Attributes (Parameters) for Verification Closure Using Specman […] Read More… from Taming the beast: A smart generation of Design Attributes (Parameters) for Verification Closure Using Specman
Verifying functionality is simply not enough […] Read More… from Verifying functionality is simply not enough
Pragmatic Verification Reuse in a Vertical World […] Read More… from Pragmatic Verification Reuse in a Vertical World
Monitors, Monitors Everywhere – Who Is Monitoring the Monitors […] Read More… from Monitors, Monitors Everywhere – Who Is Monitoring the Monitors
An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 Experience […] Read More… from An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 Experience
The Need for Speed: Understanding design factors that make multi-core parallel simulations efficient […] Read More… from The Need for Speed: Understanding design factors that make multi-core parallel simulations efficient
BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMS […] Read More… from BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMS
Traffic Profiling and Performance Instrumentation For On-Chip Interconnects […] Read More… from Traffic Profiling and Performance Instrumentation For On-Chip Interconnects
Switch the Gears of the UVM Register Package to cruise through the street named “Register Verification”. […] Read More… from Switch the Gears of the UVM Register Package to cruise through the street named “Register Verification”.
Register Verification: Do We Have Reliable Specification? […] Read More… from Register Verification: Do We Have Reliable Specification?
Low-Power Verification Automation – A Practical Approach […] Read More… from Low-Power Verification Automation – A Practical Approach
Unifying Hardware-Assisted Verification and Validation Using UVM and Emulation […] Read More… from Unifying Hardware-Assisted Verification and Validation Using UVM and Emulation
Deploying Parameterized Interface with UVM […] Read More… from Deploying Parameterized Interface with UVM
Using Formal Techniques to Verify System on Chip Reset Schemes […] Read More… from Using Formal Techniques to Verify System on Chip Reset Schemes
A Reusable, Scalable Formal App for Verifying Any Configuration of 3D IC Connectivity […] Read More… from A Reusable, Scalable Formal App for Verifying Any Configuration of 3D IC Connectivity
An Innovative Methodology for RTL and Verification IP Sharing Between Two Projects […] Read More… from An Innovative Methodology for RTL and Verification IP Sharing Between Two Projects
Seven Separate Sequence Styles Speed Stimulus Scenarios […] Read More… from Seven Separate Sequence Styles Speed Stimulus Scenarios
On Verification Coverage Metrics in Formal Verification and Speeding Verification Closure with UCIS Coverage Interoperability Standard […] Read More… from On Verification Coverage Metrics in Formal Verification and Speeding Verification Closure with UCIS Coverage Interoperability Standard
UCIS APPLICATIONS: IMPROVING VERIFICATION PRODUCTIVITY, SIMULATION THROUGHPUT, AND COVERAGE CLOSURE PROCESS […] Read More… from UCIS APPLICATIONS: IMPROVING VERIFICATION PRODUCTIVITY, SIMULATION THROUGHPUT, AND COVERAGE CLOSURE PROCESS
Systematic Application of UCIS to Improve the Automation on Verification Closure […] Read More… from Systematic Application of UCIS to Improve the Automation on Verification Closure
