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Read More… from Soft Constraints in SV: Semantics and Challenges
Event Year: 2012
Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor Core
A Practical Approach to Measuring and Improving the Functional Verification of Embedded Software
Supplementing Simulation of a Microcontroller Flash Memory Subsystem with Formal Verification
Exquisite Modeling of VIP
Conscious of Streams Managing Parallel Stimulus
There’s something wrong between Sally Sequencer and Dirk Driver (Why UVM sequencers and drivers need some relationship counseling)
e/eRM to SystemVerilog/UVM: Mind the Gap, But Don’t Miss the Train
Experiences in Migrating a Chip-Level Verification Environment from UVM-EA to UVM-1.x
Melting Verification Pot: Integrating RVM/VMM and UVM, a Practical Guide and Lessons Learned.
Graph-IC Verification
Systematically Achieving CDC Verification Closure based on Coverage Models and Coverage Metrics
BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPS
Relieving the Parameterized Coverage Headache
A 30 Minute Project Makeover Using Continuous Integration
Memory Debugging of Virtual Platforms
Failure Triage: The Neglected Debugging Problem
Experience with OVM-Based Mixed-Signal Verification of the Impedance Calibration Block for a DDR Interface
Analog Transaction Level Modeling for Verification of Mixed-Signal-Blocks
From Spec to Verification Closure: A case study of applying UVM-MS for first pass success to a complex MS-SoC design
Shaping Formal Traces without Constraints: A Case Study in Closing Code Coverage on a Crypto Engine using Formal Verification
Exhaustive Latch Flow – Through Verification with Formal Methods
Keeping Up with Chip — the Proposed SystemVerilog 2012 Standard Makes Verifying Ever-increasing Design Complexity More Efficient
How I Learned to Stop Worrying and Love Benchmarking Functional Verification!
Yikes! Why is my SystemVerilog Testbench So Slooooow?
Hardware/Software Co-Verification Using Specman and SystemC with TLM Ports
A SystemC Library for Advanced Verification – Towards an Enhanced OVM/UVM for SystemC
Register This! Experiences Applying UVM Registers
OVM & UVM Techniques for On-the-fly Reset
Easier SystemVerilog with UVM: Taming the Beast
The Case for Low-Power Simulation-to-Implementation Equivalence Checking
Holistic Automated Code Generation: No Headache with Last-Minute Changes
Better Living Through Better Class-Based SystemVerilog Debug
System Verilog Assertion Linting: Closing Potentially Critical Verification Holes
Configuring Your Resources the UVM Way!
ACE’ing the Verification of a Coherent System Using UVM
Fabric Verification
X-propagation Woes: Masking Bugs at RTL and Unnecessary Debug at the Netlist
Designing, Verifying and Building an Advanced L2 Cache Subsystem using SystemC
Is Power State Table (PST) Golden?
Low Power SoC Verification: IP Reuse and Hierarchical Composition using UPF
Holistic Automated Code Generation: No Headache with Last-Minute Changes
Better Living Through Better Class-Based SystemVerilog Debug
Soft Constraints in SystemVerilog Semantics and Challenges
SystemVerilog Assertion Linting: Closing Potentially Critical Verification Holes
Autocuration: An Implementation of a Continuous Integration System Employed in the Development of AMD’s Next-generation Microprocessor Core
A Practical Approach to Measuring and Improving the Functional Verification of Embedded Software
Supplementing Simulation of a Microcontroller Flash Memory Subsystem with Formal Veri cation
Exquisite modeling of verification IP: Challenges and Recommendations
Configuring Your Resources the UVM Way!
Conscious of Streams: Managing Parallel Stimulus
ACE’ing the Verification of a Coherent System Using UVM
There’s something wrong between Sally Sequencer and Dirk Driver – why UVM sequencers and drivers need some relationship counselling
Addressing HW/SW Interface Quality through Standards
e/eRM to SystemVerilog/UVM: Mind the Gap, But Don’t Miss the Train
Experiences in Migrating a Chip-Level Verification Environment from UVM EA to UVM 1.1
Melting Verification Pot: Integrating RVM/VMM and UVM, a Practical Guide and Lessons Learned.
Graph-IC Verification
Systematically Achieving CDC Verification Closure based on Coverage Models and Coverage Metrics
BRINGING CONTINUOUS DOMAIN INTO SYSTEMVERILOG COVERGROUPS
Relieving the Parameterized Coverage Headache
A 30 Minute Project Makeover Using Continuous Integration
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Read More… from A 30 Minute Project Makeover Using Continuous Integration