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Event Year: 2018

DVCon EU 2018 Proceedings

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Low Power Apps (Shaping the Future of Low Power Verification)

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Unveil the Mystery of Code Coverage in Low Power Designs (Achieving Power Aware Verification Closure)

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Error Injection in a Subsystem Level Constrained Random UVM Testbench

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Using Automation to Close the Loop Between Functional Requirements and Their Verification

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Formal Verification of Floating-Point Hardware with Assertion-Based VIP

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Synthesis of Decoder Tables using Formal Verification Tools

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Managing Highly Configurable Design and Verification

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Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation)

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Practical Scheme to Enhance Verification Turn-Around-Time by Using Reusable Harness Interface (RHI)

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Formal Verification of Connections at SoC-level

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Formal Architectural Specification and Verification of A Complex SOC

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Architectural Formal Verification of System-Level Deadlocks

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An Efficient and Modular Approach for Formally Verifying Cache implementations

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UVM for HLS: An Expedient Approach to the Functional Verification of HLS Designs

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How to Stay Out of the News with ISO26262-Compliant Verification

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My Testbench Used to Break! Now it Bends (Adapting to Changing Design Configurations)

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Deploying Customized Solution for Graphics Registers with UVM1.2 RAL

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Simpler Register Model

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Making Autonomous Cars Safer – One chip at a time

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Automated Seed Selection Algorithm for an Arbitrary Test Suite

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Debugging Functional Coverage Models Get The Most Out of Your Cover Crosses

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UVM Acceleration using Hardware Emulator at Pre-silicon Stage

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Transparently Checkpointing Software Test Benches to Improve Productivity of SOC Verification in an Emulation Environment

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Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-Chips

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Just do it! Who cares if a Structural Analysis tool is using Formal Verification

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Automated Physical Hierarchy Generation: Tools and Methodology

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IDEs SHOULD BE AVAILABLE TO HARDWARE ENGINEERS TOO!

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VHDL 2018 New and Noteworthy

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IEEE-Compatible UVM Reference Implementation and Verification Components

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Formal Verification in the Real World

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Bridge the Portable Test and Stimulus to UVM Simulation Environment

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Building Portable Stimulus Into your IP-XACT Flow

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Portable Stimulus vs Formal vs UVM: A Comparative Analysis of Verification Methodologies Throughout the Life of an IP Block

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Leveraging more from GLS: Using metric driven GLS stimuli to boost timing verification

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Using Formal to Exhaustively Determine Unsafe Clock Ratios Between Asynchronous Blocks

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Clock Domain Crossing Challenges in Latch Based Designs

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Improving Verification Predictability and Efficiency Using Big Data

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Don’t delay catching bugs: Using UVM based architecture to model external board delays

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Making Security Verification “SECURE”

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Ultimate Shift Left: Unleash the Power of UVM Virtual LAB Methodology upon SoC Verification

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UVM testbench design for ISA functional verification of a microprocessor

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SoC Verification of Analog IP Integration through Automated, Formal-Based, Rule-driven Spec Generation

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Is Specman Still Relevant? Using UVM-ML to Take Advantage of Multiple Verification Languages

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Fast Track Formal Verification Signoff

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REUSABLE UPF: Transitioning from RTL to Gate Level Verification

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Managing and Automating Hw/Sw Tests from IP to SoC

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Holistic Approach to IO Timing Verification Using Portable Stimulus and Assertions

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Unraveling the Complexities of Functional Coverage: An advanced guide to simplify your use model

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UVM and C – Perfect Together

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UVM Register Map Dynamic Configuration

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UVM mixed signal extensionsSharing Best Practice and Standardization Ideas

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UVM based Hardware/Software Co- Verification of a HW Coprocessor using Host Execution Techniques

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UVM Audit Tutorial Assessing UVM Testbenches to Expose Coding Errors & Improve Quality

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Using UVM-ML library to enable reuse of TLM2.0 models in UVM test benches

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Using Mutation Coverage for Advanced Bug Hunting and Verification Signoff

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Using High-level Synthesis and Emulation to Rapidly Develop AI Algorithms in Hardware

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Using Constraints for SystemC AMS Design and Verification

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Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262

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Unifying Mixed-Signal and Low-Power Verification

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Tutorial 7 Tutorial on RISC-V Design and Verification

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Temporal Decoupling – Are “Fast” and “Correct” Mutually Exclusive?

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SystemC-to-Verilog Compiler: a productivity-focused tool for hardware design in cycle-accurate SystemC

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Retrascope: Open-Source Model Checkerfor HDL Descriptions

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Requirements Driven Design Verification Flow Tutorial

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Processing deliberate verification errors during regression

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Portable Test and Stimulus: The Next Level of Verification Productivity is Here

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Performance modeling and timing verification for DRAM memory subsystems

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Open Source Solution for RISC-V Verification

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Multi-Variant Coverage: Effective Planning and Modelling

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Methodology for checking UVM VIPs

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Making ISO26262 Functional Safety Verification a Natural Extension of Functional Verification

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Machine Learning Introduction and Exemplary Application in Embedded Wireless Platforms

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Leveraging hardware emulation to accelerate SoCverification in multi-physics automotive simulation environment via the Functional Mock-up Interface

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Integrating Parallel SystemC Simulationinto Simics® Virtual Platform

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IEEE 1801 Assisted Custom IP Development and Low Power Checks Using Cadence Virtuoso Power Manager

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Hybrid Flow: A smart methodology to migrate from traditional Low Power Methodology

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Read More… from Hybrid Flow: A smart methodology to migrate from traditional Low Power Methodology

Hardware Software Co-verification in Hybrid QEMU/HDL Environment

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Gathering Memory Hierarchy Statistics in QEMU

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Functional Safety Verification for ISO 26262 – Compliant Automotive Designs

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Firmware Firmly under Control: New Optimization and Verification Techniques for Application Specific Electronic System

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Fault Effect Propagation using Verilog A for Analog Test Coverage

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Fast and FuriousQuick Innovation from Idea to Real Prototy

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Read More… from Fast and FuriousQuick Innovation from Idea to Real Prototy

Extending functionality of UVM components by using Visitor design pattern

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Enabling Digital Mixed-Signal Verification of Loading Effects in Power Regulation using SystemVerilog User-Defined Nettype

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Efficient use of Virtual Prototypes in HW/SW Development and Verification

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Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon

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Developing Dynamic Resource Management System in SoCEmulation

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Developing & Testing Automotive Software on Multi SoC ECU Architectures using Virtual Prototyping

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Designing a PSS Reuse Strategy

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Customizing UVM Agent Supporting Multi-Layered & TDM Protocols

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Covering the Last Mile in SoC-Level Deadlock Verification

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Clustering and Classification of UVM Test Failures Using Machine Learning Techniques

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Case Study of Verification Planning to Coverage Closure @Block, Subsystem and System on Chip Level

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Read More… from Case Study of Verification Planning to Coverage Closure @Block, Subsystem and System on Chip Level

Automated Configuration of Verification Environments using SpecmanMacros

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Automate and Accelerate RISC-V Verification by Compositional Formal Methods

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Agile and dynamic functional coverage using SQL on the cloud

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Addressing Asynchronous FIFO Verification Challenge

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Acceleration of product and test environment using SystemC TLM

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A Novel Performance Evaluation Methodology using Virtual Prototyping and Emulation

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A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGA

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Protocol verification of an IEEE 802.3bw PHY Application of mixed signal extensions to an UVM verification environment

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Methodology for Automated Generation and Validation of Analog Behavioral Models for Mixed-Signal Verification

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Using Constraints for SystemC AMS Design and Verification

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Fault Effect Propagation using Verilog-A for Analog Test Coverage

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Formal Verification of a Highly Configurable DDR Controller IP

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Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262

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Read More… from Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262

Qualification of a Verification IP under Requirement Based Verification standards An approach to the verification of the verification

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Read More… from Qualification of a Verification IP under Requirement Based Verification standards An approach to the verification of the verification

Improving the Confidence Level in Functional Safety Simulation Tools for ISO 26262

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Efficient Fault Injection Methods for Safety Software Testing Based on Virtual Prototypes: Application to Powertrain ECU

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Read More… from Efficient Fault Injection Methods for Safety Software Testing Based on Virtual Prototypes: Application to Powertrain ECU

Enabling Visual Design Verification Analytics – From Prototype Visualizations to an Analytics Tool using the Unity Game Engine

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Same bits, different meaning – when direct execution based simulation becomes complicated

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UPF Power Models: Empowering the power intent specification

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A New Approach to Low-Power Verification: Low Power Apps

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IEEE 1801 Assisted Custom IP Development and Low Power Checks Using Cadence Virtuoso Power Manager

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Read More… from IEEE 1801 Assisted Custom IP Development and Low Power Checks Using Cadence Virtuoso Power Manager

Multi-Variant Coverage: Effective Planning and Modelling

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Characterizing RF Wireless Receivers Performance in UVM Environment

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Automated Configuration of Verification Environments using Specman Macros DVcon Europe 2018 – Paper number 260-OH22

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Read More… from Automated Configuration of Verification Environments using Specman Macros DVcon Europe 2018 – Paper number 260-OH22

MicroTESK: Automated Architecture Validation Suite Generator for Microprocessors

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Use Stimulus Domain for Systematic Exploration of Time Dimension and Automatic Testcase Construct

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Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication endpoint

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Generating Bus Traffic Patterns

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Temporal Decoupling – Are “Fast” and “Correct” Mutually Exclusive?

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Read More… from Temporal Decoupling – Are “Fast” and “Correct” Mutually Exclusive?

Fast and Furious Quick Innovation from Idea to Real Prototype

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Read More… from Fast and Furious Quick Innovation from Idea to Real Prototype

Hybrid Flow: A smart methodolgy to migrate from traditional Low Power Methodology

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Read More… from Hybrid Flow: A smart methodolgy to migrate from traditional Low Power Methodology

Guiding Functional Verification Regression Analysis Using Machine Learning and Big Data Methods

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Read More… from Guiding Functional Verification Regression Analysis Using Machine Learning and Big Data Methods

Advanced Techniques to Accomplish Power Aware CDC Verification

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Read More… from Advanced Techniques to Accomplish Power Aware CDC Verification

Clustering and Classification of UVM Test Failures Using Machine Learning Techniques

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Read More… from Clustering and Classification of UVM Test Failures Using Machine Learning Techniques

UVM Register Map Dynamic Configuration

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Extending functionality of UVM components by using Visitor design pattern

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Read More… from Extending functionality of UVM components by using Visitor design pattern

A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGA*

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Read More… from A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGA*

Hardware construction with SystemC

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Performance modeling and timing verification for DRAM memory subsystems

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Read More… from Performance modeling and timing verification for DRAM memory subsystems

Acceleration of product and test environment development using SystemC-TLM

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Using UVM-ML library to enable reuse of TLM2.0 models in UVM test benches

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Read More… from Using UVM-ML library to enable reuse of TLM2.0 models in UVM test benches

Low Power Coverage: The Missing Piece in Dynamic Simulation

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Read More… from Low Power Coverage: The Missing Piece in Dynamic Simulation

Whose Fault Is It Formally? Formal Techniques for Optimizing ISO 26262 Fault Analysis.

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Read More… from Whose Fault Is It Formally? Formal Techniques for Optimizing ISO 26262 Fault Analysis.

Lets be Formal While Talking About Verification Quality: A Novel Approach Of Qualifying Assertion Based IPs

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IP-XACT based SoC Interconnect Verification Automation

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Functional Safety Verification For ISO 26262

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UVM Verification Environment Based on Software Design Patterns

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Common Challenges and Solutions to Integrating a UVM Testbench

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Read More… from Common Challenges and Solutions to Integrating a UVM Testbench

Deep Predictive Coverage Collection

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Formal Verification Tutorial Breaking Through the Knowledge Barrier

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UVM-based verification of a RISC-V Processor Core Using a Golden predictor model and a Configuration Layer

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SoC Verification Speed – More is Better

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Using Mutation Coverage for Advanced Bug Hunting

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Read More… from Using Mutation Coverage for Advanced Bug Hunting

Portable Test and Stimulus: The Next Level of Verification Productivity is Here

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Read More… from Portable Test and Stimulus: The Next Level of Verification Productivity is Here

Deep Learning for Design and Verification Engineers

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An Analytical View of Test Results Using CityScapes

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Hybrid Approach to Testbench and Software Driven Verification on Emulation

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Read More… from Hybrid Approach to Testbench and Software Driven Verification on Emulation

What Time Is It: Implementing a SystemVerilog Object-Oriented Wrapper for Interacting with the C Library time

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SGEN2: Evolution of a Sequence-Based Stimulus Engine for Micro-Processor Verification

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Synthesis of Decoder Tables Using Formal Verification Tools

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Comprehensive IP to SoC CDC Verification Using Hybrid Data Model

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Read More… from Comprehensive IP to SoC CDC Verification Using Hybrid Data Model

Cleaning Out Your Pipes – Pipeline Debug in UVM Testbenches

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Read More… from Cleaning Out Your Pipes – Pipeline Debug in UVM Testbenches

Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation Requirements

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Rockin’ the Polymorphism for an Elegant UVM Testbench Architecture

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Read More… from Rockin’ the Polymorphism for an Elegant UVM Testbench Architecture

UVM-FM: Reusable Extension Layer for UVMto Simplify Functional Modeling

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Read More… from UVM-FM: Reusable Extension Layer for UVMto Simplify Functional Modeling

Verification Strategy for Pipeline Type of Design

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Read More… from Verification Strategy for Pipeline Type of Design

Traditional top level static low power rule check

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A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic

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Read More… from A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic

Context-Aware DFM Rule Analysis and Scoring Using Machine Learning

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Read More… from Context-Aware DFM Rule Analysis and Scoring Using Machine Learning

Proper Probing: Flexibility on the TLM Level

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Read More… from Proper Probing: Flexibility on the TLM Level

Preventing Chip-Killing Glitches on CDC Paths with Automated Formal Analysis

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Read More… from Preventing Chip-Killing Glitches on CDC Paths with Automated Formal Analysis

Let’s be Formal While Talking About Verification Quality: A Novel Approach to Qualify Assertion Based VIPs

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Read More… from Let’s be Formal While Talking About Verification Quality: A Novel Approach to Qualify Assertion Based VIPs

FORMAL VERIFICATION OF FLOATING-POINT HARDWARE WITH ASSERTION-BASED VIP

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Read More… from FORMAL VERIFICATION OF FLOATING-POINT HARDWARE WITH ASSERTION-BASED VIP

Whose Fault Is It Formally? Formal Techniques for Optimizing ISO 26262 Fault Analysis.

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Read More… from Whose Fault Is It Formally? Formal Techniques for Optimizing ISO 26262 Fault Analysis.

Using Automation to Close the Loop Between Functional Requirements and Their Verification

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Read More… from Using Automation to Close the Loop Between Functional Requirements and Their Verification

Error Injection in a Subsystem Level Constrained Random UVM Testbench

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Read More… from Error Injection in a Subsystem Level Constrained Random UVM Testbench

Unveil the Mystery of Code Coverage in Low-Power Designs: Achieving Power Aware Verification Closure

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Read More… from Unveil the Mystery of Code Coverage in Low-Power Designs: Achieving Power Aware Verification Closure

Low Power Coverage: The Missing Piece in Dynamic Simulation

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Read More… from Low Power Coverage: The Missing Piece in Dynamic Simulation

Low Power Apps: Shaping the Future of Low Power Verification

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Read More… from Low Power Apps: Shaping the Future of Low Power Verification

Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation)

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Read More… from Challenges and Mitigations of Porting a UVM Testbench from Simulation to Transaction-Based Acceleration (Co-Emulation)

IP-XACT based SoC Interconnect Verification Automation

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Managing Highly Configurable Design and Verification

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Read More… from Managing Highly Configurable Design and Verification

Formal Verification on Deep Learning Instructions of GPU

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Read More… from Formal Verification on Deep Learning Instructions of GPU

UVM for HLS: An Expedient Approach to the Functional Verification of HLS Designs

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Read More… from UVM for HLS: An Expedient Approach to the Functional Verification of HLS Designs

Common Challenges and Solutions to Integrating a UVM Testbench in Place of a Legacy Monolithic Testing Environment

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Read More… from Common Challenges and Solutions to Integrating a UVM Testbench in Place of a Legacy Monolithic Testing Environment

UVM and C – Perfect Together

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Read More… from UVM and C – Perfect Together

UVM Verification Environment Based on Software Design Patterns

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Read More… from UVM Verification Environment Based on Software Design Patterns

An Efficient and Modular Approach for Formally Verifying Cache Implementations

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Read More… from An Efficient and Modular Approach for Formally Verifying Cache Implementations

Architectural Formal Verification of System-Level Deadlocks

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Read More… from Architectural Formal Verification of System-Level Deadlocks

FORMAL ARCHITECUTRAL SPECIFICATION AND VERIFICATION OF A COMPLEX SOC

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Read More… from FORMAL ARCHITECUTRAL SPECIFICATION AND VERIFICATION OF A COMPLEX SOC

Formal Verification of Connections at SoC-level

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Read More… from Formal Verification of Connections at SoC-level

Practical Scheme to Enhance Verification Turn-Around-Time by Using Reusable Harness Interface (RHI)

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Read More… from Practical Scheme to Enhance Verification Turn-Around-Time by Using Reusable Harness Interface (RHI)

Transparently Checkpointing Software Test Benches to Improve Productivity of SoC Verification in an Emulation Environment

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Read More… from Transparently Checkpointing Software Test Benches to Improve Productivity of SoC Verification in an Emulation Environment

UVM Acceleration Using Hardware Emulator at Pre-silicon Stage

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