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Event Year: 2022

Wrong FPGA Low Power measures that people with ASIC design experience tend to fall into and the correct method paper

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Read More… from Wrong FPGA Low Power measures that people with ASIC design experience tend to fall into and the correct method paper

Wrong FPGA Low Power measures that people with ASIC design experience tend to fall into and the correct method paper

[…]

Read More… from Wrong FPGA Low Power measures that people with ASIC design experience tend to fall into and the correct method paper

Utilization of RNM to confirm specification consistency between digital analog

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Read More… from Utilization of RNM to confirm specification consistency between digital analog

Register Modeling – Exploring Fields, Registers and Address Maps

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Read More… from Register Modeling – Exploring Fields, Registers and Address Maps

Register Modeling – Exploring Fields, Registers and Address Maps

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Read More… from Register Modeling – Exploring Fields, Registers and Address Maps

Raising the level of Formal Signoff with End-to-End Checking Methodology

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Raising the level of Formal Signoff with End-to-End Checking Methodology

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PSS action sequence modeling using Machine Learning

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Read More… from PSS action sequence modeling using Machine Learning

Machine Learning-based Smart Assessment of User Floorplan Quality without running Place & Route

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Read More… from Machine Learning-based Smart Assessment of User Floorplan Quality without running Place & Route

IEEE2804 SHIM: Software-Hardware Interface for Multi-Many-Core

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Read More… from IEEE2804 SHIM: Software-Hardware Interface for Multi-Many-Core

Functional safety architecture that suppresses increases in circuit size and power consumption in ISO26262 compliant LSI development slides

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Fast Congestion Planning and Floorplan QoR Assessment

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DVCon JP 2022 Proceedings

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Compact AI accelerator for embedded applications

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Accellera PSS being adopted in real projects Tutorial

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Closing and Awards

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DVCon Europe 2022 Proceedings Showcase Link

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Closing with Awards

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Panel: Are Processor/SoC Discontinuities Turning Verification on its Head?

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Panel: 5G Chip Design Challenges and their Impact on Verification

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Keynote: Developing the Chip-to-Cloud Architecture for the Most Desirable Cars

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Day 2 Opening

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Keynote: Challenges in Soc Verification for 5G and Beyond

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Day 1 Opening

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How the Right Mindset Increases Quality in RISC-V Verification

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A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMS

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Read More… from A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMS

uvm_mem – challenges of using UVM infrastructure in a hierarchical verification

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An Efficient Methodology for Mutation-Coverage-Collection of Formal-Property-Checking

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Read More… from An Efficient Methodology for Mutation-Coverage-Collection of Formal-Property-Checking

Types of Robustness Test According to DO-254 Guideline for Avionic Systems

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Read More… from Types of Robustness Test According to DO-254 Guideline for Avionic Systems

The Cost Of Standard Verification Methodology Implementations

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Read More… from The Cost Of Standard Verification Methodology Implementations

Reusable Verification Environment for a RISC-V Vector Accelerator

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Read More… from Reusable Verification Environment for a RISC-V Vector Accelerator

Register Testing – Exploring Tests, Register Model Libraries, Sequences and Backdoor Access

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Read More… from Register Testing – Exploring Tests, Register Model Libraries, Sequences and Backdoor Access

Unified firmware debug throughout SoC development lifecycle

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Read More… from Unified firmware debug throughout SoC development lifecycle

Agile Approaches to ASIC Verification (A3V) – A Novel Agile Flow in Functional Verification

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Read More… from Agile Approaches to ASIC Verification (A3V) – A Novel Agile Flow in Functional Verification

A Framework for the Execution of Python Tests in SystemC and Specman Testbenches

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Read More… from A Framework for the Execution of Python Tests in SystemC and Specman Testbenches

Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification

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Read More… from Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification

Challenges and Solutions for Creating Virtual Platforms of FPGA and SASIC Designs

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Read More… from Challenges and Solutions for Creating Virtual Platforms of FPGA and SASIC Designs

Modelling of UVC Monitor Class as a Finite State Machine for a Packet-Based Interface

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Read More… from Modelling of UVC Monitor Class as a Finite State Machine for a Packet-Based Interface

Overcoming System Verilog Assertions limitations through temporal decoupling and automation

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Read More… from Overcoming System Verilog Assertions limitations through temporal decoupling and automation

Using Open-Source EDA Tools in an Industrial Design Flow

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Read More… from Using Open-Source EDA Tools in an Industrial Design Flow

A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development

[…]

Read More… from A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development

A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoC

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Read More… from A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoC

A NOVEL APPROACH TO HARDWARE CONTROLLED POWER AWARE VERIFICATION WITH OPTIMISED POWER CONSUMPTION TECHNIQUES AT SOC

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Automated Creation of Reusable Generators for Analog IC Design with the Intelligent IP Method

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Development of a Core-Monitor for HW/SW Co-Debugging targetting Emulation Platform

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Read More… from Development of a Core-Monitor for HW/SW Co-Debugging targetting Emulation Platform

How creativity kills reuse – A modern take on UVM/SV TB architectures

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Read More… from How creativity kills reuse – A modern take on UVM/SV TB architectures

A UVM SystemVerilog Testbench for 5G/LTE Multi-Standard RF Transceiver

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Read More… from A UVM SystemVerilog Testbench for 5G/LTE Multi-Standard RF Transceiver

Automate Interrupt Checking with UVM Macros and Python

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Read More… from Automate Interrupt Checking with UVM Macros and Python

Automated Configuration of System Level C-Based CPU Testbench in Modern SoCs : A Novel Framework

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Read More… from Automated Configuration of System Level C-Based CPU Testbench in Modern SoCs : A Novel Framework

Building Confidence in System Level CPU Cache Coherency Verification for Complex SoCs through a Configurable Flexible and Portable Test Bench

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Read More… from Building Confidence in System Level CPU Cache Coherency Verification for Complex SoCs through a Configurable Flexible and Portable Test Bench

An Accelerated System Level CPU Verification through Simulation-Emulation Co-Existence

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Read More… from An Accelerated System Level CPU Verification through Simulation-Emulation Co-Existence

How to achieve verification closure of configurable code by combining static analysis and dynamic testing

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Read More… from How to achieve verification closure of configurable code by combining static analysis and dynamic testing

How rich descriptions enable early detection of hookup issues

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Read More… from How rich descriptions enable early detection of hookup issues

Reset Your Reset Domain Crossing (RDC) Verification with Machine Learning

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Read More… from Reset Your Reset Domain Crossing (RDC) Verification with Machine Learning

A Generic Configurable Error Injection Agent for All On-Chip Memories

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Read More… from A Generic Configurable Error Injection Agent for All On-Chip Memories

Fast, Parallel RISC-V Simulation for Rapid Software Verification

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Read More… from Fast, Parallel RISC-V Simulation for Rapid Software Verification

A Reconfigurable Interface Architecture to Protect System IP

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Read More… from A Reconfigurable Interface Architecture to Protect System IP

SAWD: Systemverilog Assertions Waveform-based Development tool

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Read More… from SAWD: Systemverilog Assertions Waveform-based Development tool

What is new in IP-XACT Std. IEEE 1685-2022?

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Read More… from What is new in IP-XACT Std. IEEE 1685-2022?

Verification of Virtual Platform Models – What do we Mean with Good Enough?

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Read More… from Verification of Virtual Platform Models – What do we Mean with Good Enough?

Verification of Inferencing Algorithm Accelerators

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Read More… from Verification of Inferencing Algorithm Accelerators

Verification of High-Speed Links through IBIS-AMI Models

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Read More… from Verification of High-Speed Links through IBIS-AMI Models

Verification 2.0 – Multi Engine, Multi-Run AI-Driven Verification

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Read More… from Verification 2.0 – Multi Engine, Multi-Run AI-Driven Verification

Taking Design Automation to the next level with User Experience Design

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Read More… from Taking Design Automation to the next level with User Experience Design

The Open Source DRAM Simulator DRAMSys4.0

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Read More… from The Open Source DRAM Simulator DRAMSys4.0

Static Sign-Off Best Practices Learnings and Experiences from Industry Use Cases

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Read More… from Static Sign-Off Best Practices Learnings and Experiences from Industry Use Cases

Fault Injection Analysis for Automotive Safety and Security

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Read More… from Fault Injection Analysis for Automotive Safety and Security

Efficient Loosely-Timed SystemC TLM-2.0 Modeling: A Hands-On Tutorial

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Read More… from Efficient Loosely-Timed SystemC TLM-2.0 Modeling: A Hands-On Tutorial

Boost your productivity in FPGA & ASIC design and verification

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Read More… from Boost your productivity in FPGA & ASIC design and verification

An end-to-end approach to Design and Verify BMS: from Requirements to Virtual Field Testing

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Read More… from An end-to-end approach to Design and Verify BMS: from Requirements to Virtual Field Testing

Achieving system dependability: the role of automation and scalability

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Read More… from Achieving system dependability: the role of automation and scalability

Accellera FS WG Update

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Read More… from Accellera FS WG Update

A Shift-left Methodology for an Early Power Closure Using EDCs and Power Analysis

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Read More… from A Shift-left Methodology for an Early Power Closure Using EDCs and Power Analysis

Types of Robustness Test According to DO-254 Guideline for Avionic Systems

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Read More… from Types of Robustness Test According to DO-254 Guideline for Avionic Systems

A novel approach to standardize reusable Modular Plug and Play Skeleton Structure (MPPSS) to expedite verification closure

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Read More… from A novel approach to standardize reusable Modular Plug and Play Skeleton Structure (MPPSS) to expedite verification closure

A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development

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Read More… from A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development

A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoC

[…]

Read More… from A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoC

Reset Your Reset Domain Crossing (RDC) Verification with Machine Learning

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Read More… from Reset Your Reset Domain Crossing (RDC) Verification with Machine Learning

Achieving system dependability: the role of automation and scalability

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Read More… from Achieving system dependability: the role of automation and scalability

Functional Safety WG Update

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Read More… from Functional Safety WG Update

Verification 2.0 – Multi Engine, Multi-Run – AI-Driven Verification

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Read More… from Verification 2.0 – Multi Engine, Multi-Run – AI-Driven Verification

Fault Injection Analysis for Automotive Safety and Security

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Read More… from Fault Injection Analysis for Automotive Safety and Security

Efficient Loosely-Timed SystemC TLM-2.0 Modeling: A Hands-On Tutorial

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Read More… from Efficient Loosely-Timed SystemC TLM-2.0 Modeling: A Hands-On Tutorial

How the Right Mindset Increases Quality in RISC-V Verification

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Read More… from How the Right Mindset Increases Quality in RISC-V Verification

UX Design & EDA – Enable Collaboration on Functional Coverage using Opens Source Software

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Read More… from UX Design & EDA – Enable Collaboration on Functional Coverage using Opens Source Software

Verification of Inferencing Algorithm Accelerators

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Read More… from Verification of Inferencing Algorithm Accelerators

A NOVEL AND EFFICIENT METHODOLOGY TO EXPEDITE COMPLEX SOC DV CLOSURE BY LEVERAGING MODULARLY ARCHITECTURED SCALABLE ENVIRONMENT

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Read More… from A NOVEL AND EFFICIENT METHODOLOGY TO EXPEDITE COMPLEX SOC DV CLOSURE BY LEVERAGING MODULARLY ARCHITECTURED SCALABLE ENVIRONMENT

A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMS

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Read More… from A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMS

uvm_mem – challenges of using UVM infrastructure in a hierarchical verification

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Read More… from uvm_mem – challenges of using UVM infrastructure in a hierarchical verification

An Efficient Methodology for Mutation-Coverage-Collection of Formal-Property-Checking

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Read More… from An Efficient Methodology for Mutation-Coverage-Collection of Formal-Property-Checking

Programmable Analysis of RISC-V Processor Simulations using WAL

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Read More… from Programmable Analysis of RISC-V Processor Simulations using WAL

Development and Verification of RISC-V Based DSP Subsystem IP: Case Study

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Read More… from Development and Verification of RISC-V Based DSP Subsystem IP: Case Study

Types of Robustness Test According to DO-254 Guideline for Avionic Systems

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Read More… from Types of Robustness Test According to DO-254 Guideline for Avionic Systems

The Cost of Standard Verification Methodology Implementations

[…]

Read More… from The Cost of Standard Verification Methodology Implementations

Reusable Verification Environment for a RISC-V Vector Accelerator

[…]

Read More… from Reusable Verification Environment for a RISC-V Vector Accelerator

Boost your productivity in FPGA & ASIC design and verification

[…]

Read More… from Boost your productivity in FPGA & ASIC design and verification

Closing the gap between requirement management and system design by requirement tracing

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Read More… from Closing the gap between requirement management and system design by requirement tracing

Register Testing – Exploring Tests, Register Model Libraries, Sequences and Backdoor Access

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Read More… from Register Testing – Exploring Tests, Register Model Libraries, Sequences and Backdoor Access

Unified Firmware Debug throughout SoC Development Lifecycle

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Read More… from Unified Firmware Debug throughout SoC Development Lifecycle

Agile Approaches to ASIC Verification (A3V) – A Novel Agile Flow in Functional Verification

[…]

Read More… from Agile Approaches to ASIC Verification (A3V) – A Novel Agile Flow in Functional Verification

Verification of Virtual Platform Models – What do we Mean with Good Enough?

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Read More… from Verification of Virtual Platform Models – What do we Mean with Good Enough?

A Framework for the Execution of Python Tests in SystemC and Specman Testbenches

[…]

Read More… from A Framework for the Execution of Python Tests in SystemC and Specman Testbenches

Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification

[…]

Read More… from Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification

Challenges and Solutions for Creating Virtual Platforms of FPGA and SASIC Designs

[…]

Read More… from Challenges and Solutions for Creating Virtual Platforms of FPGA and SASIC Designs

A shift-left Methodology for an early power closure using PowerPro

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Read More… from A shift-left Methodology for an early power closure using PowerPro

Modelling of UVC Monitor Class as a Finite State Machine for a Packet-Based Interface

[…]

Read More… from Modelling of UVC Monitor Class as a Finite State Machine for a Packet-Based Interface

Overcoming SystemVerilog Assertions limitations through temporal decoupling and automation

[…]

Read More… from Overcoming SystemVerilog Assertions limitations through temporal decoupling and automation

Using Open-Source EDA Tools in an Industrial Design Flow

[…]

Read More… from Using Open-Source EDA Tools in an Industrial Design Flow

A novel approach to standardize reusable Modular Plug and Play Skeleton Structure (MPPSS) to expedite verification closure

[…]

Read More… from A novel approach to standardize reusable Modular Plug and Play Skeleton Structure (MPPSS) to expedite verification closure

What is new in IP-XACT IEEE Std. 1685-2022?

[…]

Read More… from What is new in IP-XACT IEEE Std. 1685-2022?

A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development

[…]

Read More… from A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development

A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoC

[…]

Read More… from A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoC

A NOVEL APPROACH TO HARDWARE CONTROLLED POWER AWARE VERIFICATION WITH OPTIMISED POWER CONSUMPTION TECHNIQUES AT SOC

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Read More… from A NOVEL APPROACH TO HARDWARE CONTROLLED POWER AWARE VERIFICATION WITH OPTIMISED POWER CONSUMPTION TECHNIQUES AT SOC

Automated Creation of Reusable Generators for Analog IC Design with the Intelligent IP Method

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Read More… from Automated Creation of Reusable Generators for Analog IC Design with the Intelligent IP Method

Generic Core-Monitor for Hardware/Software Co-Debugging targeting Emulation Platform

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Read More… from Generic Core-Monitor for Hardware/Software Co-Debugging targeting Emulation Platform

The Open-Source DRAM Simulator DRAMSys4.0

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Read More… from The Open-Source DRAM Simulator DRAMSys4.0

How creativity kills reuse – A modern take on UVM/SV TB architecture

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Read More… from How creativity kills reuse – A modern take on UVM/SV TB architecture

A UVM SystemVerilog Testbench for 5G/LTE Multi-Standard RF Transceiver

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Read More… from A UVM SystemVerilog Testbench for 5G/LTE Multi-Standard RF Transceiver

Automate Interrupt Checking with UVM Macros and Python

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Read More… from Automate Interrupt Checking with UVM Macros and Python

An end-to-end approach to Design and Verify Battery Management Systems: from Requirements to Virtual Field Testing

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Read More… from An end-to-end approach to Design and Verify Battery Management Systems: from Requirements to Virtual Field Testing

Automated Configuration of System Level C-Based CPU Testbench in Modern SoCs : A Novel Framework

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Read More… from Automated Configuration of System Level C-Based CPU Testbench in Modern SoCs : A Novel Framework

Verification of High-Speed Links through IBIS-AMI Models

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Read More… from Verification of High-Speed Links through IBIS-AMI Models

Building Confidence in System level CPU Cache Coherency Verification for Complex SoC’s through a Configurable, Flexible and Portable Testbench

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Read More… from Building Confidence in System level CPU Cache Coherency Verification for Complex SoC’s through a Configurable, Flexible and Portable Testbench

An Accelerated System Level CPU Verification through Simulation-Emulation Co-Existence

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Read More… from An Accelerated System Level CPU Verification through Simulation-Emulation Co-Existence

How to achieve verification closure of configurable code by combining static analysis and dynamic testing

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Read More… from How to achieve verification closure of configurable code by combining static analysis and dynamic testing

Soumak – How rich descriptions enable early detection of hookup issues

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Read More… from Soumak – How rich descriptions enable early detection of hookup issues

Reset Your Reset Domain Crossing (RDC) Verification with Machine Learning

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Read More… from Reset Your Reset Domain Crossing (RDC) Verification with Machine Learning

A Generic Configurable Error Injection Agent for On-Chip Memories

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Read More… from A Generic Configurable Error Injection Agent for On-Chip Memories

SIM-V Fast, Parallel RISC-V Simulation for Rapid Software Verification

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Read More… from SIM-V Fast, Parallel RISC-V Simulation for Rapid Software Verification

Static Signoff Best Practices – Learnings and experiences from industry use cases

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Read More… from Static Signoff Best Practices – Learnings and experiences from industry use cases

A Reconfigurable Interface Architecture to Protect System IP

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Read More… from A Reconfigurable Interface Architecture to Protect System IP

SAWD: Systemverilog Assertions Waveform-based Development Tool

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Read More… from SAWD: Systemverilog Assertions Waveform-based Development Tool

DVCon India 2022 Proceedings

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Read More… from DVCon India 2022 Proceedings

Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IP

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Read More… from Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IP

Accelerating the SoC Integration Verification Cycle Time Leveraging the Legacy Design Confidence

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Read More… from Accelerating the SoC Integration Verification Cycle Time Leveraging the Legacy Design Confidence

Enabling high quality design sign-off with Jasper structural and auto formal checks

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Read More… from Enabling high quality design sign-off with Jasper structural and auto formal checks

Verifying the I/O peripherals of OpenTitan SOC using the Portable Stimulus Standard

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Read More… from Verifying the I/O peripherals of OpenTitan SOC using the Portable Stimulus Standard

Exhaustive validation of a cache memory controller using Formal Verification to meet performance and timing requirements

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Read More… from Exhaustive validation of a cache memory controller using Formal Verification to meet performance and timing requirements

Left shift catching of critical low power bugs with Formal Verification

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Read More… from Left shift catching of critical low power bugs with Formal Verification

Scalable Test bench Architecture and Methodology for Faster Codec and Computer Vision Scenario Verification

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Read More… from Scalable Test bench Architecture and Methodology for Faster Codec and Computer Vision Scenario Verification

Efficient Regression Management with Smart Data Mining Technique

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Read More… from Efficient Regression Management with Smart Data Mining Technique

Channel Modelling in Complex Serial IPs

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Read More… from Channel Modelling in Complex Serial IPs

Low Power Extension in UVM Power Management

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Read More… from Low Power Extension in UVM Power Management

A Novel Approach to Hardware Controlled Power Aware Verification with Optimized Power Consumption Techniques at SOC

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Read More… from A Novel Approach to Hardware Controlled Power Aware Verification with Optimized Power Consumption Techniques at SOC

Configurable Testbench (TB) for Configurable Design IP

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Read More… from Configurable Testbench (TB) for Configurable Design IP

Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex PMIC designed for SSD Applications

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Read More… from Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex PMIC designed for SSD Applications

What-If analysis of Safety Mechanism’s impacts on ETHMAC design under Functional Safety flow

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Read More… from What-If analysis of Safety Mechanism’s impacts on ETHMAC design under Functional Safety flow

A Generic Configurable Error Injection Agent for On-Chip Memories

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Read More… from A Generic Configurable Error Injection Agent for On-Chip Memories

Efficient Formal strategies to verify the robustness of the design

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Read More… from Efficient Formal strategies to verify the robustness of the design

Novel approach for SoC pipeline latency and connectivity verification using Formal

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Read More… from Novel approach for SoC pipeline latency and connectivity verification using Formal

Fault Injection Strategy to Validate ASIL-D Requirements of BMS Components

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Read More… from Fault Injection Strategy to Validate ASIL-D Requirements of BMS Components

Novel Adaptive CPU Scoreboard Methodology for a Multi-language environment

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Read More… from Novel Adaptive CPU Scoreboard Methodology for a Multi-language environment

A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage

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Read More… from A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage

The Industry eFPGA soft IP fully customizable, for hardware reconfiguration in the field

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Read More… from The Industry eFPGA soft IP fully customizable, for hardware reconfiguration in the field

Engaging with IEEE through Standards

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Read More… from Engaging with IEEE through Standards

Portable Stimulus Standard Update PSS in the Real World

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Read More… from Portable Stimulus Standard Update PSS in the Real World

IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 45 minutes!

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Read More… from IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 45 minutes!

Digital Transformation of EDA Environments To Accelerate Semiconductor Innovation

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Embracing Datapath Verification with Jasper C2RTL App

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Read More… from Embracing Datapath Verification with Jasper C2RTL App

VirtIO based GPU model

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Read More… from VirtIO based GPU model

SystemUVM™ Driving Portable Stimulus Ease-Of-Use

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Read More… from SystemUVM™ Driving Portable Stimulus Ease-Of-Use

Achieve Faster Debug Closure by Applying Big Data & Advanced RCA Technologies

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Read More… from Achieve Faster Debug Closure by Applying Big Data & Advanced RCA Technologies

Design space exploration of PIM (Processing in Memory) & PNC (Processing Near Memory) based on workload characterization

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Read More… from Design space exploration of PIM (Processing in Memory) & PNC (Processing Near Memory) based on workload characterization

Hardware Security – Industry Trends, Attacks and Solutions

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Read More… from Hardware Security – Industry Trends, Attacks and Solutions

Compute Link Express – CXL – CXL Consortium

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Read More… from Compute Link Express – CXL – CXL Consortium

Accelerating Semiconductor Time to ISO 26262 Compliance

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Read More… from Accelerating Semiconductor Time to ISO 26262 Compliance

Using UVM-e Testbenches Utilizing Metric-Driven Verification and Advanced Debug Capabilities

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Read More… from Using UVM-e Testbenches Utilizing Metric-Driven Verification and Advanced Debug Capabilities

Functional Safety Verification Methodology for ASIL-B Automotive Designs

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Read More… from Functional Safety Verification Methodology for ASIL-B Automotive Designs

Building UVM Testbenches for High Quality Serial Design IPs Modelling real world scenarios

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Read More… from Building UVM Testbenches for High Quality Serial Design IPs Modelling real world scenarios

A Novel Approach to Reduce Power Consumption By Bridging The Gap between Standalone Functional Scenario and Real Time Scenario at SOC

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Read More… from A Novel Approach to Reduce Power Consumption By Bridging The Gap between Standalone Functional Scenario and Real Time Scenario at SOC

Utilization of Emulation for accelerating the Functional Verification Closure

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Read More… from Utilization of Emulation for accelerating the Functional Verification Closure

Low Power Extension In UVM Power Management

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Read More… from Low Power Extension In UVM Power Management

Embrace Errors! Architecting UVM Testbenches for Dynamic Error Injection & Handling

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Read More… from Embrace Errors! Architecting UVM Testbenches for Dynamic Error Injection & Handling

Channel Modelling in Complex Serial IPs

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Read More… from Channel Modelling in Complex Serial IPs

NRFs Indentification & Signoff with GLS Validation

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Read More… from NRFs Indentification & Signoff with GLS Validation

Reset Verification using formal tool

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Read More… from Reset Verification using formal tool

Leveraging RAL and alternate automation (cocotb) techniques to improve Register Verification in UVM

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Read More… from Leveraging RAL and alternate automation (cocotb) techniques to improve Register Verification in UVM

Left shift catching of critical low power bugs with Formal Verification

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Read More… from Left shift catching of critical low power bugs with Formal Verification

Automated vManager regression using Jenkins

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Read More… from Automated vManager regression using Jenkins

SoC verification of Security x Safety aspects for memory programmed into secure and non-secure regions in Automotive devices

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Read More… from SoC verification of Security x Safety aspects for memory programmed into secure and non-secure regions in Automotive devices

A Holistic Overview on Preventive & Corrective Action To Handle Glitches

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Read More… from A Holistic Overview on Preventive & Corrective Action To Handle Glitches

Automating information retrieval from EDA software reports using effective parsing algorithms

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Read More… from Automating information retrieval from EDA software reports using effective parsing algorithms

Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex PMIC designed for SSD Applications

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Two Stage Framework for Corner Case Stimuli Generation Using Transformer and Reinforcement Learning

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