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Practical Schemes to Enhance Vertical, Horizontal and Platform Reusability of Verification Components in AMBA Based SoC Design […] Read More… from Practical Schemes to Enhance Vertical, Horizontal and Platform Reusability of Verification Components in AMBA Based SoC Design
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Statically Dynamic or Dynamically Static? Exploring the power of classes and enumerations in SystemVerilog Assertions for reusability and scalability […] Read More… from Statically Dynamic or Dynamically Static? Exploring the power of classes and enumerations in SystemVerilog Assertions for reusability and scalability
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Static Checking for Correctness of Functional Coverage Models […] Read More… from Static Checking for Correctness of Functional Coverage Models
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State-Space “Switching” Model of DC-DC Converters in SystemVerilog […] Read More… from State-Space “Switching” Model of DC-DC Converters in SystemVerilog
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Formal Fault Propagation Analysis that Scales to Modern Automotive SoCs […] Read More… from Formal Fault Propagation Analysis that Scales to Modern Automotive SoCs
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UPF: How to avoid traps in a Hierarchical Implementation Low Power flow? […] Read More… from UPF: How to avoid traps in a Hierarchical Implementation Low Power flow?
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Use of CDC-Jitter-Modeling inClock-Domain-Crossing-Circuits in RTL Design Phase […] Read More… from Use of CDC-Jitter-Modeling inClock-Domain-Crossing-Circuits in RTL Design Phase
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Specification by Example for Hardware Design and Verification […] Read More… from Specification by Example for Hardware Design and Verification
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Generation of (at least) UVM Register Models from IP Xact Using Model Driven SW Techniques […] Read More… from Generation of (at least) UVM Register Models from IP Xact Using Model Driven SW Techniques
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SimpleLink™ MCU Platform: IP-XACT to UVM Register Model – Standardizing IP and SoC Register Verification […] Read More… from SimpleLink™ MCU Platform: IP-XACT to UVM Register Model – Standardizing IP and SoC Register Verification
Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification Cycle […] Read More… from Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification Cycle
Efficient and Exhaustive Floating Point Verification Using Sequential Equivalence Checking […] Read More… from Efficient and Exhaustive Floating Point Verification Using Sequential Equivalence Checking
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Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation […] Read More… from Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation
Architecting “Checker IP” for AMBA protocols […] Read More… from Architecting “Checker IP” for AMBA protocols
Automatic Investigation of Power Inefficiencies […] Read More… from Automatic Investigation of Power Inefficiencies
New Constrained Random and Metric-Driven Verification Methodology using Python […] Read More… from New Constrained Random and Metric-Driven Verification Methodology using Python
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Systematic Speedup Techniques for Functional CDC Verification Closure […] Read More… from Systematic Speedup Techniques for Functional CDC Verification Closure
End to End Formal Verification Strategies for IP Verification […] Read More… from End to End Formal Verification Strategies for IP Verification
FUNCTIONAL COVERAGE OF REGISTER ACCESS VIA SERIAL BUS INTERFACE USING UVM […] Read More… from FUNCTIONAL COVERAGE OF REGISTER ACCESS VIA SERIAL BUS INTERFACE USING UVM
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PRACTICAL SCHEMES TO ENHANCE VERTICAL, HORIZONTAL AND PLATFORM REUSABILITY OF VERIFICATION COMPONENTS IN AMBA BASED SOC DESIGN […] Read More… from PRACTICAL SCHEMES TO ENHANCE VERTICAL, HORIZONTAL AND PLATFORM REUSABILITY OF VERIFICATION COMPONENTS IN AMBA BASED SOC DESIGN
Making Legacy Portable with the Portable Stimulus Specification […] Read More… from Making Legacy Portable with the Portable Stimulus Specification
UVM Interactive Debug Library: Shortening the Debug Turnaround Time […] Read More… from UVM Interactive Debug Library: Shortening the Debug Turnaround Time
Accelerating CDC Verification Closure on Gate-Level Designs […] Read More… from Accelerating CDC Verification Closure on Gate-Level Designs
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Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain Crossings […] Read More… from Comprehensive and Automated Static Tool Based Strategies for the Detection and Resolution of Reset Domain Crossings
Tackling Register Aliasing Verification Challenges in Complex ASIC Design […] Read More… from Tackling Register Aliasing Verification Challenges in Complex ASIC Design
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Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification Cycle […] Read More… from Advances in RF Transceiver SoC Verification: A Walk-Through over a 2.4 GHz Multi-Modal Integrated Transceiver Verification Cycle
Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design Verification […] Read More… from Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design Verification
Efficient and Exhaustive Floating Point Verification Using Sequential Equivalence Checking […] Read More… from Efficient and Exhaustive Floating Point Verification Using Sequential Equivalence Checking
Formal Proof for GPU Resource Management […] Read More… from Formal Proof for GPU Resource Management
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Making Formal Property Verification Mainstream: An Intel Graphics Experience […] Read More… from Making Formal Property Verification Mainstream: An Intel Graphics Experience
EARLY SOFTWARE DEVELOPMENT AND VERIFICATION METHODOLOGY USING HYBRID EMULATION PLATFORM […] Read More… from EARLY SOFTWARE DEVELOPMENT AND VERIFICATION METHODOLOGY USING HYBRID EMULATION PLATFORM
Micro-processor verification using a C++11 sequence-based stimulus engine. […] Read More… from Micro-processor verification using a C++11 sequence-based stimulus engine.
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Dynamic Regression Suite Generation Using Coverage-Based Clustering […] Read More… from Dynamic Regression Suite Generation Using Coverage-Based Clustering
Optimizing Random Test Constraints Using Machine Learning Algorithms […] Read More… from Optimizing Random Test Constraints Using Machine Learning Algorithms
Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation […] Read More… from Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation
Statically Dynamic or Dynamically Static? Exploring the power of classes and enumerations in SystemVerilog Assertions for reusability and scalability […] Read More… from Statically Dynamic or Dynamically Static? Exploring the power of classes and enumerations in SystemVerilog Assertions for reusability and scalability
Is the simulator behavior wrong for my SystemVerilog code? […] Read More… from Is the simulator behavior wrong for my SystemVerilog code?
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Doing Funny Stuff with the UVM Register Layer: Experiences Using Front Door Sequences, Predictors, and Callbacks […] Read More… from Doing Funny Stuff with the UVM Register Layer: Experiences Using Front Door Sequences, Predictors, and Callbacks
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Power Aware CDC Analysis at Top Level Using SOC Abstract Flow […] Read More… from Power Aware CDC Analysis at Top Level Using SOC Abstract Flow
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Automatic Debug Down to the Line of Code […] Read More… from Automatic Debug Down to the Line of Code
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Mixed-Signal Verification Methodology to Verify Type-C USB […] Read More… from Mixed-Signal Verification Methodology to Verify Type-C USB
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Transparent SystemC Model Factory for Scripting Languages […] Read More… from Transparent SystemC Model Factory for Scripting Languages
SYSTEM LEVEL FAULT INJECTION SIMULATION USING SIMULINK […] Read More… from SYSTEM LEVEL FAULT INJECTION SIMULATION USING SIMULINK
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Use of Portable Stimulus to Verify Task Dispatching and Scheduling Functions in an LTE Switch […] Read More… from Use of Portable Stimulus to Verify Task Dispatching and Scheduling Functions in an LTE Switch
Systematic Speedup Techniques for Functional CDC Verification Closure […] Read More… from Systematic Speedup Techniques for Functional CDC Verification Closure
End to End Formal Verification Strategies for IP Verification […] Read More… from End to End Formal Verification Strategies for IP Verification
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A Dyadic Transformation Based Methodology to Achieve Coverage Driven Verification Goal […] Read More… from A Dyadic Transformation Based Methodology to Achieve Coverage Driven Verification Goal
Novel Test Case Design Techniques for Logical Specifications of Safety Critical Systems Software in Aerial Vehicle […] Read More… from Novel Test Case Design Techniques for Logical Specifications of Safety Critical Systems Software in Aerial Vehicle
Functional Coverage of Register Access via Serial Bus Interface using UVM […] Read More… from Functional Coverage of Register Access via Serial Bus Interface using UVM
System Responsiveness Verification of large Multi-Processor System Configurations using Micro-Benchmarks and a Multi-Level Analysis […] Read More… from System Responsiveness Verification of large Multi-Processor System Configurations using Micro-Benchmarks and a Multi-Level Analysis
Automatic Investigation of Power Inefficiency […] Read More… from Automatic Investigation of Power Inefficiency
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Random Directed Low Power Coverage Methodology: A Smart Approach to Power Aware Verification Closure […] Read More… from Random Directed Low Power Coverage Methodology: A Smart Approach to Power Aware Verification Closure
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