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Event Year: 2019

DVCon EU 2019 Proceedings

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Break the SoC with Random UVM Instruction Driver

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From Device Trees to Virtual Prototypes

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Verification Strategies and Modelling for the Uninvited Guest in the System: Clock Jitter

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Improving Simulation Performance at SoC/Subsystem Level Using LITE Environment Approach

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Building And Modelling Reset Aware Testbench For IP Functional Verification

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Use of Message Bus Interface to Verify Lane Margining in PCIe

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Adaptive UVM AMOD Testbench for Configurable DSI IP

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SoC Verification Enablement Using HM Model

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Automatically Synthesizing Higher Level of Protocol Abstraction for Faster Debug and Deeper Insight Into Modern Digital Designs

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Low Power Validation on Emulation Using Portable Stimulus Standard

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Simplifying Hierarchical Low Power Designs Using Power Models in Intel Design

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Goal Driven Stimulus Solution Get Yourself Out of the Redundancy Trap

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Architecturally Scalable Testbench for Complex SoC

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Uncover: Functional Coverage Made Easy

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Automation of Waiver and Design Collateral generation for scalable IPs

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Automatic Generation of Infineon Microcontroller Product Configurations

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Hardware Implementation of Smallscale Parameterized Neural Network Inference Engine

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Scalable Multi-Domain Multi-Variant Reset Management in Complex Verification IPs

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Our Experience of Glitches at Clock Trees, CDC Paths and Reset Trees

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Exhaustive Reset Verification Enablement: Client PCIE Design Reset Verification Case Study

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A Pragmatic Approach Leveraging Portable Stimulus from Subsystem to SoC level and SoC Emulation

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Benefits of PSS Coverage at SOC and Its Limitations

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Designing A PSS Reuse Strategy

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Towards Early Validation of Firmware Using UVM Simulation Framework

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Unified Test Writing Framework for Pre and Post Silicon Verification

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Using Software Design Patterns in Testbench Development for a Multi-layer Protocol

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DV Methodology to Model Scalable/Reusable Component to Handle IO Delays/Noise/Crosstalk in Multilane DDR PHY IF

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Read More… from DV Methodology to Model Scalable/Reusable Component to Handle IO Delays/Noise/Crosstalk in Multilane DDR PHY IF

Challenges, Complexities and Advanced Verification Techniques in Stress Testing of Elastic Buffer in High Speed SERDES IPs

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Simulation Analog Fault Injection Flow for Mixed-Signal Designs

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Challenges of Formal Verification on Deep Learning Hardware Accelerator

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Read More… from Challenges of Formal Verification on Deep Learning Hardware Accelerator

Simulation Guided Formal Verification with “River Fishing” Techniques

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Formal verification of low-power RISC-V processors

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Profiling Virtual Prototypes: Simulation Performance Analysis & Optimization

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Framework for Creating Performance Model of AI Algorithms for Early Architecture Exploration

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Open Source Virtual Platforms for SW Prototyping on FPGA Based HW

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Functional-Coverage Sampling in UVM RAL Use of 2 Obscure Methods

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Leveraging IEEE 1800.2-2017 UVM for Improved RAL Modelling

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Enhanced LDPC Codec Verification in UVM

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Assisting Fault Injection Simulations for Functional Safety Sign-off using Formal

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Formal Assisted Fault Campaign for ISO26262 Certification

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High Frequency Response Tracking System Micro-architecture

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Formal for Adjacencies Expanding the Scope of Formal Verification

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Bringing DataPath Formal to Designers’ Footsteps

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Step-up your Register Access Verification

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Low Power Techniques in Emulation

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Simplifying Hierarchical Low Power Designs Using Power Models in Intel Design

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Goal Driven Stimulus Solution Get Yourself Out of the Redundancy Trap

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Read More… from Goal Driven Stimulus Solution Get Yourself Out of the Redundancy Trap

Uncover: Functional Coverage Made Easy

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Read More… from Uncover: Functional Coverage Made Easy

Automation of Waiver and Design Collateral Generation on Scalable IPs

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Automatic Generation of Infineon Microcontroller Product Configurations

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Small Scale Parameterized Inference Engine

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Scalable Multi-Domain, Multi-Variant Reset Management in Verification IPs

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Enabling Exhaustive Reset Verification Enablement: Client PCIE Design Reset Verification Case Study

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Read More… from Enabling Exhaustive Reset Verification Enablement: Client PCIE Design Reset Verification Case Study

A Pragmatic Approach Leveraging Portable Stimulus from Subsystem to SoC level and SoC Emulation

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Read More… from A Pragmatic Approach Leveraging Portable Stimulus from Subsystem to SoC level and SoC Emulation

Benefits of PSS coverage at SOC & its limitations

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Read More… from Benefits of PSS coverage at SOC & its limitations

Towards Early Validation of Firmware Using UVM Simulation Framework

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Read More… from Towards Early Validation of Firmware Using UVM Simulation Framework

Unified Test Writing Framework for Pre and Post Silicon Verification

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Read More… from Unified Test Writing Framework for Pre and Post Silicon Verification

Challenges, Complexities and Advanced Verification Techniques in Stress Testing of Elastic Buffer in High Speed SERDES IPs

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Read More… from Challenges, Complexities and Advanced Verification Techniques in Stress Testing of Elastic Buffer in High Speed SERDES IPs

Simulation Analog Fault Injection Flow for Mixed-Signal Designs

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Read More… from Simulation Analog Fault Injection Flow for Mixed-Signal Designs

Challenges of Formal Verification on Deep Learning Hardware Accelerator

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Read More… from Challenges of Formal Verification on Deep Learning Hardware Accelerator

Profiling Virtual Prototypes: Simulation Performance Analysis & Optimization

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Read More… from Profiling Virtual Prototypes: Simulation Performance Analysis & Optimization

Framework for Creating Performance Model of AI Algorithms for Early Architecture Exploration

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Read More… from Framework for Creating Performance Model of AI Algorithms for Early Architecture Exploration

Functional-Coverage Sampling in UVM RAL: Use of 2 Obscure Methods

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Read More… from Functional-Coverage Sampling in UVM RAL: Use of 2 Obscure Methods

Leveraging IEEE 1800.2-2017 UVM for Improved RAL Modelling

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Read More… from Leveraging IEEE 1800.2-2017 UVM for Improved RAL Modelling

Assisting Fault Injection Simulations for Functional Safety Sign-off using Formal

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Read More… from Assisting Fault Injection Simulations for Functional Safety Sign-off using Formal

High Frequency Response Tracking System micro-architecture

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Read More… from High Frequency Response Tracking System micro-architecture

Formal For Adjacencies Expanding the Scope of Formal Verification

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Read More… from Formal For Adjacencies Expanding the Scope of Formal Verification

Step-up your Register Access Verification

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Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication bridge

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Read More… from Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication bridge

Portable Stimulus Standard: The Promises and Pitfalls of Early Adoption

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Coherency Verification & Deadlock Detection Using Perspec/Portable Stimulus

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Smart Formal for Scalable Verification

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Connectivity and Beyond

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Taking RNM Model to the Next Level: Power-Aware Verification of Mixed-Signal Designs

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UVM and UPF: an application of UPF Information Model

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Read More… from UVM and UPF: an application of UPF Information Model

Test driving Portable Stimulus at AMD

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Product Life Cycle of Interconnect Bus:A Portable Stimulus Methodology for Performance Modeling, Design Verification, and Post-Silicon Validation

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Read More… from Product Life Cycle of Interconnect Bus:A Portable Stimulus Methodology for Performance Modeling, Design Verification, and Post-Silicon Validation

Unleashing Portable Stimulus Productivity with a Reuse Strategy

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Using Portable Stimulus to Verify an ARMv8 Sub-System SoC Integration

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Read More… from Using Portable Stimulus to Verify an ARMv8 Sub-System SoC Integration

FPGA-based Clock Domain Crossing Validation for Safety-Critical Designs

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Using Modal Analysis to Increase Clock Domain Crossing (CDC) Analysis Efficiency and Accuracy

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Read More… from Using Modal Analysis to Increase Clock Domain Crossing (CDC) Analysis Efficiency and Accuracy

A Systematic Take on Addressing Dynamic CDC Verification Challenges

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Simulation Acceleration with ZeBu to Speed IP and Platform Verification

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Read More… from Simulation Acceleration with ZeBu to Speed IP and Platform Verification

How to test the whole firmware/software when the RTL can’t fit the emulator

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High-Speed Interface IP Validation based on Virtual Emulation Platform

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Automation of Reusable Protocol-Agnostic Performance Analysis in UVM Environments

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Using Save/Restore is easy, Right?A User’s Perspective on Deploying Save/Restore

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Using Machine Learning in Register Automation and Verification

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Big Data in Verification: Making Your Engineers Smarter

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Read More… from Big Data in Verification: Making Your Engineers Smarter

Fun with UVM Sequences Coding and Debugging

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Read More… from Fun with UVM Sequences Coding and Debugging

Synchronicity: Bringing Order to the SystemVerilog/UVM Synchronizing Chaos

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Read More… from Synchronicity: Bringing Order to the SystemVerilog/UVM Synchronizing Chaos

UVM IEEE Shiny Object

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Translating and Adapting to the “real” world: SerDesMixed Signal Verification using UVM

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Novel Mixed Signal Verification Methodology Using Complex UDNs

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Formal Verification Bootcamp

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Fully Automated Functional Coverage Closure

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IEEE 1800.2 UVM – Changes Useful UVM Tricks & Techniques

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Read More… from IEEE 1800.2 UVM – Changes Useful UVM Tricks & Techniques

SystemC: Focusing on High Level Synthesis and Functional Coverage for SystemC

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Automating the formal verification sign-off flow of configurable digital IP’s

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A Coverage-Driven Formal Methodology for Verification Sign-off

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Read More… from A Coverage-Driven Formal Methodology for Verification Sign-off

Property-Driven Development of a RISC-V CPU

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Supply network connectivity: An imperative part in low power gate-level verification

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Read More… from Supply network connectivity: An imperative part in low power gate-level verification

Formal Bug Hunting with “River Fishing” Techniques

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Read More… from Formal Bug Hunting with “River Fishing” Techniques

Scalable, Re-usable UVM DMS AMS based Verification Methodology for Mixed-Signal SOCs

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Deep Learning for Engineers

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Tackling the Complexity Problem in Control and Datapath Designs with Formal Verification

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Practical Applications of the Portable Testing and Stimulus Standard (PSS)

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Read More… from Practical Applications of the Portable Testing and Stimulus Standard (PSS)

Next Gen System Design and Verification for Transportation

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Read More… from Next Gen System Design and Verification for Transportation

System-Level Security Verification Starts with the Hardware Root of Trust

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Read More… from System-Level Security Verification Starts with the Hardware Root of Trust

Simulation Runtime Optimization of Constrained Random Verification using Machine Learning Algorithms

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Read More… from Simulation Runtime Optimization of Constrained Random Verification using Machine Learning Algorithms

It’s Been 24 Hours –Should I Kill My Formal Run?

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Be a Sequence Pro to Avoid Bad Con Sequences

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Read More… from Be a Sequence Pro to Avoid Bad Con Sequences

OS aware IP Development Methodology

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Read More… from OS aware IP Development Methodology

Fully Hierarchical CDC Analysis Using Comprehensive CDC Meta-Database

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Read More… from Fully Hierarchical CDC Analysis Using Comprehensive CDC Meta-Database

Results Checking Strategies with Portable Stimulus

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Read More… from Results Checking Strategies with Portable Stimulus

Graphical Topology Info Structure for Constrained Random Verification in SoC/Subsystem Tests

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System level random verification: How it should be done

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Data-Driven Verification: Driving the next wave of productivity improvements

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Read More… from Data-Driven Verification: Driving the next wave of productivity improvements

Unified Test Writing Framework for Pre and Post Silicon Verification

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Read More… from Unified Test Writing Framework for Pre and Post Silicon Verification

Processing deliberate verification errors during regression

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Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon

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Read More… from Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon

Cadence vManager Platform and Virtuoso ADE Verifier Leading-edge technologies provide methodology for mixedsignal verification closure

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Read More… from Cadence vManager Platform and Virtuoso ADE Verifier Leading-edge technologies provide methodology for mixedsignal verification closure

Safety and Security Aware Pre-Silicon Hardware / Software Co-Development

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Revitalizing Automotive Safety Hard and Soft Error Approaches

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Be a Sequence Pro to Avoid Bad Con Sequences

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Read More… from Be a Sequence Pro to Avoid Bad Con Sequences

Customizing UVM Agent Supporting Multi-Layered & TDM Protocols

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Read More… from Customizing UVM Agent Supporting Multi-Layered & TDM Protocols

A Mixed Signal System Design Methodology in SystemC AMS for Automotive Audio Power Amplifiers

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Read More… from A Mixed Signal System Design Methodology in SystemC AMS for Automotive Audio Power Amplifiers

Covering the Last Mile in SoC-Level Deadlock Verification

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Read More… from Covering the Last Mile in SoC-Level Deadlock Verification

Portable Stimuli over UVM using portable stimuli in HW verification flow

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Read More… from Portable Stimuli over UVM using portable stimuli in HW verification flow

Designing a PSS Reuse Strategy

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Early Performance Verification of Embedded Inferencing Systems using open source SystemC NVIDIA MatchLib

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Read More… from Early Performance Verification of Embedded Inferencing Systems using open source SystemC NVIDIA MatchLib

Gathering Memory Hierarchy Statistics in QEMU

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Open Source Solution for RISC-V Verification

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Automate and Accelerate RISC-V Verification by Compositional Formal Methods

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5G / NR Explained From 3GPP 5G Standard Fundamentals To 5G Enabled Verticals

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Integrating Parallel SystemC Simulationinto Simics® Virtual Platform

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SystemC-to-Verilog Compiler: a productivity-focused tool for hardware design in cycle-accurate SystemC

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Pythonized SystemC A non-intrusive scripting approach

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RISC-V Compliance & Verification Techniques Processor Cores and Custom Extensions

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Read More… from RISC-V Compliance & Verification Techniques Processor Cores and Custom Extensions

A Generic Approach to Handling Sideband Signals

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Generic Testbench/Portable Stimulus/Promotability

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Advance your Design and Verification Flow Using IP XACT

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Addressing Asynchronous FIFO Verification Challenge

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Agile and dynamic functional coverage using SQL on the cloud

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Read More… from Agile and dynamic functional coverage using SQL on the cloud

Transaction‐Based Testing with OSVVM and the OSVVM Model Library

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Read More… from Transaction‐Based Testing with OSVVM and the OSVVM Model Library

Applying Design Patterns to Maximize Verification Reuse at Block, Subsystem and System on Chip Level

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Read More… from Applying Design Patterns to Maximize Verification Reuse at Block, Subsystem and System on Chip Level

Results Checking Strategies with Portable Stimulus

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Random Stimuli Models for UVM Registers

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Building Smart SoCs Using Virtual Prototyping for the Design and SoC Integration of Deep Learning Accelerators

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Read More… from Building Smart SoCs Using Virtual Prototyping for the Design and SoC Integration of Deep Learning Accelerators

Methodology for checking UVM VIPs

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Next Gen System Design and Verification for Transportation

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Read More… from Next Gen System Design and Verification for Transportation

Leveraging hardware emulation to accelerate SoCverification in multi-physics automotive simulation environment via the Functional Mock-up Interface

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Read More… from Leveraging hardware emulation to accelerate SoCverification in multi-physics automotive simulation environment via the Functional Mock-up Interface

Developing Dynamic Resource Management System in SoCEmulation

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A Novel Performance Evaluation Methodology using Virtual Prototyping and Emulation

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Read More… from A Novel Performance Evaluation Methodology using Virtual Prototyping and Emulation

RISC-V Integrity: A Guide for Developers and Integrators

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Read More… from RISC-V Integrity: A Guide for Developers and Integrators

SysML based Architecture Definition and Platform Generation Flow

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Read More… from SysML based Architecture Definition and Platform Generation Flow

Development of Flexi Performance Analysis Platform for Multi–SoC Networking Systems

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Read More… from Development of Flexi Performance Analysis Platform for Multi–SoC Networking Systems

Unified Functional Safety Verification Platform for ISO 26262 Compliant Automotive

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Read More… from Unified Functional Safety Verification Platform for ISO 26262 Compliant Automotive

QED & Symbolic QED Pre-silicon Verification, Post-silicon Validation, Industrial Results

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Read More… from QED & Symbolic QED Pre-silicon Verification, Post-silicon Validation, Industrial Results

UVM based Hardware/Software Co-Verification of a HW Coprocessor using Host Execution Techniques

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Semi-formal Reformulation of Requirements for Formal Property Verification

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Retrascope: Open-Source Model Checkerfor HDL Descriptions

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Read More… from Retrascope: Open-Source Model Checkerfor HDL Descriptions

ISO 26262 Fault Analysis in Safety Mechanisms Considering the impact of residual and latent faults in hardware safety mechanisms

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Read More… from ISO 26262 Fault Analysis in Safety Mechanisms Considering the impact of residual and latent faults in hardware safety mechanisms

UVM SystemC Functional coverage & constrained randomization

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Read More… from UVM SystemC Functional coverage & constrained randomization

Overcoming Challenges in SoC RTL Verification of USB Subsystem

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Read More… from Overcoming Challenges in SoC RTL Verification of USB Subsystem

Enabling Digital Mixed-Signal Verification of Loading Effects in Power Regulation using SystemVerilog User-Defined Nettype

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Read More… from Enabling Digital Mixed-Signal Verification of Loading Effects in Power Regulation using SystemVerilog User-Defined Nettype

Novel Approach to ASIC Prototyping

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Read More… from Novel Approach to ASIC Prototyping

Emulation Testbench Optimizations for better Hardware Software Co-Validation

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Read More… from Emulation Testbench Optimizations for better Hardware Software Co-Validation

How to Create Reusable Portable Testing and Stimulus Standard (PSS) Verification IP

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Read More… from How to Create Reusable Portable Testing and Stimulus Standard (PSS) Verification IP

Utilizing Technology Implementation Data in blended hardware/software power optimization.

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Read More… from Utilizing Technology Implementation Data in blended hardware/software power optimization.

System Model – A Testbench Library Component Aided for Emulating User Interaction

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Read More… from System Model – A Testbench Library Component Aided for Emulating User Interaction

Moving beyond Assertions: An Innovative approach to Low-Power Checking using UPF Tcl Apps

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Read More… from Moving beyond Assertions: An Innovative approach to Low-Power Checking using UPF Tcl Apps

Clock Domain Crossing Verification in Transistor-level Design

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Read More… from Clock Domain Crossing Verification in Transistor-level Design

Multiplier-Adder-Converter Linear Piecewise Approximation for Low Power Graphics Applications

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Read More… from Multiplier-Adder-Converter Linear Piecewise Approximation for Low Power Graphics Applications

Verification of Accelerators in System Context

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Read More… from Verification of Accelerators in System Context

Introducing your team to an IDE

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Read More… from Introducing your team to an IDE

Using UPF Information Model APIs to write re-usable Low Power Testbenches and customized coverage models for Low Power

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Read More… from Using UPF Information Model APIs to write re-usable Low Power Testbenches and customized coverage models for Low Power

In pursuit of Faster Register Abstract Layer (RAL) Model

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Read More… from In pursuit of Faster Register Abstract Layer (RAL) Model

Verification Reuse for a Non-Transaction Based Design across Multiple Platforms

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Read More… from Verification Reuse for a Non-Transaction Based Design across Multiple Platforms

Conquer the Graphics Legacy: Develop the Customized UVM VIP Embedded a Cycle-based C++ Reference Model

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Read More… from Conquer the Graphics Legacy: Develop the Customized UVM VIP Embedded a Cycle-based C++ Reference Model

Timing Coverage: An Approach to Analyzing Performance Holes

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Read More… from Timing Coverage: An Approach to Analyzing Performance Holes

Interfacing Python with a Systemverilog Test Bench

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Read More… from Interfacing Python with a Systemverilog Test Bench

SystemC FMU for Verification of Advanced Driver Assistance Systems

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Read More… from SystemC FMU for Verification of Advanced Driver Assistance Systems

Predicting Bad Commits

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Dynamic Control Over UVM Register Backdoor Hierarchy

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Read More… from Dynamic Control Over UVM Register Backdoor Hierarchy

An efficient analog fault-injection flow harnessing the power of abstraction

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Read More… from An efficient analog fault-injection flow harnessing the power of abstraction

Transaction Recording Anywhere Anytime

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Read More… from Transaction Recording Anywhere Anytime

Flexible Checker: A one-stop shop for all your checkers and a methodology for elastic scoreboarding

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Read More… from Flexible Checker: A one-stop shop for all your checkers and a methodology for elastic scoreboarding

An Enhanced Stimulus and Checking Mechanism on Cache Verification

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Read More… from An Enhanced Stimulus and Checking Mechanism on Cache Verification

SystemVerilog Format of Portable Stimulus

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Read More… from SystemVerilog Format of Portable Stimulus

Efficient hierarchical low power verification of custom designs using static and dynamic techniques

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Read More… from Efficient hierarchical low power verification of custom designs using static and dynamic techniques

Supply network connectivity: An imperative part in low power gate-level verification

[…]

Read More… from Supply network connectivity: An imperative part in low power gate-level verification

UVM and UPF: an application of UPF Information Model

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Read More… from UVM and UPF: an application of UPF Information Model

Taking Real-Value Modeling to the next level: Power-aware verification of mixed-signal designs

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Read More… from Taking Real-Value Modeling to the next level: Power-aware verification of mixed-signal designs

Connectivity and Beyond

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Read More… from Connectivity and Beyond

Formal Bug Hunting with “River Fishing” Techniques

[…]

Read More… from Formal Bug Hunting with “River Fishing” Techniques

Smart Formal for Scalable Verification

[…]

Read More… from Smart Formal for Scalable Verification

Coherency Verification & Deadlock Detection Using Perspec/Portable Stimulus

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PSS: The Promises and Pitfalls of Early Adoption

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Read More… from PSS: The Promises and Pitfalls of Early Adoption

Portable Stimulus Driven SystemVerilog/UVM verification environment for the verification of a high-capacity Ethernet communication bridge

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FPGA-based Clock Domain Crossing Validation for Safety-Critical Designs

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Unleashing Portable Stimulus Productivity with a PSS Reuse Strategy

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Results Checking Strategies with Portable Stimulus

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Product Life Cycle of an Interconnect Bus: A Portable Stimulus Methodology for Performance Modeling, Design Verification, and Post-Silicon Validation

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Test-driving PSS for System Low-Power Validation

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Yikes! Why is My SystemVerilog Still So Slooooow?

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Read More… from Yikes! Why is My SystemVerilog Still So Slooooow?

OS-aware IP Development Methodology

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High-Speed Interface IP Validation based on Virtual Emulation Platform

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How to test the whole firmware/software when the RTL can’t fit the emulator

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NVMe Development and Debug for a 16 x Multicore System

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Fully Hierarchical CDC Analysis Using Comprehensive CDC Meta Database

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A Systematic Take on Addressing Dynamic CDC Verification Challenges

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Using Modal Analysis to Increase Clock Domain Crossing (CDC) Analysis Efficiency and Accuracy

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Novel Mixed Signal Verification Methodology using complex UDNs

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Translating and Adapting to the “real” world: SerDes Mixed Signal Verification using UVM

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UVM IEEE Shiny Object

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Synchronicity: Bringing Order to SystemVerilog/UVM Synchronizing Chaos

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Fun with UVM Sequences – Coding and Debugging

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Big Data in Verification: Making Your Engineers Smarter

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Simulation Runtime Optimization of Constrained Random Verification using Machine Learning Algorithms

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Using Machine Learning in Register Automation and Verification

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Using Save/Restore is Easy, Right? A User’s Perspective on Deploying Save/Restore in a Mature Verification Methodology

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Automation of Reusable Protocol-Agnostic Performance Analysis in UVM Environments

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Property-Driven Development of a RISC-V CPU

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A Coverage-Driven Formal Methodology for Verification Sign-off

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Automating the formal verification sign-off flow of configurable digital IP’s

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Graphical Topology Info Structure for Constrained Random Verification in SoC/Subsystem Tests

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System-Level Random Verification: How it should be done

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Fully Automated Functional Coverage Closure

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SCALABLE, RE-USABLE UVM DMS AMS BASED VERIFICATION METHODOLOGY FOR MIXED-SIGNAL SOCS

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