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Power Dynamics: Shaping the future of the data centric era and the role of AI […] Read More… from Power Dynamics: Shaping the future of the data centric era and the role of AI
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AI Agents for Design and Verification Opportunities and Challenges […] Read More… from AI Agents for Design and Verification Opportunities and Challenges
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Breakthrough in CDC-RDC Verification Defining a Standard for Interoperable Abstract Model […] Read More… from Breakthrough in CDC-RDC Verification Defining a Standard for Interoperable Abstract Model
Effective Methodologies to Accelerate Security Verificat ion […] Read More… from Effective Methodologies to Accelerate Security Verificat ion
SIGMA: Sign-off Intelligence with GenAI for Methodical Assurance in Formal Verification […] Read More… from SIGMA: Sign-off Intelligence with GenAI for Methodical Assurance in Formal Verification
A novel ML-Driven Simulation Log Debugger […] Read More… from A novel ML-Driven Simulation Log Debugger
Real-Time Performance Insights: AI-Accelerated Trace-Driven Analysis for Multi-GPU Pre-Silicon Verification Environments […] Read More… from Real-Time Performance Insights: AI-Accelerated Trace-Driven Analysis for Multi-GPU Pre-Silicon Verification Environments
Early FMEDA at RTL for Functional Safety: Correlating RTL Metrics to GLS for Accurate Architectural Analysis […] Read More… from Early FMEDA at RTL for Functional Safety: Correlating RTL Metrics to GLS for Accurate Architectural Analysis
Closing the safety Verification Loop, FMEDA-Driven Fault Simulation and Advanced Debug for Efficient Fault Classification […] Read More… from Closing the safety Verification Loop, FMEDA-Driven Fault Simulation and Advanced Debug for Efficient Fault Classification
Accelerating Bare Metal Driver Development with Linux Drivers and System Verilog DPI-C […] Read More… from Accelerating Bare Metal Driver Development with Linux Drivers and System Verilog DPI-C
Automate the Pain Away: HW/SW Interface Design Methodology […] Read More… from Automate the Pain Away: HW/SW Interface Design Methodology
Properly Introducing Python to your UVM Testbench […] Read More… from Properly Introducing Python to your UVM Testbench
Passive Token Accounting for Cost Aware LLM Assistance In continuous SoC verification workflows […] Read More… from Passive Token Accounting for Cost Aware LLM Assistance In continuous SoC verification workflows
DUET: Agentic Design Understanding via Experimentation and Testing […] Read More… from DUET: Agentic Design Understanding via Experimentation and Testing
A New Methodology for Formal Equivalence Checking of Sorting Algorithms […] Read More… from A New Methodology for Formal Equivalence Checking of Sorting Algorithms
Automated Root-Cause Analysis of GPU Pipeline Corruptions in Graphics and Compute Workloads […] Read More… from Automated Root-Cause Analysis of GPU Pipeline Corruptions in Graphics and Compute Workloads
Streamlining RAL-based Cross-Coverage and Sequence Coverage through Automation […] Read More… from Streamlining RAL-based Cross-Coverage and Sequence Coverage through Automation
Threat Modeling for SoC Security Design: IEEE P3164 SA-EDI Standardization […] Read More… from Threat Modeling for SoC Security Design: IEEE P3164 SA-EDI Standardization
Etabot: Multi-Agent Verification Management with Cha t-Accessible Midpoint Metrics and Finish-Date Forecasts […] Read More… from Etabot: Multi-Agent Verification Management with Cha t-Accessible Midpoint Metrics and Finish-Date Forecasts
Beyond Heuristics: AI/ML Driven Verification for Design Sign-off […] Read More… from Beyond Heuristics: AI/ML Driven Verification for Design Sign-off
AI Driven Advanced Debugging in SoC Design Verification […] Read More… from AI Driven Advanced Debugging in SoC Design Verification
Exploring UVM TLM2 based Sequence, Sequencer and Driver in UVM […] Read More… from Exploring UVM TLM2 based Sequence, Sequencer and Driver in UVM
Optimizing Functional Fault Grading Flow for Memory Designs […] Read More… from Optimizing Functional Fault Grading Flow for Memory Designs
From Specification to Closure: A Semi-Automated Coverage Driven Verification Methodology for Cache Coherent Home Nodes […] Read More… from From Specification to Closure: A Semi-Automated Coverage Driven Verification Methodology for Cache Coherent Home Nodes
Scalable Formal Verification Framework for NoC System Address Map Configurations […] Read More… from Scalable Formal Verification Framework for NoC System Address Map Configurations
A GPT-2 Tabular Transformer Model for Automated DRAM Verification […] Read More… from A GPT-2 Tabular Transformer Model for Automated DRAM Verification
AI-Driven Adaptive Emulation for Accelerated Pre-Silicon Debug: High-Fidelity Silicon Replay […] Read More… from AI-Driven Adaptive Emulation for Accelerated Pre-Silicon Debug: High-Fidelity Silicon Replay
An AI Agent Framework with Elasticsearch for Scalable Post-Silicon Debug Automation […] Read More… from An AI Agent Framework with Elasticsearch for Scalable Post-Silicon Debug Automation
Unified AI-Driven Verification: Combining Spec-RAG, Memory Networks, and Generative AI […] Read More… from Unified AI-Driven Verification: Combining Spec-RAG, Memory Networks, and Generative AI
Early Deep Bug Discovery via Re-run Acceleration and Para llel Mu lti-depth BMC Exploration […] Read More… from Early Deep Bug Discovery via Re-run Acceleration and Para llel Mu lti-depth BMC Exploration
A Platform-Based Approach to Reduce Verification Turn-Around Time in Memory Designs […] Read More… from A Platform-Based Approach to Reduce Verification Turn-Around Time in Memory Designs
IP-XACT Demystified: An In-Depth Training on the IEEE 1685-2022 IP-XACT Standard […] Read More… from IP-XACT Demystified: An In-Depth Training on the IEEE 1685-2022 IP-XACT Standard
Scaling Formal Verification of Network-On Chip Using Path Decomposition […] Read More… from Scaling Formal Verification of Network-On Chip Using Path Decomposition
Enhancing Automotive ECU Design with Digital Twin Simulat ion: Comparative Study of Virtual Platform, FPGA Prototyping, and Edge Device Configurations […] Read More… from Enhancing Automotive ECU Design with Digital Twin Simulat ion: Comparative Study of Virtual Platform, FPGA Prototyping, and Edge Device Configurations
A3-Tiered Agentic AI Framework for Verificat ion Regression […] Read More… from A3-Tiered Agentic AI Framework for Verificat ion Regression
A Novel Fast Regression: An AI/ML Driven Automated Sanity Regression Flow […] Read More… from A Novel Fast Regression: An AI/ML Driven Automated Sanity Regression Flow
Security Verification in Practice Lessons from Pre-Silicon Analysis of SoC Subsystems […] Read More… from Security Verification in Practice Lessons from Pre-Silicon Analysis of SoC Subsystems
Breaking the wait: Real-Time Post-Processing for Data Integrity Verification in SerDes Systems […] Read More… from Breaking the wait: Real-Time Post-Processing for Data Integrity Verification in SerDes Systems
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Harnessing Volatility: Innovative Strategies for Register Synchronization in UVM RAL […] Read More… from Harnessing Volatility: Innovative Strategies for Register Synchronization in UVM RAL
ConnChecker: Automated Root-Cause Analysis for Connectivity Check via Graph […] Read More… from ConnChecker: Automated Root-Cause Analysis for Connectivity Check via Graph
A Modern Debug Paradigm Using Python Based Visualization […] Read More… from A Modern Debug Paradigm Using Python Based Visualization
Database Driven RTL Simulation: Fighting Billion-Gate Verification Bottlenecks […] Read More… from Database Driven RTL Simulation: Fighting Billion-Gate Verification Bottlenecks
FVDebug: LLM-Driven Formal Verification Debugging Assistant […] Read More… from FVDebug: LLM-Driven Formal Verification Debugging Assistant
IP-XACT Based PSS Modeling For Shift-Left SoC Verification […] Read More… from IP-XACT Based PSS Modeling For Shift-Left SoC Verification
GLS Shift Over Through Timing Constraint Verification: A Comprehensive Framework […] Read More… from GLS Shift Over Through Timing Constraint Verification: A Comprehensive Framework
RISC-V Reuse Made Easy by Interface Generation and Integration Automation […] Read More… from RISC-V Reuse Made Easy by Interface Generation and Integration Automation
AI Agent-based Error Resolution System for SoC RTL Verification […] Read More… from AI Agent-based Error Resolution System for SoC RTL Verification
An Approach to Create Scalable Power Management Verification Environment […] Read More… from An Approach to Create Scalable Power Management Verification Environment
plusargs++: Make Plusargs Great … Like They Never Were Before […] Read More… from plusargs++: Make Plusargs Great … Like They Never Were Before
RTL Performance Isn’t Just a Number – It’s a Story […] Read More… from RTL Performance Isn’t Just a Number – It’s a Story
An Efficient Random Instruction Sequence Generation for Verification of Domain Specific Architecture Processor […] Read More… from An Efficient Random Instruction Sequence Generation for Verification of Domain Specific Architecture Processor
Towards Self-Adaptive SoC Design Verification:KG-Enhanced Generative AI, RL and Backpropagation Debugging […] Read More… from Towards Self-Adaptive SoC Design Verification:KG-Enhanced Generative AI, RL and Backpropagation Debugging
There and Back Again: Simulation-to-Silicon Scenario Reuse with PSS […] Read More… from There and Back Again: Simulation-to-Silicon Scenario Reuse with PSS
Multi-Agent Orchestration for Autonomous Regression Management […] Read More… from Multi-Agent Orchestration for Autonomous Regression Management
Breaking Down Failures: Elementary Subpart Granularity Being Foundation of Safety Analysis & Verification […] Read More… from Breaking Down Failures: Elementary Subpart Granularity Being Foundation of Safety Analysis & Verification
Taming Configuration Complexity: A UVM Based Approach To IP Verification […] Read More… from Taming Configuration Complexity: A UVM Based Approach To IP Verification
Application of Metamorphic Testing to Mixed Signal Systems with Behavioral Models […] Read More… from Application of Metamorphic Testing to Mixed Signal Systems with Behavioral Models
SIGMA: Sign-off Intelligence with GenAI for Methodical Assurance in Formal Verification […] Read More… from SIGMA: Sign-off Intelligence with GenAI for Methodical Assurance in Formal Verification
Effective Methodologies to Accelerate Security Verification […] Read More… from Effective Methodologies to Accelerate Security Verification
A novel ML-Driven Simulation Log Debugger […] Read More… from A novel ML-Driven Simulation Log Debugger
Real-Time Performance Insights: AI-Accelerated Trace-Driven Analysis for Multi-GPU Pre-Silicon Verification Environments […] Read More… from Real-Time Performance Insights: AI-Accelerated Trace-Driven Analysis for Multi-GPU Pre-Silicon Verification Environments
Early FMEDA at RTL for Functional Safety: Correlating RTL Metrics to GLS for Accurate Architectural Analysis […] Read More… from Early FMEDA at RTL for Functional Safety: Correlating RTL Metrics to GLS for Accurate Architectural Analysis
Closing the safety Verification Loop, FMEDA Driven Fault Simulation and Advanced Debug for Efficient Fault Classification […] Read More… from Closing the safety Verification Loop, FMEDA Driven Fault Simulation and Advanced Debug for Efficient Fault Classification
Accelerating Bare Metal Driver Development with Linux Drivers and System Verilog DPI-C. […] Read More… from Accelerating Bare Metal Driver Development with Linux Drivers and System Verilog DPI-C.
IP-XACT Based PSS Modeling For Shift-Left SoC Verification […] Read More… from IP-XACT Based PSS Modeling For Shift-Left SoC Verification
Properly Introducing Python To Your UVM Testbench […] Read More… from Properly Introducing Python To Your UVM Testbench
GLS Shift Over Through Timing Constraint Verification: A Comprehensive Framework […] Read More… from GLS Shift Over Through Timing Constraint Verification: A Comprehensive Framework
LFSR: Beyond the Sequential – Unlocking the Potential of Immediate Nth Cycle Output […] Read More… from LFSR: Beyond the Sequential – Unlocking the Potential of Immediate Nth Cycle Output
Passive Token Accounting For Cost-Aware LLM Assistance In Continuous SoC Verification Workflows […] Read More… from Passive Token Accounting For Cost-Aware LLM Assistance In Continuous SoC Verification Workflows
DUET: Agentic Design Understanding via Experimentation and Testing […] Read More… from DUET: Agentic Design Understanding via Experimentation and Testing
A New Methodology for Formal Equivalence Checking of Sorting Algorithms […] Read More… from A New Methodology for Formal Equivalence Checking of Sorting Algorithms
Automated Root-Cause Analysis of GPU Pipeline Corruptions in Graphics and Compute Workloads […] Read More… from Automated Root-Cause Analysis of GPU Pipeline Corruptions in Graphics and Compute Workloads
Streamlining RAL-based Cross-Coverage and Sequence Coverage through Automation […] Read More… from Streamlining RAL-based Cross-Coverage and Sequence Coverage through Automation
RISC-V Reuse Made Easy by Interface Generation and Integration Automation […] Read More… from RISC-V Reuse Made Easy by Interface Generation and Integration Automation
Threat Modeling for SoC Security Design: IEEE P3164 SA-EDI Standardization […] Read More… from Threat Modeling for SoC Security Design: IEEE P3164 SA-EDI Standardization
Etabot: Multi‑Agent Verification Management with Chat‑Accessible Midpoint Metrics and Finish-Date Forecasts […] Read More… from Etabot: Multi‑Agent Verification Management with Chat‑Accessible Midpoint Metrics and Finish-Date Forecasts
Beyond Heuristics: AI/ML Driven Verification for Design Sign-off […] Read More… from Beyond Heuristics: AI/ML Driven Verification for Design Sign-off
AI Driven Advanced Debugging in SoC Design Verification […] Read More… from AI Driven Advanced Debugging in SoC Design Verification
AI Agent-based Error Resolution System for SoC RTL Verification […] Read More… from AI Agent-based Error Resolution System for SoC RTL Verification
Optimizing Functional Fault Grading Flow for Memory Designs […] Read More… from Optimizing Functional Fault Grading Flow for Memory Designs
An Approach to Create Scalable Power Management Verification Environment […] Read More… from An Approach to Create Scalable Power Management Verification Environment
Exploring UVM TLM2 based Sequence, Sequencer and Driver in UVM […] Read More… from Exploring UVM TLM2 based Sequence, Sequencer and Driver in UVM
From Specification to Closure: A Semi-Automated Coverage-Driven Verification Methodology for Cache Coherent Home Nodes […] Read More… from From Specification to Closure: A Semi-Automated Coverage-Driven Verification Methodology for Cache Coherent Home Nodes
Scalable Formal Verification Framework for NoC System Address Map Configurations […] Read More… from Scalable Formal Verification Framework for NoC System Address Map Configurations
plusargs++: Make Plusargs Great … Like They Never Were Before […] Read More… from plusargs++: Make Plusargs Great … Like They Never Were Before
A GPT-2 Tabular Transformer Model for Automated DRAM Verification […] Read More… from A GPT-2 Tabular Transformer Model for Automated DRAM Verification
RTL Performance Isn’t Just a Number – It’s a Story […] Read More… from RTL Performance Isn’t Just a Number – It’s a Story
AI-Driven Adaptive Emulation for Accelerated Pre-Silicon Debug: High-Fidelity Silicon Replay […] Read More… from AI-Driven Adaptive Emulation for Accelerated Pre-Silicon Debug: High-Fidelity Silicon Replay
An AI Agent Framework with Elasticsearch for Scalable Post-Silicon Debug Automation […] Read More… from An AI Agent Framework with Elasticsearch for Scalable Post-Silicon Debug Automation
An Efficient Random Instruction Sequence Generation for Verification of Domain Specific Architecture Processor […] Read More… from An Efficient Random Instruction Sequence Generation for Verification of Domain Specific Architecture Processor
Unified AI-Driven Verification: Combining Spec-RAG, Memory Networks, and Generative AI […] Read More… from Unified AI-Driven Verification: Combining Spec-RAG, Memory Networks, and Generative AI
Early Deep Bug Discovery via Re-run Acceleration and Parallel Multi-Depth Bounded Model Checking (BMC) Exploration […] Read More… from Early Deep Bug Discovery via Re-run Acceleration and Parallel Multi-Depth Bounded Model Checking (BMC) Exploration
Towards Self-Adaptive SoC Design Verification: KG-Enhanced Generative AI, RL and Backpropagation Debugging […] Read More… from Towards Self-Adaptive SoC Design Verification: KG-Enhanced Generative AI, RL and Backpropagation Debugging
A Platform-Based Approach to Reduce Verification Turn-Around Time in Memory Designs […] Read More… from A Platform-Based Approach to Reduce Verification Turn-Around Time in Memory Designs
There and Back Again: Simulation-to-Silicon Scenario Reuse with PSS […] Read More… from There and Back Again: Simulation-to-Silicon Scenario Reuse with PSS
Scaling Formal Verification of Network On Chip Using Path Decomposition […] Read More… from Scaling Formal Verification of Network On Chip Using Path Decomposition
Enhancing Automotive ECU Design with Digital Twin Simulation: Comparative Study of Virtual Platform, FPGA Prototyping, and Edge Device Configurations […] Read More… from Enhancing Automotive ECU Design with Digital Twin Simulation: Comparative Study of Virtual Platform, FPGA Prototyping, and Edge Device Configurations
A 3-tiered agentic AI Framework for Verification Regression […] Read More… from A 3-tiered agentic AI Framework for Verification Regression
Multi-Agent Orchestration for Autonomous Regression Management […] Read More… from Multi-Agent Orchestration for Autonomous Regression Management
A Novel Fast Regression: An AI/ML Driven Automated Sanity Regression Flow […] Read More… from A Novel Fast Regression: An AI/ML Driven Automated Sanity Regression Flow
Security Verification in Practice: Lessons from Pre-Silicon Analysis of SoC Subsystems […] Read More… from Security Verification in Practice: Lessons from Pre-Silicon Analysis of SoC Subsystems
Breaking the Wait: Customizable, Real-Time Post-Processing for Data Integrity Verification in SerDes Systems […] Read More… from Breaking the Wait: Customizable, Real-Time Post-Processing for Data Integrity Verification in SerDes Systems
Breaking Down Failures: Elementary Subpart Granularity Being Foundation of Safety Analysis & Verification […] Read More… from Breaking Down Failures: Elementary Subpart Granularity Being Foundation of Safety Analysis & Verification
Integrating RTL design and UVM Testbench with Hyperledger Blockchain and Machine Learning for better efficiency and optimisation. […] Read More… from Integrating RTL design and UVM Testbench with Hyperledger Blockchain and Machine Learning for better efficiency and optimisation.
Taming Configuration Complexity: A UVM-Based Approach To IP Verification […] Read More… from Taming Configuration Complexity: A UVM-Based Approach To IP Verification
Harnessing Volatility: Innovative Strategies for Register Synchronization in UVM RAL […] Read More… from Harnessing Volatility: Innovative Strategies for Register Synchronization in UVM RAL
ConnChecker: Automated Root-Cause Analysis for Formal Connectivity Check via Graph […] Read More… from ConnChecker: Automated Root-Cause Analysis for Formal Connectivity Check via Graph
FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures […] Read More… from FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures
Database Driven RTL Simulation: Fighting Billion-Gate Verification Bottlenecks […] Read More… from Database Driven RTL Simulation: Fighting Billion-Gate Verification Bottlenecks
Application of Metamorphic Testing to Mixed Signal Systems with Behavioral Models […] Read More… from Application of Metamorphic Testing to Mixed Signal Systems with Behavioral Models
A Modern Debug Paradigm: Python Visualization for DDR Memory Controller’s Performance Analysis […] Read More… from A Modern Debug Paradigm: Python Visualization for DDR Memory Controller’s Performance Analysis
