Sanity Test Case Selection by Machine Learning Approach […] Read More… from Sanity Test Case Selection by Machine Learning Approach
Modernizing the Hardware / Software Interface – Life beyond spreadsheets, how to bring your SoC register design into the 21st Century […] Read More… from Modernizing the Hardware / Software Interface – Life beyond spreadsheets, how to bring your SoC register design into the 21st Century
How Agentic AI is Reinventing Chip Design and Verification […] Read More… from How Agentic AI is Reinventing Chip Design and Verification
Taming the Waveform Tsunami: Agentic AI for Smarter Debugging […] Read More… from Taming the Waveform Tsunami: Agentic AI for Smarter Debugging
UPF Centric Agentic Tool for UPVM frameworks Seamessly Integrated to Low Power ASICs […] Read More… from UPF Centric Agentic Tool for UPVM frameworks Seamessly Integrated to Low Power ASICs
Secure Multi-CPU Memory Access in PCIe via Tokenized Address Space Management […] Read More… from Secure Multi-CPU Memory Access in PCIe via Tokenized Address Space Management
Automatically Fix RTL Lint Violations with GenAI […] Read More… from Automatically Fix RTL Lint Violations with GenAI
EP-Ready Hardware-Assisted-Verification Platforms […] Read More… from EP-Ready Hardware-Assisted-Verification Platforms
Harnessing AI/ML for Superior Regression Management – Boost Verification Efficiency […] Read More… from Harnessing AI/ML for Superior Regression Management – Boost Verification Efficiency
Accelerate Verification, Streamline Challenges: A Comprehensive HBM Model Solution […] Read More… from Accelerate Verification, Streamline Challenges: A Comprehensive HBM Model Solution
A Video Entropy Coder Design and Verification Using HLS and HLV […] Read More… from A Video Entropy Coder Design and Verification Using HLS and HLV
Efficient Debug Strategies for PCIe Gen6 Verification Using Verification IP […] Read More… from Efficient Debug Strategies for PCIe Gen6 Verification Using Verification IP
Debugging RTL with Transactions – Small, simple changes enabling higher level understanding […] Read More… from Debugging RTL with Transactions – Small, simple changes enabling higher level understanding
Formal-driven assurance of RISC-V Cores with AI-Ready FPUs […] Read More… from Formal-driven assurance of RISC-V Cores with AI-Ready FPUs
Dynamic Switching Performance of GaN HEMTs in Boost Converter Topology Using Double Pulse Test (DPT) with Parasitic-Induced Effects […] Read More… from Dynamic Switching Performance of GaN HEMTs in Boost Converter Topology Using Double Pulse Test (DPT) with Parasitic-Induced Effects
Fast IP/SoC Test Generation with SystemVIPs and Test Suite Synthesis […] Read More… from Fast IP/SoC Test Generation with SystemVIPs and Test Suite Synthesis
Taming Operational Power in Early Design Stage […] Read More… from Taming Operational Power in Early Design Stage
Nailing Down the Debug Complexities of Complex Device Inter-Connect’s Signal Pattern […] Read More… from Nailing Down the Debug Complexities of Complex Device Inter-Connect’s Signal Pattern
Session 3.5: Boost SoC Development Efficiency with Arteris SoC Integration Automation Software – Automate Design Flow and Register Management […] Read More… from Session 3.5: Boost SoC Development Efficiency with Arteris SoC Integration Automation Software – Automate Design Flow and Register Management
Session 3.1: AutoDV: Boost SoC Verification by Automatic Construction […] Read More… from Session 3.1: AutoDV: Boost SoC Verification by Automatic Construction
Session 2.8: A Comprehensive Data-Driven Function Verification Process […] Read More… from Session 2.8: A Comprehensive Data-Driven Function Verification Process
Session 2.7: Better Late Than Never – Collecting Coverage From Ones and Zeroes […] Read More… from Session 2.7: Better Late Than Never – Collecting Coverage From Ones and Zeroes
Session 2.3: Integrated verification ecosystem for regression management, coverage convergence, and debug automation […] Read More… from Session 2.3: Integrated verification ecosystem for regression management, coverage convergence, and debug automation
Session 2.2: Trojan Horse Detection for RISC-V Cores Using Cross-Auditing […] Read More… from Session 2.2: Trojan Horse Detection for RISC-V Cores Using Cross-Auditing
Session 2.1: The ASIC Renaissance – A glance into the future SoC enablement […] Read More… from Session 2.1: The ASIC Renaissance – A glance into the future SoC enablement
Session 1.8: Adopts ISA-Formal On High-End Out-Of-Order Execute RISC-V Cores […] Read More… from Session 1.8: Adopts ISA-Formal On High-End Out-Of-Order Execute RISC-V Cores
Session 1.7: Left-shifting Testbench Development Using Environment Inversion in UVM […] Read More… from Session 1.7: Left-shifting Testbench Development Using Environment Inversion in UVM
Session 1.6: Verifying Configurable AndesCore Processors by Using Portable Testing and Stimulus Standard (PSS) […] Read More… from Session 1.6: Verifying Configurable AndesCore Processors by Using Portable Testing and Stimulus Standard (PSS)
Session 1.5: Exploring Token-Based Strategies to Enhance Data Security and Memory Management in PCIe Devices […] Read More… from Session 1.5: Exploring Token-Based Strategies to Enhance Data Security and Memory Management in PCIe Devices
Session 1.3: Solving Memory Configurations Challenge with SVRAND Verification Flow […] Read More… from Session 1.3: Solving Memory Configurations Challenge with SVRAND Verification Flow
Session 1.2: Improving UVM test benches using UVM Run time phases […] Read More… from Session 1.2: Improving UVM test benches using UVM Run time phases
Keynote 3: Empowering Innovation in Logic Verification: Harnessing Collective Wisdom Across Tools, Processes, and People […] Read More… from Keynote 3: Empowering Innovation in Logic Verification: Harnessing Collective Wisdom Across Tools, Processes, and People
Model-Based Design The Top-Level System Design Method […] Read More… from Model-Based Design The Top-Level System Design Method
A Novel Approach to Accelerate Latency of Assertion Simulation […] Read More… from A Novel Approach to Accelerate Latency of Assertion Simulation
Formal Sign-off Methodology for IP Blocks […] Read More… from Formal Sign-off Methodology for IP Blocks
Verification Challenges & Solutions of 10BaseT1s Automotive Ethernet PHY […] Read More… from Verification Challenges & Solutions of 10BaseT1s Automotive Ethernet PHY
Reducing the simulation life cycle time using Artificial Intelligence and Machine learning techniques on Big Data dataset […] Read More… from Reducing the simulation life cycle time using Artificial Intelligence and Machine learning techniques on Big Data dataset
Design and Verification of the PLL using the new DCO and Its Applications to Built-In Speed Grading of Arithmetic Circuits […] Read More… from Design and Verification of the PLL using the new DCO and Its Applications to Built-In Speed Grading of Arithmetic Circuits
SAR ADC Layout Generation Using Digital Place-and-Route Tools […] Read More… from SAR ADC Layout Generation Using Digital Place-and-Route Tools
Improve the quality of SystemC IPs through coverage-driven random verification […] Read More… from Improve the quality of SystemC IPs through coverage-driven random verification
UVM Scoreboards and Checkers Memory, TLB and Cache […] Read More… from UVM Scoreboards and Checkers Memory, TLB and Cache
UVM-based extended Low Power Library package with Low Power Multi-Core Architectures […] Read More… from UVM-based extended Low Power Library package with Low Power Multi-Core Architectures
Scalable Mixed Features Stimulus Generation for Cluster Network Using Sequence Decorator […] Read More… from Scalable Mixed Features Stimulus Generation for Cluster Network Using Sequence Decorator
Autonomous Verification: Are We There Yet? […] Read More… from Autonomous Verification: Are We There Yet?
Accellera, Standards, and Semiconductor Supply Chain […] Read More… from Accellera, Standards, and Semiconductor Supply Chain
