Expediting SoC Design Verification Closure by Accelerating Gate Level Simulations using Streamlined Smart Decentralized Testbench

Author(s):
Harshal Kothari, Eldin Ben Jacob, Chandrachud Murali, Sriram Kazhiyur Sounderrajan, Somasunder Kattepura Sreenath
Location:
United States
Year:
2024
Type:
Paper
Format:
pdf