Getting Rid of False Errors when Verifying LSI Designs Including Non-Determinism […] Read More… from Getting Rid of False Errors when Verifying LSI Designs Including Non-Determinism
Simple & Rapid Design Verification using SystemVerilog Testbench on Intel’s Next-Generation Microprocessor […] Read More… from Simple & Rapid Design Verification using SystemVerilog Testbench on Intel’s Next-Generation Microprocessor
Exhaustive Equivalence Checking on AMD’s Next-generation Microprocessor Core […] Read More… from Exhaustive Equivalence Checking on AMD’s Next-generation Microprocessor Core
An Automatic Visual System Performance Stress Test for TLM Designs […] Read More… from An Automatic Visual System Performance Stress Test for TLM Designs
Automated approach to Register Design and Verification of complex SOC […] Read More… from Automated approach to Register Design and Verification of complex SOC
Traversing the Interconnect: Automating Configurable Verification Environment Development […] Read More… from Traversing the Interconnect: Automating Configurable Verification Environment Development
Panning for Gold in RTL Using Transactions […] Read More… from Panning for Gold in RTL Using Transactions
Functional coverage-driven verification with SystemC on multiple level of abstraction […] Read More… from Functional coverage-driven verification with SystemC on multiple level of abstraction
Pay Me Now or Pay Me Later Exploring the Implementation and Analysis Cost Trade-Offs of Coverage Model Design […] Read More… from Pay Me Now or Pay Me Later Exploring the Implementation and Analysis Cost Trade-Offs of Coverage Model Design
From the Magician’s Hat: Developing a Multi-Methodology PCIe Gen2 VIP […] Read More… from From the Magician’s Hat: Developing a Multi-Methodology PCIe Gen2 VIP
Parameters and OVM — Can’t They Just Get Along? […] Read More… from Parameters and OVM — Can’t They Just Get Along?
Are OVM & UVM Macros Evil? A Cost-Benefit Analysis […] Read More… from Are OVM & UVM Macros Evil? A Cost-Benefit Analysis
Stepwise Refinement and Reuse: The Key to ESL […] Read More… from Stepwise Refinement and Reuse: The Key to ESL
An experience to finish code refinement earlier at behavioral level […] Read More… from An experience to finish code refinement earlier at behavioral level
Verification Patterns in the Multicore SoC Domain […] Read More… from Verification Patterns in the Multicore SoC Domain
Optimizing Area and Power Using Formal Method […] Read More… from Optimizing Area and Power Using Formal Method
Low Power Static Verification- Beyond Linting and Corruption Semantics […] Read More… from Low Power Static Verification- Beyond Linting and Corruption Semantics
Achieving First-Time Success with a UPF-based Low Power Verification Flow […] Read More… from Achieving First-Time Success with a UPF-based Low Power Verification Flow
Addressing the verification challenge of SERDES-based FPGAs: The performance/accuracy/efficiency trade-off […] Read More… from Addressing the verification challenge of SERDES-based FPGAs: The performance/accuracy/efficiency trade-off
CompMon: Ensuring Rigorous Protocol Specification and IP Compliance […] Read More… from CompMon: Ensuring Rigorous Protocol Specification and IP Compliance
A Smart Synchronizer – Pragmatic way to cross asynchronous clock domains […] Read More… from A Smart Synchronizer – Pragmatic way to cross asynchronous clock domains
Off To The Races With Your Accelerated SystemVerilog Testbench (A Methodology for Hardware-Assisted Acceleration of SystemVerilog Testbenches) […] Read More… from Off To The Races With Your Accelerated SystemVerilog Testbench (A Methodology for Hardware-Assisted Acceleration of SystemVerilog Testbenches)
Transaction-Based Acceleration—Strong Ammunition In Any Verification Arsenal […] Read More… from Transaction-Based Acceleration—Strong Ammunition In Any Verification Arsenal
Comparison of TLM2-Quantum Keeping and TLM+-Resource Modeling with regard to Timing in Virtual Prototypes […] Read More… from Comparison of TLM2-Quantum Keeping and TLM+-Resource Modeling with regard to Timing in Virtual Prototypes
Advanced Testbench Configuration with Resources […] Read More… from Advanced Testbench Configuration with Resources
Metric Driven Verification of Mixed-Signal Designs […] Read More… from Metric Driven Verification of Mixed-Signal Designs
Plan & Metric Driven Mixed-Signal Verification for Medical Devices […] Read More… from Plan & Metric Driven Mixed-Signal Verification for Medical Devices
Application of SystemC/SystemC-AMS in 3G Virtual Prototyping […] Read More… from Application of SystemC/SystemC-AMS in 3G Virtual Prototyping
An Innovative Methodology for Verifying Mixed-Signal Components […] Read More… from An Innovative Methodology for Verifying Mixed-Signal Components
GoldMine: Automatic Assertion Generation and Coverage Closure in Design Validation […] Read More… from GoldMine: Automatic Assertion Generation and Coverage Closure in Design Validation
Plugging the Holes: SystemC and VHDL Functional Coverage Methodology […] Read More… from Plugging the Holes: SystemC and VHDL Functional Coverage Methodology
Case Study: Low-Power Verification Success Depends on Positive Pessimism […] Read More… from Case Study: Low-Power Verification Success Depends on Positive Pessimism
Case Study: Power-aware IP and Mixed-Signal Veri […] Read More… from Case Study: Power-aware IP and Mixed-Signal Veri
Mixed Signal Assertion-Based Verification […] Read More… from Mixed Signal Assertion-Based Verification
Parallel Computing for Functional Verification and Compute Farms: The Holy Matrimony […] Read More… from Parallel Computing for Functional Verification and Compute Farms: The Holy Matrimony
Assertion Based Self-checking of Analog Circuits for Circuit Verification and Model Validation in SPICE and Co-simulation Environments […] Read More… from Assertion Based Self-checking of Analog Circuits for Circuit Verification and Model Validation in SPICE and Co-simulation Environments
High-Level Synthesis Walks the Talk: Synthesizing a Complete Graphics Processing Application […] Read More… from High-Level Synthesis Walks the Talk: Synthesizing a Complete Graphics Processing Application
Towards Provable Protocol Conformance of Serial Automotive Communication IP […] Read More… from Towards Provable Protocol Conformance of Serial Automotive Communication IP
Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL Synthesis […] Read More… from Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL Synthesis
So There’s My Bug! Debugging Universal Verification Methodology (UVM) Environments […] Read More… from So There’s My Bug! Debugging Universal Verification Methodology (UVM) Environments
A Practical Look @ SystemVerilog Coverage – Tips, Tricks, and Gotchas […] Read More… from A Practical Look @ SystemVerilog Coverage – Tips, Tricks, and Gotchas
First Reports from the UVM Trenches: User-friendly, Versatile and Malleable, or just the Emperor’s New Methodology? […] Read More… from First Reports from the UVM Trenches: User-friendly, Versatile and Malleable, or just the Emperor’s New Methodology?
SystemVerilog FrameWorksTM Scoreboard: An Open Source Implementation Using UVM […] Read More… from SystemVerilog FrameWorksTM Scoreboard: An Open Source Implementation Using UVM
OVM & UVM Techniques for Terminating Tests […] Read More… from OVM & UVM Techniques for Terminating Tests
Easier UVM for Functional Verification by Mainstream Users […] Read More… from Easier UVM for Functional Verification by Mainstream Users
