| A Novel Approach to Accelerate Latency of Assertion Simulation | Jack Yen, Felix Tung | 2023 | Paper | | y2023 | paper |
| Accellera, Standards, and Semiconductor Supply Chain | Lu Dai | 2023 | Presentation | | y2023 | presentation |
| Autonomous Verification: Are We There Yet? | Ajay Singh | 2023 | Presentation | | y2023 | presentation |
| Building a Virtual Driver for Emulator | Chen Chih-Chiang | 2023 | Paper | | y2023 | paper |
| Debug Automation with AI | Craig Yang, Jaw Lee, Sherwin Lai | 2023 | Paper | | y2023 | paper |
| Design and Verification of the PLL using the new DCO and Its Applications to Built-In Speed Grading of Arithmetic Circuits | Yi-Sheng Wang, Hsiang-Kai Teng, Shi-Yu Huang | 2023 | Paper | | y2023 | paper |
| Formal Sign-off Methodology for IP Blocks | Anna Chang, Chia-An Hsu | 2023 | Paper | | y2023 | paper |
| Improve the quality of SystemC IPs through coverage-driven random verification | Trung Pham, Huy Phan, Masayuki Masuda | 2023 | Paper | | y2023 | paper |
| Model-Based Design The Top-Level System Design Method | Alan P. Su | 2023 | Paper | | y2023 | paper |
| Reducing the simulation life cycle time using Artificial Intelligence and Machine learning techniques on Big Data dataset | Darshan Sarod, Pratham Khande, Gopi Srinivas Deepala, Priyanka Gharat, Avnita Pal | 2023 | Paper | | y2023 | paper |
| SAR ADC Layout Generation Using Digital Place-and-Route Tools | Yao-Hung Tsai and Shen-Iuan Liu | 2023 | Paper | | y2023 | paper |
| Scalable Mixed Features Stimulus Generation for Cluster Network Using Sequence Decorator | Chi-Ming Li | 2023 | Paper | | y2023 | paper |
| UVM Scoreboards and Checkers Memory, TLB and Cache | Rich Edelman, C. H. Liu | 2023 | Paper | | y2023 | paper |
| UVM-based extended Low Power Library package with Low Power Multi-Core Architectures | Avnita Pal, Priyanka Gharat | 2023 | Paper | | y2023 | paper |
| Verification Challenges & Solutions of 10BaseT1s Automotive Ethernet PHY | Harshdeep Verma, Vedansh Seth | 2023 | Paper | | y2023 | paper |
