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Event Year: 2022

DVCon India 2022 Proceedings

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Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IP

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Accelerating the SoC Integration Verification Cycle Time Leveraging the Legacy Design Confidence

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Enabling high quality design sign-off with Jasper structural and auto formal checks

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Verifying the I/O peripherals of OpenTitan SOC using the Portable Stimulus Standard

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Exhaustive validation of a cache memory controller using Formal Verification to meet performance and timing requirements

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Left shift catching of critical low power bugs with Formal Verification

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Scalable Test bench Architecture and Methodology for Faster Codec and Computer Vision Scenario Verification

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Efficient Regression Management with Smart Data Mining Technique

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Channel Modelling in Complex Serial IPs

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Low Power Extension in UVM Power Management

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A Novel Approach to Hardware Controlled Power Aware Verification with Optimized Power Consumption Techniques at SOC

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Configurable Testbench (TB) for Configurable Design IP

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Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex PMIC designed for SSD Applications

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What-If analysis of Safety Mechanism’s impacts on ETHMAC design under Functional Safety flow

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A Generic Configurable Error Injection Agent for On-Chip Memories

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Efficient Formal strategies to verify the robustness of the design

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Novel approach for SoC pipeline latency and connectivity verification using Formal

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Fault Injection Strategy to Validate ASIL-D Requirements of BMS Components

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Novel Adaptive CPU Scoreboard Methodology for a Multi-language environment

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A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage

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The Industry eFPGA soft IP fully customizable, for hardware reconfiguration in the field

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Engaging with IEEE through Standards

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Portable Stimulus Standard Update PSS in the Real World

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IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 45 minutes!

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Digital Transformation of EDA Environments To Accelerate Semiconductor Innovation

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Embracing Datapath Verification with Jasper C2RTL App

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VirtIO based GPU model

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SystemUVM™ Driving Portable Stimulus Ease-Of-Use

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Achieve Faster Debug Closure by Applying Big Data & Advanced RCA Technologies

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Design space exploration of PIM (Processing in Memory) & PNC (Processing Near Memory) based on workload characterization

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Hardware Security – Industry Trends, Attacks and Solutions

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Compute Link Express – CXL – CXL Consortium

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Accelerating Semiconductor Time to ISO 26262 Compliance

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Using UVM-e Testbenches Utilizing Metric-Driven Verification and Advanced Debug Capabilities

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Functional Safety Verification Methodology for ASIL-B Automotive Designs

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Building UVM Testbenches for High Quality Serial Design IPs Modelling real world scenarios

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A Novel Approach to Reduce Power Consumption By Bridging The Gap between Standalone Functional Scenario and Real Time Scenario at SOC

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Utilization of Emulation for accelerating the Functional Verification Closure

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Low Power Extension In UVM Power Management

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Embrace Errors! Architecting UVM Testbenches for Dynamic Error Injection & Handling

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Channel Modelling in Complex Serial IPs

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NRFs Indentification & Signoff with GLS Validation

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Reset Verification using formal tool

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Leveraging RAL and alternate automation (cocotb) techniques to improve Register Verification in UVM

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Left shift catching of critical low power bugs with Formal Verification

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Automated vManager regression using Jenkins

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SoC verification of Security x Safety aspects for memory programmed into secure and non-secure regions in Automotive devices

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A Holistic Overview on Preventive & Corrective Action To Handle Glitches

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Automating information retrieval from EDA software reports using effective parsing algorithms

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Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex PMIC designed for SSD Applications

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Logic Equivalence Check without Low Power – you are at risk!!

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Verifying the I/O peripherals of OpenTitan SOC using the Portable Stimulus Standard

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Read More… from Verifying the I/O peripherals of OpenTitan SOC using the Portable Stimulus Standard

Solving Problems with hierarchical CDC analysis of large designs with encrypted blocks

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Innovative methodologies for analyzing CDC and RDC violations in complex SoC using Automations, formal verification, and Hierarchical CDC model

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Read More… from Innovative methodologies for analyzing CDC and RDC violations in complex SoC using Automations, formal verification, and Hierarchical CDC model

Bringing Reset Domains and Power Domains together – Non resettable registers amplifying issues in Power-Aware RDC Verification due to UPF Instrumentation

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Left shift catching of critical low power bugs with Formal Verification

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Disciplined Post Silicon Validation using ML Intelligence

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Debug Time Reduction by Automatic Generation of Waiver List Using ML Techniques

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A Generic Configurable Error Injection Agent for All On-Chip Memories

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Read More… from A Generic Configurable Error Injection Agent for All On-Chip Memories

Accelerating the SoC Integration Verification Cycle Time Leveraging the Legacy Design Confidence

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Read More… from Accelerating the SoC Integration Verification Cycle Time Leveraging the Legacy Design Confidence

Part 9 An Efficient Methodology for Development of Cryptographic Engines

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Efficient Regression Management with Smart Data Mining Technique 

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Scalable Test bench Architecture and Methodology for Faster Codec and Computer Vision Scenario Verification

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Read More… from Scalable Test bench Architecture and Methodology for Faster Codec and Computer Vision Scenario Verification

Novel Adaptive CPU Scoreboard Methodology for a Multi-language environment

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Verification Reuse Strategy for RTL Quality SoC Functional Virtual Prototypes

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Methodology for system-level comparison of ARM vs RISC-V cores for latency and power consumption

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Novel Methodology for TLM Model Unit Verification

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Efficacious verification of Loopback and Equalization in PCIe By Using Novel approach

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Building Configurable UVM Testbench for Configurable Design IP (Configurable TB)

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UVM Based Generic Interrupt Handler (UGIH)

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Shifting Left CXL Interop using Simulation Techniques

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Overcoming Challenges in Functional Verification of Automotive Traffic Schedulers

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Read More… from Overcoming Challenges in Functional Verification of Automotive Traffic Schedulers

Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IP

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Read More… from Advancements in UVM Test Bench Architecture for Verifying High Speed MIPI MPHY 5.0 IP

A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage

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Read More… from A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage

“What-If” analysis of Safety Mechanism’s impacts on ETHMAC design under Functional Safety flow

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Read More… from “What-If” analysis of Safety Mechanism’s impacts on ETHMAC design under Functional Safety flow

Fault Injection Strategy to Validate ASIL-D Requirements of BMS Components

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Read More… from Fault Injection Strategy to Validate ASIL-D Requirements of BMS Components

Enabling high quality design sign-off with structural and auto formal checks

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Read More… from Enabling high quality design sign-off with structural and auto formal checks

Efficient Formal strategies to verify the robustness of the design

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Read More… from Efficient Formal strategies to verify the robustness of the design

Novel approach for SoC pipeline latency and connectivity verification using Formal

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Read More… from Novel approach for SoC pipeline latency and connectivity verification using Formal

Exhaustive validation of a cache memory controller using Formal Verification to meet performance and timing requirements

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Read More… from Exhaustive validation of a cache memory controller using Formal Verification to meet performance and timing requirements

Effective Formal Deadlock Verification Methodologies for Interconnect design

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Read More… from Effective Formal Deadlock Verification Methodologies for Interconnect design

OIL check of PCIe with Formal Verification

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The Formal Way – Fast and Accurate Hashing Algorithm Verification

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A Recipe for swift Tape-out of Derivative SoCs: A Comprehensive Validation Approach using Formal-based Sequential Equivalence and Connectivity Checking

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Retry with Confidence: Use Formal Property Verification to Verify Link Layer Retry (LLR) Mechanism of Compute Express Link (CXL)

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DVCon U.S. 2022 Proceedings

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DVCon US 2022 Proceedings

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Bringing UVM to VHDL

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Accellera UVM-AMS Standard Update

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The Best Verification Strategy You’ve Never Heard Of

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System Verification with MatchLib

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Portable Stimulus Standard Update: PSS in the Real World

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Proven Strategies for Better Verification Planning: DVCon 2022 Workshop

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Machine Learning Driven Verification A Step Function in Productivity and Throughput

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Virtual Platforms to Shift-Left Software Development and System Verification

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Is Your Hardware Dependable?

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IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 90 minutes!

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Introduction to the 5 Levels of RISC-V Processor Verification

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“In-Emulator” UVM++ Randomized Testbenches for High Performance Functional Verification

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Finding Hidden Bugs In Deep Cycles: Advanced Debug Methodologies for Software-first System Validation

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Estimating Power Dissipation of End-User Application on RTL

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Read More… from Estimating Power Dissipation of End-User Application on RTL

Building a Comprehensive Hardware Security Methodology

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Read More… from Building a Comprehensive Hardware Security Methodology

An Overview of Security Annotation for Electronic Design Integration (SA-EDI) Standard

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Read More… from An Overview of Security Annotation for Electronic Design Integration (SA-EDI) Standard

Why Not “Connect” Using UVM Connect: Mixed Language Communication Got Easier with UVMC

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Read More… from Why Not “Connect” Using UVM Connect: Mixed Language Communication Got Easier with UVMC

What Does The Sequence Say? Powering Productivity with Polymorphism

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Read More… from What Does The Sequence Say? Powering Productivity with Polymorphism

Using PSS-2.0 Hardware-Software Interface to validate 4G/5G Forward Error Correction Encoder/Decoder IP in Emulation & Silicon

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Read More… from Using PSS-2.0 Hardware-Software Interface to validate 4G/5G Forward Error Correction Encoder/Decoder IP in Emulation & Silicon

Two-Stage Framework for Corner Case Stimuli Generation Using Transformer and Reinforcement Learning

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Test Parameter Tuning with Blackbox Optimization: A Simple Yet Effective Way to Improve Coverage

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Read More… from Test Parameter Tuning with Blackbox Optimization: A Simple Yet Effective Way to Improve Coverage

SystemC Virtual Prototype: Ride the earliest train for Time-To-Market!

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Read More… from SystemC Virtual Prototype: Ride the earliest train for Time-To-Market!

Systematic Constraint Relaxation (SCR): Hunting for Over-Constrained Stimulus

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Read More… from Systematic Constraint Relaxation (SCR): Hunting for Over-Constrained Stimulus

Successive Refinement – An Approach to Decouple Front End and Back End Power Intent

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Raising the Level of Formal Signoff with End-to-End Checking Methodology

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PSS Action Sequence Modeling Using Machine Learning

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Read More… from PSS Action Sequence Modeling Using Machine Learning

Problematic Bi-Directional Port Connections: How Well Is Your Simulator Filling the UPF LRM Void?

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Read More… from Problematic Bi-Directional Port Connections: How Well Is Your Simulator Filling the UPF LRM Void?

Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads Using Hybrid System Level Emulation SoC Platform

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Path-Based UPF Strategies: Optimally Manage Power on Your Designs

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Optimizing Turnaround Times in a Continuous Integration Flow Using a Scheduler Based Implementation

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Novel GUI Based UVM Test Bench Template Builder

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Never Too Late With Formal: Stepwise Guide for Applying Formal Verification in Post-Silicon Phase to Avoid Re-Spins

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Modeling Memory Coherency During Concurrent/Simultaneous Accesses

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Modeling Analog Devices using SV-RNM

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Mixed-Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP Simulation

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Read More… from Mixed-Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP Simulation

Mixed-Signal Design Verification: Leveraging the Best of AMS and DMS

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Metadata Based Testbench Generation Automation

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Maximizing Formal ROI through Accelerated IP Verification Sign-off

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Machine Learning Based Verification Planning Methodology Using Design and Verification Data

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Read More… from Machine Learning Based Verification Planning Methodology Using Design and Verification Data

Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges

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Read More… from Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges

Leaping Left: Seamless IP to SoC Hand-off

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Is It a Software Bug? Is It a Hardware Bug?

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Innovative Uses of SystemVerilog Bind Statements within Formal Verification

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Hybrid Emulation: Accelerating Software Driven Verification and Debug

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Read More… from Hybrid Emulation: Accelerating Software Driven Verification and Debug

How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage

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Hopscotch: A Scalable Flow-Graph Based Approach to Formally Specify and Verify Memory-Tagged Store Execution in Arm CPUs

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Hierarchical UPF: Uniform UPF across FE & BE

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Fnob: Command Line-Dynamic Random Generator

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Flattening the UVM Learning Curve Automated Solutions for DSP Filter Verification

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Finding a Needle in a Haystack: A Novel Log Analysis Method with Test Clustering in Distributed Systems

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Reusable System-Level Power-Aware IP Modeling Approach

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Evaluating the Feasibility of a RISCV Core for Real-Time Applications Using a Virtual Prototype

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Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software Verification

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Emulation Based Power and Performance Workloads on ML NPUs

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Read More… from Emulation Based Power and Performance Workloads on ML NPUs

Confidently Sign-Off Any Low-Power Designs Without Consequences

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Co-Developing Firmware and IP with PSS

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Case Study: Successes and Challenges of Validation Content Reuse

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CAMEL: A Flexible Cache Model for Cache Verification

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Caching Tool Run Results in Large-Scale RTL Development Projects

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BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering Problem

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Avoiding Confounding Configurations An RDC Methodology for Configurable Designs

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Automatic Translation of Natural Language to SystemVerilog Assertions

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Advanced UVM Command Line Processor for Central Maintenance and Randomization of Control Knobs

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Advanced Functional Verification for Automotive System on a Chip

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Read More… from Advanced Functional Verification for Automotive System on a Chip

Adaptive Test Generation for Fast Functional Coverage Closure

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Read More… from Adaptive Test Generation for Fast Functional Coverage Closure

Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing Products

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Read More… from Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing Products

Accelerating Error Handling Verification of Complex Systems: A Formal Approach

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Read More… from Accelerating Error Handling Verification of Complex Systems: A Formal Approach

A Hybrid Verification Solution to RISC-V Vector Extension

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A UVM SystemVerilog Testbench for Analog/Mixed-Signal Verification: A Digitally-Programmable Analog Filter Example

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A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain Crossings

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A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation

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Read More… from A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation

A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISCV Core

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Read More… from A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISCV Core

Why Not “Connect” Using UVM Connect: Mixed Language Communication Got Easier with UVMC

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Read More… from Why Not “Connect” Using UVM Connect: Mixed Language Communication Got Easier with UVMC

Successive Refinement – An Approach to Decouple Front Front-End and Back Back-End Power Intent

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Read More… from Successive Refinement – An Approach to Decouple Front Front-End and Back Back-End Power Intent

Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads using Hybrid System Level Emulation SoC Platform

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Read More… from Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads using Hybrid System Level Emulation SoC Platform

Novel GUI Based UVM Test Bench Template Builder

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Read More… from Novel GUI Based UVM Test Bench Template Builder

Modeling Analog Devices Using SV-RNM

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Read More… from Modeling Analog Devices Using SV-RNM

Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges

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Read More… from Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges

Hybrid Emulation: Accelerating Software Driven Verification and Debug

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Read More… from Hybrid Emulation: Accelerating Software Driven Verification and Debug

Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software Verification

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Read More… from Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software Verification

Emulation Based Power and Performance Workloads on ML NPUs

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Read More… from Emulation Based Power and Performance Workloads on ML NPUs

Confidently Sign-off Any low-Power Designs without Consequences

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Read More… from Confidently Sign-off Any low-Power Designs without Consequences

Successes and Challenges of Validation Content Reuse

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Read More… from Successes and Challenges of Validation Content Reuse

Avoiding Confounding Configurations an RDC Methodology for Configurable Designs

[…]

Read More… from Avoiding Confounding Configurations an RDC Methodology for Configurable Designs

Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing Products

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Read More… from Accelerating Performance, Power and Functional Validation of Computer Vision Use Cases on Next Generation Edge Inferencing Products

A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation

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Read More… from A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation

What Does The Sequence Say? Powering Productivity with Polymorphism

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Read More… from What Does The Sequence Say? Powering Productivity with Polymorphism

Portable Stimulus Standard’s Hardware Software Interface (HSI) to validate 4G 5G Forward Error Correction Encoder/Decoder IP in Emulation Silicon

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Read More… from Portable Stimulus Standard’s Hardware Software Interface (HSI) to validate 4G 5G Forward Error Correction Encoder/Decoder IP in Emulation Silicon

Two Stage Framework for Corner Case Stimuli Generation Using Transformer and Reinforcement Learning

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Read More… from Two Stage Framework for Corner Case Stimuli Generation Using Transformer and Reinforcement Learning

Test Parameter Tuning with Blackbox Optimization: A Simple Yet Effective Way to Improve Coverage

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Read More… from Test Parameter Tuning with Blackbox Optimization: A Simple Yet Effective Way to Improve Coverage

SystemC Virtual Prototype: Ride the Earliest Train for Time-To-Market

[…]

Read More… from SystemC Virtual Prototype: Ride the Earliest Train for Time-To-Market

Systematic Constraint Relaxation (SCR): Hunting for Over Constrained Stimulus

[…]

Read More… from Systematic Constraint Relaxation (SCR): Hunting for Over Constrained Stimulus

Raising the level of Formal Signoff with End to End Checking Methodology

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Read More… from Raising the level of Formal Signoff with End to End Checking Methodology

PSS Action Sequence Modeling Using Machine Learning

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Read More… from PSS Action Sequence Modeling Using Machine Learning

Problematic Bi-Directional Port Connections: How Well is Your Simulator Filling the UPF LRM Void?

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Read More… from Problematic Bi-Directional Port Connections: How Well is Your Simulator Filling the UPF LRM Void?

Path-based UPF Strategies: Optimally Manage Power on your Designs

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Optimizing Turnaround Times In A CI Flow Using a Scheduler Implementation

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Never Too Late with Formal: Stepwise Guide for Applying FV in Post Si Phase to Avoid Re-Spins

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Modeling Memory Coherency for Concurrent/Parallel Accesses

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Hierarchical UPF: Uniform UPF across FE & BE

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Fnob: Command Line-Dynamic Random Generator

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Flattening the UVM Learning Curve: Automated Solutions for DSP Filter Verification

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Finding a Needle in a Haystack: A Novel Log Analysis Method with Test Clustering in Distributed System

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Extension of the Power-Aware IP Reuse Approach to ESL

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Evaluating the Feasibility of a RISC V Core for Real Time Applications Using a Virtual Prototype

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Co-Developing IP and SoC Bring-Up Firmware with PSS

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CAMEL – A Flexible Cache Model for Cache Verification

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Caching Tool Run Results in Large Scale RTL Development Projects

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BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering Problem

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Automatic Translation of Natural Language to SystemVerilog Assertions

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Advanced UVM Command Line Processor

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Advanced Functional Verification for Automotive System on a Chip

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Adaptive Test Generation for Fast Functional Coverage Closure

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Accelerating Error Handling Verification Of Complex Systems: A Formal Approach

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A Hybrid Verification Solution to RISC V Vector Extension

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A UVM Testbench for Analog Verification: A Programmable Filter Example

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A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain Crossings

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A Comparative Study of CHISEL and SystemVerilog Based on Logical Equivalent SweRV EL2 RISC V Core

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Mixed Signal Design Verification: Leveraging the Best of AMS and DMS

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Modeling Memory Coherency for concurrent/parallel accesses

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Mixed Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP Simulation

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Metadata Based Testbench Generation

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Maximizing Formal ROI through Accelerated IP Verification Sign-off

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Machine Learning Based Verification Planning Methodology Using Design and Verification Data

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Leaping Left: Seamless IP to SoC Hand off

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Is It a Software Bug? It Is a Hardware Bug?

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Innovative Uses of SystemVerilog Bind Statements within Formal Verification

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How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage

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Hopscotch: A Scalable Flow-Graph Based Approach to Verify CPU Store Execution

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